From 05744f4e40b3f6bb487703af5d80baeee782bf97 Mon Sep 17 00:00:00 2001 From: Dr-Noob Date: Wed, 12 Apr 2023 18:55:56 +0200 Subject: [PATCH] [v1.03][RISCV] Add support for RISCV extensions --- src/common/cpu.h | 16 ++++++- src/common/printer.c | 105 ++++++++++++++++++++++++++++++++++++++++++- src/riscv/riscv.c | 40 +++++++++++++++++ src/riscv/riscv.h | 26 +++++++++++ src/riscv/udev.c | 6 +++ src/riscv/udev.h | 1 + 6 files changed, 190 insertions(+), 4 deletions(-) diff --git a/src/common/cpu.h b/src/common/cpu.h index 0db2fbf..449fbe0 100644 --- a/src/common/cpu.h +++ b/src/common/cpu.h @@ -120,16 +120,28 @@ struct features { #endif }; +struct extensions { + char* str; + uint32_t mask; +}; + struct cpuInfo { - VENDOR cpu_vendor; + VENDOR cpu_vendor; struct uarch* arch; struct hypervisor* hv; struct frequency* freq; struct cache* cach; struct topology* topo; - struct features* feat; int64_t peak_performance; + // Similar but not exactly equal + // to struct features +#ifdef ARCH_RISCV + struct extensions* ext; +#else + struct features* feat; +#endif + #if defined(ARCH_X86) || defined(ARCH_PPC) // CPU name from model char* cpu_name; diff --git a/src/common/printer.c b/src/common/printer.c index c778626..9216fb7 100644 --- a/src/common/printer.c +++ b/src/common/printer.c @@ -66,6 +66,8 @@ enum { ATTRIBUTE_ALTIVEC, #elif ARCH_ARM ATTRIBUTE_FEATURES, +#elif ARCH_RISCV + ATTRIBUTE_EXTENSIONS, #endif ATTRIBUTE_L1i, ATTRIBUTE_L1d, @@ -99,6 +101,8 @@ static const char* ATTRIBUTE_FIELDS [] = { "Altivec: ", #elif defined(ARCH_ARM) "Features: ", +#elif defined(ARCH_RISCV) + "Extensions: ", #endif "L1i Size:", "L1d Size:", @@ -132,6 +136,8 @@ static const char* ATTRIBUTE_FIELDS_SHORT [] = { "Altivec: ", #elif defined(ARCH_ARM) "Features: ", +#elif defined(ARCH_RISCV) + "Extensions: ", #endif "L1i Size:", "L1d Size:", @@ -442,7 +448,7 @@ uint32_t longest_field_length(struct ascii* art, int la) { return max; } -#if defined(ARCH_X86) || defined(ARCH_PPC) || defined(ARCH_RISCV) +#if defined(ARCH_X86) || defined(ARCH_PPC) void print_ascii_generic(struct ascii* art, uint32_t la, int32_t termw, const char** attribute_fields, bool hybrid_architecture) { struct ascii_logo* logo = art->art; int attr_to_print = 0; @@ -925,6 +931,98 @@ bool print_cpufetch_arm(struct cpuInfo* cpu, STYLE s, struct color** cs, struct #endif #ifdef ARCH_RISCV +// https://stackoverflow.com/questions/109023/count-the-number-of-set-bits-in-a-32-bit-integer +int number_of_bits(uint32_t i) { + i = i - ((i >> 1) & 0x55555555); // add pairs of bits + i = (i & 0x33333333) + ((i >> 2) & 0x33333333); // quads + i = (i + (i >> 4)) & 0x0F0F0F0F; // groups of 8 + + return (i * 0x01010101) >> 24; // horizontal sum of bytes +} + +void print_ascii_riscv(struct ascii* art, uint32_t la, int32_t termw, const char** attribute_fields, uint32_t extensions_mask) { + struct ascii_logo* logo = art->art; + int attr_to_print = 0; + int attr_type; + char* attr_value; + int32_t beg_space; + int32_t space_right; + int32_t ext_list_size = sizeof(extension_list)/sizeof(extension_list[0]); + int32_t ext_num = 0; + int32_t ext_to_print = 0; + int32_t num_extensions = number_of_bits(extensions_mask); + int32_t space_up = ((int)logo->height - (int)(art->n_attributes_set + num_extensions))/2; + int32_t space_down = (int)logo->height - (int)(art->n_attributes_set + num_extensions) - (int)space_up; + uint32_t logo_pos = 0; + int32_t iters = max(logo->height, art->n_attributes_set); + + struct line_buffer* lbuf = emalloc(sizeof(struct line_buffer)); + lbuf->buf = emalloc(sizeof(char) * LINE_BUFFER_SIZE); + lbuf->pos = 0; + lbuf->chars = 0; + + printf("\n"); + for(int32_t n=0; n < iters; n++) { + // 1. Print logo + if(space_up > 0 || (space_up + n >= 0 && space_up + n < (int)logo->height)) { + for(uint32_t i=0; i < logo->width; i++) { + if(logo->art[logo_pos] == '$') { + if(logo->replace_blocks) logo_pos += 3; + else parse_print_color(art, lbuf, &logo_pos); + } + if(logo->replace_blocks && logo->art[logo_pos] != ' ') { + if(logo->art[logo_pos] == '#') printOut(lbuf, 1, "%s%c%s", logo->color_ascii[0], ' ', art->reset); + else if(logo->art[logo_pos] == '@') printOut(lbuf, 1, "%s%c%s", logo->color_ascii[1], ' ', art->reset); + else if(logo->art[logo_pos] == '%') printOut(lbuf, 1, "%s%c%s", logo->color_ascii[2], ' ', art->reset); + else printOut(lbuf, 1, "%c", logo->art[logo_pos]); + } + else + printOut(lbuf, 1, "%c", logo->art[logo_pos]); + + logo_pos++; + } + printOut(lbuf, 0, "%s", art->reset); + } + else { + // If logo should not be printed, fill with spaces + printOut(lbuf, logo->width, "%*c", logo->width, ' '); + } + + // 2. Print text + if(space_up < 0 || (n > space_up-1 && n < (int)logo->height - space_down)) { + attr_type = art->attributes[attr_to_print]->type; + attr_value = art->attributes[attr_to_print]->value; + + // Print extension + if(attr_to_print > 0 && art->attributes[attr_to_print-1]->type == ATTRIBUTE_EXTENSIONS && ext_num != num_extensions) { + // Search for the extension to print + while(ext_to_print < ext_list_size && !((extensions_mask >> extension_list[ext_to_print].id) & 1U)) ext_to_print++; + if(ext_to_print == ext_list_size) { + printBug("print_ascii_riscv: Unable to find the extension to print"); + } + + printOut(lbuf, 3 + strlen(extension_list[ext_to_print].str), "%s - %s%s", logo->color_text[0], extension_list[ext_to_print].str, art->reset); + ext_num++; + ext_to_print++; + } + else { + attr_to_print++; + beg_space = 0; + space_right = 2 + 1 + (la - strlen(attribute_fields[attr_type])); + + printOut(lbuf, beg_space + strlen(attribute_fields[attr_type]) + space_right + strlen(attr_value), + "%*s%s%s%s%*s%s%s%s", beg_space, "", logo->color_text[0], attribute_fields[attr_type], art->reset, space_right, "", logo->color_text[1], attr_value, art->reset); + } + } + printOutLine(lbuf, art, termw); + printf("\n"); + } + printf("\n"); + + free(lbuf->buf); + free(lbuf); +} + bool print_cpufetch_riscv(struct cpuInfo* cpu, STYLE s, struct color** cs, struct terminal* term) { struct ascii* art = set_ascii(get_soc_vendor(cpu->soc), s); if(art == NULL) @@ -950,6 +1048,9 @@ bool print_cpufetch_riscv(struct cpuInfo* cpu, STYLE s, struct color** cs, struc setAttribute(art,ATTRIBUTE_UARCH,uarch); setAttribute(art,ATTRIBUTE_NCORES, n_cores); setAttribute(art,ATTRIBUTE_FREQUENCY,max_frequency); + if(extensions != NULL) { + setAttribute(art,ATTRIBUTE_EXTENSIONS,extensions); + } /*setAttribute(art,ATTRIBUTE_L1i,l1i); setAttribute(art,ATTRIBUTE_L1d,l1d); setAttribute(art,ATTRIBUTE_L2,l2); @@ -971,7 +1072,7 @@ bool print_cpufetch_riscv(struct cpuInfo* cpu, STYLE s, struct color** cs, struc longest_attribute = longest_attribute_length(art, attribute_fields); } - print_ascii_generic(art, longest_attribute, term->w, attribute_fields, false); + print_ascii_riscv(art, longest_attribute, term->w, attribute_fields, cpu->ext->mask); return true; } diff --git a/src/riscv/riscv.c b/src/riscv/riscv.c index 3a3a78b..67e40b7 100644 --- a/src/riscv/riscv.c +++ b/src/riscv/riscv.c @@ -28,6 +28,40 @@ int64_t get_peak_performance(struct cpuInfo* cpu) { return flops; } +struct extensions* get_extensions_from_str(char* str) { + struct extensions* ext = emalloc(sizeof(struct extensions)); + ext->mask = 0; + ext->str = NULL; + + if(str == NULL) { + return ext; + } + + int len = sizeof(char) * (strlen(str)+1); + ext->str = emalloc(sizeof(char) * len); + memset(ext->str, 0, len); + strncpy(ext->str, str, sizeof(char) * len); + + // Code inspired in Linux kernel: + // https://elixir.bootlin.com/linux/v6.2.10/source/arch/riscv/kernel/cpufeature.c + char* isa = str; + if (!strncmp(isa, "rv32", 4)) + isa += 4; + else if (!strncmp(isa, "rv64", 4)) + isa += 4; + else { + printBug("get_extensions_from_str: ISA string must start with rv64 or rv32"); + return ext; + } + + for(char* e = isa; *e != '\0'; e++) { + int n = *e - 'a'; + ext->mask |= 1UL << n; + } + + return ext; +} + struct cpuInfo* get_cpu_info(void) { struct cpuInfo* cpu = malloc(sizeof(struct cpuInfo)); //init_cpu_info(cpu); @@ -37,8 +71,11 @@ struct cpuInfo* get_cpu_info(void) { cpu->topo = topo; char* cpuinfo_str = get_uarch_from_cpuinfo(); + char* ext_str = get_extensions_from_cpuinfo(); cpu->hv = emalloc(sizeof(struct hypervisor)); cpu->hv->present = false; + cpu->ext = get_extensions_from_str(ext_str); + if(cpu->ext->str != NULL && cpu->ext->mask == 0) return NULL; cpu->arch = get_uarch_from_cpuinfo_str(cpuinfo_str, cpu); cpu->soc = get_soc(); cpu->freq = get_frequency_info(0); @@ -57,6 +94,9 @@ char* get_str_topology(struct cpuInfo* cpu, struct topology* topo) { } char* get_str_extensions(struct cpuInfo* cpu) { + if(cpu->ext != NULL) { + return cpu->ext->str; + } return NULL; } diff --git a/src/riscv/riscv.h b/src/riscv/riscv.h index b9729fb..fcbdff1 100644 --- a/src/riscv/riscv.h +++ b/src/riscv/riscv.h @@ -3,6 +3,32 @@ #include "../common/cpu.h" +struct extension { + int id; + char* str; +}; + +// https://en.wikichip.org/wiki/risc-v/standard_extensions +// Included all except for G +static const struct extension extension_list[] = { + { 'i' - 'a', "(I) Integer Instruction Set" }, + { 'm' - 'a', "(M) Integer Multiplication and Division" }, + { 'a' - 'a', "(A) Atomic Instructions" }, + { 'f' - 'a', "(F) Single-Precision Floating-Point" }, + { 'd' - 'a', "(D) Double-Precision Floating-Point" }, + { 'q' - 'a', "(Q) Quad-Precision Floating-Point" }, + { 'l' - 'a', "(L) Decimal Floating-Point" }, + { 'c' - 'a', "(C) Compressed Instructions" }, + { 'b' - 'a', "(B) Double-Precision Floating-Point" }, + { 'j' - 'a', "(J) Dynamically Translated Languages" }, + { 't' - 'a', "(T) Transactional Memory" }, + { 'p' - 'a', "(P) Packed-SIMD Instructions" }, + { 'v' - 'a', "(V) Vector Operations" }, + { 'n' - 'a', "(N) User-Level Interrupts" }, + { 'h' - 'a', "(H) Hypervisor" }, + { 's' - 'a', "(S) Supervisor-level Instructions" } +}; + struct cpuInfo* get_cpu_info(void); char* get_str_topology(struct cpuInfo* cpu, struct topology* topo); char* get_str_extensions(struct cpuInfo* cpu); diff --git a/src/riscv/udev.c b/src/riscv/udev.c index a880f7e..1769e9e 100644 --- a/src/riscv/udev.c +++ b/src/riscv/udev.c @@ -7,6 +7,7 @@ #define _PATH_CPUINFO "/proc/cpuinfo" #define _PATH_DEVTREE "/proc/device-tree/compatible" #define CPUINFO_UARCH_STR "uarch\t\t: " +#define CPUINFO_EXTENSIONS_STR "isa\t\t: " #define DEVTREE_HARDWARE_FIELD 0 char* get_field_from_devtree(int DEVTREE_FIELD) { @@ -84,3 +85,8 @@ char* get_hardware_from_devtree(void) { char* get_uarch_from_cpuinfo(void) { return parse_cpuinfo_field(CPUINFO_UARCH_STR); } + +char* get_extensions_from_cpuinfo() { + return parse_cpuinfo_field(CPUINFO_EXTENSIONS_STR); +} + diff --git a/src/riscv/udev.h b/src/riscv/udev.h index 33e1a19..48a54db 100644 --- a/src/riscv/udev.h +++ b/src/riscv/udev.h @@ -7,5 +7,6 @@ char* get_hardware_from_devtree(void); char* get_uarch_from_cpuinfo(void); +char* get_extensions_from_cpuinfo(void); #endif