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[v0.87][ARM] cpuInfo now holds all the structs (freq, cache, etc), instead of having them separated. This allows ARM to represent a single CPU, because from its pointer, it is able to access the specific frequency, cache, etc

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Dr-Noob
2020-11-22 09:57:50 +01:00
parent f5ec566577
commit 0875c4d425
7 changed files with 179 additions and 190 deletions
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93
src/common/cpu.h
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@@ -56,51 +56,6 @@ struct hypervisor {
VENDOR hv_vendor;
};
struct cpuInfo {
#ifdef ARCH_X86
bool AVX;
bool AVX2;
bool AVX512;
bool SSE;
bool SSE2;
bool SSE3;
bool SSSE3;
bool SSE4a;
bool SSE4_1;
bool SSE4_2;
bool FMA3;
bool FMA4;
#endif
bool AES;
bool SHA;
VENDOR cpu_vendor;
struct uarch* arch;
struct hypervisor* hv;
#ifdef ARCH_X86
// CPU name from model
char* cpu_name;
// Max cpuids levels
uint32_t maxLevels;
// Max cpuids extended levels
uint32_t maxExtendedLevels;
#elif ARCH_ARM
// Main ID register
uint32_t midr;
#endif
#ifdef ARCH_ARM
VENDOR soc;
char* soc_name;
// If SoC contains more than one CPU and they
// are different, the others will be stored in
// the next_cpu field
struct cpuInfo* next_cpu;
uint8_t num_cpus;
#endif
};
struct cach {
int32_t size;
uint8_t num_caches;
@@ -131,6 +86,54 @@ struct topology {
#endif
};
struct cpuInfo {
#ifdef ARCH_X86
bool AVX;
bool AVX2;
bool AVX512;
bool SSE;
bool SSE2;
bool SSE3;
bool SSSE3;
bool SSE4a;
bool SSE4_1;
bool SSE4_2;
bool FMA3;
bool FMA4;
#endif
bool AES;
bool SHA;
VENDOR cpu_vendor;
struct uarch* arch;
struct hypervisor* hv;
struct frequency* freq;
struct cache* cach;
struct topology* topo;
#ifdef ARCH_X86
// CPU name from model
char* cpu_name;
// Max cpuids levels
uint32_t maxLevels;
// Max cpuids extended levels
uint32_t maxExtendedLevels;
#elif ARCH_ARM
// Main ID register
uint32_t midr;
#endif
#ifdef ARCH_ARM
VENDOR soc;
char* soc_name;
// If SoC contains more than one CPU and they
// are different, the others will be stored in
// the next_cpu field
struct cpuInfo* next_cpu;
uint8_t num_cpus;
#endif
};
#ifdef ARCH_X86
char* get_str_cpu_name(struct cpuInfo* cpu);
#endif