mirror of
https://github.com/Dr-Noob/cpufetch.git
synced 2026-03-25 16:00:39 +01:00
Fix compilation in Windows and add support for bind to specific cores. Separate APIC code in other file
This commit is contained in:
Dr-Noob
6
Makefile
6
Makefile
@@ -4,12 +4,14 @@ CXXFLAGS=-Wall -Wextra -Werror -fstack-protector-all -pedantic -Wno-unused -std=
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SANITY_FLAGS=-Wfloat-equal -Wshadow -Wpointer-arith -Wstrict-overflow=5 -Wformat=2
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SRC_DIR=src/
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SOURCE=$(SRC_DIR)main.c $(SRC_DIR)cpuid.c $(SRC_DIR)cpuid_asm.c $(SRC_DIR)printer.c $(SRC_DIR)args.c $(SRC_DIR)global.c
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HEADERS=$(SRC_DIR)cpuid.h $(SRC_DIR)cpuid_asm.h $(SRC_DIR)printer.h $(SRC_DIR)ascii.h $(SRC_DIR)args.h $(SRC_DIR)global.h
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SOURCE=$(SRC_DIR)main.c $(SRC_DIR)cpuid.c $(SRC_DIR)apic.c $(SRC_DIR)cpuid_asm.c $(SRC_DIR)printer.c $(SRC_DIR)args.c $(SRC_DIR)global.c
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HEADERS=$(SRC_DIR)cpuid.h $(SRC_DIR)apic.h $(SRC_DIR)cpuid_asm.h $(SRC_DIR)printer.h $(SRC_DIR)ascii.h $(SRC_DIR)args.h $(SRC_DIR)global.h
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ifneq ($(OS),Windows_NT)
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SOURCE += $(SRC_DIR)udev.c
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HEADERS += $(SRC_DIR)udev.h
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else
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SANITY_FLAGS += -Wno-pedantic-ms-format
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endif
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OUTPUT=cpufetch
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245
src/apic.c
Normal file
245
src/apic.c
Normal file
@@ -0,0 +1,245 @@
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#ifdef _WIN32
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#include <windows.h>
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#else
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#define _GNU_SOURCE
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#include <sched.h>
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#endif
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#include <stdlib.h>
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#include <stdint.h>
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#include <string.h>
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#include <stdio.h>
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#include "apic.h"
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#include "cpuid_asm.h"
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#include "global.h"
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/*
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* bit_scan_reverse and create_mask code taken from:
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* https://software.intel.com/content/www/us/en/develop/articles/intel-64-architecture-processor-topology-enumeration.html
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*/
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unsigned char bit_scan_reverse(uint32_t* index, uint64_t mask) {
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for(uint64_t i = (8 * sizeof(uint64_t)); i > 0; i--) {
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if((mask & (1LL << (i-1))) != 0) {
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*index = (uint64_t) (i-1);
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break;
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}
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}
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return (unsigned char) (mask != 0);
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}
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uint32_t create_mask(uint32_t num_entries, uint32_t *mask_width) {
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uint32_t i;
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uint64_t k;
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// NearestPo2(numEntries) is the nearest power of 2 integer that is not less than numEntries
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// The most significant bit of (numEntries * 2 -1) matches the above definition
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k = (uint64_t)(num_entries) * 2 -1;
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if (bit_scan_reverse(&i, k) == 0) {
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if (mask_width) *mask_width = 0;
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return 0;
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}
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if (mask_width) *mask_width = i;
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if (i == 31) return (uint32_t ) -1;
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return (1 << i) -1;
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}
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uint32_t get_apic_id(bool x2apic_id) {
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uint32_t eax = 0;
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uint32_t ebx = 0;
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uint32_t ecx = 0;
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uint32_t edx = 0;
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if(x2apic_id) {
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eax = 0x0000000B;
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cpuid(&eax, &ebx, &ecx, &edx);
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return edx;
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}
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else {
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eax = 0x00000001;
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cpuid(&eax, &ebx, &ecx, &edx);
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return (ebx >> 24);
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}
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}
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bool bind_to_cpu(int cpu_id) {
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#ifdef _WIN32
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HANDLE process = GetCurrentProcess();
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DWORD_PTR processAffinityMask = 1 << cpu_id;
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return SetProcessAffinityMask(process, processAffinityMask);
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#else
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cpu_set_t currentCPU;
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CPU_ZERO(¤tCPU);
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CPU_SET(cpu_id, ¤tCPU);
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if (sched_setaffinity (0, sizeof(currentCPU), ¤tCPU) == -1) {
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perror("sched_setaffinity");
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return false;
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}
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return true;
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#endif
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}
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bool fill_topo_masks_apic(struct topology** topo) {
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uint32_t eax = 0x00000001;
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uint32_t ebx = 0;
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uint32_t ecx = 0;
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uint32_t edx = 0;
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uint32_t core_plus_smt_id_max_cnt;
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uint32_t core_id_max_cnt;
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uint32_t smt_id_per_core_max_cnt;
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uint32_t SMTIDPerCoreMaxCnt;
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cpuid(&eax, &ebx, &ecx, &edx);
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core_plus_smt_id_max_cnt = (ebx >> 16) & 0xFF;
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eax = 0x00000004;
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ecx = 0;
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cpuid(&eax, &ebx, &ecx, &edx);
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core_id_max_cnt = (eax >> 26) + 1;
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smt_id_per_core_max_cnt = core_plus_smt_id_max_cnt / core_id_max_cnt;
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(*topo)->apic->smt_mask = create_mask(smt_id_per_core_max_cnt, &((*topo)->apic->smt_mask_width));
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(*topo)->apic->core_mask = create_mask(core_id_max_cnt,&((*topo)->apic->pkg_mask_shift));
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(*topo)->apic->pkg_mask_shift += (*topo)->apic->smt_mask_width;
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(*topo)->apic->core_mask <<= (*topo)->apic->smt_mask_width;
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(*topo)->apic->pkg_mask = (-1) ^ ((*topo)->apic->core_mask | (*topo)->apic->smt_mask);
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return true;
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}
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bool fill_topo_masks_x2apic(struct topology** topo) {
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int32_t level_type;
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int32_t level_shift;
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int32_t coreplus_smt_mask;
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bool level2 = false;
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bool level1 = false;
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uint32_t eax = 0;
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uint32_t ebx = 0;
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uint32_t ecx = 0;
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uint32_t edx = 0;
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uint32_t i = 0;
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while(true) {
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eax = 0x0000000B;
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ecx = i;
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cpuid(&eax, &ebx, &ecx, &edx);
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if(ebx == 0) break;
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level_type = (ecx >> 8) & 0xFF;
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level_shift = eax & 0xFFF;
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switch(level_type) {
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case 1: // SMT
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(*topo)->apic->smt_mask = ~(0xFFFFFFFF << level_shift);
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(*topo)->apic->smt_mask_width = level_shift;
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(*topo)->smt_supported = ebx & 0xFFFF;
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level1 = true;
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break;
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case 2: // Core
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coreplus_smt_mask = ~(0xFFFFFFFF << level_shift);
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(*topo)->apic->pkg_mask_shift = level_shift;
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(*topo)->apic->pkg_mask = (-1) ^ coreplus_smt_mask;
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level2 = true;
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break;
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default:
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printErr("Found invalid level when querying topology: %d", level_type);
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break;
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}
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i++; // sublevel to query
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}
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if (level1 && level2) {
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(*topo)->apic->core_mask = coreplus_smt_mask ^ (*topo)->apic->smt_mask;
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}
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else if (!level2 && level1) {
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(*topo)->apic->core_mask = 0;
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(*topo)->apic->pkg_mask_shift = (*topo)->apic->smt_mask_width;
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(*topo)->apic->pkg_mask = (-1) ^ (*topo)->apic->smt_mask;
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}
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else {
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printErr("SMT level was not found when querying topology");
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return false;
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}
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return true;
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}
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bool build_topo_from_apic(uint32_t* apic_pkg, uint32_t* apic_core, uint32_t* apic_smt, struct topology** topo) {
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uint32_t sockets[64];
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uint32_t smt[64];
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memset(sockets, 0, sizeof(uint32_t) * 64);
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memset(smt, 0, sizeof(uint32_t) * 64);
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for(int i=0; i < (*topo)->total_cores; i++) {
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sockets[apic_pkg[i]] = 1;
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smt[apic_smt[i]] = 1;
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}
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for(int i=0; i < 64; i++) {
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if(sockets[i] != 0)
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(*topo)->sockets++;
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if(smt[i] != 0)
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(*topo)->smt_available++;
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}
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(*topo)->logical_cores = (*topo)->total_cores / (*topo)->sockets;
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(*topo)->physical_cores = (*topo)->logical_cores / (*topo)->smt_available;
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return true;
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}
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bool get_topology_from_apic(uint32_t cpuid_max_levels, struct topology** topo) {
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uint32_t apic_id;
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uint32_t* apic_pkg = malloc(sizeof(uint32_t) * (*topo)->total_cores);
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uint32_t* apic_core = malloc(sizeof(uint32_t) * (*topo)->total_cores);
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uint32_t* apic_smt = malloc(sizeof(uint32_t) * (*topo)->total_cores);
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bool x2apic_id = cpuid_max_levels >= 0x0000000B;
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if(x2apic_id) {
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if(!fill_topo_masks_x2apic(topo))
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return false;
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}
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else {
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if(!fill_topo_masks_apic(topo))
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return false;
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}
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for(int i=0; i < (*topo)->total_cores; i++) {
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if(!bind_to_cpu(i)) {
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printErr("Failed binding to CPU %d", i);
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return false;
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}
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apic_id = get_apic_id(x2apic_id);
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apic_pkg[i] = (apic_id & (*topo)->apic->pkg_mask) >> (*topo)->apic->pkg_mask_shift;
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apic_core[i] = (apic_id & (*topo)->apic->core_mask) >> (*topo)->apic->smt_mask_width;
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apic_smt[i] = apic_id & (*topo)->apic->smt_mask;
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}
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/* DEBUG
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for(int i=0; i < (*topo)->total_cores; i++)
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printf("[%2d] 0x%.8X\n", i, apic_pkg[i]);
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printf("\n");
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for(int i=0; i < (*topo)->total_cores; i++)
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printf("[%2d] 0x%.8X\n", i, apic_core[i]);
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printf("\n");
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for(int i=0; i < (*topo)->total_cores; i++)
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printf("[%2d] 0x%.8X\n", i, apic_smt[i]);*/
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bool ret = build_topo_from_apic(apic_pkg, apic_core, apic_smt, topo);
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// Assumption: If we cant get smt_available, we assume it is equal to smt_supported...
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if(!x2apic_id) (*topo)->smt_supported = (*topo)->smt_available;
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return ret;
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}
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17
src/apic.h
Normal file
17
src/apic.h
Normal file
@@ -0,0 +1,17 @@
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#ifndef __APIC__
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#define __APIC__
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#include <stdbool.h>
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#include "cpuid.h"
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struct apic {
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uint32_t pkg_mask;
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uint32_t pkg_mask_shift;
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uint32_t core_mask;
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uint32_t smt_mask_width;
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uint32_t smt_mask;
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};
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bool get_topology_from_apic(uint32_t cpuid_max_levels, struct topology** topo);
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#endif
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253
src/cpuid.c
253
src/cpuid.c
@@ -1,10 +1,8 @@
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#ifdef _WIN32
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#include <windows.h>
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#include <windows.h>
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#else
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#define _GNU_SOURCE
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#include <sched.h>
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#include <unistd.h>
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#include "udev.h"
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#include "udev.h"
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#include <unistd.h>
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#endif
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#include <stdio.h>
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@@ -16,6 +14,7 @@
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#include "cpuid.h"
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#include "cpuid_asm.h"
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#include "global.h"
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#include "apic.h"
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#define VENDOR_INTEL_STRING "GenuineIntel"
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#define VENDOR_AMD_STRING "AuthenticAMD"
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@@ -75,24 +74,6 @@ struct frequency {
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int64_t max;
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};
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struct apic {
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uint32_t pkg_mask;
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uint32_t pkg_mask_shift;
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uint32_t core_mask;
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uint32_t smt_mask_width;
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uint32_t smt_mask;
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};
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struct topology {
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int64_t total_cores;
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uint32_t physical_cores;
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uint32_t logical_cores;
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uint32_t smt_available; // Number of SMT that is currently enabled
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uint32_t smt_supported; // Number of SMT that CPU supports (equal to smt_available if SMT is enabled)
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uint32_t sockets;
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struct apic* apic;
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};
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void init_cpu_info(struct cpuInfo* cpu) {
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cpu->AVX = false;
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cpu->AVX2 = false;
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@@ -281,230 +262,6 @@ struct cpuInfo* get_cpu_info() {
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return cpu;
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}
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bool bind_to_cpu(int cpu_id) {
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#ifdef _WIN32 // TODO
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return false;
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#else
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cpu_set_t currentCPU;
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CPU_ZERO(¤tCPU);
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CPU_SET(cpu_id, ¤tCPU);
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if (sched_setaffinity (0, sizeof(currentCPU), ¤tCPU) == -1) {
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perror("sched_setaffinity");
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return false;
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}
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return true;
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#endif
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}
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uint32_t get_apic_id(bool x2apic_id) {
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uint32_t eax = 0;
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uint32_t ebx = 0;
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uint32_t ecx = 0;
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uint32_t edx = 0;
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if(x2apic_id) {
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eax = 0x0000000B;
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cpuid(&eax, &ebx, &ecx, &edx);
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return edx;
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}
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else {
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eax = 0x00000001;
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cpuid(&eax, &ebx, &ecx, &edx);
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return (ebx >> 24);
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}
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}
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bool fill_topo_masks_x2apic(struct topology** topo) {
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int32_t level_type;
|
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int32_t level_shift;
|
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|
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int32_t coreplus_smt_mask;
|
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bool level2 = false;
|
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bool level1 = false;
|
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|
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uint32_t eax = 0;
|
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uint32_t ebx = 0;
|
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uint32_t ecx = 0;
|
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uint32_t edx = 0;
|
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uint32_t i = 0;
|
||||
|
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while(true) {
|
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eax = 0x0000000B;
|
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ecx = i;
|
||||
cpuid(&eax, &ebx, &ecx, &edx);
|
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if(ebx == 0) break;
|
||||
|
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level_type = (ecx >> 8) & 0xFF;
|
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level_shift = eax & 0xFFF;
|
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|
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switch(level_type) {
|
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case 1: // SMT
|
||||
(*topo)->apic->smt_mask = ~(0xFFFFFFFF << level_shift);
|
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(*topo)->apic->smt_mask_width = level_shift;
|
||||
(*topo)->smt_supported = ebx & 0xFFFF;
|
||||
level1 = true;
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break;
|
||||
case 2: // Core
|
||||
coreplus_smt_mask = ~(0xFFFFFFFF << level_shift);
|
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(*topo)->apic->pkg_mask_shift = level_shift;
|
||||
(*topo)->apic->pkg_mask = (-1) ^ coreplus_smt_mask;
|
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level2 = true;
|
||||
break;
|
||||
default:
|
||||
printErr("Found invalid level when querying topology: %d", level_type);
|
||||
break;
|
||||
}
|
||||
|
||||
i++; // sublevel to query
|
||||
}
|
||||
|
||||
if (level1 && level2) {
|
||||
(*topo)->apic->core_mask = coreplus_smt_mask ^ (*topo)->apic->smt_mask;
|
||||
}
|
||||
else if (!level2 && level1) {
|
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(*topo)->apic->core_mask = 0;
|
||||
(*topo)->apic->pkg_mask_shift = (*topo)->apic->smt_mask_width;
|
||||
(*topo)->apic->pkg_mask = (-1) ^ (*topo)->apic->smt_mask;
|
||||
}
|
||||
else {
|
||||
printErr("SMT level was not found when querying topology");
|
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return false;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
unsigned char bit_scan_reverse(uint32_t* index, uint64_t mask) {
|
||||
for(uint64_t i = (8 * sizeof(uint64_t)); i > 0; i--) {
|
||||
if((mask & (1LL << (i-1))) != 0) {
|
||||
*index = (uint64_t) (i-1);
|
||||
break;
|
||||
}
|
||||
}
|
||||
return (unsigned char)( mask != 0);
|
||||
}
|
||||
|
||||
uint32_t create_mask(uint32_t num_entries, uint32_t *mask_width) {
|
||||
uint32_t i;
|
||||
uint64_t k;
|
||||
|
||||
// NearestPo2(numEntries) is the nearest power of 2 integer that is not less than numEntries
|
||||
// The most significant bit of (numEntries * 2 -1) matches the above definition
|
||||
|
||||
k = (uint64_t)(num_entries) * 2 -1;
|
||||
|
||||
if (bit_scan_reverse(&i, k) == 0) {
|
||||
if (mask_width) *mask_width = 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (mask_width) *mask_width = i;
|
||||
if (i == 31) return (uint32_t ) -1;
|
||||
|
||||
return (1 << i) -1;
|
||||
}
|
||||
|
||||
bool fill_topo_masks_apic(struct topology** topo) {
|
||||
uint32_t eax = 0x00000001;
|
||||
uint32_t ebx = 0;
|
||||
uint32_t ecx = 0;
|
||||
uint32_t edx = 0;
|
||||
uint32_t core_plus_smt_id_max_cnt;
|
||||
uint32_t core_id_max_cnt;
|
||||
uint32_t smt_id_per_core_max_cnt;
|
||||
uint32_t SMTIDPerCoreMaxCnt;
|
||||
|
||||
cpuid(&eax, &ebx, &ecx, &edx);
|
||||
|
||||
core_plus_smt_id_max_cnt = (ebx >> 16) & 0xFF; // MAL?
|
||||
|
||||
eax = 0x00000004;
|
||||
ecx = 0;
|
||||
cpuid(&eax, &ebx, &ecx, &edx);
|
||||
|
||||
core_id_max_cnt = (eax >> 26) + 1;
|
||||
smt_id_per_core_max_cnt = core_plus_smt_id_max_cnt / core_id_max_cnt;
|
||||
|
||||
(*topo)->apic->smt_mask = create_mask(smt_id_per_core_max_cnt, &((*topo)->apic->smt_mask_width));
|
||||
(*topo)->apic->core_mask = create_mask(core_id_max_cnt,&((*topo)->apic->pkg_mask_shift));
|
||||
(*topo)->apic->pkg_mask_shift += (*topo)->apic->smt_mask_width;
|
||||
(*topo)->apic->core_mask <<= (*topo)->apic->smt_mask_width;
|
||||
(*topo)->apic->pkg_mask = (-1) ^ ((*topo)->apic->core_mask | (*topo)->apic->smt_mask);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
bool build_topo_from_apic(uint32_t* apic_pkg, uint32_t* apic_core, uint32_t* apic_smt, struct topology** topo) {
|
||||
uint32_t sockets[64];
|
||||
uint32_t smt[64];
|
||||
|
||||
memset(sockets, 0, sizeof(uint32_t) * 64);
|
||||
memset(smt, 0, sizeof(uint32_t) * 64);
|
||||
|
||||
for(int i=0; i < (*topo)->total_cores; i++) {
|
||||
sockets[apic_pkg[i]] = 1;
|
||||
smt[apic_smt[i]] = 1;
|
||||
}
|
||||
for(int i=0; i < 64; i++) {
|
||||
if(sockets[i] != 0)
|
||||
(*topo)->sockets++;
|
||||
if(smt[i] != 0)
|
||||
(*topo)->smt_available++;
|
||||
}
|
||||
|
||||
(*topo)->logical_cores = (*topo)->total_cores / (*topo)->sockets;
|
||||
(*topo)->physical_cores = (*topo)->logical_cores / (*topo)->smt_available;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
bool get_topology_from_apic(struct cpuInfo* cpu, struct topology** topo) {
|
||||
uint32_t apic_id;
|
||||
uint32_t* apic_pkg = malloc(sizeof(uint32_t) * (*topo)->total_cores);
|
||||
uint32_t* apic_core = malloc(sizeof(uint32_t) * (*topo)->total_cores);
|
||||
uint32_t* apic_smt = malloc(sizeof(uint32_t) * (*topo)->total_cores);
|
||||
bool x2apic_id = cpu->maxLevels >= 0x0000000B;
|
||||
|
||||
if(x2apic_id) {
|
||||
if(!fill_topo_masks_x2apic(topo))
|
||||
return false;
|
||||
}
|
||||
else {
|
||||
if(!fill_topo_masks_apic(topo))
|
||||
return false;
|
||||
}
|
||||
|
||||
for(int i=0; i < (*topo)->total_cores; i++) {
|
||||
if(!bind_to_cpu(i)) {
|
||||
printErr("Failed binding to CPU %d", i);
|
||||
return false;
|
||||
}
|
||||
apic_id = get_apic_id(x2apic_id);
|
||||
|
||||
apic_pkg[i] = (apic_id & (*topo)->apic->pkg_mask) >> (*topo)->apic->pkg_mask_shift;
|
||||
apic_core[i] = (apic_id & (*topo)->apic->core_mask) >> (*topo)->apic->smt_mask_width;
|
||||
apic_smt[i] = apic_id & (*topo)->apic->smt_mask;
|
||||
}
|
||||
|
||||
/* DEBUG
|
||||
for(int i=0; i < (*topo)->total_cores; i++)
|
||||
printf("[%2d] 0x%.8X\n", i, apic_pkg[i]);
|
||||
printf("\n");
|
||||
for(int i=0; i < (*topo)->total_cores; i++)
|
||||
printf("[%2d] 0x%.8X\n", i, apic_core[i]);
|
||||
printf("\n");
|
||||
for(int i=0; i < (*topo)->total_cores; i++)
|
||||
printf("[%2d] 0x%.8X\n", i, apic_smt[i]);*/
|
||||
|
||||
|
||||
bool ret = build_topo_from_apic(apic_pkg, apic_core, apic_smt, topo);
|
||||
|
||||
// Assumption: If we cant get smt_available, we assume it is equal to smt_supported...
|
||||
if(!x2apic_id) (*topo)->smt_supported = (*topo)->smt_available;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
// Main reference: https://software.intel.com/content/www/us/en/develop/articles/intel-64-architecture-processor-topology-enumeration.html
|
||||
// Very interesting resource: https://wiki.osdev.org/Detecting_CPU_Topology_(80x86)
|
||||
struct topology* get_topology_info(struct cpuInfo* cpu) {
|
||||
@@ -535,7 +292,7 @@ struct topology* get_topology_info(struct cpuInfo* cpu) {
|
||||
switch(cpu->cpu_vendor) {
|
||||
case VENDOR_INTEL:
|
||||
if (cpu->maxLevels >= 0x00000004) {
|
||||
get_topology_from_apic(cpu, &topo);
|
||||
get_topology_from_apic(cpu->maxLevels, &topo);
|
||||
}
|
||||
else {
|
||||
printErr("Can't read topology information from cpuid (needed level is 0x%.8X, max is 0x%.8X)", 0x00000001, cpu->maxLevels);
|
||||
|
||||
11
src/cpuid.h
11
src/cpuid.h
@@ -13,7 +13,16 @@
|
||||
struct cpuInfo;
|
||||
struct frequency;
|
||||
struct cache;
|
||||
struct topology;
|
||||
|
||||
struct topology {
|
||||
int64_t total_cores;
|
||||
uint32_t physical_cores;
|
||||
uint32_t logical_cores;
|
||||
uint32_t smt_available; // Number of SMT that is currently enabled
|
||||
uint32_t smt_supported; // Number of SMT that CPU supports (equal to smt_available if SMT is enabled)
|
||||
uint32_t sockets;
|
||||
struct apic* apic;
|
||||
};
|
||||
|
||||
typedef int32_t VENDOR;
|
||||
|
||||
|
||||
@@ -147,6 +147,13 @@ struct ascii* set_ascii(VENDOR cpuVendor, STYLE style, struct colors* cs) {
|
||||
}
|
||||
art->ascii_chars[1] = '#';
|
||||
|
||||
#ifdef _WIN32
|
||||
strcpy(art->color1_ascii,COL_NONE);
|
||||
strcpy(art->color2_ascii,COL_NONE);
|
||||
strcpy(art->color1_text,COL_NONE);
|
||||
strcpy(art->color2_text,COL_NONE);
|
||||
art->reset[0] = '\0';
|
||||
#else
|
||||
switch(style) {
|
||||
case STYLE_EMPTY:
|
||||
#ifdef _WIN32
|
||||
@@ -200,6 +207,7 @@ struct ascii* set_ascii(VENDOR cpuVendor, STYLE style, struct colors* cs) {
|
||||
printBug("Found invalid style (%d)",style);
|
||||
return NULL;
|
||||
}
|
||||
#endif
|
||||
|
||||
char tmp[NUMBER_OF_LINES*LINE_SIZE];
|
||||
if(cpuVendor == VENDOR_INTEL) strcpy(tmp, INTEL_ASCII);
|
||||
|
||||
Reference in New Issue
Block a user