[v0.96] Dont treat unknown unified cache as a bug, since there are some processors with eDRAM which supports this level, like #41

This commit is contained in:
Dr-Noob
2021-04-07 11:10:45 +02:00
parent c7cc8be712
commit 2879876500

View File

@@ -364,13 +364,12 @@ bool get_cache_topology_amd(struct cpuInfo* cpu, struct topology* topo) {
topo->cach->L3->num_caches = topo->logical_cores / num_sharing_cache; topo->cach->L3->num_caches = topo->logical_cores / num_sharing_cache;
} }
else { else {
printBug("Found unified cache at level %d (expected == 2 or 3)", cache_level); printWarn("Found unknown unified cache at level %d", cache_level);
return false;
} }
break; break;
default: // Unknown Type Cache default: // Unknown cache type
printBug("Unknown Type Cache found at ID %d", i); printBug("Unknown cache type %d with level %d found at i=%d", cache_type, cache_level, i);
return false; return false;
} }
} }
@@ -573,13 +572,12 @@ struct cache* get_cache_info_general(struct cache* cach, uint32_t level) {
cach->L3->exists = true; cach->L3->exists = true;
} }
else { else {
printBug("Found unified cache at level %d (expected == 2 or 3)", cache_level); printWarn("Found unknown unified cache at level %d (size is %d bytes)", cache_level, cache_total_size);
return NULL;
} }
break; break;
default: // Unknown Type Cache default: // Unknown cache type
printBug("Unknown Type Cache found at ID %d", i); printBug("Unknown cache type %d with level %d found at i=%d", cache_type, cache_level, i);
return NULL; return NULL;
} }
} }