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[v1.03] Merge bugfix branch to include Snapd patch

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Dr-Noob
2023-01-17 18:41:12 +01:00
parent ba8bbdd252 f960a97477
commit 2b8a942a98
3 changed files with 21 additions and 3 deletions
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6
src/arm/soc.c
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@@ -517,6 +517,12 @@ bool match_special(char* soc_name, struct system_on_chip* soc) {
return true;
}
// Snapdragon 8 Gen 1 reported as "taro"
if(strcmp(soc_name, "taro") == 0) {
fill_soc(soc, "8 Gen 1", SOC_SNAPD_SM8450, 4);
return true;
}
return false;
}

3
src/arm/socs.h
View File

@@ -252,6 +252,7 @@ enum {
SOC_SNAPD_SM8250,
SOC_SNAPD_SM8250_AB,
SOC_SNAPD_SM8350,
SOC_SNAPD_SM8450,
// APPLE
SOC_APPLE_M1,
SOC_APPLE_M1_PRO,
@@ -289,7 +290,7 @@ inline static VENDOR get_soc_vendor_from_soc(SOC soc) {
else if(soc >= SOC_HISILICON_3620 && soc <= SOC_HISILICON_3690) return SOC_VENDOR_KIRIN;
else if(soc >= SOC_EXYNOS_3475 && soc <= SOC_EXYNOS_880) return SOC_VENDOR_EXYNOS;
else if(soc >= SOC_MTK_MT6893 && soc <= SOC_MTK_MT8783) return SOC_VENDOR_MEDIATEK;
else if(soc >= SOC_SNAPD_QSD8650 && soc <= SOC_SNAPD_SM8350) return SOC_VENDOR_SNAPDRAGON;
else if(soc >= SOC_SNAPD_QSD8650 && soc <= SOC_SNAPD_SM8450) return SOC_VENDOR_SNAPDRAGON;
else if(soc >= SOC_APPLE_M1 && soc <= SOC_APPLE_M2) return SOC_VENDOR_APPLE;
else if(soc >= SOC_ALLWINNER_A10 && soc <= SOC_ALLWINNER_R328) return SOC_VENDOR_ALLWINNER;
return SOC_VENDOR_UNKNOWN;

15
src/arm/uarch.c
View File

@@ -33,7 +33,8 @@ enum {
ISA_ARMv8_2_A,
ISA_ARMv8_3_A,
ISA_ARMv8_4_A,
ISA_ARMv8_5_A
ISA_ARMv8_5_A,
ISA_ARMv9_A
};
enum {
@@ -65,7 +66,10 @@ enum {
UARCH_CORTEX_A76,
UARCH_CORTEX_A77,
UARCH_CORTEX_A78,
UARCH_CORTEX_A510,
UARCH_CORTEX_A710,
UARCH_CORTEX_X1,
UARCH_CORTEX_X2,
UARCH_NEOVERSE_N1,
UARCH_NEOVERSE_E1,
UARCH_SCORPION,
@@ -136,7 +140,10 @@ static const ISA isas_uarch[] = {
[UARCH_CORTEX_A76] = ISA_ARMv8_2_A,
[UARCH_CORTEX_A77] = ISA_ARMv8_2_A,
[UARCH_CORTEX_A78] = ISA_ARMv8_2_A,
[UARCH_CORTEX_A510] = ISA_ARMv9_A,
[UARCH_CORTEX_A710] = ISA_ARMv9_A,
[UARCH_CORTEX_X1] = ISA_ARMv8_2_A,
[UARCH_CORTEX_X2] = ISA_ARMv9_A,
[UARCH_NEOVERSE_N1] = ISA_ARMv8_2_A,
[UARCH_NEOVERSE_E1] = ISA_ARMv8_2_A,
[UARCH_BRAHMA_B15] = ISA_ARMv7_A, // Same as Cortex-A15
@@ -178,7 +185,8 @@ static char* isas_string[] = {
[ISA_ARMv8_2_A] = "ARMv8.2",
[ISA_ARMv8_3_A] = "ARMv8.3",
[ISA_ARMv8_4_A] = "ARMv8.4",
[ISA_ARMv8_5_A] = "ARMv8.5"
[ISA_ARMv8_5_A] = "ARMv8.5",
[ISA_ARMv9_A] = "ARMv9"
};
#define UARCH_START if (false) {}
@@ -248,6 +256,9 @@ struct uarch* get_uarch_from_midr(uint32_t midr, struct cpuInfo* cpu) {
CHECK_UARCH(arch, cpu, 'A', 0xD0E, NA, NA, "Cortex-A76", UARCH_CORTEX_A76, CPU_VENDOR_ARM)
CHECK_UARCH(arch, cpu, 'A', 0xD41, NA, NA, "Cortex-A78", UARCH_CORTEX_A78, CPU_VENDOR_ARM)
CHECK_UARCH(arch, cpu, 'A', 0xD44, NA, NA, "Cortex-X1", UARCH_CORTEX_X1, CPU_VENDOR_ARM)
CHECK_UARCH(arch, cpu, 'A', 0xD46, NA, NA, "Cortex‑A510", UARCH_CORTEX_A510, CPU_VENDOR_ARM)
CHECK_UARCH(arch, cpu, 'A', 0xD47, NA, NA, "Cortex‑A710", UARCH_CORTEX_A710, CPU_VENDOR_ARM)
CHECK_UARCH(arch, cpu, 'A', 0xD48, NA, NA, "Cortex-X2", UARCH_CORTEX_X2, CPU_VENDOR_ARM)
CHECK_UARCH(arch, cpu, 'A', 0xD4A, NA, NA, "Neoverse E1", UARCH_NEOVERSE_E1, CPU_VENDOR_ARM)
CHECK_UARCH(arch, cpu, 'B', 0x00F, NA, NA, "Brahma B15", UARCH_BRAHMA_B15, CPU_VENDOR_BROADCOM)