diff --git a/src/common/cpu.h b/src/common/cpu.h index 1a45100..0db2fbf 100644 --- a/src/common/cpu.h +++ b/src/common/cpu.h @@ -23,6 +23,7 @@ enum { // ARCH_RISCV CPU_VENDOR_RISCV, CPU_VENDOR_SIFIVE, + CPU_VENDOR_THEAD, // OTHERS CPU_VENDOR_UNKNOWN, CPU_VENDOR_INVALID diff --git a/src/common/printer.c b/src/common/printer.c index 7e1248a..c778626 100644 --- a/src/common/printer.c +++ b/src/common/printer.c @@ -934,7 +934,7 @@ bool print_cpufetch_riscv(struct cpuInfo* cpu, STYLE s, struct color** cs, struc char* uarch = get_str_uarch(cpu); char* manufacturing_process = get_str_process(cpu->soc); char* soc_name = get_soc_name(cpu->soc); - char* features = get_str_features(cpu); + char* extensions = get_str_extensions(cpu); char* max_frequency = get_str_freq(cpu->freq); char* n_cores = get_str_topology(cpu, cpu->topo); diff --git a/src/riscv/riscv.c b/src/riscv/riscv.c index f314e4b..3a3a78b 100644 --- a/src/riscv/riscv.c +++ b/src/riscv/riscv.c @@ -56,7 +56,7 @@ char* get_str_topology(struct cpuInfo* cpu, struct topology* topo) { return string; } -char* get_str_features(struct cpuInfo* cpu) { +char* get_str_extensions(struct cpuInfo* cpu) { return NULL; } diff --git a/src/riscv/riscv.h b/src/riscv/riscv.h index e644077..b9729fb 100644 --- a/src/riscv/riscv.h +++ b/src/riscv/riscv.h @@ -5,7 +5,7 @@ struct cpuInfo* get_cpu_info(void); char* get_str_topology(struct cpuInfo* cpu, struct topology* topo); -char* get_str_features(struct cpuInfo* cpu); +char* get_str_extensions(struct cpuInfo* cpu); void print_debug(struct cpuInfo* cpu); #endif diff --git a/src/riscv/uarch.c b/src/riscv/uarch.c index ed68ebf..0821993 100644 --- a/src/riscv/uarch.c +++ b/src/riscv/uarch.c @@ -16,7 +16,11 @@ struct uarch { enum { UARCH_UNKNOWN, // SIFIVE - UARCH_U74MC + UARCH_U54, + UARCH_U74, + // THEAD + UARCH_C906, + UARCH_C910 }; #define UARCH_START if (false) {} @@ -31,6 +35,9 @@ void fill_uarch(struct uarch* arch, struct cpuInfo* cpu, char* str, MICROARCH u, strcpy(arch->uarch_str, str); } +// https://elixir.bootlin.com/linux/latest/source/Documentation/devicetree/bindings/riscv/cpus.yaml +// SiFive: https://www.sifive.com/risc-v-core-ip +// T-Head: https://www.t-head.cn/product/c906 struct uarch* get_uarch_from_cpuinfo_str(char* cpuinfo_str, struct cpuInfo* cpu) { struct uarch* arch = emalloc(sizeof(struct uarch)); if(cpuinfo_str == NULL) { @@ -39,8 +46,23 @@ struct uarch* get_uarch_from_cpuinfo_str(char* cpuinfo_str, struct cpuInfo* cpu) return arch; } + // U74/U74-MC: + // SiFive says that U74-MC is "Multicore: four U74 cores and one S76 core" while + // U74 is "High performance Linux-capable processor". It's like U74-MC is somehow a small SoC containing + // the U74 and the S76? Then U74-MC is not a microarchitecture per se... UARCH_START - CHECK_UARCH(arch, cpu, cpuinfo_str, "sifive,u74-mc", "U74-MC", UARCH_U74MC, CPU_VENDOR_SIFIVE) + CHECK_UARCH(arch, cpu, cpuinfo_str, "sifive,bullet0", "U74", UARCH_U74, CPU_VENDOR_SIFIVE) // bullet0 is present in U740, which has U74 + // CHECK_UARCH(arch, cpu, cpuinfo_str, "sifive,e5", "XXXXXX", UARCH_U74, CPU_VENDOR_SIFIVE) + // CHECK_UARCH(arch, cpu, cpuinfo_str, "sifive,e7", "XXXXXX", UARCH_U74, CPU_VENDOR_SIFIVE) + // CHECK_UARCH(arch, cpu, cpuinfo_str, "sifive,e71", "XXXXXX", UARCH_U74, CPU_VENDOR_SIFIVE) + // CHECK_UARCH(arch, cpu, cpuinfo_str, "sifive,rocket0", "XXXXXX", UARCH_U74, CPU_VENDOR_SIFIVE) + // CHECK_UARCH(arch, cpu, cpuinfo_str, "sifive,u5", "XXXXXX", UARCH_U74, CPU_VENDOR_SIFIVE) + CHECK_UARCH(arch, cpu, cpuinfo_str, "sifive,u54", "U54", UARCH_U54, CPU_VENDOR_SIFIVE) + // CHECK_UARCH(arch, cpu, cpuinfo_str, "sifive,u7", "XXXXXX", UARCH_U74, CPU_VENDOR_SIFIVE) + CHECK_UARCH(arch, cpu, cpuinfo_str, "sifive,u74", "U74", UARCH_U74, CPU_VENDOR_SIFIVE) + CHECK_UARCH(arch, cpu, cpuinfo_str, "sifive,u74-mc", "U74", UARCH_U74, CPU_VENDOR_SIFIVE) + CHECK_UARCH(arch, cpu, cpuinfo_str, "thead,c906", "T-Head C906", UARCH_C906, CPU_VENDOR_THEAD) + CHECK_UARCH(arch, cpu, cpuinfo_str, "thead,c910", "T-Head C910", UARCH_C910, CPU_VENDOR_THEAD) UARCH_END return arch;