From bcf8b8171d0ff3b5c6cf836cbc9f64dd9625cede Mon Sep 17 00:00:00 2001 From: Dr-Noob Date: Sun, 17 Sep 2023 23:14:49 +0100 Subject: [PATCH 1/5] [v1.04][RISCV] Temporary fix to parse multi-letter extensions --- src/riscv/riscv.c | 37 ++++++++++++++++++++++++++++++++++--- 1 file changed, 34 insertions(+), 3 deletions(-) diff --git a/src/riscv/riscv.c b/src/riscv/riscv.c index a069916..6d7bf83 100644 --- a/src/riscv/riscv.c +++ b/src/riscv/riscv.c @@ -28,6 +28,27 @@ int64_t get_peak_performance(struct cpuInfo* cpu) { return flops; } +// Returns the length of the multi-letter +// extension, or -1 if an error occurs +int parse_multi_letter_extension(struct extensions* ext, char* e) { + if(*e != '_') return -1; + char* multi_letter_extension_end = strstr(e+1, "_"); + if(multi_letter_extension_end == NULL) { + // This is the last extension, find the end + // of the string + multi_letter_extension_end = e + strlen(e); + } + + int multi_letter_extension_len = multi_letter_extension_end-(e+1); + + // TODO: Parse extension and fill ext struct + char* multi_letter_extension = emalloc(multi_letter_extension_len); + strncpy(multi_letter_extension, e+1, multi_letter_extension_len); + printWarn("Not parsed multi-letter extension: %s", multi_letter_extension); + + return multi_letter_extension_len; +} + struct extensions* get_extensions_from_str(char* str) { struct extensions* ext = emalloc(sizeof(struct extensions)); ext->mask = 0; @@ -42,7 +63,7 @@ struct extensions* get_extensions_from_str(char* str) { memset(ext->str, 0, len); strncpy(ext->str, str, sizeof(char) * len); - // Code inspired in Linux kernel: + // Code inspired in Linux kernel (riscv_fill_hwcap): // https://elixir.bootlin.com/linux/v6.2.10/source/arch/riscv/kernel/cpufeature.c char* isa = str; if (!strncmp(isa, "rv32", 4)) @@ -55,8 +76,18 @@ struct extensions* get_extensions_from_str(char* str) { } for(char* e = isa; *e != '\0'; e++) { - int n = *e - 'a'; - ext->mask |= 1UL << n; + if(*e == '_') { + // Multi-letter extension + int multi_letter_extension_len = parse_multi_letter_extension(ext, e); + if(multi_letter_extension_len == -1) { + return ext; + } + e += multi_letter_extension_len; + } + else { + int n = *e - 'a'; + ext->mask |= 1UL << n; + } } return ext; From 4fa3dc2076289ee9a40d626dd090cc51e8781639 Mon Sep 17 00:00:00 2001 From: Dr-Noob Date: Mon, 18 Sep 2023 08:20:32 +0100 Subject: [PATCH 2/5] [v1.04][RISCV] First support for parsing multi-letter extensions --- src/riscv/riscv.c | 26 ++++++++++++++++++++++++-- src/riscv/riscv.h | 30 ++++++++++++++++++++++++++++++ 2 files changed, 54 insertions(+), 2 deletions(-) diff --git a/src/riscv/riscv.c b/src/riscv/riscv.c index 6d7bf83..e166f4c 100644 --- a/src/riscv/riscv.c +++ b/src/riscv/riscv.c @@ -9,6 +9,11 @@ #include "uarch.h" #include "soc.h" +#define SET_ISA_EXT_MAP(name, bit) \ + if(strncmp(multi_letter_extension, name, \ + multi_letter_extension_len) == 0) \ + ext->mask |= 1UL << bit; \ + struct frequency* get_frequency_info(uint32_t core) { struct frequency* freq = emalloc(sizeof(struct frequency)); @@ -41,10 +46,27 @@ int parse_multi_letter_extension(struct extensions* ext, char* e) { int multi_letter_extension_len = multi_letter_extension_end-(e+1); - // TODO: Parse extension and fill ext struct char* multi_letter_extension = emalloc(multi_letter_extension_len); strncpy(multi_letter_extension, e+1, multi_letter_extension_len); - printWarn("Not parsed multi-letter extension: %s", multi_letter_extension); + // TODO: Add more extensions + // https://en.wikipedia.org/wiki/RISC-V + SET_ISA_EXT_MAP("smaia", RISCV_ISA_EXT_SMAIA); + SET_ISA_EXT_MAP("ssaia", RISCV_ISA_EXT_SSAIA); + SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF); + SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC); + SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL); + SET_ISA_EXT_MAP("svnapot", RISCV_ISA_EXT_SVNAPOT); + SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT); + SET_ISA_EXT_MAP("zba", RISCV_ISA_EXT_ZBA); + SET_ISA_EXT_MAP("zbb", RISCV_ISA_EXT_ZBB); + SET_ISA_EXT_MAP("zbs", RISCV_ISA_EXT_ZBS); + SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM); + SET_ISA_EXT_MAP("zicboz", RISCV_ISA_EXT_ZICBOZ); + SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE); + else { + printBug("parse_multi_letter_extension: Unknown multi-letter extension: %s", multi_letter_extension); + return -1; + } return multi_letter_extension_len; } diff --git a/src/riscv/riscv.h b/src/riscv/riscv.h index fcbdff1..8ec8119 100644 --- a/src/riscv/riscv.h +++ b/src/riscv/riscv.h @@ -29,6 +29,36 @@ static const struct extension extension_list[] = { { 's' - 'a', "(S) Supervisor-level Instructions" } }; +#define RISCV_ISA_EXT_MAX 64 +#define RISCV_ISA_EXT_NAME_LEN_MAX 32 +#define RISCV_ISA_EXT_BASE 26 + +// This enum represent the logical ID for multi-letter RISC-V ISA extensions. +// The logical ID should start from RISCV_ISA_EXT_BASE and must not exceed +// RISCV_ISA_EXT_MAX. +#define RISCV_ISA_EXT_BASE 26 + +#define RISCV_ISA_EXT_SSCOFPMF 26 +#define RISCV_ISA_EXT_SSTC 27 +#define RISCV_ISA_EXT_SVINVAL 28 +#define RISCV_ISA_EXT_SVPBMT 29 +#define RISCV_ISA_EXT_ZBB 30 +#define RISCV_ISA_EXT_ZICBOM 31 +#define RISCV_ISA_EXT_ZIHINTPAUSE 32 +#define RISCV_ISA_EXT_SVNAPOT 33 +#define RISCV_ISA_EXT_ZICBOZ 34 +#define RISCV_ISA_EXT_SMAIA 35 +#define RISCV_ISA_EXT_SSAIA 36 +#define RISCV_ISA_EXT_ZBA 37 +#define RISCV_ISA_EXT_ZBS 38 +#define RISCV_ISA_EXT_ZICNTR 39 +#define RISCV_ISA_EXT_ZICSR 40 +#define RISCV_ISA_EXT_ZIFENCEI 41 +#define RISCV_ISA_EXT_ZIHPM 42 + +#define RISCV_ISA_EXT_MAX 64 +#define RISCV_ISA_EXT_NAME_LEN_MAX 32 + struct cpuInfo* get_cpu_info(void); char* get_str_topology(struct cpuInfo* cpu, struct topology* topo); char* get_str_extensions(struct cpuInfo* cpu); From a12defaf4b6c5a62dbe83fa55c4a11aeefef7dbf Mon Sep 17 00:00:00 2001 From: Dr-Noob Date: Tue, 19 Sep 2023 08:18:13 +0100 Subject: [PATCH 3/5] [v1.04][RISCV] Define to enum --- src/riscv/riscv.h | 47 +++++++++++++++++++++++------------------------ 1 file changed, 23 insertions(+), 24 deletions(-) diff --git a/src/riscv/riscv.h b/src/riscv/riscv.h index 8ec8119..fc9f746 100644 --- a/src/riscv/riscv.h +++ b/src/riscv/riscv.h @@ -29,35 +29,34 @@ static const struct extension extension_list[] = { { 's' - 'a', "(S) Supervisor-level Instructions" } }; -#define RISCV_ISA_EXT_MAX 64 +#define RISCV_ISA_EXT_MAX 64 #define RISCV_ISA_EXT_NAME_LEN_MAX 32 -#define RISCV_ISA_EXT_BASE 26 +#define RISCV_ISA_EXT_BASE 26 // This enum represent the logical ID for multi-letter RISC-V ISA extensions. // The logical ID should start from RISCV_ISA_EXT_BASE and must not exceed // RISCV_ISA_EXT_MAX. -#define RISCV_ISA_EXT_BASE 26 - -#define RISCV_ISA_EXT_SSCOFPMF 26 -#define RISCV_ISA_EXT_SSTC 27 -#define RISCV_ISA_EXT_SVINVAL 28 -#define RISCV_ISA_EXT_SVPBMT 29 -#define RISCV_ISA_EXT_ZBB 30 -#define RISCV_ISA_EXT_ZICBOM 31 -#define RISCV_ISA_EXT_ZIHINTPAUSE 32 -#define RISCV_ISA_EXT_SVNAPOT 33 -#define RISCV_ISA_EXT_ZICBOZ 34 -#define RISCV_ISA_EXT_SMAIA 35 -#define RISCV_ISA_EXT_SSAIA 36 -#define RISCV_ISA_EXT_ZBA 37 -#define RISCV_ISA_EXT_ZBS 38 -#define RISCV_ISA_EXT_ZICNTR 39 -#define RISCV_ISA_EXT_ZICSR 40 -#define RISCV_ISA_EXT_ZIFENCEI 41 -#define RISCV_ISA_EXT_ZIHPM 42 - -#define RISCV_ISA_EXT_MAX 64 -#define RISCV_ISA_EXT_NAME_LEN_MAX 32 +enum riscv_isa_ext_id { + RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE, + RISCV_ISA_EXT_SSTC, + RISCV_ISA_EXT_SVINVAL, + RISCV_ISA_EXT_SVPBMT, + RISCV_ISA_EXT_ZBB, + RISCV_ISA_EXT_ZICBOM, + RISCV_ISA_EXT_ZIHINTPAUSE, + RISCV_ISA_EXT_SVNAPOT, + RISCV_ISA_EXT_ZICBOZ, + RISCV_ISA_EXT_SMAIA, + RISCV_ISA_EXT_SSAIA, + RISCV_ISA_EXT_ZBA, + RISCV_ISA_EXT_ZBS, + RISCV_ISA_EXT_ZICNTR, + RISCV_ISA_EXT_ZICSR, + RISCV_ISA_EXT_ZIFENCEI, + RISCV_ISA_EXT_ZIHPM, + RISCV_ISA_EXT_ID_MAX +}; +static_assert(RISCV_ISA_EXT_ID_MAX <= RISCV_ISA_EXT_MAX); struct cpuInfo* get_cpu_info(void); char* get_str_topology(struct cpuInfo* cpu, struct topology* topo); From bd3c66395d19808bcc75fe4ca17f2b434561abdb Mon Sep 17 00:00:00 2001 From: Dr-Noob Date: Fri, 22 Sep 2023 21:39:17 +0100 Subject: [PATCH 4/5] [v1.04][RISCV] Add multi-letter extensions to list --- src/riscv/riscv.c | 31 +++++++++++----------- src/riscv/riscv.h | 67 +++++++++++++++++++++++++++++------------------ 2 files changed, 58 insertions(+), 40 deletions(-) diff --git a/src/riscv/riscv.c b/src/riscv/riscv.c index e166f4c..a09af21 100644 --- a/src/riscv/riscv.c +++ b/src/riscv/riscv.c @@ -48,21 +48,22 @@ int parse_multi_letter_extension(struct extensions* ext, char* e) { char* multi_letter_extension = emalloc(multi_letter_extension_len); strncpy(multi_letter_extension, e+1, multi_letter_extension_len); - // TODO: Add more extensions - // https://en.wikipedia.org/wiki/RISC-V - SET_ISA_EXT_MAP("smaia", RISCV_ISA_EXT_SMAIA); - SET_ISA_EXT_MAP("ssaia", RISCV_ISA_EXT_SSAIA); - SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF); - SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC); - SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL); - SET_ISA_EXT_MAP("svnapot", RISCV_ISA_EXT_SVNAPOT); - SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT); - SET_ISA_EXT_MAP("zba", RISCV_ISA_EXT_ZBA); - SET_ISA_EXT_MAP("zbb", RISCV_ISA_EXT_ZBB); - SET_ISA_EXT_MAP("zbs", RISCV_ISA_EXT_ZBS); - SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM); - SET_ISA_EXT_MAP("zicboz", RISCV_ISA_EXT_ZICBOZ); - SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE); + // This should be up-to-date with + // https://elixir.bootlin.com/linux/latest/source/arch/riscv/kernel/cpufeature.c + // which should represent the list of extensions available in real chips + SET_ISA_EXT_MAP("smaia", RISCV_ISA_EXT_SMAIA) + SET_ISA_EXT_MAP("ssaia", RISCV_ISA_EXT_SSAIA) + SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF) + SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC) + SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL) + SET_ISA_EXT_MAP("svnapot", RISCV_ISA_EXT_SVNAPOT) + SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT) + SET_ISA_EXT_MAP("zba", RISCV_ISA_EXT_ZBA) + SET_ISA_EXT_MAP("zbb", RISCV_ISA_EXT_ZBB) + SET_ISA_EXT_MAP("zbs", RISCV_ISA_EXT_ZBS) + SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM) + SET_ISA_EXT_MAP("zicboz", RISCV_ISA_EXT_ZICBOZ) + SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE) else { printBug("parse_multi_letter_extension: Unknown multi-letter extension: %s", multi_letter_extension); return -1; diff --git a/src/riscv/riscv.h b/src/riscv/riscv.h index fc9f746..d6bc9b2 100644 --- a/src/riscv/riscv.h +++ b/src/riscv/riscv.h @@ -8,34 +8,12 @@ struct extension { char* str; }; -// https://en.wikichip.org/wiki/risc-v/standard_extensions -// Included all except for G -static const struct extension extension_list[] = { - { 'i' - 'a', "(I) Integer Instruction Set" }, - { 'm' - 'a', "(M) Integer Multiplication and Division" }, - { 'a' - 'a', "(A) Atomic Instructions" }, - { 'f' - 'a', "(F) Single-Precision Floating-Point" }, - { 'd' - 'a', "(D) Double-Precision Floating-Point" }, - { 'q' - 'a', "(Q) Quad-Precision Floating-Point" }, - { 'l' - 'a', "(L) Decimal Floating-Point" }, - { 'c' - 'a', "(C) Compressed Instructions" }, - { 'b' - 'a', "(B) Double-Precision Floating-Point" }, - { 'j' - 'a', "(J) Dynamically Translated Languages" }, - { 't' - 'a', "(T) Transactional Memory" }, - { 'p' - 'a', "(P) Packed-SIMD Instructions" }, - { 'v' - 'a', "(V) Vector Operations" }, - { 'n' - 'a', "(N) User-Level Interrupts" }, - { 'h' - 'a', "(H) Hypervisor" }, - { 's' - 'a', "(S) Supervisor-level Instructions" } -}; - -#define RISCV_ISA_EXT_MAX 64 #define RISCV_ISA_EXT_NAME_LEN_MAX 32 #define RISCV_ISA_EXT_BASE 26 +// https://elixir.bootlin.com/linux/latest/source/arch/riscv/include/asm/hwcap.h // This enum represent the logical ID for multi-letter RISC-V ISA extensions. -// The logical ID should start from RISCV_ISA_EXT_BASE and must not exceed -// RISCV_ISA_EXT_MAX. +// The logical ID should start from RISCV_ISA_EXT_BASE enum riscv_isa_ext_id { RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE, RISCV_ISA_EXT_SSTC, @@ -56,7 +34,46 @@ enum riscv_isa_ext_id { RISCV_ISA_EXT_ZIHPM, RISCV_ISA_EXT_ID_MAX }; -static_assert(RISCV_ISA_EXT_ID_MAX <= RISCV_ISA_EXT_MAX); + +// https://five-embeddev.com/riscv-isa-manual/latest/preface.html#preface +// https://en.wikichip.org/wiki/risc-v/standard_extensions +// Included all except for G +static const struct extension extension_list[] = { + { 'i' - 'a', "(I) Integer Instruction Set" }, + { 'm' - 'a', "(M) Integer Multiplication and Division" }, + { 'a' - 'a', "(A) Atomic Instructions" }, + { 'f' - 'a', "(F) Single-Precision Floating-Point" }, + { 'd' - 'a', "(D) Double-Precision Floating-Point" }, + { 'q' - 'a', "(Q) Quad-Precision Floating-Point" }, + { 'l' - 'a', "(L) Decimal Floating-Point" }, + { 'c' - 'a', "(C) Compressed Instructions" }, + { 'b' - 'a', "(B) Double-Precision Floating-Point" }, + { 'j' - 'a', "(J) Dynamically Translated Languages" }, + { 't' - 'a', "(T) Transactional Memory" }, + { 'p' - 'a', "(P) Packed-SIMD Instructions" }, + { 'v' - 'a', "(V) Vector Operations" }, + { 'n' - 'a', "(N) User-Level Interrupts" }, + { 'h' - 'a', "(H) Hypervisor" }, + { 's' - 'a', "(S) Supervisor-level Instructions" }, + // multi-letter extensions + { RISCV_ISA_EXT_SSCOFPMF, "(Sscofpmf) Count OverFlow and Privilege Mode Filtering" }, + { RISCV_ISA_EXT_SSTC, "(Sstc) S and VS level Time Compare" }, + { RISCV_ISA_EXT_SVINVAL, "(Svinval) Fast TLB Invalidation" }, + { RISCV_ISA_EXT_SVPBMT, "(Svpbmt) Page-based Memory Types" }, + { RISCV_ISA_EXT_ZBB, "(Zbb) Basic bit-manipulation" }, + { RISCV_ISA_EXT_ZICBOM, "(Zicbom) Cache Block Management Operations" }, + { RISCV_ISA_EXT_ZIHINTPAUSE, "(Zihintpause) Pause Hint" }, + { RISCV_ISA_EXT_SVNAPOT, "(Svnapot) Naturally Aligned Power of Two Pages" }, + { RISCV_ISA_EXT_ZICBOZ, "(Zicboz) Cache Block Zero Operations" }, + { RISCV_ISA_EXT_SMAIA, "(Smaia) Advanced Interrupt Architecture" }, + { RISCV_ISA_EXT_SSAIA, "(Ssaia) Advanced Interrupt Architecture" }, + { RISCV_ISA_EXT_ZBA, "(Zba) Address Generation" }, + { RISCV_ISA_EXT_ZBS, "(Zbs) Single-bit Instructions" }, + { RISCV_ISA_EXT_ZICNTR, "(Zicntr) Base Counters and Timers" }, + { RISCV_ISA_EXT_ZICSR, "(Zicsr) Control and Status Register" }, + { RISCV_ISA_EXT_ZIFENCEI, "(Zifencei) Instruction-Fetch Fence" }, + { RISCV_ISA_EXT_ZIHPM, "(Zihpm) Hardware Performance Counters" } +}; struct cpuInfo* get_cpu_info(void); char* get_str_topology(struct cpuInfo* cpu, struct topology* topo); From 6c69ab0a0096c5cd6b6c1434b01143fed6269580 Mon Sep 17 00:00:00 2001 From: Dr-Noob Date: Sun, 24 Sep 2023 11:59:43 +0100 Subject: [PATCH 5/5] [v1.04][RISCV] Extend extension mask to 64 bit. Fix SET_ISA_EXT_MAP else condition. Fix print_ascii_riscv iters computation --- src/common/cpu.h | 2 +- src/common/printer.c | 16 +++++++--------- src/riscv/riscv.c | 30 ++++++++++++++++++------------ 3 files changed, 26 insertions(+), 22 deletions(-) diff --git a/src/common/cpu.h b/src/common/cpu.h index 0b4d701..f294c41 100644 --- a/src/common/cpu.h +++ b/src/common/cpu.h @@ -123,7 +123,7 @@ struct features { struct extensions { char* str; - uint32_t mask; + uint64_t mask; }; struct cpuInfo { diff --git a/src/common/printer.c b/src/common/printer.c index 0948333..f09e97c 100644 --- a/src/common/printer.c +++ b/src/common/printer.c @@ -917,16 +917,14 @@ bool print_cpufetch_arm(struct cpuInfo* cpu, STYLE s, struct color** cs, struct #endif #ifdef ARCH_RISCV -// https://stackoverflow.com/questions/109023/count-the-number-of-set-bits-in-a-32-bit-integer -int number_of_bits(uint32_t i) { - i = i - ((i >> 1) & 0x55555555); // add pairs of bits - i = (i & 0x33333333) + ((i >> 2) & 0x33333333); // quads - i = (i + (i >> 4)) & 0x0F0F0F0F; // groups of 8 - - return (i * 0x01010101) >> 24; // horizontal sum of bytes +// https://stackoverflow.com/a/2709523 +uint64_t number_of_bits(uint64_t i) { + i = i - ((i >> 1) & 0x5555555555555555); + i = (i & 0x3333333333333333) + ((i >> 2) & 0x3333333333333333); + return (((i + (i >> 4)) & 0xF0F0F0F0F0F0F0F) * 0x101010101010101) >> 56; } -void print_ascii_riscv(struct ascii* art, uint32_t la, int32_t termw, const char** attribute_fields, uint32_t extensions_mask) { +void print_ascii_riscv(struct ascii* art, uint32_t la, int32_t termw, const char** attribute_fields, uint64_t extensions_mask) { struct ascii_logo* logo = art->art; int attr_to_print = 0; int attr_type; @@ -940,7 +938,7 @@ void print_ascii_riscv(struct ascii* art, uint32_t la, int32_t termw, const char int32_t space_up = ((int)logo->height - (int)(art->n_attributes_set + num_extensions))/2; int32_t space_down = (int)logo->height - (int)(art->n_attributes_set + num_extensions) - (int)space_up; uint32_t logo_pos = 0; - int32_t iters = max(logo->height, art->n_attributes_set); + int32_t iters = max(logo->height, art->n_attributes_set + num_extensions); struct line_buffer* lbuf = emalloc(sizeof(struct line_buffer)); lbuf->buf = emalloc(sizeof(char) * LINE_BUFFER_SIZE); diff --git a/src/riscv/riscv.c b/src/riscv/riscv.c index a09af21..6c1624d 100644 --- a/src/riscv/riscv.c +++ b/src/riscv/riscv.c @@ -9,10 +9,12 @@ #include "uarch.h" #include "soc.h" -#define SET_ISA_EXT_MAP(name, bit) \ - if(strncmp(multi_letter_extension, name, \ - multi_letter_extension_len) == 0) \ - ext->mask |= 1UL << bit; \ +#define SET_ISA_EXT_MAP(name, bit) \ + if(strncmp(multi_letter_extension, name, \ + multi_letter_extension_len) == 0) { \ + ext->mask |= 1UL << bit; \ + maskset = true; \ + } \ struct frequency* get_frequency_info(uint32_t core) { struct frequency* freq = emalloc(sizeof(struct frequency)); @@ -45,26 +47,30 @@ int parse_multi_letter_extension(struct extensions* ext, char* e) { } int multi_letter_extension_len = multi_letter_extension_end-(e+1); - + bool maskset = false; char* multi_letter_extension = emalloc(multi_letter_extension_len); strncpy(multi_letter_extension, e+1, multi_letter_extension_len); // This should be up-to-date with // https://elixir.bootlin.com/linux/latest/source/arch/riscv/kernel/cpufeature.c // which should represent the list of extensions available in real chips - SET_ISA_EXT_MAP("smaia", RISCV_ISA_EXT_SMAIA) - SET_ISA_EXT_MAP("ssaia", RISCV_ISA_EXT_SSAIA) SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF) SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC) SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL) - SET_ISA_EXT_MAP("svnapot", RISCV_ISA_EXT_SVNAPOT) SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT) - SET_ISA_EXT_MAP("zba", RISCV_ISA_EXT_ZBA) SET_ISA_EXT_MAP("zbb", RISCV_ISA_EXT_ZBB) - SET_ISA_EXT_MAP("zbs", RISCV_ISA_EXT_ZBS) SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM) - SET_ISA_EXT_MAP("zicboz", RISCV_ISA_EXT_ZICBOZ) SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE) - else { + SET_ISA_EXT_MAP("svnapot", RISCV_ISA_EXT_SVNAPOT) + SET_ISA_EXT_MAP("zicboz", RISCV_ISA_EXT_ZICBOZ) + SET_ISA_EXT_MAP("smaia", RISCV_ISA_EXT_SMAIA) + SET_ISA_EXT_MAP("ssaia", RISCV_ISA_EXT_SSAIA) + SET_ISA_EXT_MAP("zba", RISCV_ISA_EXT_ZBA) + SET_ISA_EXT_MAP("zbs", RISCV_ISA_EXT_ZBS) + SET_ISA_EXT_MAP("zicntr", RISCV_ISA_EXT_ZICNTR) + SET_ISA_EXT_MAP("zicsr", RISCV_ISA_EXT_ZICSR) + SET_ISA_EXT_MAP("zifencei", RISCV_ISA_EXT_ZIFENCEI) + SET_ISA_EXT_MAP("zihpm", RISCV_ISA_EXT_ZIHPM) + if(!maskset) { printBug("parse_multi_letter_extension: Unknown multi-letter extension: %s", multi_letter_extension); return -1; }