mirror of
https://github.com/Dr-Noob/cpufetch.git
synced 2026-03-25 07:50:40 +01:00
Add code to detect CPU microarchitecture (Intel only, at the moment)
This commit is contained in:
Dr-Noob
4
Makefile
4
Makefile
@@ -4,8 +4,8 @@ CXXFLAGS=-Wall -Wextra -Werror -pedantic -fstack-protector-all -pedantic -std=c9
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SANITY_FLAGS=-Wfloat-equal -Wshadow -Wpointer-arith -Wstrict-overflow=5 -Wformat=2
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SANITY_FLAGS=-Wfloat-equal -Wshadow -Wpointer-arith -Wstrict-overflow=5 -Wformat=2
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SRC_DIR=src/
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SRC_DIR=src/
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SOURCE=$(SRC_DIR)main.c $(SRC_DIR)cpuid.c $(SRC_DIR)apic.c $(SRC_DIR)cpuid_asm.c $(SRC_DIR)printer.c $(SRC_DIR)args.c $(SRC_DIR)global.c
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SOURCE=$(SRC_DIR)main.c $(SRC_DIR)cpuid.c $(SRC_DIR)apic.c $(SRC_DIR)cpuid_asm.c $(SRC_DIR)printer.c $(SRC_DIR)args.c $(SRC_DIR)global.c $(SRC_DIR)uarch.c
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HEADERS=$(SRC_DIR)cpuid.h $(SRC_DIR)apic.h $(SRC_DIR)cpuid_asm.h $(SRC_DIR)printer.h $(SRC_DIR)ascii.h $(SRC_DIR)args.h $(SRC_DIR)global.h
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HEADERS=$(SRC_DIR)cpuid.h $(SRC_DIR)apic.h $(SRC_DIR)cpuid_asm.h $(SRC_DIR)printer.h $(SRC_DIR)ascii.h $(SRC_DIR)args.h $(SRC_DIR)global.h $(SRC_DIR)uarch.h
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ifneq ($(OS),Windows_NT)
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ifneq ($(OS),Windows_NT)
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SOURCE += $(SRC_DIR)udev.c
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SOURCE += $(SRC_DIR)udev.c
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20
src/cpuid.c
20
src/cpuid.c
@@ -15,6 +15,7 @@
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#include "cpuid_asm.h"
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#include "cpuid_asm.h"
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#include "global.h"
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#include "global.h"
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#include "apic.h"
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#include "apic.h"
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#include "uarch.h"
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#define VENDOR_INTEL_STRING "GenuineIntel"
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#define VENDOR_INTEL_STRING "GenuineIntel"
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#define VENDOR_AMD_STRING "AuthenticAMD"
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#define VENDOR_AMD_STRING "AuthenticAMD"
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@@ -165,6 +166,23 @@ char* get_str_cpu_name_internal() {
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return name;
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return name;
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}
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}
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struct uarch* get_cpu_uarch() {
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uint32_t eax = 0x00000001;
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uint32_t ebx = 0;
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uint32_t ecx = 0;
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uint32_t edx = 0;
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cpuid(&eax, &ebx, &ecx, &edx);
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uint32_t stepping = eax & 0xF;
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uint32_t model = (eax >> 4) & 0xF;
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uint32_t emodel = (eax >> 16) & 0xF;
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uint32_t family = (eax >> 8) & 0xF;
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uint32_t efamily = (eax >> 20) & 0xFF;
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return get_uarch_from_cpuid(efamily, family, emodel, model, (int)stepping);
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}
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struct cpuInfo* get_cpu_info() {
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struct cpuInfo* get_cpu_info() {
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struct cpuInfo* cpu = malloc(sizeof(struct cpuInfo));
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struct cpuInfo* cpu = malloc(sizeof(struct cpuInfo));
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init_cpu_info(cpu);
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init_cpu_info(cpu);
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@@ -258,6 +276,8 @@ struct cpuInfo* get_cpu_info() {
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sprintf(cpu->cpu_name,"Unknown");
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sprintf(cpu->cpu_name,"Unknown");
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printWarn("Can't read cpu name from cpuid (needed extended level is 0x%.8X, max is 0x%.8X)", 0x80000004, cpu->maxExtendedLevels);
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printWarn("Can't read cpu name from cpuid (needed extended level is 0x%.8X, max is 0x%.8X)", 0x80000004, cpu->maxExtendedLevels);
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}
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}
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cpu->arch = get_cpu_uarch(cpu);
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return cpu;
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return cpu;
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}
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}
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@@ -37,6 +37,8 @@ struct cpuInfo {
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uint32_t maxLevels;
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uint32_t maxLevels;
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// Max cpuids extended levels
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// Max cpuids extended levels
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uint32_t maxExtendedLevels;
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uint32_t maxExtendedLevels;
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struct uarch* arch;
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};
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};
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struct cach {
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struct cach {
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200
src/uarch.c
Normal file
200
src/uarch.c
Normal file
@@ -0,0 +1,200 @@
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#include <stdbool.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include "uarch.h"
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/*
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* - Intel Microcode Revision Guidance (MRG):
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* https://www.intel.com/content/dam/www/public/us/en/documents/corporate-information/SA00270-microcode-update-guidance.pdf
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* - cpuid codes are based on Todd Allen's cpuid program
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* http://www.etallen.com/cpuid.html
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*/
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typedef uint32_t MICROARCH;
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// No stepping
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#define NS 0
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// Unknown manufacturing process
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#define UNK -1
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#define UARCH_UNKNOWN 0x000
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#define UARCH_P5 0x001
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#define UARCH_P6 0x002
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#define UARCH_DOTHAN 0x003
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#define UARCH_YONAH 0x004
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#define UARCH_MEROM 0x005
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#define UARCH_PENYR 0x006
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#define UARCH_NEHALEM 0x007
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#define UARCH_WESTMERE 0x008
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#define UARCH_BONNELL 0x009
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#define UARCH_SALTWELL 0x010
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#define UARCH_SANDY_BRIDGE 0x011
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#define UARCH_SILVERMONT 0x012
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#define UARCH_IVY_BRIDGE 0x013
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#define UARCH_HASWELL 0x014
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#define UARCH_BROADWELL 0x015
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#define UARCH_AIRMONT 0x016
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#define UARCH_KABY_LAKE 0x017
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#define UARCH_SKYLAKE 0x018
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#define UARCH_CASCADE_LAKE 0x019
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#define UARCH_COOPER_LAKE 0x020
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#define UARCH_KNIGHTS_LANDING 0x021
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#define UARCH_KNIGHTS_MILL 0x022
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#define UARCH_GOLDMONT 0x023
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#define UARCH_PALM_COVE 0x024
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#define UARCH_SUNNY_COVE 0x025
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#define UARCH_GOLDMONT_PLUS 0x026
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#define UARCH_TREMONT 0x027
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#define UARCH_WILLOW_COVE 0x028
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#define UARCH_COFFE_LAKE 0x029
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#define UARCH_ITANIUM 0x030
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#define UARCH_KNIGHTS_FERRY 0x031
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#define UARCH_KNIGHTS_CORNER 0x032
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#define UARCH_WILLAMETTE 0x033
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#define UARCH_NORTHWOOD 0x034
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#define UARCH_PRESCOTT 0x035
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#define UARCH_CEDAR_MILL 0x036
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#define UARCH_ITANIUM2 0x037
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struct uarch {
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MICROARCH uarch;
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char* uarch_str;
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int32_t process; // measured in nanometers
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};
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#define UARCH_START if (false) {}
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#define CHECK_UARCH(arch, ef_, f_, em_, m_, s_, str, uarch, process) \
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else if (ef_ == ef && f_ == f && em_ == em && m_ == m && (s_ == NS || s_ == s)) fill_uarch(arch, str, uarch, process);
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#define UARCH_END else { arch->uarch = UARCH_UNKNOWN; }
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void fill_uarch(struct uarch* arch, char* str, MICROARCH u, uint32_t process) {
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arch->uarch_str = malloc(sizeof(char) * strlen(str));
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strcpy(arch->uarch_str, str);
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arch->uarch = u;
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arch->process= process;
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}
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// inspired in Todd Allen's decode_uarch_intel
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struct uarch* get_uarch_from_cpuid(uint32_t ef, uint32_t f, uint32_t em, uint32_t m, int s) {
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struct uarch* arch = malloc(sizeof(struct uarch));
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// EF: Extended Family //
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// F: Family //
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// EM: Extended Model //
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// M: Model //
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// S: Stepping //
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// ----------------------------------------------------------------------------- //
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// EF F EM M S //
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UARCH_START
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CHECK_UARCH(arch, 0, 5, 0, 0, NS, "P5", UARCH_P5, 800)
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CHECK_UARCH(arch, 0, 5, 0, 1, NS, "P5", UARCH_P5, 800)
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CHECK_UARCH(arch, 0, 5, 0, 2, NS, "P5", UARCH_P5, UNK)
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CHECK_UARCH(arch, 0, 5, 0, 3, NS, "P5", UARCH_P5, 600)
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CHECK_UARCH(arch, 0, 5, 0, 4, NS, "P5 MMX", UARCH_P5, UNK)
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CHECK_UARCH(arch, 0, 5, 0, 7, NS, "P5 MMX", UARCH_P5, UNK)
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CHECK_UARCH(arch, 0, 5, 0, 8, NS, "P5 MMX", UARCH_P5, 250)
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CHECK_UARCH(arch, 0, 5, 0, 9, NS, "P5 MMX", UARCH_P5, UNK)
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CHECK_UARCH(arch, 0, 6, 0, 0, NS, "P6 Pentium II", UARCH_P6, UNK)
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CHECK_UARCH(arch, 0, 6, 0, 1, NS, "P6 Pentium II", UARCH_P6, UNK) // process depends on core
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CHECK_UARCH(arch, 0, 6, 0, 2, NS, "P6 Pentium II", UARCH_P6, UNK)
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CHECK_UARCH(arch, 0, 6, 0, 3, NS, "P6 Pentium II", UARCH_P6, 350)
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CHECK_UARCH(arch, 0, 6, 0, 4, NS, "P6 Pentium II", UARCH_P6, UNK)
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CHECK_UARCH(arch, 0, 6, 0, 5, NS, "P6 Pentium II", UARCH_P6, 250)
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CHECK_UARCH(arch, 0, 6, 0, 6, NS, "P6 Pentium II", UARCH_P6, UNK)
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CHECK_UARCH(arch, 0, 6, 0, 7, NS, "P6 Pentium III", UARCH_P6, 250)
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CHECK_UARCH(arch, 0, 6, 0, 8, NS, "P6 Pentium III", UARCH_P6, 180)
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CHECK_UARCH(arch, 0, 6, 0, 9, NS, "P6 Pentium M", UARCH_P6, 130)
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CHECK_UARCH(arch, 0, 6, 0, 10, NS, "P6 Pentium III", UARCH_P6, 180)
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CHECK_UARCH(arch, 0, 6, 0, 11, NS, "P6 Pentium III", UARCH_P6, 130)
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CHECK_UARCH(arch, 0, 6, 0, 13, NS, "Dothan", UARCH_DOTHAN, UNK) // process depends on core
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CHECK_UARCH(arch, 0, 6, 0, 14, NS, "Yonah", UARCH_YONAH, 65)
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CHECK_UARCH(arch, 0, 6, 0, 15, NS, "Merom", UARCH_MEROM, 65)
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CHECK_UARCH(arch, 0, 6, 1, 5, NS, "Dothan", UARCH_DOTHAN, 90)
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CHECK_UARCH(arch, 0, 6, 1, 6, NS, "Merom", UARCH_MEROM, 65)
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CHECK_UARCH(arch, 0, 6, 1, 7, NS, "Penryn", UARCH_PENYR, 45)
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CHECK_UARCH(arch, 0, 6, 1, 10, NS, "Nehalem", UARCH_NEHALEM, 45)
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CHECK_UARCH(arch, 0, 6, 1, 12, NS, "Bonnell", UARCH_BONNELL, 45)
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CHECK_UARCH(arch, 0, 6, 1, 13, NS, "Penryn", UARCH_PENYR, 45)
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CHECK_UARCH(arch, 0, 6, 1, 14, NS, "Nehalem", UARCH_NEHALEM, 45)
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CHECK_UARCH(arch, 0, 6, 1, 15, NS, "Nehalem", UARCH_NEHALEM, 45)
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CHECK_UARCH(arch, 0, 6, 2, 5, NS, "Westmere", UARCH_WESTMERE, 32)
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CHECK_UARCH(arch, 0, 6, 2 , 6, NS, "Bonnell", UARCH_BONNELL, 45)
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CHECK_UARCH(arch, 0, 6, 2, 7, NS, "Saltwell", UARCH_SALTWELL, 32)
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CHECK_UARCH(arch, 0, 6, 2, 10, NS, "Sandy Bridge", UARCH_SANDY_BRIDGE, 32)
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CHECK_UARCH(arch, 0, 6, 2, 12, NS, "Westmere", UARCH_WESTMERE, 32)
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CHECK_UARCH(arch, 0, 6, 2, 13, NS, "Sandy Bridge", UARCH_SANDY_BRIDGE, 32)
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CHECK_UARCH(arch, 0, 6, 2, 14, NS, "Nehalem", UARCH_NEHALEM, 45)
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CHECK_UARCH(arch, 0, 6, 2, 15, NS, "Westmere", UARCH_WESTMERE, 32)
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CHECK_UARCH(arch, 0, 6, 3, 5, NS, "Saltwell", UARCH_SALTWELL, 14)
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CHECK_UARCH(arch, 0, 6, 3, 6, NS, "Saltwell", UARCH_SALTWELL, 32)
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CHECK_UARCH(arch, 0, 6, 3, 7, NS, "Silvermont", UARCH_SILVERMONT, 22)
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CHECK_UARCH(arch, 0, 6, 3, 10, NS, "Ivy Bridge", UARCH_IVY_BRIDGE, 22)
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CHECK_UARCH(arch, 0, 6, 3, 12, NS, "Haswell", UARCH_HASWELL, 22)
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CHECK_UARCH(arch, 0, 6, 3, 13, NS, "Broadwell", UARCH_BROADWELL, 14)
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CHECK_UARCH(arch, 0, 6, 3, 14, NS, "Ivy Bridge", UARCH_IVY_BRIDGE, 22)
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CHECK_UARCH(arch, 0, 6, 3, 15, NS, "Haswell", UARCH_HASWELL, 22)
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CHECK_UARCH(arch, 0, 6, 4, 5, NS, "Haswell", UARCH_HASWELL, 22)
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CHECK_UARCH(arch, 0, 6, 4, 6, NS, "Haswell", UARCH_HASWELL, 22)
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CHECK_UARCH(arch, 0, 6, 4, 7, NS, "Broadwell", UARCH_BROADWELL, 14)
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CHECK_UARCH(arch, 0, 6, 4, 10, NS, "Silvermont", UARCH_SILVERMONT, 22) // no docs, but /proc/cpuinfo seen in wild
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CHECK_UARCH(arch, 0, 6, 4, 12, NS, "Airmont", UARCH_AIRMONT, 14)
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CHECK_UARCH(arch, 0, 6, 4, 13, NS, "Silvermont", UARCH_SILVERMONT, 22)
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CHECK_UARCH(arch, 0, 6, 4, 14, 8, "Kaby Lake", UARCH_KABY_LAKE, 14)
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CHECK_UARCH(arch, 0, 6, 4, 14, NS, "Skylake", UARCH_SKYLAKE, 14)
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CHECK_UARCH(arch, 0, 6, 4, 15, NS, "Broadwell", UARCH_BROADWELL, 14)
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CHECK_UARCH(arch, 0, 6, 5, 5, 6, "Cascade Lake", UARCH_CASCADE_LAKE, 14) // no docs, but example from Greg Stewart
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CHECK_UARCH(arch, 0, 6, 5, 5, 7, "Cascade Lake", UARCH_CASCADE_LAKE, 14)
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CHECK_UARCH(arch, 0, 6, 5, 5, 10, "Cooper Lake", UARCH_COOPER_LAKE, 14)
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CHECK_UARCH(arch, 0, 6, 5, 5, NS, "Skylake", UARCH_SKYLAKE, 14)
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CHECK_UARCH(arch, 0, 6, 5, 6, NS, "Broadwell", UARCH_BROADWELL, 14)
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CHECK_UARCH(arch, 0, 6, 5, 7, NS, "Knights Landing", UARCH_KNIGHTS_LANDING, 14)
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CHECK_UARCH(arch, 0, 6, 5, 10, NS, "Silvermont", UARCH_SILVERMONT, 22) // no spec update; only MSR_CPUID_table* so far
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CHECK_UARCH(arch, 0, 6, 5, 12, NS, "Goldmont", UARCH_GOLDMONT, 14)
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CHECK_UARCH(arch, 0, 6, 5, 13, NS, "Silvermont", UARCH_SILVERMONT, 22) // no spec update; only MSR_CPUID_table* so far
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CHECK_UARCH(arch, 0, 6, 5, 14, 8, "Kaby Lake", UARCH_KABY_LAKE, 14)
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CHECK_UARCH(arch, 0, 6, 5, 14, NS, "Skylake", UARCH_SKYLAKE, 14)
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CHECK_UARCH(arch, 0, 6, 5, 15, NS, "Goldmont", UARCH_GOLDMONT, 14)
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CHECK_UARCH(arch, 0, 6, 6, 6, NS, "Palm Cove", UARCH_PALM_COVE, 10) // no spec update; only MSR_CPUID_table* so far
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CHECK_UARCH(arch, 0, 6, 6, 10, NS, "Sunny Cove", UARCH_SUNNY_COVE, 10) // no spec update; only MSR_CPUID_table* so far
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CHECK_UARCH(arch, 0, 6, 6, 12, NS, "Sunny Cove", UARCH_SUNNY_COVE, 10) // no spec update; only MSR_CPUID_table* so far
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CHECK_UARCH(arch, 0, 6, 7, 5, NS, "Airmont", UARCH_AIRMONT, 14) // no spec update; whispers & rumors
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CHECK_UARCH(arch, 0, 6, 7, 10, NS, "Goldmont Plus", UARCH_GOLDMONT_PLUS, 14)
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CHECK_UARCH(arch, 0, 6, 7, 13, NS, "Sunny Cove", UARCH_SUNNY_COVE, 10) // no spec update; only MSR_CPUID_table* so far
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CHECK_UARCH(arch, 0, 6, 7, 14, NS, "Sunny Cove", UARCH_SUNNY_COVE, 10)
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CHECK_UARCH(arch, 0, 6, 8, 5, NS, "Knights Mill", UARCH_KNIGHTS_MILL, 14) // no spec update; only MSR_CPUID_table* so far
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CHECK_UARCH(arch, 0, 6, 8, 6, NS, "Tremont", UARCH_TREMONT, 10) // LX*
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CHECK_UARCH(arch, 0, 6, 8, 10, NS, "Tremont", UARCH_TREMONT, 10) // no spec update; only geekbench.com example
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CHECK_UARCH(arch, 0, 6, 8, 12, NS, "Willow Cove", UARCH_WILLOW_COVE, 10) // found only on en.wikichip.org
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CHECK_UARCH(arch, 0, 6, 8, 13, NS, "Willow Cove", UARCH_WILLOW_COVE, 10) // LX*
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CHECK_UARCH(arch, 0, 6, 8, 14, NS, "Kaby Lake", UARCH_KABY_LAKE, 14)
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CHECK_UARCH(arch, 0, 6, 9, 6, NS, "Tremont", UARCH_TREMONT, 10) // LX*
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CHECK_UARCH(arch, 0, 6, 9, 12, NS, "Tremont", UARCH_TREMONT, 10) // LX*
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CHECK_UARCH(arch, 0, 6, 9, 13, NS, "Sunny Cove", UARCH_SUNNY_COVE, 10) // LX*
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CHECK_UARCH(arch, 0, 6, 9, 14, 9, "Kaby Lake", UARCH_KABY_LAKE, 14)
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CHECK_UARCH(arch, 0, 6, 9, 14, 10, "Coffee Lake", UARCH_COFFE_LAKE, 14)
|
||||||
|
CHECK_UARCH(arch, 0, 6, 9, 14, 11, "Coffee Lake", UARCH_COFFE_LAKE, 14)
|
||||||
|
CHECK_UARCH(arch, 0, 6, 9, 14, 12, "Coffee Lake", UARCH_COFFE_LAKE, 14)
|
||||||
|
CHECK_UARCH(arch, 0, 6, 9, 14, 13, "Coffee Lake", UARCH_COFFE_LAKE, 14)
|
||||||
|
CHECK_UARCH(arch, 0, 6, 10, 5, NS, "Kaby Lake", UARCH_KABY_LAKE, 14) // LX*
|
||||||
|
CHECK_UARCH(arch, 0, 6, 10, 6, NS, "Kaby Lake", UARCH_KABY_LAKE, 14) // no spec update; only instlatx64 example
|
||||||
|
CHECK_UARCH(arch, 0, 11, 0, 0, NS, "Knights Ferry", UARCH_KNIGHTS_FERRY, 45) // found only on en.wikichip.org
|
||||||
|
CHECK_UARCH(arch, 0, 11, 0, 1, NS, "Knights Corner", UARCH_KNIGHTS_CORNER, 22)
|
||||||
|
CHECK_UARCH(arch, 0, 15, 0, 0, NS, "Willamette", UARCH_WILLAMETTE, 180)
|
||||||
|
CHECK_UARCH(arch, 0, 15, 0, 1, NS, "Willamette", UARCH_WILLAMETTE, 180)
|
||||||
|
CHECK_UARCH(arch, 0, 15, 0, 2, NS, "Northwood", UARCH_NORTHWOOD, 130)
|
||||||
|
CHECK_UARCH(arch, 0, 15, 0, 3, NS, "Prescott", UARCH_PRESCOTT, 90)
|
||||||
|
CHECK_UARCH(arch, 0, 15, 0, 4, NS, "Prescott", UARCH_PRESCOTT, 90)
|
||||||
|
CHECK_UARCH(arch, 0, 15, 0, 6, NS, "Cedar Mill", UARCH_CEDAR_MILL, 65)
|
||||||
|
CHECK_UARCH(arch, 1, 15, 0, 0, NS, "Itanium2", UARCH_ITANIUM2, 180)
|
||||||
|
CHECK_UARCH(arch, 1, 15, 0, 1, NS, "Itanium2", UARCH_ITANIUM2, 130)
|
||||||
|
CHECK_UARCH(arch, 1, 15, 0, 2, NS, "Itanium2", UARCH_ITANIUM2, 130)
|
||||||
|
UARCH_END
|
||||||
|
|
||||||
|
// DEBUG
|
||||||
|
//printf("M=0x%.8X EM=0x%.8X F=0x%.8X EF=0x%.8X S=0x%.8X\n", m, em, f, ef, s);
|
||||||
|
//printf("Your arch: %s\n", arch->uarch_str);
|
||||||
|
|
||||||
|
return arch;
|
||||||
|
}
|
||||||
10
src/uarch.h
Normal file
10
src/uarch.h
Normal file
@@ -0,0 +1,10 @@
|
|||||||
|
#ifndef __UARCH__
|
||||||
|
#define __UARCH__
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
struct uarch;
|
||||||
|
|
||||||
|
struct uarch* get_uarch_from_cpuid(uint32_t ef, uint32_t f, uint32_t em, uint32_t m, int s);
|
||||||
|
|
||||||
|
#endif
|
||||||
Reference in New Issue
Block a user