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Fix #21 and #22: Obtain the number of caches of every level instead of guessing them. It is done by fetching cache topology from apic. It works, but it needs a big refactoring. Moreover, it currently works only on Intel CPUs, so this breaks the cache in AMD.

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Dr-Noob
2020-08-29 21:50:51 +02:00
parent d8dad29a57
commit 69cc08759a
6 changed files with 206 additions and 103 deletions
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8
src/printer.c
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@@ -323,10 +323,10 @@ bool print_cpufetch(struct cpuInfo* cpu, struct cache* cach, struct frequency* f
char* fma = get_str_fma(cpu);
char* aes = get_str_aes(cpu);
char* sha = get_str_sha(cpu);
char* l1i = get_str_l1i(cach, topo);
char* l1d = get_str_l1d(cach, topo);
char* l2 = get_str_l2(cach, topo);
char* l3 = get_str_l3(cach, topo);
char* l1i = get_str_l1i(topo->cach);
char* l1d = get_str_l1d(topo->cach);
char* l2 = get_str_l2(topo->cach);
char* l3 = get_str_l3(topo->cach);
char* pp = get_str_peak_performance(cpu,topo,get_freq(freq));
setAttribute(art,ATTRIBUTE_NAME,cpu_name);