thelilfrog/cpufetch
1
0
Fork 0
mirror of https://github.com/Dr-Noob/cpufetch.git synced 2026-03-25 07:50:40 +01:00
Code Issues Packages Projects Releases Wiki Activity

[v1.04][RISCV] Extend extension mask to 64 bit. Fix SET_ISA_EXT_MAP else condition. Fix print_ascii_riscv iters computation

Browse Source
This commit is contained in:
Dr-Noob
2023-09-24 11:59:43 +01:00
parent bd3c66395d
commit 6c69ab0a00
3 changed files with 26 additions and 22 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/common/cpu.h
View File

@@ -123,7 +123,7 @@ struct features {
struct extensions { struct extensions {
char* str; char* str;
uint32_t mask; uint64_t mask;
}; };
struct cpuInfo { struct cpuInfo {

16
src/common/printer.c
View File

@@ -917,16 +917,14 @@ bool print_cpufetch_arm(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
#endif #endif
#ifdef ARCH_RISCV #ifdef ARCH_RISCV
// https://stackoverflow.com/questions/109023/count-the-number-of-set-bits-in-a-32-bit-integer // https://stackoverflow.com/a/2709523
int number_of_bits(uint32_t i) { uint64_t number_of_bits(uint64_t i) {
i = i - ((i >> 1) & 0x55555555); // add pairs of bits i = i - ((i >> 1) & 0x5555555555555555);
i = (i & 0x33333333) + ((i >> 2) & 0x33333333); // quads i = (i & 0x3333333333333333) + ((i >> 2) & 0x3333333333333333);
i = (i + (i >> 4)) & 0x0F0F0F0F; // groups of 8 return (((i + (i >> 4)) & 0xF0F0F0F0F0F0F0F) * 0x101010101010101) >> 56;
return (i * 0x01010101) >> 24; // horizontal sum of bytes
} }
void print_ascii_riscv(struct ascii* art, uint32_t la, int32_t termw, const char** attribute_fields, uint32_t extensions_mask) { void print_ascii_riscv(struct ascii* art, uint32_t la, int32_t termw, const char** attribute_fields, uint64_t extensions_mask) {
struct ascii_logo* logo = art->art; struct ascii_logo* logo = art->art;
int attr_to_print = 0; int attr_to_print = 0;
int attr_type; int attr_type;
@@ -940,7 +938,7 @@ void print_ascii_riscv(struct ascii* art, uint32_t la, int32_t termw, const char
int32_t space_up = ((int)logo->height - (int)(art->n_attributes_set + num_extensions))/2; int32_t space_up = ((int)logo->height - (int)(art->n_attributes_set + num_extensions))/2;
int32_t space_down = (int)logo->height - (int)(art->n_attributes_set + num_extensions) - (int)space_up; int32_t space_down = (int)logo->height - (int)(art->n_attributes_set + num_extensions) - (int)space_up;
uint32_t logo_pos = 0; uint32_t logo_pos = 0;
int32_t iters = max(logo->height, art->n_attributes_set); int32_t iters = max(logo->height, art->n_attributes_set + num_extensions);
struct line_buffer* lbuf = emalloc(sizeof(struct line_buffer)); struct line_buffer* lbuf = emalloc(sizeof(struct line_buffer));
lbuf->buf = emalloc(sizeof(char) * LINE_BUFFER_SIZE); lbuf->buf = emalloc(sizeof(char) * LINE_BUFFER_SIZE);

24
src/riscv/riscv.c
View File

@@ -11,8 +11,10 @@
#define SET_ISA_EXT_MAP(name, bit) \ #define SET_ISA_EXT_MAP(name, bit) \
if(strncmp(multi_letter_extension, name, \ if(strncmp(multi_letter_extension, name, \
multi_letter_extension_len) == 0) \ multi_letter_extension_len) == 0) { \
ext->mask |= 1UL << bit; \ ext->mask |= 1UL << bit; \
maskset = true; \
} \
struct frequency* get_frequency_info(uint32_t core) { struct frequency* get_frequency_info(uint32_t core) {
struct frequency* freq = emalloc(sizeof(struct frequency)); struct frequency* freq = emalloc(sizeof(struct frequency));
@@ -45,26 +47,30 @@ int parse_multi_letter_extension(struct extensions* ext, char* e) {
} }
int multi_letter_extension_len = multi_letter_extension_end-(e+1); int multi_letter_extension_len = multi_letter_extension_end-(e+1);
bool maskset = false;
char* multi_letter_extension = emalloc(multi_letter_extension_len); char* multi_letter_extension = emalloc(multi_letter_extension_len);
strncpy(multi_letter_extension, e+1, multi_letter_extension_len); strncpy(multi_letter_extension, e+1, multi_letter_extension_len);
// This should be up-to-date with // This should be up-to-date with
// https://elixir.bootlin.com/linux/latest/source/arch/riscv/kernel/cpufeature.c // https://elixir.bootlin.com/linux/latest/source/arch/riscv/kernel/cpufeature.c
// which should represent the list of extensions available in real chips // which should represent the list of extensions available in real chips
SET_ISA_EXT_MAP("smaia", RISCV_ISA_EXT_SMAIA)
SET_ISA_EXT_MAP("ssaia", RISCV_ISA_EXT_SSAIA)
SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF) SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF)
SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC) SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC)
SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL) SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL)
SET_ISA_EXT_MAP("svnapot", RISCV_ISA_EXT_SVNAPOT)
SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT) SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT)
SET_ISA_EXT_MAP("zba", RISCV_ISA_EXT_ZBA)
SET_ISA_EXT_MAP("zbb", RISCV_ISA_EXT_ZBB) SET_ISA_EXT_MAP("zbb", RISCV_ISA_EXT_ZBB)
SET_ISA_EXT_MAP("zbs", RISCV_ISA_EXT_ZBS)
SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM) SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM)
SET_ISA_EXT_MAP("zicboz", RISCV_ISA_EXT_ZICBOZ)
SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE) SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE)
else { SET_ISA_EXT_MAP("svnapot", RISCV_ISA_EXT_SVNAPOT)
SET_ISA_EXT_MAP("zicboz", RISCV_ISA_EXT_ZICBOZ)
SET_ISA_EXT_MAP("smaia", RISCV_ISA_EXT_SMAIA)
SET_ISA_EXT_MAP("ssaia", RISCV_ISA_EXT_SSAIA)
SET_ISA_EXT_MAP("zba", RISCV_ISA_EXT_ZBA)
SET_ISA_EXT_MAP("zbs", RISCV_ISA_EXT_ZBS)
SET_ISA_EXT_MAP("zicntr", RISCV_ISA_EXT_ZICNTR)
SET_ISA_EXT_MAP("zicsr", RISCV_ISA_EXT_ZICSR)
SET_ISA_EXT_MAP("zifencei", RISCV_ISA_EXT_ZIFENCEI)
SET_ISA_EXT_MAP("zihpm", RISCV_ISA_EXT_ZIHPM)
if(!maskset) {
printBug("parse_multi_letter_extension: Unknown multi-letter extension: %s", multi_letter_extension); printBug("parse_multi_letter_extension: Unknown multi-letter extension: %s", multi_letter_extension);
return -1; return -1;
} }