mirror of
https://github.com/Dr-Noob/cpufetch.git
synced 2026-03-25 07:50:40 +01:00
Code refactoring. Forgot to add verbose option to help
This commit is contained in:
Dr-Noob
148
src/apic.c
148
src/apic.c
@@ -83,7 +83,7 @@ bool bind_to_cpu(int cpu_id) {
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#endif
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}
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bool fill_topo_masks_apic(struct topology** topo) {
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bool fill_topo_masks_apic(struct topology* topo) {
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uint32_t eax = 0x00000001;
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uint32_t ebx = 0;
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uint32_t ecx = 0;
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@@ -103,16 +103,16 @@ bool fill_topo_masks_apic(struct topology** topo) {
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core_id_max_cnt = (eax >> 26) + 1;
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smt_id_per_core_max_cnt = core_plus_smt_id_max_cnt / core_id_max_cnt;
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(*topo)->apic->smt_mask = create_mask(smt_id_per_core_max_cnt, &((*topo)->apic->smt_mask_width));
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(*topo)->apic->core_mask = create_mask(core_id_max_cnt,&((*topo)->apic->pkg_mask_shift));
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(*topo)->apic->pkg_mask_shift += (*topo)->apic->smt_mask_width;
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(*topo)->apic->core_mask <<= (*topo)->apic->smt_mask_width;
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(*topo)->apic->pkg_mask = (-1) ^ ((*topo)->apic->core_mask | (*topo)->apic->smt_mask);
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topo->apic->smt_mask = create_mask(smt_id_per_core_max_cnt, &(topo->apic->smt_mask_width));
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topo->apic->core_mask = create_mask(core_id_max_cnt,&(topo->apic->pkg_mask_shift));
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topo->apic->pkg_mask_shift += topo->apic->smt_mask_width;
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topo->apic->core_mask <<= topo->apic->smt_mask_width;
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topo->apic->pkg_mask = (-1) ^ (topo->apic->core_mask | topo->apic->smt_mask);
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return true;
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}
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bool fill_topo_masks_x2apic(struct topology** topo) {
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bool fill_topo_masks_x2apic(struct topology* topo) {
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int32_t level_type;
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int32_t level_shift;
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@@ -137,15 +137,15 @@ bool fill_topo_masks_x2apic(struct topology** topo) {
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switch(level_type) {
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case 1: // SMT
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(*topo)->apic->smt_mask = ~(0xFFFFFFFF << level_shift);
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(*topo)->apic->smt_mask_width = level_shift;
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(*topo)->smt_supported = ebx & 0xFFFF;
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topo->apic->smt_mask = ~(0xFFFFFFFF << level_shift);
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topo->apic->smt_mask_width = level_shift;
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topo->smt_supported = ebx & 0xFFFF;
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level1 = true;
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break;
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case 2: // Core
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coreplus_smt_mask = ~(0xFFFFFFFF << level_shift);
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(*topo)->apic->pkg_mask_shift = level_shift;
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(*topo)->apic->pkg_mask = (-1) ^ coreplus_smt_mask;
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topo->apic->pkg_mask_shift = level_shift;
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topo->apic->pkg_mask = (-1) ^ coreplus_smt_mask;
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level2 = true;
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break;
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default:
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@@ -157,12 +157,12 @@ bool fill_topo_masks_x2apic(struct topology** topo) {
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}
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if (level1 && level2) {
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(*topo)->apic->core_mask = coreplus_smt_mask ^ (*topo)->apic->smt_mask;
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topo->apic->core_mask = coreplus_smt_mask ^ topo->apic->smt_mask;
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}
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else if (!level2 && level1) {
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(*topo)->apic->core_mask = 0;
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(*topo)->apic->pkg_mask_shift = (*topo)->apic->smt_mask_width;
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(*topo)->apic->pkg_mask = (-1) ^ (*topo)->apic->smt_mask;
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topo->apic->core_mask = 0;
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topo->apic->pkg_mask_shift = topo->apic->smt_mask_width;
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topo->apic->pkg_mask = (-1) ^ topo->apic->smt_mask;
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}
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else {
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printErr("SMT level was not found when querying topology");
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@@ -172,28 +172,23 @@ bool fill_topo_masks_x2apic(struct topology** topo) {
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return true;
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}
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bool arr_contains_value(uint32_t* arr, uint32_t value, uint32_t arr_size) {
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for(uint32_t i=0; i < arr_size; i++) {
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if(arr[i] == value) return true;
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}
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return false;
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}
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uint32_t max_apic_id_size(uint32_t** cache_id_apic, struct topology** topo) {
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// Not a very elegant solution. The width should always be as long
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// as the number of cores, but in the case of Xeon Phi KNL it is not
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uint32_t max_apic_id_size(uint32_t** cache_id_apic, struct topology* topo) {
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uint32_t max = 0;
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for(int i=0; i < (*topo)->cach->max_cache_level; i++) {
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for(int j=0; j < (*topo)->total_cores; j++) {
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for(int i=0; i < topo->cach->max_cache_level; i++) {
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for(int j=0; j < topo->total_cores; j++) {
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if(cache_id_apic[j][i] > max) max = cache_id_apic[j][i];
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}
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}
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max++;
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if(max > (*topo)->total_cores) return max;
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return (*topo)->total_cores;
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if(max > topo->total_cores) return max;
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return topo->total_cores;
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}
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bool build_topo_from_apic(uint32_t* apic_pkg, uint32_t* apic_smt, uint32_t** cache_id_apic, struct topology** topo) {
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bool build_topo_from_apic(uint32_t* apic_pkg, uint32_t* apic_smt, uint32_t** cache_id_apic, struct topology* topo) {
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uint32_t size = max_apic_id_size(cache_id_apic, topo);
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uint32_t* sockets = malloc(sizeof(uint32_t) * size);
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uint32_t* smt = malloc(sizeof(uint32_t) * size);
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@@ -204,32 +199,34 @@ bool build_topo_from_apic(uint32_t* apic_pkg, uint32_t* apic_smt, uint32_t** cac
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memset(smt, 0, sizeof(uint32_t) * size);
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memset(apic_id, 0, sizeof(uint32_t) * size);
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for(int i=0; i < (*topo)->total_cores; i++) {
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// System topology
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for(int i=0; i < topo->total_cores; i++) {
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sockets[apic_pkg[i]] = 1;
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smt[apic_smt[i]] = 1;
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}
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for(int i=0; i < (*topo)->total_cores; i++) {
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for(int i=0; i < topo->total_cores; i++) {
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if(sockets[i] != 0)
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(*topo)->sockets++;
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topo->sockets++;
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if(smt[i] != 0)
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(*topo)->smt_available++;
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topo->smt_available++;
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}
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(*topo)->logical_cores = (*topo)->total_cores / (*topo)->sockets;
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(*topo)->physical_cores = (*topo)->logical_cores / (*topo)->smt_available;
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topo->logical_cores = topo->total_cores / topo->sockets;
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topo->physical_cores = topo->logical_cores / topo->smt_available;
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for(int i=0; i < (*topo)->cach->max_cache_level; i++) {
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// Cache topology
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for(int i=0; i < topo->cach->max_cache_level; i++) {
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num_caches = 0;
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memset(apic_id, 0, sizeof(uint32_t) * size);
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for(int c=0; c < (*topo)->total_cores; c++) {
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for(int c=0; c < topo->total_cores; c++) {
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apic_id[cache_id_apic[c][i]]++;
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}
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for(uint32_t c=0; c < size; c++) {
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if(apic_id[c] > 0) num_caches++;
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}
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(*topo)->cach->cach_arr[i]->num_caches = num_caches;
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topo->cach->cach_arr[i]->num_caches = num_caches;
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}
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free(sockets);
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@@ -239,41 +236,39 @@ bool build_topo_from_apic(uint32_t* apic_pkg, uint32_t* apic_smt, uint32_t** cac
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return true;
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}
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bool get_cache_topology_from_apic(struct topology** topo) {
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void get_cache_topology_from_apic(struct topology* topo) {
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uint32_t eax = 0x00000004;
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uint32_t ebx = 0;
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uint32_t ecx = 0;
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uint32_t edx = 0;
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for(int i=0; i < (*topo)->cach->max_cache_level; i++) {
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for(int i=0; i < topo->cach->max_cache_level; i++) {
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eax = 0x00000004;
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ecx = i;
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cpuid(&eax, &ebx, &ecx, &edx);
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uint32_t SMTMaxCntPerEachCache = ((eax >> 14) & 0x7FF) + 1;
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uint32_t EachCacheMaskWidth_targ_subleaf;
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(*topo)->apic->cache_select_mask[i] = create_mask(SMTMaxCntPerEachCache,&EachCacheMaskWidth_targ_subleaf);
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uint32_t dummy;
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topo->apic->cache_select_mask[i] = create_mask(SMTMaxCntPerEachCache,&dummy);
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}
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}
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return true;
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}
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bool get_topology_from_apic(struct cpuInfo* cpu, struct topology** topo) {
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bool get_topology_from_apic(struct cpuInfo* cpu, struct topology* topo) {
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uint32_t apic_id;
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uint32_t* apic_pkg = malloc(sizeof(uint32_t) * (*topo)->total_cores);
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uint32_t* apic_core = malloc(sizeof(uint32_t) * (*topo)->total_cores);
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uint32_t* apic_smt = malloc(sizeof(uint32_t) * (*topo)->total_cores);
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uint32_t** cache_smt_id_apic = malloc(sizeof(uint32_t*) * (*topo)->total_cores);
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uint32_t** cache_id_apic = malloc(sizeof(uint32_t*) * (*topo)->total_cores);
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uint32_t* apic_pkg = malloc(sizeof(uint32_t) * topo->total_cores);
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uint32_t* apic_core = malloc(sizeof(uint32_t) * topo->total_cores);
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uint32_t* apic_smt = malloc(sizeof(uint32_t) * topo->total_cores);
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uint32_t** cache_smt_id_apic = malloc(sizeof(uint32_t*) * topo->total_cores);
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uint32_t** cache_id_apic = malloc(sizeof(uint32_t*) * topo->total_cores);
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bool x2apic_id = cpu->maxLevels >= 0x0000000B;
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for(int i=0; i < (*topo)->total_cores; i++) {
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cache_smt_id_apic[i] = malloc(sizeof(uint32_t) * ((*topo)->cach->max_cache_level));
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cache_id_apic[i] = malloc(sizeof(uint32_t) * ((*topo)->cach->max_cache_level));
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for(int i=0; i < topo->total_cores; i++) {
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cache_smt_id_apic[i] = malloc(sizeof(uint32_t) * (topo->cach->max_cache_level));
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cache_id_apic[i] = malloc(sizeof(uint32_t) * (topo->cach->max_cache_level));
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}
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(*topo)->apic->cache_select_mask = malloc(sizeof(uint32_t) * ((*topo)->cach->max_cache_level));
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(*topo)->apic->cache_id_apic = malloc(sizeof(uint32_t) * ((*topo)->cach->max_cache_level));
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topo->apic->cache_select_mask = malloc(sizeof(uint32_t) * (topo->cach->max_cache_level));
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topo->apic->cache_id_apic = malloc(sizeof(uint32_t) * (topo->cach->max_cache_level));
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if(x2apic_id) {
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if(!fill_topo_masks_x2apic(topo))
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@@ -286,46 +281,57 @@ bool get_topology_from_apic(struct cpuInfo* cpu, struct topology** topo) {
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get_cache_topology_from_apic(topo);
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for(int i=0; i < (*topo)->total_cores; i++) {
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for(int i=0; i < topo->total_cores; i++) {
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if(!bind_to_cpu(i)) {
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printErr("Failed binding to CPU %d", i);
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return false;
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}
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apic_id = get_apic_id(x2apic_id);
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apic_pkg[i] = (apic_id & (*topo)->apic->pkg_mask) >> (*topo)->apic->pkg_mask_shift;
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apic_core[i] = (apic_id & (*topo)->apic->core_mask) >> (*topo)->apic->smt_mask_width;
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apic_smt[i] = apic_id & (*topo)->apic->smt_mask;
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apic_pkg[i] = (apic_id & topo->apic->pkg_mask) >> topo->apic->pkg_mask_shift;
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apic_core[i] = (apic_id & topo->apic->core_mask) >> topo->apic->smt_mask_width;
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apic_smt[i] = apic_id & topo->apic->smt_mask;
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for(int c=0; c < (*topo)->cach->max_cache_level; c++) {
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cache_smt_id_apic[i][c] = apic_id & (*topo)->apic->cache_select_mask[c];
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cache_id_apic[i][c] = apic_id & (-1 ^ (*topo)->apic->cache_select_mask[c]);
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for(int c=0; c < topo->cach->max_cache_level; c++) {
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cache_smt_id_apic[i][c] = apic_id & topo->apic->cache_select_mask[c];
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cache_id_apic[i][c] = apic_id & (-1 ^ topo->apic->cache_select_mask[c]);
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}
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}
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/* DEBUG
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for(int i=0; i < (*topo)->cach->max_cache_level; i++) {
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for(int i=0; i < topo->cach->max_cache_level; i++) {
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printf("[CACH %1d]", i);
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for(int j=0; j < (*topo)->total_cores; j++)
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for(int j=0; j < topo->total_cores; j++)
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printf("[%03d]", cache_id_apic[j][i]);
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printf("\n");
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}
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for(int i=0; i < (*topo)->total_cores; i++)
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for(int i=0; i < topo->total_cores; i++)
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printf("[%2d] 0x%.8X\n", i, apic_pkg[i]);
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printf("\n");
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for(int i=0; i < (*topo)->total_cores; i++)
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for(int i=0; i < topo->total_cores; i++)
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printf("[%2d] 0x%.8X\n", i, apic_core[i]);
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printf("\n");
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for(int i=0; i < (*topo)->total_cores; i++)
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for(int i=0; i < topo->total_cores; i++)
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printf("[%2d] 0x%.8X\n", i, apic_smt[i]);*/
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bool ret = build_topo_from_apic(apic_pkg, apic_smt, cache_id_apic, topo);
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// Assumption: If we cant get smt_available, we assume it is equal to smt_supported...
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if (!x2apic_id) (*topo)->smt_supported = (*topo)->smt_available;
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if (!x2apic_id) {
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printWarn("Can't read SMT from cpuid (needed level is 0x%.8X, max is 0x%.8X)", 0x0000000B, cpu->maxLevels);
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topo->smt_supported = topo->smt_available;
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}
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//TODO: free
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free(apic_pkg);
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free(apic_core);
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free(apic_smt);
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for(int i=0; i < topo->total_cores; i++) {
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free(cache_smt_id_apic[i]);
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free(cache_id_apic[i]);
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}
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free(cache_smt_id_apic);
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free(cache_id_apic);
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return ret;
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}
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@@ -339,7 +345,7 @@ uint32_t is_smt_enabled_amd(struct topology* topo) {
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return false;
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}
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id = get_apic_id(false) & 1; // get the last bit
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if(id == 1) return 2; // We assume there isn't any AMD CPU with more than 2th per core. TODO: Fix
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if(id == 1) return 2; // We assume there isn't any AMD CPU with more than 2th per core.
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}
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return 1;
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@@ -14,7 +14,7 @@ struct apic {
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uint32_t* cache_id_apic;
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};
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bool get_topology_from_apic(struct cpuInfo* cpu, struct topology** topo);
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bool get_topology_from_apic(struct cpuInfo* cpu, struct topology* topo);
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uint32_t is_smt_enabled_amd(struct topology* topo);
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#endif
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132
src/cpuid.c
132
src/cpuid.c
@@ -58,15 +58,46 @@ void init_cpu_info(struct cpuInfo* cpu) {
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cpu->AES = false;
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cpu->SHA = false;
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}
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void init_topology_struct(struct topology** topo) {
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/*
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void init_topology_struct(struct topology* topo, struct cache* cach) {
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(*topo)->total_cores = 0;
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(*topo)->physical_cores = 0;
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(*topo)->logical_cores = 0;
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(*topo)->smt_available = 0;
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(*topo)->smt_supported = 0;
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(*topo)->sockets = 0;
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// TODO: The other fields...
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(*topo)->apic = malloc(sizeof(struct apic));
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(*topo)->cach = cach;
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}*/
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void init_topology_struct(struct topology* topo, struct cache* cach) {
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topo->total_cores = 0;
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topo->physical_cores = 0;
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topo->logical_cores = 0;
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topo->smt_available = 0;
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topo->smt_supported = 0;
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topo->sockets = 0;
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topo->apic = malloc(sizeof(struct apic));
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topo->cach = cach;
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}
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void init_cache_struct(struct cache* cach) {
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cach->L1i = malloc(sizeof(struct cach));
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cach->L1d = malloc(sizeof(struct cach));
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cach->L2 = malloc(sizeof(struct cach));
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cach->L3 = malloc(sizeof(struct cach));
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cach->cach_arr = malloc(sizeof(struct cach*) * 4);
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cach->cach_arr[0] = cach->L1i;
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cach->cach_arr[1] = cach->L1d;
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cach->cach_arr[2] = cach->L2;
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cach->cach_arr[3] = cach->L3;
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cach->max_cache_level = 0;
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cach->L1i->exists = false;
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cach->L1d->exists = false;
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cach->L2->exists = false;
|
||||
cach->L3->exists = false;
|
||||
}
|
||||
|
||||
void get_cpu_vendor_internal(char* name, uint32_t ebx,uint32_t ecx,uint32_t edx) {
|
||||
@@ -245,18 +276,18 @@ uint8_t get_number_llc_amd(struct topology* topo) {
|
||||
return topo->logical_cores / num_sharing_cache;
|
||||
}
|
||||
|
||||
void get_cache_topology(struct cpuInfo* cpu, struct topology** topo) {
|
||||
(*topo)->cach->L1i->num_caches = (*topo)->physical_cores;
|
||||
(*topo)->cach->L1d->num_caches = (*topo)->physical_cores;
|
||||
(*topo)->cach->L2->num_caches = (*topo)->physical_cores;
|
||||
void guess_cache_topology_amd(struct cpuInfo* cpu, struct topology* topo) {
|
||||
topo->cach->L1i->num_caches = topo->physical_cores;
|
||||
topo->cach->L1d->num_caches = topo->physical_cores;
|
||||
topo->cach->L2->num_caches = topo->physical_cores;
|
||||
|
||||
if((*topo)->cach->L3->size != UNKNOWN) {
|
||||
if(topo->cach->L3->exists) {
|
||||
if(cpu->maxExtendedLevels >= 0x8000001D) {
|
||||
(*topo)->cach->L3->num_caches = get_number_llc_amd(*topo);
|
||||
topo->cach->L3->num_caches = get_number_llc_amd(topo);
|
||||
}
|
||||
else {
|
||||
printWarn("Can't read topology information from cpuid (needed extended level is 0x%.8X, max is 0x%.8X)", 0x8000001D, cpu->maxExtendedLevels);
|
||||
(*topo)->cach->L3->num_caches = 1;
|
||||
topo->cach->L3->num_caches = 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -265,9 +296,7 @@ void get_cache_topology(struct cpuInfo* cpu, struct topology** topo) {
|
||||
// Very interesting resource: https://wiki.osdev.org/Detecting_CPU_Topology_(80x86)
|
||||
struct topology* get_topology_info(struct cpuInfo* cpu, struct cache* cach) {
|
||||
struct topology* topo = malloc(sizeof(struct topology));
|
||||
topo->apic = malloc(sizeof(struct apic));
|
||||
topo->cach = cach;
|
||||
init_topology_struct(&topo);
|
||||
init_topology_struct(topo, cach);
|
||||
|
||||
uint32_t eax = 0;
|
||||
uint32_t ebx = 0;
|
||||
@@ -292,7 +321,7 @@ struct topology* get_topology_info(struct cpuInfo* cpu, struct cache* cach) {
|
||||
switch(cpu->cpu_vendor) {
|
||||
case VENDOR_INTEL:
|
||||
if (cpu->maxLevels >= 0x00000004) {
|
||||
get_topology_from_apic(cpu, &topo);
|
||||
get_topology_from_apic(cpu, topo);
|
||||
}
|
||||
else {
|
||||
printErr("Can't read topology information from cpuid (needed level is 0x%.8X, max is 0x%.8X)", 0x00000001, cpu->maxLevels);
|
||||
@@ -339,7 +368,7 @@ struct topology* get_topology_info(struct cpuInfo* cpu, struct cache* cach) {
|
||||
else
|
||||
topo->sockets = topo->total_cores / topo->physical_cores;
|
||||
|
||||
get_cache_topology(cpu, &topo);
|
||||
guess_cache_topology_amd(cpu, topo);
|
||||
|
||||
break;
|
||||
|
||||
@@ -353,16 +382,7 @@ struct topology* get_topology_info(struct cpuInfo* cpu, struct cache* cach) {
|
||||
|
||||
struct cache* get_cache_info(struct cpuInfo* cpu) {
|
||||
struct cache* cach = malloc(sizeof(struct cache));
|
||||
cach->L1i = malloc(sizeof(struct cach));
|
||||
cach->L1d = malloc(sizeof(struct cach));
|
||||
cach->L2 = malloc(sizeof(struct cach));
|
||||
cach->L3 = malloc(sizeof(struct cach));
|
||||
cach->cach_arr = malloc(sizeof(struct cach*) * 4);
|
||||
cach->cach_arr[0] = cach->L1i;
|
||||
cach->cach_arr[1] = cach->L1d;
|
||||
cach->cach_arr[2] = cach->L2;
|
||||
cach->cach_arr[3] = cach->L3;
|
||||
cach->max_cache_level = 0;
|
||||
init_cache_struct(cach);
|
||||
|
||||
uint32_t eax = 0;
|
||||
uint32_t ebx = 0;
|
||||
@@ -387,8 +407,9 @@ struct cache* get_cache_info(struct cpuInfo* cpu) {
|
||||
}
|
||||
}
|
||||
|
||||
// We suppose there are 4 caches (at most)
|
||||
for(int i=0; i < 4; i++) {
|
||||
int i=0;
|
||||
int32_t cache_type;
|
||||
do {
|
||||
eax = level; // get cache info
|
||||
ebx = 0;
|
||||
ecx = i; // cache id
|
||||
@@ -396,10 +417,10 @@ struct cache* get_cache_info(struct cpuInfo* cpu) {
|
||||
|
||||
cpuid(&eax, &ebx, &ecx, &edx);
|
||||
|
||||
int32_t cache_type = eax & 0x1F;
|
||||
cache_type = eax & 0x1F;
|
||||
|
||||
// If its 0, we tried fetching a non existing cache
|
||||
if (cache_type > 0) { // TODO: Change to while not == 0
|
||||
if (cache_type > 0) {
|
||||
int32_t cache_level = (eax >>= 5) & 0x7;
|
||||
uint32_t cache_sets = ecx + 1;
|
||||
uint32_t cache_coherency_line_size = (ebx & 0xFFF) + 1;
|
||||
@@ -416,6 +437,7 @@ struct cache* get_cache_info(struct cpuInfo* cpu) {
|
||||
return NULL;
|
||||
}
|
||||
cach->L1d->size = cache_total_size;
|
||||
cach->L1d->exists = true;
|
||||
break;
|
||||
|
||||
case 2: // Instruction Cache (We assume this is L1i)
|
||||
@@ -424,11 +446,18 @@ struct cache* get_cache_info(struct cpuInfo* cpu) {
|
||||
return NULL;
|
||||
}
|
||||
cach->L1i->size = cache_total_size;
|
||||
cach->L1i->exists = true;
|
||||
break;
|
||||
|
||||
case 3: // Unified Cache (This may be L2 or L3)
|
||||
if(cache_level == 2) cach->L2->size = cache_total_size;
|
||||
else if(cache_level == 3) cach->L3->size = cache_total_size;
|
||||
if(cache_level == 2) {
|
||||
cach->L2->size = cache_total_size;
|
||||
cach->L2->exists = true;
|
||||
}
|
||||
else if(cache_level == 3) {
|
||||
cach->L3->size = cache_total_size;
|
||||
cach->L3->exists = true;
|
||||
}
|
||||
else {
|
||||
printBug("Found unified cache at level %d (expected == 2 or 3)", cache_level);
|
||||
return NULL;
|
||||
@@ -440,17 +469,9 @@ struct cache* get_cache_info(struct cpuInfo* cpu) {
|
||||
return NULL;
|
||||
}
|
||||
}
|
||||
else if(i == 2) {
|
||||
cach->L2->size = UNKNOWN;
|
||||
}
|
||||
else if(i == 3) {
|
||||
cach->L3->size = UNKNOWN;
|
||||
}
|
||||
else {
|
||||
printBug("Could not find cache ID %d", i);
|
||||
return NULL;
|
||||
}
|
||||
}
|
||||
|
||||
i++;
|
||||
} while (cache_type > 0);
|
||||
|
||||
// Sanity checks. If we read values greater than this, they can't be valid ones
|
||||
// The values were chosen by me
|
||||
@@ -462,8 +483,8 @@ struct cache* get_cache_info(struct cpuInfo* cpu) {
|
||||
printBug("Invalid L1d size: %dKB", cach->L1d->size/1024);
|
||||
return NULL;
|
||||
}
|
||||
if(cach->L2->size != UNKNOWN) {
|
||||
if(cach->L3->size != UNKNOWN && cach->L2->size > 2 * 1048576) {
|
||||
if(cach->L2->exists) {
|
||||
if(cach->L3->exists && cach->L2->size > 2 * 1048576) {
|
||||
printBug("Invalid L2 size: %dMB", cach->L2->size/(1048576));
|
||||
return NULL;
|
||||
}
|
||||
@@ -472,11 +493,11 @@ struct cache* get_cache_info(struct cpuInfo* cpu) {
|
||||
return NULL;
|
||||
}
|
||||
}
|
||||
if(cach->L3->size != UNKNOWN && cach->L3->size > 100 * 1048576) {
|
||||
if(cach->L3->exists && cach->L3->size > 100 * 1048576) {
|
||||
printBug("Invalid L3 size: %dMB", cach->L3->size/(1048576));
|
||||
return NULL;
|
||||
}
|
||||
if(cach->L2->size == UNKNOWN) {
|
||||
if(!cach->L2->exists) {
|
||||
printBug("Could not find L2 cache");
|
||||
return NULL;
|
||||
}
|
||||
@@ -490,11 +511,11 @@ struct frequency* get_frequency_info(struct cpuInfo* cpu) {
|
||||
if(cpu->maxLevels < 0x16) {
|
||||
#ifdef _WIN32
|
||||
printErr("Can't read frequency information from cpuid (needed level is %d, max is %d)", 0x16, cpu->maxLevels);
|
||||
freq->base = UNKNOWN;
|
||||
freq->max = UNKNOWN;
|
||||
freq->base = UNKNOWN_FREQ;
|
||||
freq->max = UNKNOWN_FREQ;
|
||||
#else
|
||||
printWarn("Can't read frequency information from cpuid (needed level is %d, max is %d). Using udev", 0x16, cpu->maxLevels);
|
||||
freq->base = UNKNOWN;
|
||||
freq->base = UNKNOWN_FREQ;
|
||||
freq->max = get_max_freq_from_file();
|
||||
#endif
|
||||
}
|
||||
@@ -584,7 +605,7 @@ char* get_str_peak_performance(struct cpuInfo* cpu, struct topology* topo, int64
|
||||
char* string = malloc(sizeof(char)*size);
|
||||
|
||||
//First check we have consistent data
|
||||
if(freq == UNKNOWN) {
|
||||
if(freq == UNKNOWN_FREQ) {
|
||||
snprintf(string,strlen(STRING_UNKNOWN)+1,STRING_UNKNOWN);
|
||||
return string;
|
||||
}
|
||||
@@ -842,12 +863,12 @@ char* get_str_l1d(struct cache* cach) {
|
||||
}
|
||||
|
||||
char* get_str_l2(struct cache* cach) {
|
||||
assert(cach->L2->size != UNKNOWN);
|
||||
assert(cach->L2->exists);
|
||||
return get_str_cache(cach->L2->size, cach->L2->num_caches);
|
||||
}
|
||||
|
||||
char* get_str_l3(struct cache* cach) {
|
||||
if(cach->L3->size == UNKNOWN)
|
||||
if(!cach->L3->exists)
|
||||
return NULL;
|
||||
return get_str_cache(cach->L3->size, cach->L3->num_caches);
|
||||
}
|
||||
@@ -857,7 +878,7 @@ char* get_str_freq(struct frequency* freq) {
|
||||
uint32_t size = (4+3+1);
|
||||
assert(strlen(STRING_UNKNOWN)+1 <= size);
|
||||
char* string = malloc(sizeof(char)*size);
|
||||
if(freq->max == UNKNOWN)
|
||||
if(freq->max == UNKNOWN_FREQ)
|
||||
snprintf(string,strlen(STRING_UNKNOWN)+1,STRING_UNKNOWN);
|
||||
else if(freq->max >= 1000)
|
||||
snprintf(string,size,"%.2f"STRING_GIGAHERZ,(float)(freq->max)/1000);
|
||||
@@ -873,10 +894,15 @@ void print_levels(struct cpuInfo* cpu, char* cpu_name) {
|
||||
}
|
||||
|
||||
void free_topo_struct(struct topology* topo) {
|
||||
free(topo->apic->cache_select_mask);
|
||||
free(topo->apic->cache_id_apic);
|
||||
free(topo->apic);
|
||||
free(topo);
|
||||
}
|
||||
|
||||
void free_cache_struct(struct cache* cach) {
|
||||
for(int i=0; i < 4; i++) free(cach->cach_arr[i]);
|
||||
free(cach->cach_arr);
|
||||
free(cach);
|
||||
}
|
||||
|
||||
|
||||
@@ -8,7 +8,7 @@
|
||||
#define VENDOR_AMD 2
|
||||
#define VENDOR_INVALID 3
|
||||
|
||||
#define UNKNOWN -1
|
||||
#define UNKNOWN_FREQ -1
|
||||
|
||||
typedef int32_t VENDOR;
|
||||
|
||||
@@ -42,6 +42,7 @@ struct cpuInfo {
|
||||
struct cach {
|
||||
int32_t size;
|
||||
uint8_t num_caches;
|
||||
bool exists;
|
||||
// plenty of more properties to include in the future...
|
||||
};
|
||||
|
||||
|
||||
@@ -21,6 +21,7 @@ Options: \n\
|
||||
* legacy \n\
|
||||
--help Prints this help and exit\n\
|
||||
--levels Prints CPU model and cpuid levels (debug purposes)\n\
|
||||
--verbose Prints extra information (if available) about how cpufetch tried fetching information\n\
|
||||
--version Prints cpufetch version and exit\n",
|
||||
argv[0]);
|
||||
}
|
||||
|
||||
@@ -24,7 +24,7 @@ long get_freq_from_file(char* path) {
|
||||
if(fd == -1) {
|
||||
perror("open");
|
||||
printBug("Could not open '%s'", path);
|
||||
return UNKNOWN;
|
||||
return UNKNOWN_FREQ;
|
||||
}
|
||||
|
||||
//File exists, read it
|
||||
@@ -45,7 +45,7 @@ long get_freq_from_file(char* path) {
|
||||
perror("strtol");
|
||||
printBug("Failed parsing '%s' file. Read data was: '%s'", path, buf);
|
||||
free(buf);
|
||||
return UNKNOWN;
|
||||
return UNKNOWN_FREQ;
|
||||
}
|
||||
|
||||
// We will be getting the frequency in KHz
|
||||
@@ -53,7 +53,7 @@ long get_freq_from_file(char* path) {
|
||||
// greater than 10 GHz or less than 100 MHz
|
||||
if(ret > 10000 * 1000 || ret < 100 * 1000) {
|
||||
printBug("Invalid data was read from file '%s': %ld\n", path, ret);
|
||||
return UNKNOWN;
|
||||
return UNKNOWN_FREQ;
|
||||
}
|
||||
|
||||
free(buf);
|
||||
|
||||
Reference in New Issue
Block a user