diff --git a/src/riscv/riscv.c b/src/riscv/riscv.c index 103862f..08668b7 100644 --- a/src/riscv/riscv.c +++ b/src/riscv/riscv.c @@ -72,6 +72,64 @@ int parse_multi_letter_extension(struct extensions* ext, char* e) { SET_ISA_EXT_MAP("zicsr", RISCV_ISA_EXT_ZICSR) SET_ISA_EXT_MAP("zifencei", RISCV_ISA_EXT_ZIFENCEI) SET_ISA_EXT_MAP("zihpm", RISCV_ISA_EXT_ZIHPM) + SET_ISA_EXT_MAP("smstateen", RISCV_ISA_EXT_SMSTATEEN) + SET_ISA_EXT_MAP("zicond", RISCV_ISA_EXT_ZICOND) + SET_ISA_EXT_MAP("zbc", RISCV_ISA_EXT_ZBC) + SET_ISA_EXT_MAP("zbkb", RISCV_ISA_EXT_ZBKB) + SET_ISA_EXT_MAP("zbkc", RISCV_ISA_EXT_ZBKC) + SET_ISA_EXT_MAP("zbkx", RISCV_ISA_EXT_ZBKX) + SET_ISA_EXT_MAP("zknd", RISCV_ISA_EXT_ZKND) + SET_ISA_EXT_MAP("zkne", RISCV_ISA_EXT_ZKNE) + SET_ISA_EXT_MAP("zknh", RISCV_ISA_EXT_ZKNH) + SET_ISA_EXT_MAP("zkr", RISCV_ISA_EXT_ZKR) + SET_ISA_EXT_MAP("zksed", RISCV_ISA_EXT_ZKSED) + SET_ISA_EXT_MAP("zksh", RISCV_ISA_EXT_ZKSH) + SET_ISA_EXT_MAP("zkt", RISCV_ISA_EXT_ZKT) + SET_ISA_EXT_MAP("zvbb", RISCV_ISA_EXT_ZVBB) + SET_ISA_EXT_MAP("zvbc", RISCV_ISA_EXT_ZVBC) + SET_ISA_EXT_MAP("zvkb", RISCV_ISA_EXT_ZVKB) + SET_ISA_EXT_MAP("zvkg", RISCV_ISA_EXT_ZVKG) + SET_ISA_EXT_MAP("zvkned", RISCV_ISA_EXT_ZVKNED) + SET_ISA_EXT_MAP("zvknha", RISCV_ISA_EXT_ZVKNHA) + SET_ISA_EXT_MAP("zvknhb", RISCV_ISA_EXT_ZVKNHB) + SET_ISA_EXT_MAP("zvksed", RISCV_ISA_EXT_ZVKSED) + SET_ISA_EXT_MAP("zvksh", RISCV_ISA_EXT_ZVKSH) + SET_ISA_EXT_MAP("zvkt", RISCV_ISA_EXT_ZVKT) + SET_ISA_EXT_MAP("zfh", RISCV_ISA_EXT_ZFH) + SET_ISA_EXT_MAP("zfhmin", RISCV_ISA_EXT_ZFHMIN) + SET_ISA_EXT_MAP("zihintntl", RISCV_ISA_EXT_ZIHINTNTL) + SET_ISA_EXT_MAP("zvfh", RISCV_ISA_EXT_ZVFH) + SET_ISA_EXT_MAP("zvfhmin", RISCV_ISA_EXT_ZVFHMIN) + SET_ISA_EXT_MAP("zfa", RISCV_ISA_EXT_ZFA) + SET_ISA_EXT_MAP("ztso", RISCV_ISA_EXT_ZTSO) + SET_ISA_EXT_MAP("zacas", RISCV_ISA_EXT_ZACAS) + SET_ISA_EXT_MAP("zve32x", RISCV_ISA_EXT_ZVE32X) + SET_ISA_EXT_MAP("zve32f", RISCV_ISA_EXT_ZVE32F) + SET_ISA_EXT_MAP("zve64x", RISCV_ISA_EXT_ZVE64X) + SET_ISA_EXT_MAP("zve64f", RISCV_ISA_EXT_ZVE64F) + SET_ISA_EXT_MAP("zve64d", RISCV_ISA_EXT_ZVE64D) + SET_ISA_EXT_MAP("zimop", RISCV_ISA_EXT_ZIMOP) + SET_ISA_EXT_MAP("zca", RISCV_ISA_EXT_ZCA) + SET_ISA_EXT_MAP("zcb", RISCV_ISA_EXT_ZCB) + SET_ISA_EXT_MAP("zcd", RISCV_ISA_EXT_ZCD) + SET_ISA_EXT_MAP("zcf", RISCV_ISA_EXT_ZCF) + SET_ISA_EXT_MAP("zcmop", RISCV_ISA_EXT_ZCMOP) + SET_ISA_EXT_MAP("zawrs", RISCV_ISA_EXT_ZAWRS) + SET_ISA_EXT_MAP("svvptc", RISCV_ISA_EXT_SVVPTC) + SET_ISA_EXT_MAP("smmpm", RISCV_ISA_EXT_SMMPM) + SET_ISA_EXT_MAP("smnpm", RISCV_ISA_EXT_SMNPM) + SET_ISA_EXT_MAP("ssnpm", RISCV_ISA_EXT_SSNPM) + SET_ISA_EXT_MAP("zabha", RISCV_ISA_EXT_ZABHA) + SET_ISA_EXT_MAP("ziccrse", RISCV_ISA_EXT_ZICCRSE) + SET_ISA_EXT_MAP("svade", RISCV_ISA_EXT_SVADE) + SET_ISA_EXT_MAP("svadu", RISCV_ISA_EXT_SVADU) + SET_ISA_EXT_MAP("zfbfmin", RISCV_ISA_EXT_ZFBFMIN) + SET_ISA_EXT_MAP("zvfbfmin", RISCV_ISA_EXT_ZVFBFMIN) + SET_ISA_EXT_MAP("zvfbfwma", RISCV_ISA_EXT_ZVFBFWMA) + SET_ISA_EXT_MAP("zaamo", RISCV_ISA_EXT_ZAAMO) + SET_ISA_EXT_MAP("zalrsc", RISCV_ISA_EXT_ZALRSC) + SET_ISA_EXT_MAP("zicbop", RISCV_ISA_EXT_ZICBOP) + if(!maskset) { printBug("parse_multi_letter_extension: Unknown multi-letter extension: %s", multi_letter_extension); return -1; diff --git a/src/riscv/riscv.h b/src/riscv/riscv.h index 307a595..de280d3 100644 --- a/src/riscv/riscv.h +++ b/src/riscv/riscv.h @@ -23,7 +23,6 @@ enum riscv_isa_ext_id { RISCV_ISA_EXT_ZICBOM, RISCV_ISA_EXT_ZIHINTPAUSE, RISCV_ISA_EXT_SVNAPOT, - RISCV_ISA_EXT_ZICBOP, RISCV_ISA_EXT_ZICBOZ, RISCV_ISA_EXT_SMAIA, RISCV_ISA_EXT_SSAIA, @@ -33,12 +32,70 @@ enum riscv_isa_ext_id { RISCV_ISA_EXT_ZICSR, RISCV_ISA_EXT_ZIFENCEI, RISCV_ISA_EXT_ZIHPM, + RISCV_ISA_EXT_SMSTATEEN, + RISCV_ISA_EXT_ZICOND, + RISCV_ISA_EXT_ZBC, + RISCV_ISA_EXT_ZBKB, + RISCV_ISA_EXT_ZBKC, + RISCV_ISA_EXT_ZBKX, + RISCV_ISA_EXT_ZKND, + RISCV_ISA_EXT_ZKNE, + RISCV_ISA_EXT_ZKNH, + RISCV_ISA_EXT_ZKR, + RISCV_ISA_EXT_ZKSED, + RISCV_ISA_EXT_ZKSH, + RISCV_ISA_EXT_ZKT, + RISCV_ISA_EXT_ZVBB, + RISCV_ISA_EXT_ZVBC, + RISCV_ISA_EXT_ZVKB, + RISCV_ISA_EXT_ZVKG, + RISCV_ISA_EXT_ZVKNED, + RISCV_ISA_EXT_ZVKNHA, + RISCV_ISA_EXT_ZVKNHB, + RISCV_ISA_EXT_ZVKSED, + RISCV_ISA_EXT_ZVKSH, + RISCV_ISA_EXT_ZVKT, + RISCV_ISA_EXT_ZFH, + RISCV_ISA_EXT_ZFHMIN, + RISCV_ISA_EXT_ZIHINTNTL, + RISCV_ISA_EXT_ZVFH, + RISCV_ISA_EXT_ZVFHMIN, + RISCV_ISA_EXT_ZFA, + RISCV_ISA_EXT_ZTSO, + RISCV_ISA_EXT_ZACAS, + RISCV_ISA_EXT_ZVE32X, + RISCV_ISA_EXT_ZVE32F, + RISCV_ISA_EXT_ZVE64X, + RISCV_ISA_EXT_ZVE64F, + RISCV_ISA_EXT_ZVE64D, + RISCV_ISA_EXT_ZIMOP, + RISCV_ISA_EXT_ZCA, + RISCV_ISA_EXT_ZCB, + RISCV_ISA_EXT_ZCD, + RISCV_ISA_EXT_ZCF, + RISCV_ISA_EXT_ZCMOP, + RISCV_ISA_EXT_ZAWRS, + RISCV_ISA_EXT_SVVPTC, + RISCV_ISA_EXT_SMMPM, + RISCV_ISA_EXT_SMNPM, + RISCV_ISA_EXT_SSNPM, + RISCV_ISA_EXT_ZABHA, + RISCV_ISA_EXT_ZICCRSE, + RISCV_ISA_EXT_SVADE, + RISCV_ISA_EXT_SVADU, + RISCV_ISA_EXT_ZFBFMIN, + RISCV_ISA_EXT_ZVFBFMIN, + RISCV_ISA_EXT_ZVFBFWMA, + RISCV_ISA_EXT_ZAAMO, + RISCV_ISA_EXT_ZALRSC, + RISCV_ISA_EXT_ZICBOP, RISCV_ISA_EXT_ID_MAX }; // https://five-embeddev.com/riscv-isa-manual/latest/preface.html#preface // https://en.wikichip.org/wiki/risc-v/standard_extensions // (Zicbop) https://github.com/riscv/riscv-CMOs/blob/master/cmobase/Zicbop.adoc +// https://raw.githubusercontent.com/riscv/riscv-CMOs/master/specifications/cmobase-v1.0.1.pdf // Included all except for G static const struct extension extension_list[] = { { 'i' - 'a', "(I) Integer Instruction Set" }, @@ -74,7 +131,64 @@ static const struct extension extension_list[] = { { RISCV_ISA_EXT_ZICNTR, "(Zicntr) Base Counters and Timers" }, { RISCV_ISA_EXT_ZICSR, "(Zicsr) Control and Status Register" }, { RISCV_ISA_EXT_ZIFENCEI, "(Zifencei) Instruction-Fetch Fence" }, - { RISCV_ISA_EXT_ZIHPM, "(Zihpm) Hardware Performance Counters" } + { RISCV_ISA_EXT_ZIHPM, "(Zihpm) Hardware Performance Counters" }, + { RISCV_ISA_EXT_SMSTATEEN, "(smstateen) " }, + { RISCV_ISA_EXT_ZICOND, "(zicond) " }, + { RISCV_ISA_EXT_ZBC, "(zbc) " }, + { RISCV_ISA_EXT_ZBKB, "(zbkb) " }, + { RISCV_ISA_EXT_ZBKC, "(zbkc) " }, + { RISCV_ISA_EXT_ZBKX, "(zbkx) " }, + { RISCV_ISA_EXT_ZKND, "(zknd) " }, + { RISCV_ISA_EXT_ZKNE, "(zkne) " }, + { RISCV_ISA_EXT_ZKNH, "(zknh) " }, + { RISCV_ISA_EXT_ZKR, "(zkr) " }, + { RISCV_ISA_EXT_ZKSED, "(zksed) " }, + { RISCV_ISA_EXT_ZKSH, "(zksh) " }, + { RISCV_ISA_EXT_ZKT, "(zkt) " }, + { RISCV_ISA_EXT_ZVBB, "(zvbb) " }, + { RISCV_ISA_EXT_ZVBC, "(zvbc) " }, + { RISCV_ISA_EXT_ZVKB, "(zvkb) " }, + { RISCV_ISA_EXT_ZVKG, "(zvkg) " }, + { RISCV_ISA_EXT_ZVKNED, "(zvkned) " }, + { RISCV_ISA_EXT_ZVKNHA, "(zvknha) " }, + { RISCV_ISA_EXT_ZVKNHB, "(zvknhb) " }, + { RISCV_ISA_EXT_ZVKSED, "(zvksed) " }, + { RISCV_ISA_EXT_ZVKSH, "(zvksh) " }, + { RISCV_ISA_EXT_ZVKT, "(zvkt) " }, + { RISCV_ISA_EXT_ZFH, "(zfh) " }, + { RISCV_ISA_EXT_ZFHMIN, "(zfhmin) " }, + { RISCV_ISA_EXT_ZIHINTNTL, "(zihintntl) " }, + { RISCV_ISA_EXT_ZVFH, "(zvfh) " }, + { RISCV_ISA_EXT_ZVFHMIN, "(zvfhmin) " }, + { RISCV_ISA_EXT_ZFA, "(zfa) " }, + { RISCV_ISA_EXT_ZTSO, "(ztso) " }, + { RISCV_ISA_EXT_ZACAS, "(zacas) " }, + { RISCV_ISA_EXT_ZVE32X, "(zve32x) " }, + { RISCV_ISA_EXT_ZVE32F, "(zve32f) " }, + { RISCV_ISA_EXT_ZVE64X, "(zve64x) " }, + { RISCV_ISA_EXT_ZVE64F, "(zve64f) " }, + { RISCV_ISA_EXT_ZVE64D, "(zve64d) " }, + { RISCV_ISA_EXT_ZIMOP, "(zimop) " }, + { RISCV_ISA_EXT_ZCA, "(zca) " }, + { RISCV_ISA_EXT_ZCB, "(zcb) " }, + { RISCV_ISA_EXT_ZCD, "(zcd) " }, + { RISCV_ISA_EXT_ZCF, "(zcf) " }, + { RISCV_ISA_EXT_ZCMOP, "(zcmop) " }, + { RISCV_ISA_EXT_ZAWRS, "(zawrs) " }, + { RISCV_ISA_EXT_SVVPTC, "(svvptc) " }, + { RISCV_ISA_EXT_SMMPM, "(smmpm) " }, + { RISCV_ISA_EXT_SMNPM, "(smnpm) " }, + { RISCV_ISA_EXT_SSNPM, "(ssnpm) " }, + { RISCV_ISA_EXT_ZABHA, "(zabha) " }, + { RISCV_ISA_EXT_ZICCRSE, "(ziccrse) " }, + { RISCV_ISA_EXT_SVADE, "(svade) " }, + { RISCV_ISA_EXT_SVADU, "(svadu) " }, + { RISCV_ISA_EXT_ZFBFMIN, "(zfbfmin) " }, + { RISCV_ISA_EXT_ZVFBFMIN, "(zvfbfmin) " }, + { RISCV_ISA_EXT_ZVFBFWMA, "(zvfbfwma) " }, + { RISCV_ISA_EXT_ZAAMO, "(zaamo) " }, + { RISCV_ISA_EXT_ZALRSC, "(zalrsc) " }, + { RISCV_ISA_EXT_ZICBOP, "(zicbop) " }, }; struct cpuInfo* get_cpu_info(void);