[v1.03][RISCV] Implementing basic skeleton for RISC-V backend

This commit is contained in:
Dr-Noob
2023-04-01 16:46:54 +02:00
parent 1f450b23a1
commit 9a69a7f58d
10 changed files with 141 additions and 6 deletions

View File

@@ -20,6 +20,8 @@ enum {
CPU_VENDOR_SAMSUNG,
CPU_VENDOR_MARVELL,
CPU_VENDOR_PHYTIUM,
// ARCH_RISCV
CPU_VENDOR_RISCV,
// OTHERS
CPU_VENDOR_UNKNOWN,
CPU_VENDOR_INVALID
@@ -149,7 +151,7 @@ struct cpuInfo {
uint32_t midr;
#endif
#ifdef ARCH_ARM
#if defined(ARCH_ARM) || defined(ARCH_RISCV)
struct system_on_chip* soc;
#endif