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[v1.03][RISCV] Implementing basic skeleton for RISC-V backend
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@@ -20,6 +20,8 @@ enum {
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CPU_VENDOR_SAMSUNG,
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CPU_VENDOR_MARVELL,
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CPU_VENDOR_PHYTIUM,
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// ARCH_RISCV
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CPU_VENDOR_RISCV,
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// OTHERS
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CPU_VENDOR_UNKNOWN,
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CPU_VENDOR_INVALID
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@@ -149,7 +151,7 @@ struct cpuInfo {
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uint32_t midr;
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#endif
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#ifdef ARCH_ARM
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#if defined(ARCH_ARM) || defined(ARCH_RISCV)
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struct system_on_chip* soc;
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#endif
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