From a12defaf4b6c5a62dbe83fa55c4a11aeefef7dbf Mon Sep 17 00:00:00 2001
From: Dr-Noob <peibolms@gmail.com>
Date: Tue, 19 Sep 2023 08:18:13 +0100
Subject: [PATCH] [v1.04][RISCV] Define to enum

---
 src/riscv/riscv.h | 47 +++++++++++++++++++++++------------------------
 1 file changed, 23 insertions(+), 24 deletions(-)

diff --git a/src/riscv/riscv.h b/src/riscv/riscv.h
index 8ec8119..fc9f746 100644
--- a/src/riscv/riscv.h
+++ b/src/riscv/riscv.h
@@ -29,35 +29,34 @@ static const struct extension extension_list[] = {
   { 's' - 'a', "(S) Supervisor-level Instructions" }
 };
 
-#define RISCV_ISA_EXT_MAX	64
+#define RISCV_ISA_EXT_MAX	   64
 #define RISCV_ISA_EXT_NAME_LEN_MAX 32
-#define RISCV_ISA_EXT_BASE 26
+#define RISCV_ISA_EXT_BASE         26
 
 // This enum represent the logical ID for multi-letter RISC-V ISA extensions.
 // The logical ID should start from RISCV_ISA_EXT_BASE and must not exceed
 // RISCV_ISA_EXT_MAX.
-#define RISCV_ISA_EXT_BASE		26
-
-#define RISCV_ISA_EXT_SSCOFPMF		26
-#define RISCV_ISA_EXT_SSTC		27
-#define RISCV_ISA_EXT_SVINVAL		28
-#define RISCV_ISA_EXT_SVPBMT		29
-#define RISCV_ISA_EXT_ZBB		30
-#define RISCV_ISA_EXT_ZICBOM		31
-#define RISCV_ISA_EXT_ZIHINTPAUSE	32
-#define RISCV_ISA_EXT_SVNAPOT		33
-#define RISCV_ISA_EXT_ZICBOZ		34
-#define RISCV_ISA_EXT_SMAIA		35
-#define RISCV_ISA_EXT_SSAIA		36
-#define RISCV_ISA_EXT_ZBA		37
-#define RISCV_ISA_EXT_ZBS		38
-#define RISCV_ISA_EXT_ZICNTR		39
-#define RISCV_ISA_EXT_ZICSR		40
-#define RISCV_ISA_EXT_ZIFENCEI		41
-#define RISCV_ISA_EXT_ZIHPM		42
-
-#define RISCV_ISA_EXT_MAX		64
-#define RISCV_ISA_EXT_NAME_LEN_MAX	32
+enum riscv_isa_ext_id {
+  RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE,
+  RISCV_ISA_EXT_SSTC,
+  RISCV_ISA_EXT_SVINVAL,
+  RISCV_ISA_EXT_SVPBMT,
+  RISCV_ISA_EXT_ZBB,
+  RISCV_ISA_EXT_ZICBOM,
+  RISCV_ISA_EXT_ZIHINTPAUSE,
+  RISCV_ISA_EXT_SVNAPOT,
+  RISCV_ISA_EXT_ZICBOZ,
+  RISCV_ISA_EXT_SMAIA,
+  RISCV_ISA_EXT_SSAIA,
+  RISCV_ISA_EXT_ZBA,
+  RISCV_ISA_EXT_ZBS,
+  RISCV_ISA_EXT_ZICNTR,
+  RISCV_ISA_EXT_ZICSR,
+  RISCV_ISA_EXT_ZIFENCEI,
+  RISCV_ISA_EXT_ZIHPM,
+  RISCV_ISA_EXT_ID_MAX
+};
+static_assert(RISCV_ISA_EXT_ID_MAX <= RISCV_ISA_EXT_MAX);
 
 struct cpuInfo* get_cpu_info(void);
 char* get_str_topology(struct cpuInfo* cpu, struct topology* topo);