diff --git a/src/common/cpu.h b/src/common/cpu.h index 1a92624..fbfb108 100644 --- a/src/common/cpu.h +++ b/src/common/cpu.h @@ -138,7 +138,7 @@ struct features { struct extensions { char* str; - uint64_t mask; + bool* mask; // allocated at runtime with size RISCV_ISA_EXT_ID_MAX }; struct cpuInfo { diff --git a/src/common/printer.c b/src/common/printer.c index 84e46c8..617a2f4 100644 --- a/src/common/printer.c +++ b/src/common/printer.c @@ -949,14 +949,7 @@ bool print_cpufetch_arm(struct cpuInfo* cpu, STYLE s, struct color** cs, struct #endif #ifdef ARCH_RISCV -// https://stackoverflow.com/a/2709523 -uint64_t number_of_bits(uint64_t i) { - i = i - ((i >> 1) & 0x5555555555555555); - i = (i & 0x3333333333333333) + ((i >> 2) & 0x3333333333333333); - return (((i + (i >> 4)) & 0xF0F0F0F0F0F0F0F) * 0x101010101010101) >> 56; -} - -void print_ascii_riscv(struct ascii* art, uint32_t la, int32_t termw, bool use_short, uint64_t extensions_mask) { +void print_ascii_riscv(struct ascii* art, uint32_t la, int32_t termw, bool use_short, bool* extensions_mask) { struct ascii_logo* logo = art->art; int attr_to_print = 0; int attr_type; @@ -966,7 +959,7 @@ void print_ascii_riscv(struct ascii* art, uint32_t la, int32_t termw, bool use_s int32_t ext_list_size = sizeof(extension_list)/sizeof(extension_list[0]); int32_t ext_num = 0; int32_t ext_to_print = 0; - int32_t num_extensions = number_of_bits(extensions_mask); + int32_t num_extensions = get_num_extensions(extensions_mask); int32_t space_up = ((int)logo->height - (int)(art->n_attributes_set + num_extensions))/2; int32_t space_down = (int)logo->height - (int)(art->n_attributes_set + num_extensions) - (int)space_up; uint32_t logo_pos = 0; @@ -1012,7 +1005,9 @@ void print_ascii_riscv(struct ascii* art, uint32_t la, int32_t termw, bool use_s // Print extension if(attr_to_print > 0 && art->attributes[attr_to_print-1]->type == ATTRIBUTE_EXTENSIONS && ext_num != num_extensions) { // Search for the extension to print - while(ext_to_print < ext_list_size && !((extensions_mask >> extension_list[ext_to_print].id) & 1U)) ext_to_print++; + while (ext_to_print < ext_list_size && !((extensions_mask[extension_list[ext_to_print].id]))) + ext_to_print++; + if(ext_to_print == ext_list_size) { printBug("print_ascii_riscv: Unable to find the extension to print"); } diff --git a/src/riscv/riscv.c b/src/riscv/riscv.c index 103862f..f701a13 100644 --- a/src/riscv/riscv.c +++ b/src/riscv/riscv.c @@ -12,7 +12,7 @@ #define SET_ISA_EXT_MAP(name, bit) \ if(strncmp(multi_letter_extension, name, \ multi_letter_extension_len) == 0) { \ - ext->mask |= 1UL << bit; \ + ext->mask[bit] = true; \ maskset = true; \ } \ @@ -62,7 +62,6 @@ int parse_multi_letter_extension(struct extensions* ext, char* e) { SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM) SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE) SET_ISA_EXT_MAP("svnapot", RISCV_ISA_EXT_SVNAPOT) - SET_ISA_EXT_MAP("zicbop", RISCV_ISA_EXT_ZICBOP) SET_ISA_EXT_MAP("zicboz", RISCV_ISA_EXT_ZICBOZ) SET_ISA_EXT_MAP("smaia", RISCV_ISA_EXT_SMAIA) SET_ISA_EXT_MAP("ssaia", RISCV_ISA_EXT_SSAIA) @@ -72,6 +71,65 @@ int parse_multi_letter_extension(struct extensions* ext, char* e) { SET_ISA_EXT_MAP("zicsr", RISCV_ISA_EXT_ZICSR) SET_ISA_EXT_MAP("zifencei", RISCV_ISA_EXT_ZIFENCEI) SET_ISA_EXT_MAP("zihpm", RISCV_ISA_EXT_ZIHPM) + SET_ISA_EXT_MAP("smstateen", RISCV_ISA_EXT_SMSTATEEN) + SET_ISA_EXT_MAP("zicond", RISCV_ISA_EXT_ZICOND) + SET_ISA_EXT_MAP("zbc", RISCV_ISA_EXT_ZBC) + SET_ISA_EXT_MAP("zbkb", RISCV_ISA_EXT_ZBKB) + SET_ISA_EXT_MAP("zbkc", RISCV_ISA_EXT_ZBKC) + SET_ISA_EXT_MAP("zbkx", RISCV_ISA_EXT_ZBKX) + SET_ISA_EXT_MAP("zknd", RISCV_ISA_EXT_ZKND) + SET_ISA_EXT_MAP("zkne", RISCV_ISA_EXT_ZKNE) + SET_ISA_EXT_MAP("zknh", RISCV_ISA_EXT_ZKNH) + SET_ISA_EXT_MAP("zkr", RISCV_ISA_EXT_ZKR) + SET_ISA_EXT_MAP("zksed", RISCV_ISA_EXT_ZKSED) + SET_ISA_EXT_MAP("zksh", RISCV_ISA_EXT_ZKSH) + SET_ISA_EXT_MAP("zkt", RISCV_ISA_EXT_ZKT) + SET_ISA_EXT_MAP("zvbb", RISCV_ISA_EXT_ZVBB) + SET_ISA_EXT_MAP("zvbc", RISCV_ISA_EXT_ZVBC) + SET_ISA_EXT_MAP("zvkb", RISCV_ISA_EXT_ZVKB) + SET_ISA_EXT_MAP("zvkg", RISCV_ISA_EXT_ZVKG) + SET_ISA_EXT_MAP("zvkned", RISCV_ISA_EXT_ZVKNED) + SET_ISA_EXT_MAP("zvknha", RISCV_ISA_EXT_ZVKNHA) + SET_ISA_EXT_MAP("zvknhb", RISCV_ISA_EXT_ZVKNHB) + SET_ISA_EXT_MAP("zvksed", RISCV_ISA_EXT_ZVKSED) + SET_ISA_EXT_MAP("zvksh", RISCV_ISA_EXT_ZVKSH) + SET_ISA_EXT_MAP("zvkt", RISCV_ISA_EXT_ZVKT) + SET_ISA_EXT_MAP("zfh", RISCV_ISA_EXT_ZFH) + SET_ISA_EXT_MAP("zfhmin", RISCV_ISA_EXT_ZFHMIN) + SET_ISA_EXT_MAP("zihintntl", RISCV_ISA_EXT_ZIHINTNTL) + SET_ISA_EXT_MAP("zvfh", RISCV_ISA_EXT_ZVFH) + SET_ISA_EXT_MAP("zvfhmin", RISCV_ISA_EXT_ZVFHMIN) + SET_ISA_EXT_MAP("zfa", RISCV_ISA_EXT_ZFA) + SET_ISA_EXT_MAP("ztso", RISCV_ISA_EXT_ZTSO) + SET_ISA_EXT_MAP("zacas", RISCV_ISA_EXT_ZACAS) + SET_ISA_EXT_MAP("zve32x", RISCV_ISA_EXT_ZVE32X) + SET_ISA_EXT_MAP("zve32f", RISCV_ISA_EXT_ZVE32F) + SET_ISA_EXT_MAP("zve64x", RISCV_ISA_EXT_ZVE64X) + SET_ISA_EXT_MAP("zve64f", RISCV_ISA_EXT_ZVE64F) + SET_ISA_EXT_MAP("zve64d", RISCV_ISA_EXT_ZVE64D) + SET_ISA_EXT_MAP("zimop", RISCV_ISA_EXT_ZIMOP) + SET_ISA_EXT_MAP("zca", RISCV_ISA_EXT_ZCA) + SET_ISA_EXT_MAP("zcb", RISCV_ISA_EXT_ZCB) + SET_ISA_EXT_MAP("zcd", RISCV_ISA_EXT_ZCD) + SET_ISA_EXT_MAP("zcf", RISCV_ISA_EXT_ZCF) + SET_ISA_EXT_MAP("zcmop", RISCV_ISA_EXT_ZCMOP) + SET_ISA_EXT_MAP("zawrs", RISCV_ISA_EXT_ZAWRS) + SET_ISA_EXT_MAP("svvptc", RISCV_ISA_EXT_SVVPTC) + SET_ISA_EXT_MAP("smmpm", RISCV_ISA_EXT_SMMPM) + SET_ISA_EXT_MAP("smnpm", RISCV_ISA_EXT_SMNPM) + SET_ISA_EXT_MAP("ssnpm", RISCV_ISA_EXT_SSNPM) + SET_ISA_EXT_MAP("zabha", RISCV_ISA_EXT_ZABHA) + SET_ISA_EXT_MAP("ziccrse", RISCV_ISA_EXT_ZICCRSE) + SET_ISA_EXT_MAP("svade", RISCV_ISA_EXT_SVADE) + SET_ISA_EXT_MAP("svadu", RISCV_ISA_EXT_SVADU) + SET_ISA_EXT_MAP("zfbfmin", RISCV_ISA_EXT_ZFBFMIN) + SET_ISA_EXT_MAP("zvfbfmin", RISCV_ISA_EXT_ZVFBFMIN) + SET_ISA_EXT_MAP("zvfbfwma", RISCV_ISA_EXT_ZVFBFWMA) + SET_ISA_EXT_MAP("zaamo", RISCV_ISA_EXT_ZAAMO) + SET_ISA_EXT_MAP("zalrsc", RISCV_ISA_EXT_ZALRSC) + SET_ISA_EXT_MAP("zicbop", RISCV_ISA_EXT_ZICBOP) + SET_ISA_EXT_MAP("ime", RISCV_ISA_EXT_IME) + if(!maskset) { printBug("parse_multi_letter_extension: Unknown multi-letter extension: %s", multi_letter_extension); return -1; @@ -94,7 +152,7 @@ bool valid_extension(char ext) { struct extensions* get_extensions_from_str(char* str) { struct extensions* ext = emalloc(sizeof(struct extensions)); - ext->mask = 0; + ext->mask = ecalloc(RISCV_ISA_EXT_ID_MAX, sizeof(bool)); ext->str = NULL; if(str == NULL) { @@ -107,6 +165,8 @@ struct extensions* get_extensions_from_str(char* str) { // Code inspired in Linux kernel (riscv_fill_hwcap): // https://elixir.bootlin.com/linux/v6.2.10/source/arch/riscv/kernel/cpufeature.c + // Now it seems to be here in riscv_parse_isa_string: + // https://elixir.bootlin.com/linux/v6.16/source/arch/riscv/kernel/cpufeature.c char* isa = str; if (!strncmp(isa, "rv32", 4)) isa += 4; @@ -138,7 +198,7 @@ struct extensions* get_extensions_from_str(char* str) { // adding it to the mask if(valid_extension(*e)) { int n = *e - 'a'; - ext->mask |= 1UL << n; + ext->mask[n] = true; } else { printBug("get_extensions_from_str: Invalid extension: '%c'", *e); @@ -149,6 +209,18 @@ struct extensions* get_extensions_from_str(char* str) { return ext; } +uint32_t get_num_extensions(bool* mask) { + uint32_t num = 0; + for (int i=0; i < RISCV_ISA_EXT_ID_MAX; i++) { + if (mask[i]) num++; + } + return num; +} + +bool is_mask_empty(bool* mask) { + return get_num_extensions(mask) == 0; +} + struct cpuInfo* get_cpu_info(void) { struct cpuInfo* cpu = malloc(sizeof(struct cpuInfo)); //init_cpu_info(cpu); @@ -161,7 +233,7 @@ struct cpuInfo* get_cpu_info(void) { cpu->hv = emalloc(sizeof(struct hypervisor)); cpu->hv->present = false; cpu->ext = get_extensions_from_str(ext_str); - if(cpu->ext->str != NULL && cpu->ext->mask == 0) return NULL; + if(cpu->ext->str != NULL && is_mask_empty(cpu->ext->mask)) return NULL; cpu->arch = get_uarch(cpu); cpu->soc = get_soc(cpu); cpu->freq = get_frequency_info(0); diff --git a/src/riscv/riscv.h b/src/riscv/riscv.h index 307a595..1c98a54 100644 --- a/src/riscv/riscv.h +++ b/src/riscv/riscv.h @@ -23,7 +23,6 @@ enum riscv_isa_ext_id { RISCV_ISA_EXT_ZICBOM, RISCV_ISA_EXT_ZIHINTPAUSE, RISCV_ISA_EXT_SVNAPOT, - RISCV_ISA_EXT_ZICBOP, RISCV_ISA_EXT_ZICBOZ, RISCV_ISA_EXT_SMAIA, RISCV_ISA_EXT_SSAIA, @@ -33,12 +32,74 @@ enum riscv_isa_ext_id { RISCV_ISA_EXT_ZICSR, RISCV_ISA_EXT_ZIFENCEI, RISCV_ISA_EXT_ZIHPM, + RISCV_ISA_EXT_SMSTATEEN, + RISCV_ISA_EXT_ZICOND, + RISCV_ISA_EXT_ZBC, + RISCV_ISA_EXT_ZBKB, + RISCV_ISA_EXT_ZBKC, + RISCV_ISA_EXT_ZBKX, + RISCV_ISA_EXT_ZKND, + RISCV_ISA_EXT_ZKNE, + RISCV_ISA_EXT_ZKNH, + RISCV_ISA_EXT_ZKR, + RISCV_ISA_EXT_ZKSED, + RISCV_ISA_EXT_ZKSH, + RISCV_ISA_EXT_ZKT, + RISCV_ISA_EXT_ZVBB, + RISCV_ISA_EXT_ZVBC, + RISCV_ISA_EXT_ZVKB, + RISCV_ISA_EXT_ZVKG, + RISCV_ISA_EXT_ZVKNED, + RISCV_ISA_EXT_ZVKNHA, + RISCV_ISA_EXT_ZVKNHB, + RISCV_ISA_EXT_ZVKSED, + RISCV_ISA_EXT_ZVKSH, + RISCV_ISA_EXT_ZVKT, + RISCV_ISA_EXT_ZFH, + RISCV_ISA_EXT_ZFHMIN, + RISCV_ISA_EXT_ZIHINTNTL, + RISCV_ISA_EXT_ZVFH, + RISCV_ISA_EXT_ZVFHMIN, + RISCV_ISA_EXT_ZFA, + RISCV_ISA_EXT_ZTSO, + RISCV_ISA_EXT_ZACAS, + RISCV_ISA_EXT_ZVE32X, + RISCV_ISA_EXT_ZVE32F, + RISCV_ISA_EXT_ZVE64X, + RISCV_ISA_EXT_ZVE64F, + RISCV_ISA_EXT_ZVE64D, + RISCV_ISA_EXT_ZIMOP, + RISCV_ISA_EXT_ZCA, + RISCV_ISA_EXT_ZCB, + RISCV_ISA_EXT_ZCD, + RISCV_ISA_EXT_ZCF, + RISCV_ISA_EXT_ZCMOP, + RISCV_ISA_EXT_ZAWRS, + RISCV_ISA_EXT_SVVPTC, + RISCV_ISA_EXT_SMMPM, + RISCV_ISA_EXT_SMNPM, + RISCV_ISA_EXT_SSNPM, + RISCV_ISA_EXT_ZABHA, + RISCV_ISA_EXT_ZICCRSE, + RISCV_ISA_EXT_SVADE, + RISCV_ISA_EXT_SVADU, + RISCV_ISA_EXT_ZFBFMIN, + RISCV_ISA_EXT_ZVFBFMIN, + RISCV_ISA_EXT_ZVFBFWMA, + RISCV_ISA_EXT_ZAAMO, + RISCV_ISA_EXT_ZALRSC, + RISCV_ISA_EXT_ZICBOP, + RISCV_ISA_EXT_IME, // This is not in the kernel! but it was seen on a Muse Pi Pro board RISCV_ISA_EXT_ID_MAX }; // https://five-embeddev.com/riscv-isa-manual/latest/preface.html#preface // https://en.wikichip.org/wiki/risc-v/standard_extensions // (Zicbop) https://github.com/riscv/riscv-CMOs/blob/master/cmobase/Zicbop.adoc +// https://raw.githubusercontent.com/riscv/riscv-CMOs/master/specifications/cmobase-v1.0.1.pdf +// https://www.kernel.org/doc/Documentation/devicetree/bindings/riscv/extensions.yaml +// https://gcc.gnu.org/onlinedocs/gcc/RISC-V-Options.html +// (Ime) https://github.com/riscv/integrated-matrix-extension (not confirmed, just a guess...) // Included all except for G static const struct extension extension_list[] = { { 'i' - 'a', "(I) Integer Instruction Set" }, @@ -74,12 +135,71 @@ static const struct extension extension_list[] = { { RISCV_ISA_EXT_ZICNTR, "(Zicntr) Base Counters and Timers" }, { RISCV_ISA_EXT_ZICSR, "(Zicsr) Control and Status Register" }, { RISCV_ISA_EXT_ZIFENCEI, "(Zifencei) Instruction-Fetch Fence" }, - { RISCV_ISA_EXT_ZIHPM, "(Zihpm) Hardware Performance Counters" } + { RISCV_ISA_EXT_ZIHPM, "(Zihpm) Hardware Performance Counters" }, + { RISCV_ISA_EXT_SMSTATEEN, "(Smstateen) Supervisor/Hypervisor State Enable" }, + { RISCV_ISA_EXT_ZICOND, "(Zicond) Integer Conditional Operations" }, + { RISCV_ISA_EXT_ZBC, "(Zbc) Carry-Less Multiplication" }, + { RISCV_ISA_EXT_ZBKB, "(Zbkb) Bit-Manipulation for Cryptography (Byte ops)" }, + { RISCV_ISA_EXT_ZBKC, "(Zbkc) Bit-Manipulation for Cryptography (Carry-less ops)" }, + { RISCV_ISA_EXT_ZBKX, "(Zbkx) Bit-Manipulation for Cryptography (Crossbar ops)" }, + { RISCV_ISA_EXT_ZKND, "(Zknd) NIST AES Decryption Instructions" }, + { RISCV_ISA_EXT_ZKNE, "(Zkne) NIST AES Encryption Instructions" }, + { RISCV_ISA_EXT_ZKNH, "(Zknh) NIST Hash (SHA-2/SHA-3) Instructions" }, + { RISCV_ISA_EXT_ZKR, "(Zkr) Entropy Source Reading (Random)" }, + { RISCV_ISA_EXT_ZKSED, "(Zksed) SM4 Block Cipher Decryption" }, + { RISCV_ISA_EXT_ZKSH, "(Zksh) SM3 Hash Instructions" }, + { RISCV_ISA_EXT_ZKT, "(Zkt) Data-Independent Execution Latency" }, + { RISCV_ISA_EXT_ZVBB, "(Zvbb) Vector Basic Bit-Manipulation" }, + { RISCV_ISA_EXT_ZVBC, "(Zvbc) Vector Carry-Less Multiplication" }, + { RISCV_ISA_EXT_ZVKB, "(Zvkb) Vector Cryptography (Byte ops)" }, + { RISCV_ISA_EXT_ZVKG, "(Zvkg) Vector GCM/GMAC Instructions" }, + { RISCV_ISA_EXT_ZVKNED, "(Zvkned) Vector AES Decryption" }, + { RISCV_ISA_EXT_ZVKNHA, "(Zvknha) Vector SHA-2 Hash (A variant)" }, + { RISCV_ISA_EXT_ZVKNHB, "(Zvknhb) Vector SHA-2 Hash (B variant)" }, + { RISCV_ISA_EXT_ZVKSED, "(Zvksed) Vector SM4 Block Cipher Decryption" }, + { RISCV_ISA_EXT_ZVKSH, "(Zvksh) Vector SM3 Hash Instructions" }, + { RISCV_ISA_EXT_ZVKT, "(Zvkt) Vector Data-Independent Execution Latency" }, + { RISCV_ISA_EXT_ZFH, "(Zfh) Half-Precision Floating Point" }, + { RISCV_ISA_EXT_ZFHMIN, "(Zfhmin) Minimal Half-Precision Floating Point" }, + { RISCV_ISA_EXT_ZIHINTNTL, "(Zihintntl) Non-Temporal Load/Store Hints" }, + { RISCV_ISA_EXT_ZVFH, "(Zvfh) Vector Half-Precision Floating Point" }, + { RISCV_ISA_EXT_ZVFHMIN, "(Zvfhmin) Minimal Vector Half-Precision Floating Point" }, + { RISCV_ISA_EXT_ZFA, "(Zfa) Additional Floating-Point Instructions" }, + { RISCV_ISA_EXT_ZTSO, "(Ztso) Total Store Ordering Memory Model" }, + { RISCV_ISA_EXT_ZACAS, "(Zacas) Atomic Compare-and-Swap" }, + { RISCV_ISA_EXT_ZVE32X, "(Zve32x) Embedded Vector Integer (32-bit elements)" }, + { RISCV_ISA_EXT_ZVE32F, "(Zve32f) Embedded Vector Floating Point (f32)" }, + { RISCV_ISA_EXT_ZVE64X, "(Zve64x) Embedded Vector Integer (64-bit elements)" }, + { RISCV_ISA_EXT_ZVE64F, "(Zve64f) Embedded Vector Floating Point (f64)" }, + { RISCV_ISA_EXT_ZVE64D, "(Zve64d) Embedded Vector Double-Precision FP (f64)" }, + { RISCV_ISA_EXT_ZIMOP, "(Zimop) Integer Multiply-Only Instructions" }, + { RISCV_ISA_EXT_ZCA, "(Zca) Compressed Integer Instructions" }, + { RISCV_ISA_EXT_ZCB, "(Zcb) Compressed Bit-Manipulation Instructions" }, + { RISCV_ISA_EXT_ZCD, "(Zcd) Compressed Double-Precision FP Instructions" }, + { RISCV_ISA_EXT_ZCF, "(Zcf) Compressed Single-Precision FP Instructions" }, + { RISCV_ISA_EXT_ZCMOP, "(Zcmop) Compressed Multiply-Only Instructions" }, + { RISCV_ISA_EXT_ZAWRS, "(Zawrs) Wait-on-Reservation-Set Instruction" }, + { RISCV_ISA_EXT_SVVPTC, "(Svvptc) Supervisor Virtual Page Table Cache Control" }, + { RISCV_ISA_EXT_SMMPM, "(Smmpm) Supervisor Memory Protection Modification" }, + { RISCV_ISA_EXT_SMNPM, "(Smnpm) Supervisor Non-Privileged Memory Access Control" }, + { RISCV_ISA_EXT_SSNPM, "(Ssnpm) Supervisor Secure Non-Privileged Memory" }, + { RISCV_ISA_EXT_ZABHA, "(Zabha) Atomic Byte/Halfword Operations" }, + { RISCV_ISA_EXT_ZICCRSE, "(Ziccrse) Cache Control Range Start/End Operations" }, + { RISCV_ISA_EXT_SVADE, "(Svade) Supervisor Virtual Address Deferred Exception" }, + { RISCV_ISA_EXT_SVADU, "(Svadu) Supervisor Virtual Address Dirty Update" }, + { RISCV_ISA_EXT_ZFBFMIN, "(Zfbfmin) Minimal BFloat16 Floating Point" }, + { RISCV_ISA_EXT_ZVFBFMIN, "(Zvfbfmin) Vector Minimal BFloat16 Floating Point" }, + { RISCV_ISA_EXT_ZVFBFWMA, "(Zvfbfwma) Vector BFloat16 Widening Multiply-Accumulate" }, + { RISCV_ISA_EXT_ZAAMO, "(Zaamo) Atomic Memory Operation (AMO) Instructions" }, + { RISCV_ISA_EXT_ZALRSC, "(Zalrsc) Atomic Load-Reserved/Store-Conditional" }, + { RISCV_ISA_EXT_ZICBOP, "(Zicbop) Cache Block Prefetch/Zero Operations" }, + { RISCV_ISA_EXT_IME, "(Ime) Integrated Matrix Extension" }, }; struct cpuInfo* get_cpu_info(void); char* get_str_topology(struct cpuInfo* cpu, struct topology* topo); char* get_str_extensions(struct cpuInfo* cpu); +uint32_t get_num_extensions(bool* mask); void print_debug(struct cpuInfo* cpu); #endif