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[v1.06][ARM] Update get_vpus_width to match SVE detection

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Dr-Noob
2024-09-02 08:26:58 +01:00
parent 057a36efd5
commit bd38951439
1 changed files with 15 additions and 21 deletions
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10
src/arm/uarch.c
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@@ -314,18 +314,13 @@ int get_vpus_width(struct cpuInfo* cpu) {
// If the CPU has NEON, width can be 64 or 128 [1]. // If the CPU has NEON, width can be 64 or 128 [1].
// In >= ARMv8, NEON are 128 bits width [2] // In >= ARMv8, NEON are 128 bits width [2]
// If the CPU has SVE/SVE2, width can be between 128-2048 [3], // If the CPU has SVE/SVE2, width can be between 128-2048 [3],
// so we must check the exact width depending on // so we get the exact value from cntb [4]
// the exact chip (Neoverse V1 uses 256b implementations.)
// //
// [1] https://en.wikipedia.org/wiki/ARM_architecture_family#Advanced_SIMD_(Neon) // [1] https://en.wikipedia.org/wiki/ARM_architecture_family#Advanced_SIMD_(Neon)
// [2] https://developer.arm.com/documentation/102474/0100/Fundamentals-of-Armv8-Neon-technology // [2] https://developer.arm.com/documentation/102474/0100/Fundamentals-of-Armv8-Neon-technology
// [3] https://www.anandtech.com/show/16640/arm-announces-neoverse-v1-n2-platforms-cpus-cmn700-mesh/5 // [3] https://www.anandtech.com/show/16640/arm-announces-neoverse-v1-n2-platforms-cpus-cmn700-mesh/5
// [4] https://developer.arm.com/documentation/ddi0596/2020-12/SVE-Instructions/CNTB--CNTD--CNTH--CNTW--Set-scalar-to-multiple-of-predicate-constraint-element-count-
MICROARCH ua = cpu->arch->uarch;
switch(ua) {
case UARCH_NEOVERSE_V1:
return 256;
default:
if (cpu->feat->SVE && cpu->feat->cntb > 0) { if (cpu->feat->SVE && cpu->feat->cntb > 0) {
return cpu->feat->cntb * 8; return cpu->feat->cntb * 8;
} }
@@ -341,7 +336,6 @@ int get_vpus_width(struct cpuInfo* cpu) {
return 32; return 32;
} }
} }
}
int get_number_of_vpus(struct cpuInfo* cpu) { int get_number_of_vpus(struct cpuInfo* cpu) {
MICROARCH ua = cpu->arch->uarch; MICROARCH ua = cpu->arch->uarch;