From bd3c66395d19808bcc75fe4ca17f2b434561abdb Mon Sep 17 00:00:00 2001 From: Dr-Noob Date: Fri, 22 Sep 2023 21:39:17 +0100 Subject: [PATCH] [v1.04][RISCV] Add multi-letter extensions to list --- src/riscv/riscv.c | 31 +++++++++++----------- src/riscv/riscv.h | 67 +++++++++++++++++++++++++++++------------------ 2 files changed, 58 insertions(+), 40 deletions(-) diff --git a/src/riscv/riscv.c b/src/riscv/riscv.c index e166f4c..a09af21 100644 --- a/src/riscv/riscv.c +++ b/src/riscv/riscv.c @@ -48,21 +48,22 @@ int parse_multi_letter_extension(struct extensions* ext, char* e) { char* multi_letter_extension = emalloc(multi_letter_extension_len); strncpy(multi_letter_extension, e+1, multi_letter_extension_len); - // TODO: Add more extensions - // https://en.wikipedia.org/wiki/RISC-V - SET_ISA_EXT_MAP("smaia", RISCV_ISA_EXT_SMAIA); - SET_ISA_EXT_MAP("ssaia", RISCV_ISA_EXT_SSAIA); - SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF); - SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC); - SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL); - SET_ISA_EXT_MAP("svnapot", RISCV_ISA_EXT_SVNAPOT); - SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT); - SET_ISA_EXT_MAP("zba", RISCV_ISA_EXT_ZBA); - SET_ISA_EXT_MAP("zbb", RISCV_ISA_EXT_ZBB); - SET_ISA_EXT_MAP("zbs", RISCV_ISA_EXT_ZBS); - SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM); - SET_ISA_EXT_MAP("zicboz", RISCV_ISA_EXT_ZICBOZ); - SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE); + // This should be up-to-date with + // https://elixir.bootlin.com/linux/latest/source/arch/riscv/kernel/cpufeature.c + // which should represent the list of extensions available in real chips + SET_ISA_EXT_MAP("smaia", RISCV_ISA_EXT_SMAIA) + SET_ISA_EXT_MAP("ssaia", RISCV_ISA_EXT_SSAIA) + SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF) + SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC) + SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL) + SET_ISA_EXT_MAP("svnapot", RISCV_ISA_EXT_SVNAPOT) + SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT) + SET_ISA_EXT_MAP("zba", RISCV_ISA_EXT_ZBA) + SET_ISA_EXT_MAP("zbb", RISCV_ISA_EXT_ZBB) + SET_ISA_EXT_MAP("zbs", RISCV_ISA_EXT_ZBS) + SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM) + SET_ISA_EXT_MAP("zicboz", RISCV_ISA_EXT_ZICBOZ) + SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE) else { printBug("parse_multi_letter_extension: Unknown multi-letter extension: %s", multi_letter_extension); return -1; diff --git a/src/riscv/riscv.h b/src/riscv/riscv.h index fc9f746..d6bc9b2 100644 --- a/src/riscv/riscv.h +++ b/src/riscv/riscv.h @@ -8,34 +8,12 @@ struct extension { char* str; }; -// https://en.wikichip.org/wiki/risc-v/standard_extensions -// Included all except for G -static const struct extension extension_list[] = { - { 'i' - 'a', "(I) Integer Instruction Set" }, - { 'm' - 'a', "(M) Integer Multiplication and Division" }, - { 'a' - 'a', "(A) Atomic Instructions" }, - { 'f' - 'a', "(F) Single-Precision Floating-Point" }, - { 'd' - 'a', "(D) Double-Precision Floating-Point" }, - { 'q' - 'a', "(Q) Quad-Precision Floating-Point" }, - { 'l' - 'a', "(L) Decimal Floating-Point" }, - { 'c' - 'a', "(C) Compressed Instructions" }, - { 'b' - 'a', "(B) Double-Precision Floating-Point" }, - { 'j' - 'a', "(J) Dynamically Translated Languages" }, - { 't' - 'a', "(T) Transactional Memory" }, - { 'p' - 'a', "(P) Packed-SIMD Instructions" }, - { 'v' - 'a', "(V) Vector Operations" }, - { 'n' - 'a', "(N) User-Level Interrupts" }, - { 'h' - 'a', "(H) Hypervisor" }, - { 's' - 'a', "(S) Supervisor-level Instructions" } -}; - -#define RISCV_ISA_EXT_MAX 64 #define RISCV_ISA_EXT_NAME_LEN_MAX 32 #define RISCV_ISA_EXT_BASE 26 +// https://elixir.bootlin.com/linux/latest/source/arch/riscv/include/asm/hwcap.h // This enum represent the logical ID for multi-letter RISC-V ISA extensions. -// The logical ID should start from RISCV_ISA_EXT_BASE and must not exceed -// RISCV_ISA_EXT_MAX. +// The logical ID should start from RISCV_ISA_EXT_BASE enum riscv_isa_ext_id { RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE, RISCV_ISA_EXT_SSTC, @@ -56,7 +34,46 @@ enum riscv_isa_ext_id { RISCV_ISA_EXT_ZIHPM, RISCV_ISA_EXT_ID_MAX }; -static_assert(RISCV_ISA_EXT_ID_MAX <= RISCV_ISA_EXT_MAX); + +// https://five-embeddev.com/riscv-isa-manual/latest/preface.html#preface +// https://en.wikichip.org/wiki/risc-v/standard_extensions +// Included all except for G +static const struct extension extension_list[] = { + { 'i' - 'a', "(I) Integer Instruction Set" }, + { 'm' - 'a', "(M) Integer Multiplication and Division" }, + { 'a' - 'a', "(A) Atomic Instructions" }, + { 'f' - 'a', "(F) Single-Precision Floating-Point" }, + { 'd' - 'a', "(D) Double-Precision Floating-Point" }, + { 'q' - 'a', "(Q) Quad-Precision Floating-Point" }, + { 'l' - 'a', "(L) Decimal Floating-Point" }, + { 'c' - 'a', "(C) Compressed Instructions" }, + { 'b' - 'a', "(B) Double-Precision Floating-Point" }, + { 'j' - 'a', "(J) Dynamically Translated Languages" }, + { 't' - 'a', "(T) Transactional Memory" }, + { 'p' - 'a', "(P) Packed-SIMD Instructions" }, + { 'v' - 'a', "(V) Vector Operations" }, + { 'n' - 'a', "(N) User-Level Interrupts" }, + { 'h' - 'a', "(H) Hypervisor" }, + { 's' - 'a', "(S) Supervisor-level Instructions" }, + // multi-letter extensions + { RISCV_ISA_EXT_SSCOFPMF, "(Sscofpmf) Count OverFlow and Privilege Mode Filtering" }, + { RISCV_ISA_EXT_SSTC, "(Sstc) S and VS level Time Compare" }, + { RISCV_ISA_EXT_SVINVAL, "(Svinval) Fast TLB Invalidation" }, + { RISCV_ISA_EXT_SVPBMT, "(Svpbmt) Page-based Memory Types" }, + { RISCV_ISA_EXT_ZBB, "(Zbb) Basic bit-manipulation" }, + { RISCV_ISA_EXT_ZICBOM, "(Zicbom) Cache Block Management Operations" }, + { RISCV_ISA_EXT_ZIHINTPAUSE, "(Zihintpause) Pause Hint" }, + { RISCV_ISA_EXT_SVNAPOT, "(Svnapot) Naturally Aligned Power of Two Pages" }, + { RISCV_ISA_EXT_ZICBOZ, "(Zicboz) Cache Block Zero Operations" }, + { RISCV_ISA_EXT_SMAIA, "(Smaia) Advanced Interrupt Architecture" }, + { RISCV_ISA_EXT_SSAIA, "(Ssaia) Advanced Interrupt Architecture" }, + { RISCV_ISA_EXT_ZBA, "(Zba) Address Generation" }, + { RISCV_ISA_EXT_ZBS, "(Zbs) Single-bit Instructions" }, + { RISCV_ISA_EXT_ZICNTR, "(Zicntr) Base Counters and Timers" }, + { RISCV_ISA_EXT_ZICSR, "(Zicsr) Control and Status Register" }, + { RISCV_ISA_EXT_ZIFENCEI, "(Zifencei) Instruction-Fetch Fence" }, + { RISCV_ISA_EXT_ZIHPM, "(Zihpm) Hardware Performance Counters" } +}; struct cpuInfo* get_cpu_info(void); char* get_str_topology(struct cpuInfo* cpu, struct topology* topo);