From bf7571605431c3319ba9d8dbfd580138e6600b8e Mon Sep 17 00:00:00 2001 From: Dr-Noob Date: Sun, 29 Aug 2021 09:52:54 +0200 Subject: [PATCH] [v1.00][ARM] Add Cortex X1 and Snapd 888+ in ARM detection --- src/arm/soc.c | 1 + src/arm/uarch.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/src/arm/soc.c b/src/arm/soc.c index 8e67e37..9cc5ce3 100644 --- a/src/arm/soc.c +++ b/src/arm/soc.c @@ -447,6 +447,7 @@ bool match_qualcomm(char* soc_name, struct system_on_chip* soc) { SOC_EQ(tmp, "SM8250", "865", SOC_SNAPD_SM8250, soc, 7) SOC_EQ(tmp, "SM8250-AB", "865+", SOC_SNAPD_SM8250_AB, soc, 7) SOC_EQ(tmp, "SM8350", "888", SOC_SNAPD_SM8350, soc, 5) + SOC_EQ(tmp, "SM8350-AC", "888+", SOC_SNAPD_SM8350, soc, 5) SOC_END } diff --git a/src/arm/uarch.c b/src/arm/uarch.c index d3d4d79..7fda404 100644 --- a/src/arm/uarch.c +++ b/src/arm/uarch.c @@ -64,6 +64,7 @@ enum { UARCH_CORTEX_A76, UARCH_CORTEX_A77, UARCH_CORTEX_A78, + UARCH_CORTEX_X1, UARCH_NEOVERSE_N1, UARCH_NEOVERSE_E1, UARCH_SCORPION, @@ -130,6 +131,7 @@ static const ISA isas_uarch[] = { [UARCH_CORTEX_A76] = ISA_ARMv8_2_A, [UARCH_CORTEX_A77] = ISA_ARMv8_2_A, [UARCH_CORTEX_A78] = ISA_ARMv8_2_A, + [UARCH_CORTEX_X1] = ISA_ARMv8_2_A, [UARCH_NEOVERSE_N1] = ISA_ARMv8_2_A, [UARCH_NEOVERSE_E1] = ISA_ARMv8_2_A, [UARCH_BRAHMA_B15] = ISA_ARMv7_A, // Same as Cortex-A15 @@ -236,6 +238,7 @@ struct uarch* get_uarch_from_midr(uint32_t midr, struct cpuInfo* cpu) { CHECK_UARCH(arch, cpu, 'A', 0xD0D, NA, NA, "Cortex-A77", UARCH_CORTEX_A77, CPU_VENDOR_ARM) CHECK_UARCH(arch, cpu, 'A', 0xD0E, NA, NA, "Cortex-A76", UARCH_CORTEX_A76, CPU_VENDOR_ARM) CHECK_UARCH(arch, cpu, 'A', 0xD41, NA, NA, "Cortex-A78", UARCH_CORTEX_A78, CPU_VENDOR_ARM) + CHECK_UARCH(arch, cpu, 'A', 0xD44, NA, NA, "Cortex-X1", UARCH_CORTEX_X1, CPU_VENDOR_ARM) CHECK_UARCH(arch, cpu, 'A', 0xD4A, NA, NA, "Neoverse E1", UARCH_NEOVERSE_E1, CPU_VENDOR_ARM) CHECK_UARCH(arch, cpu, 'B', 0x00F, NA, NA, "Brahma B15", UARCH_BRAHMA_B15, CPU_VENDOR_BROADCOM)