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https://github.com/Dr-Noob/cpufetch.git
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[v1.05] Implement new approach to infer SoC from the uarch. Add support for Kunpeng SoCs
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@@ -10,7 +10,6 @@
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// Data not available
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#define NA -1
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typedef uint32_t MICROARCH;
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typedef uint32_t ISA;
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struct uarch {
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@@ -37,89 +36,6 @@ enum {
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ISA_ARMv9_A
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};
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enum {
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UARCH_UNKNOWN,
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// ARM
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UARCH_ARM7,
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UARCH_ARM9,
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UARCH_ARM1136,
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UARCH_ARM1156,
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UARCH_ARM1176,
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UARCH_ARM11MPCORE,
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UARCH_CORTEX_A5,
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UARCH_CORTEX_A7,
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UARCH_CORTEX_A8,
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UARCH_CORTEX_A9,
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UARCH_CORTEX_A12,
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UARCH_CORTEX_A15,
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UARCH_CORTEX_A17,
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UARCH_CORTEX_A32,
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UARCH_CORTEX_A35,
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UARCH_CORTEX_A53,
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UARCH_CORTEX_A55r0, // ARM Cortex-A55 revision 0 (restricted dual-issue capabilities compared to revision 1+).
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UARCH_CORTEX_A55,
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UARCH_CORTEX_A57,
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UARCH_CORTEX_A65,
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UARCH_CORTEX_A72,
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UARCH_CORTEX_A73,
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UARCH_CORTEX_A75,
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UARCH_CORTEX_A76,
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UARCH_CORTEX_A77,
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UARCH_CORTEX_A78,
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UARCH_CORTEX_A510,
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UARCH_CORTEX_A710,
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UARCH_CORTEX_A715,
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UARCH_CORTEX_X1,
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UARCH_CORTEX_X2,
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UARCH_CORTEX_X3,
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UARCH_NEOVERSE_N1,
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UARCH_NEOVERSE_E1,
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UARCH_NEOVERSE_V1,
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UARCH_SCORPION,
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UARCH_KRAIT,
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UARCH_KYRO,
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UARCH_FALKOR,
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UARCH_SAPHIRA,
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UARCH_DENVER,
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UARCH_DENVER2,
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UARCH_CARMEL,
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// SAMSUNG
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UARCH_EXYNOS_M1, // Samsung Exynos M1 (Exynos 8890 big cores)
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UARCH_EXYNOS_M2, // Samsung Exynos M2 (Exynos 8895 big cores)
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UARCH_EXYNOS_M3, // Samsung Exynos M3 (Exynos 9810 big cores)
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UARCH_EXYNOS_M4, // Samsung Exynos M4 (Exynos 9820 big cores)
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UARCH_EXYNOS_M5, // Samsung Exynos M5 (Exynos 9830 big cores)
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// APPLE
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UARCH_SWIFT, // Apple A6 and A6X processors.
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UARCH_CYCLONE, // Apple A7 processor.
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UARCH_TYPHOON, // Apple A8 and A8X processor
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UARCH_TWISTER, // Apple A9 and A9X processor.
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UARCH_HURRICANE, // Apple A10 and A10X processor.
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UARCH_MONSOON, // Apple A11 processor (big cores).
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UARCH_MISTRAL, // Apple A11 processor (little cores).
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UARCH_VORTEX, // Apple A12 processor (big cores).
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UARCH_TEMPEST, // Apple A12 processor (big cores).
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UARCH_LIGHTNING, // Apple A13 processor (big cores).
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UARCH_THUNDER, // Apple A13 processor (little cores).
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UARCH_ICESTORM, // Apple M1 processor (little cores).
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UARCH_FIRESTORM, // Apple M1 processor (big cores).
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UARCH_BLIZZARD, // Apple M2 processor (little cores).
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UARCH_AVALANCHE, // Apple M2 processor (big cores).
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UARCH_SAWTOOTH, // Apple M3 processor (little cores).
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UARCH_EVEREST, // Apple M3 processor (big cores).
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// CAVIUM
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UARCH_THUNDERX, // Cavium ThunderX
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UARCH_THUNDERX2, // Cavium ThunderX2 (originally Broadcom Vulkan).
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// MARVELL
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UARCH_PJ4,
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UARCH_BRAHMA_B15,
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UARCH_BRAHMA_B53,
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UARCH_XGENE, // Applied Micro X-Gene.
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UARCH_TAISHAN_V110, // HiSilicon TaiShan v110 (Huawei Kunpeng 920 series processors).
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// PHYTIUM
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UARCH_XIAOMI, // Not to be confused with Xiaomi Inc
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};
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static const ISA isas_uarch[] = {
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[UARCH_ARM1136] = ISA_ARMv6,
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[UARCH_ARM1156] = ISA_ARMv6_T2,
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@@ -159,6 +75,7 @@ static const ISA isas_uarch[] = {
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[UARCH_THUNDERX] = ISA_ARMv8_A,
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[UARCH_THUNDERX2] = ISA_ARMv8_1_A,
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[UARCH_TAISHAN_V110] = ISA_ARMv8_2_A,
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[UARCH_TAISHAN_V200] = ISA_ARMv8_2_A, // Not confirmed
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[UARCH_DENVER] = ISA_ARMv8_A,
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[UARCH_DENVER2] = ISA_ARMv8_A,
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[UARCH_CARMEL] = ISA_ARMv8_A,
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@@ -284,8 +201,9 @@ struct uarch* get_uarch_from_midr(uint32_t midr, struct cpuInfo* cpu) {
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CHECK_UARCH(arch, cpu, 'C', 0x0A3, NA, NA, "ThunderX 81XX", UARCH_THUNDERX, CPU_VENDOR_CAVIUM)
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CHECK_UARCH(arch, cpu, 'C', 0x0AF, NA, NA, "ThunderX2 99XX", UARCH_THUNDERX2, CPU_VENDOR_CAVIUM)
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CHECK_UARCH(arch, cpu, 'H', 0xD01, NA, NA, "TaiShan v110", UARCH_TAISHAN_V110, CPU_VENDOR_HUAWUEI) // Kunpeng 920 series
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CHECK_UARCH(arch, cpu, 'H', 0xD40, NA, NA, "Cortex-A76", UARCH_CORTEX_A76, CPU_VENDOR_ARM) // Kirin 980 Big/Medium cores -> Cortex-A76
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CHECK_UARCH(arch, cpu, 'H', 0xD01, NA, NA, "TaiShan v110", UARCH_TAISHAN_V110, CPU_VENDOR_HUAWEI) // Kunpeng 920 series
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CHECK_UARCH(arch, cpu, 'H', 0xD02, NA, NA, "TaiShan v200", UARCH_TAISHAN_V200, CPU_VENDOR_HUAWEI) // Kunpeng 930 series (found in openeuler: https://mailweb.openeuler.org/hyperkitty/list/kernel@openeuler.org/message/XQCV7NX2UKRIUWUFKRF4PO3QENCOUFR3)
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CHECK_UARCH(arch, cpu, 'H', 0xD40, NA, NA, "Cortex-A76", UARCH_CORTEX_A76, CPU_VENDOR_ARM) // Kirin 980 Big/Medium cores -> Cortex-A76
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CHECK_UARCH(arch, cpu, 'N', 0x000, NA, NA, "Denver", UARCH_DENVER, CPU_VENDOR_NVIDIA)
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CHECK_UARCH(arch, cpu, 'N', 0x003, NA, NA, "Denver2", UARCH_DENVER2, CPU_VENDOR_NVIDIA)
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@@ -437,6 +355,10 @@ char* get_str_uarch(struct cpuInfo* cpu) {
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return cpu->arch->uarch_str;
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}
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MICROARCH get_uarch(struct uarch* arch) {
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return arch->uarch;
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}
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void free_uarch_struct(struct uarch* arch) {
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free(arch->uarch_str);
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free(arch);
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