From c4a7761a12978e7cc796e17a1b6b721720b125d8 Mon Sep 17 00:00:00 2001 From: Dr-Noob Date: Thu, 30 Oct 2025 19:28:34 +0100 Subject: [PATCH] Add description for missign extensions --- src/riscv/riscv.h | 109 +++++++++++++++++++++++----------------------- 1 file changed, 55 insertions(+), 54 deletions(-) diff --git a/src/riscv/riscv.h b/src/riscv/riscv.h index 407ad39..1c98a54 100644 --- a/src/riscv/riscv.h +++ b/src/riscv/riscv.h @@ -98,6 +98,7 @@ enum riscv_isa_ext_id { // (Zicbop) https://github.com/riscv/riscv-CMOs/blob/master/cmobase/Zicbop.adoc // https://raw.githubusercontent.com/riscv/riscv-CMOs/master/specifications/cmobase-v1.0.1.pdf // https://www.kernel.org/doc/Documentation/devicetree/bindings/riscv/extensions.yaml +// https://gcc.gnu.org/onlinedocs/gcc/RISC-V-Options.html // (Ime) https://github.com/riscv/integrated-matrix-extension (not confirmed, just a guess...) // Included all except for G static const struct extension extension_list[] = { @@ -135,63 +136,63 @@ static const struct extension extension_list[] = { { RISCV_ISA_EXT_ZICSR, "(Zicsr) Control and Status Register" }, { RISCV_ISA_EXT_ZIFENCEI, "(Zifencei) Instruction-Fetch Fence" }, { RISCV_ISA_EXT_ZIHPM, "(Zihpm) Hardware Performance Counters" }, - { RISCV_ISA_EXT_SMSTATEEN, "(Smstateen) " }, + { RISCV_ISA_EXT_SMSTATEEN, "(Smstateen) Supervisor/Hypervisor State Enable" }, { RISCV_ISA_EXT_ZICOND, "(Zicond) Integer Conditional Operations" }, { RISCV_ISA_EXT_ZBC, "(Zbc) Carry-Less Multiplication" }, - { RISCV_ISA_EXT_ZBKB, "(Zbkb) " }, - { RISCV_ISA_EXT_ZBKC, "(Zbkc) " }, - { RISCV_ISA_EXT_ZBKX, "(Zbkx) " }, - { RISCV_ISA_EXT_ZKND, "(Zknd) " }, - { RISCV_ISA_EXT_ZKNE, "(Zkne) " }, - { RISCV_ISA_EXT_ZKNH, "(Zknh) " }, - { RISCV_ISA_EXT_ZKR, "(Zkr) " }, - { RISCV_ISA_EXT_ZKSED, "(Zksed) " }, - { RISCV_ISA_EXT_ZKSH, "(Zksh) " }, + { RISCV_ISA_EXT_ZBKB, "(Zbkb) Bit-Manipulation for Cryptography (Byte ops)" }, + { RISCV_ISA_EXT_ZBKC, "(Zbkc) Bit-Manipulation for Cryptography (Carry-less ops)" }, + { RISCV_ISA_EXT_ZBKX, "(Zbkx) Bit-Manipulation for Cryptography (Crossbar ops)" }, + { RISCV_ISA_EXT_ZKND, "(Zknd) NIST AES Decryption Instructions" }, + { RISCV_ISA_EXT_ZKNE, "(Zkne) NIST AES Encryption Instructions" }, + { RISCV_ISA_EXT_ZKNH, "(Zknh) NIST Hash (SHA-2/SHA-3) Instructions" }, + { RISCV_ISA_EXT_ZKR, "(Zkr) Entropy Source Reading (Random)" }, + { RISCV_ISA_EXT_ZKSED, "(Zksed) SM4 Block Cipher Decryption" }, + { RISCV_ISA_EXT_ZKSH, "(Zksh) SM3 Hash Instructions" }, { RISCV_ISA_EXT_ZKT, "(Zkt) Data-Independent Execution Latency" }, - { RISCV_ISA_EXT_ZVBB, "(Zvbb) " }, - { RISCV_ISA_EXT_ZVBC, "(Zvbc) " }, - { RISCV_ISA_EXT_ZVKB, "(Zvkb) " }, - { RISCV_ISA_EXT_ZVKG, "(Zvkg) " }, - { RISCV_ISA_EXT_ZVKNED, "(Zvkned) " }, - { RISCV_ISA_EXT_ZVKNHA, "(Zvknha) " }, - { RISCV_ISA_EXT_ZVKNHB, "(Zvknhb) " }, - { RISCV_ISA_EXT_ZVKSED, "(Zvksed) " }, - { RISCV_ISA_EXT_ZVKSH, "(Zvksh) " }, - { RISCV_ISA_EXT_ZVKT, "(Zvkt) " }, - { RISCV_ISA_EXT_ZFH, "(Zfh) " }, - { RISCV_ISA_EXT_ZFHMIN, "(Zfhmin) " }, - { RISCV_ISA_EXT_ZIHINTNTL, "(Zihintntl) " }, - { RISCV_ISA_EXT_ZVFH, "(Zvfh) " }, - { RISCV_ISA_EXT_ZVFHMIN, "(Zvfhmin) " }, - { RISCV_ISA_EXT_ZFA, "(Zfa) " }, - { RISCV_ISA_EXT_ZTSO, "(Ztso) " }, - { RISCV_ISA_EXT_ZACAS, "(Zacas) " }, - { RISCV_ISA_EXT_ZVE32X, "(Zve32x) Vector Extensions (i32)" }, - { RISCV_ISA_EXT_ZVE32F, "(Zve32f) Vector Extensions (f32)" }, - { RISCV_ISA_EXT_ZVE64X, "(Zve64x) Vector Extensions (i64)" }, - { RISCV_ISA_EXT_ZVE64F, "(Zve64f) Vector Extensions (f64)" }, - { RISCV_ISA_EXT_ZVE64D, "(Zve64d) Vector Extensions (???)" }, - { RISCV_ISA_EXT_ZIMOP, "(Zimop) " }, - { RISCV_ISA_EXT_ZCA, "(Zca) " }, - { RISCV_ISA_EXT_ZCB, "(Zcb) " }, - { RISCV_ISA_EXT_ZCD, "(Zcd) " }, - { RISCV_ISA_EXT_ZCF, "(Zcf) " }, - { RISCV_ISA_EXT_ZCMOP, "(Zcmop) " }, - { RISCV_ISA_EXT_ZAWRS, "(Zawrs) " }, - { RISCV_ISA_EXT_SVVPTC, "(Svvptc) " }, - { RISCV_ISA_EXT_SMMPM, "(Smmpm) " }, - { RISCV_ISA_EXT_SMNPM, "(Smnpm) " }, - { RISCV_ISA_EXT_SSNPM, "(Ssnpm) " }, - { RISCV_ISA_EXT_ZABHA, "(Zabha) " }, - { RISCV_ISA_EXT_ZICCRSE, "(Ziccrse) " }, - { RISCV_ISA_EXT_SVADE, "(Svade) " }, - { RISCV_ISA_EXT_SVADU, "(Svadu) " }, - { RISCV_ISA_EXT_ZFBFMIN, "(Zfbfmin) " }, - { RISCV_ISA_EXT_ZVFBFMIN, "(Zvfbfmin) " }, - { RISCV_ISA_EXT_ZVFBFWMA, "(Zvfbfwma) " }, - { RISCV_ISA_EXT_ZAAMO, "(Zaamo) " }, - { RISCV_ISA_EXT_ZALRSC, "(Zalrsc) " }, - { RISCV_ISA_EXT_ZICBOP, "(Zicbop) " }, + { RISCV_ISA_EXT_ZVBB, "(Zvbb) Vector Basic Bit-Manipulation" }, + { RISCV_ISA_EXT_ZVBC, "(Zvbc) Vector Carry-Less Multiplication" }, + { RISCV_ISA_EXT_ZVKB, "(Zvkb) Vector Cryptography (Byte ops)" }, + { RISCV_ISA_EXT_ZVKG, "(Zvkg) Vector GCM/GMAC Instructions" }, + { RISCV_ISA_EXT_ZVKNED, "(Zvkned) Vector AES Decryption" }, + { RISCV_ISA_EXT_ZVKNHA, "(Zvknha) Vector SHA-2 Hash (A variant)" }, + { RISCV_ISA_EXT_ZVKNHB, "(Zvknhb) Vector SHA-2 Hash (B variant)" }, + { RISCV_ISA_EXT_ZVKSED, "(Zvksed) Vector SM4 Block Cipher Decryption" }, + { RISCV_ISA_EXT_ZVKSH, "(Zvksh) Vector SM3 Hash Instructions" }, + { RISCV_ISA_EXT_ZVKT, "(Zvkt) Vector Data-Independent Execution Latency" }, + { RISCV_ISA_EXT_ZFH, "(Zfh) Half-Precision Floating Point" }, + { RISCV_ISA_EXT_ZFHMIN, "(Zfhmin) Minimal Half-Precision Floating Point" }, + { RISCV_ISA_EXT_ZIHINTNTL, "(Zihintntl) Non-Temporal Load/Store Hints" }, + { RISCV_ISA_EXT_ZVFH, "(Zvfh) Vector Half-Precision Floating Point" }, + { RISCV_ISA_EXT_ZVFHMIN, "(Zvfhmin) Minimal Vector Half-Precision Floating Point" }, + { RISCV_ISA_EXT_ZFA, "(Zfa) Additional Floating-Point Instructions" }, + { RISCV_ISA_EXT_ZTSO, "(Ztso) Total Store Ordering Memory Model" }, + { RISCV_ISA_EXT_ZACAS, "(Zacas) Atomic Compare-and-Swap" }, + { RISCV_ISA_EXT_ZVE32X, "(Zve32x) Embedded Vector Integer (32-bit elements)" }, + { RISCV_ISA_EXT_ZVE32F, "(Zve32f) Embedded Vector Floating Point (f32)" }, + { RISCV_ISA_EXT_ZVE64X, "(Zve64x) Embedded Vector Integer (64-bit elements)" }, + { RISCV_ISA_EXT_ZVE64F, "(Zve64f) Embedded Vector Floating Point (f64)" }, + { RISCV_ISA_EXT_ZVE64D, "(Zve64d) Embedded Vector Double-Precision FP (f64)" }, + { RISCV_ISA_EXT_ZIMOP, "(Zimop) Integer Multiply-Only Instructions" }, + { RISCV_ISA_EXT_ZCA, "(Zca) Compressed Integer Instructions" }, + { RISCV_ISA_EXT_ZCB, "(Zcb) Compressed Bit-Manipulation Instructions" }, + { RISCV_ISA_EXT_ZCD, "(Zcd) Compressed Double-Precision FP Instructions" }, + { RISCV_ISA_EXT_ZCF, "(Zcf) Compressed Single-Precision FP Instructions" }, + { RISCV_ISA_EXT_ZCMOP, "(Zcmop) Compressed Multiply-Only Instructions" }, + { RISCV_ISA_EXT_ZAWRS, "(Zawrs) Wait-on-Reservation-Set Instruction" }, + { RISCV_ISA_EXT_SVVPTC, "(Svvptc) Supervisor Virtual Page Table Cache Control" }, + { RISCV_ISA_EXT_SMMPM, "(Smmpm) Supervisor Memory Protection Modification" }, + { RISCV_ISA_EXT_SMNPM, "(Smnpm) Supervisor Non-Privileged Memory Access Control" }, + { RISCV_ISA_EXT_SSNPM, "(Ssnpm) Supervisor Secure Non-Privileged Memory" }, + { RISCV_ISA_EXT_ZABHA, "(Zabha) Atomic Byte/Halfword Operations" }, + { RISCV_ISA_EXT_ZICCRSE, "(Ziccrse) Cache Control Range Start/End Operations" }, + { RISCV_ISA_EXT_SVADE, "(Svade) Supervisor Virtual Address Deferred Exception" }, + { RISCV_ISA_EXT_SVADU, "(Svadu) Supervisor Virtual Address Dirty Update" }, + { RISCV_ISA_EXT_ZFBFMIN, "(Zfbfmin) Minimal BFloat16 Floating Point" }, + { RISCV_ISA_EXT_ZVFBFMIN, "(Zvfbfmin) Vector Minimal BFloat16 Floating Point" }, + { RISCV_ISA_EXT_ZVFBFWMA, "(Zvfbfwma) Vector BFloat16 Widening Multiply-Accumulate" }, + { RISCV_ISA_EXT_ZAAMO, "(Zaamo) Atomic Memory Operation (AMO) Instructions" }, + { RISCV_ISA_EXT_ZALRSC, "(Zalrsc) Atomic Load-Reserved/Store-Conditional" }, + { RISCV_ISA_EXT_ZICBOP, "(Zicbop) Cache Block Prefetch/Zero Operations" }, { RISCV_ISA_EXT_IME, "(Ime) Integrated Matrix Extension" }, };