From d36123a363fcf22652c105b756b2dd2efe25abf5 Mon Sep 17 00:00:00 2001 From: Dr-Noob Date: Thu, 30 Oct 2025 09:07:04 +0100 Subject: [PATCH] Completing extension strings... --- src/riscv/riscv.h | 120 +++++++++++++++++++++++----------------------- 1 file changed, 61 insertions(+), 59 deletions(-) diff --git a/src/riscv/riscv.h b/src/riscv/riscv.h index 310253f..407ad39 100644 --- a/src/riscv/riscv.h +++ b/src/riscv/riscv.h @@ -89,7 +89,7 @@ enum riscv_isa_ext_id { RISCV_ISA_EXT_ZAAMO, RISCV_ISA_EXT_ZALRSC, RISCV_ISA_EXT_ZICBOP, - RISCV_ISA_EXT_IME, + RISCV_ISA_EXT_IME, // This is not in the kernel! but it was seen on a Muse Pi Pro board RISCV_ISA_EXT_ID_MAX }; @@ -97,6 +97,8 @@ enum riscv_isa_ext_id { // https://en.wikichip.org/wiki/risc-v/standard_extensions // (Zicbop) https://github.com/riscv/riscv-CMOs/blob/master/cmobase/Zicbop.adoc // https://raw.githubusercontent.com/riscv/riscv-CMOs/master/specifications/cmobase-v1.0.1.pdf +// https://www.kernel.org/doc/Documentation/devicetree/bindings/riscv/extensions.yaml +// (Ime) https://github.com/riscv/integrated-matrix-extension (not confirmed, just a guess...) // Included all except for G static const struct extension extension_list[] = { { 'i' - 'a', "(I) Integer Instruction Set" }, @@ -133,64 +135,64 @@ static const struct extension extension_list[] = { { RISCV_ISA_EXT_ZICSR, "(Zicsr) Control and Status Register" }, { RISCV_ISA_EXT_ZIFENCEI, "(Zifencei) Instruction-Fetch Fence" }, { RISCV_ISA_EXT_ZIHPM, "(Zihpm) Hardware Performance Counters" }, - { RISCV_ISA_EXT_SMSTATEEN, "(smstateen) " }, - { RISCV_ISA_EXT_ZICOND, "(zicond) " }, - { RISCV_ISA_EXT_ZBC, "(zbc) " }, - { RISCV_ISA_EXT_ZBKB, "(zbkb) " }, - { RISCV_ISA_EXT_ZBKC, "(zbkc) " }, - { RISCV_ISA_EXT_ZBKX, "(zbkx) " }, - { RISCV_ISA_EXT_ZKND, "(zknd) " }, - { RISCV_ISA_EXT_ZKNE, "(zkne) " }, - { RISCV_ISA_EXT_ZKNH, "(zknh) " }, - { RISCV_ISA_EXT_ZKR, "(zkr) " }, - { RISCV_ISA_EXT_ZKSED, "(zksed) " }, - { RISCV_ISA_EXT_ZKSH, "(zksh) " }, - { RISCV_ISA_EXT_ZKT, "(zkt) " }, - { RISCV_ISA_EXT_ZVBB, "(zvbb) " }, - { RISCV_ISA_EXT_ZVBC, "(zvbc) " }, - { RISCV_ISA_EXT_ZVKB, "(zvkb) " }, - { RISCV_ISA_EXT_ZVKG, "(zvkg) " }, - { RISCV_ISA_EXT_ZVKNED, "(zvkned) " }, - { RISCV_ISA_EXT_ZVKNHA, "(zvknha) " }, - { RISCV_ISA_EXT_ZVKNHB, "(zvknhb) " }, - { RISCV_ISA_EXT_ZVKSED, "(zvksed) " }, - { RISCV_ISA_EXT_ZVKSH, "(zvksh) " }, - { RISCV_ISA_EXT_ZVKT, "(zvkt) " }, - { RISCV_ISA_EXT_ZFH, "(zfh) " }, - { RISCV_ISA_EXT_ZFHMIN, "(zfhmin) " }, - { RISCV_ISA_EXT_ZIHINTNTL, "(zihintntl) " }, - { RISCV_ISA_EXT_ZVFH, "(zvfh) " }, - { RISCV_ISA_EXT_ZVFHMIN, "(zvfhmin) " }, - { RISCV_ISA_EXT_ZFA, "(zfa) " }, - { RISCV_ISA_EXT_ZTSO, "(ztso) " }, - { RISCV_ISA_EXT_ZACAS, "(zacas) " }, - { RISCV_ISA_EXT_ZVE32X, "(zve32x) " }, - { RISCV_ISA_EXT_ZVE32F, "(zve32f) " }, - { RISCV_ISA_EXT_ZVE64X, "(zve64x) " }, - { RISCV_ISA_EXT_ZVE64F, "(zve64f) " }, - { RISCV_ISA_EXT_ZVE64D, "(zve64d) " }, - { RISCV_ISA_EXT_ZIMOP, "(zimop) " }, - { RISCV_ISA_EXT_ZCA, "(zca) " }, - { RISCV_ISA_EXT_ZCB, "(zcb) " }, - { RISCV_ISA_EXT_ZCD, "(zcd) " }, - { RISCV_ISA_EXT_ZCF, "(zcf) " }, - { RISCV_ISA_EXT_ZCMOP, "(zcmop) " }, - { RISCV_ISA_EXT_ZAWRS, "(zawrs) " }, - { RISCV_ISA_EXT_SVVPTC, "(svvptc) " }, - { RISCV_ISA_EXT_SMMPM, "(smmpm) " }, - { RISCV_ISA_EXT_SMNPM, "(smnpm) " }, - { RISCV_ISA_EXT_SSNPM, "(ssnpm) " }, - { RISCV_ISA_EXT_ZABHA, "(zabha) " }, - { RISCV_ISA_EXT_ZICCRSE, "(ziccrse) " }, - { RISCV_ISA_EXT_SVADE, "(svade) " }, - { RISCV_ISA_EXT_SVADU, "(svadu) " }, - { RISCV_ISA_EXT_ZFBFMIN, "(zfbfmin) " }, - { RISCV_ISA_EXT_ZVFBFMIN, "(zvfbfmin) " }, - { RISCV_ISA_EXT_ZVFBFWMA, "(zvfbfwma) " }, - { RISCV_ISA_EXT_ZAAMO, "(zaamo) " }, - { RISCV_ISA_EXT_ZALRSC, "(zalrsc) " }, - { RISCV_ISA_EXT_ZICBOP, "(zicbop) " }, - { RISCV_ISA_EXT_IME, "(ime) Integrated Matrix Extension" }, + { RISCV_ISA_EXT_SMSTATEEN, "(Smstateen) " }, + { RISCV_ISA_EXT_ZICOND, "(Zicond) Integer Conditional Operations" }, + { RISCV_ISA_EXT_ZBC, "(Zbc) Carry-Less Multiplication" }, + { RISCV_ISA_EXT_ZBKB, "(Zbkb) " }, + { RISCV_ISA_EXT_ZBKC, "(Zbkc) " }, + { RISCV_ISA_EXT_ZBKX, "(Zbkx) " }, + { RISCV_ISA_EXT_ZKND, "(Zknd) " }, + { RISCV_ISA_EXT_ZKNE, "(Zkne) " }, + { RISCV_ISA_EXT_ZKNH, "(Zknh) " }, + { RISCV_ISA_EXT_ZKR, "(Zkr) " }, + { RISCV_ISA_EXT_ZKSED, "(Zksed) " }, + { RISCV_ISA_EXT_ZKSH, "(Zksh) " }, + { RISCV_ISA_EXT_ZKT, "(Zkt) Data-Independent Execution Latency" }, + { RISCV_ISA_EXT_ZVBB, "(Zvbb) " }, + { RISCV_ISA_EXT_ZVBC, "(Zvbc) " }, + { RISCV_ISA_EXT_ZVKB, "(Zvkb) " }, + { RISCV_ISA_EXT_ZVKG, "(Zvkg) " }, + { RISCV_ISA_EXT_ZVKNED, "(Zvkned) " }, + { RISCV_ISA_EXT_ZVKNHA, "(Zvknha) " }, + { RISCV_ISA_EXT_ZVKNHB, "(Zvknhb) " }, + { RISCV_ISA_EXT_ZVKSED, "(Zvksed) " }, + { RISCV_ISA_EXT_ZVKSH, "(Zvksh) " }, + { RISCV_ISA_EXT_ZVKT, "(Zvkt) " }, + { RISCV_ISA_EXT_ZFH, "(Zfh) " }, + { RISCV_ISA_EXT_ZFHMIN, "(Zfhmin) " }, + { RISCV_ISA_EXT_ZIHINTNTL, "(Zihintntl) " }, + { RISCV_ISA_EXT_ZVFH, "(Zvfh) " }, + { RISCV_ISA_EXT_ZVFHMIN, "(Zvfhmin) " }, + { RISCV_ISA_EXT_ZFA, "(Zfa) " }, + { RISCV_ISA_EXT_ZTSO, "(Ztso) " }, + { RISCV_ISA_EXT_ZACAS, "(Zacas) " }, + { RISCV_ISA_EXT_ZVE32X, "(Zve32x) Vector Extensions (i32)" }, + { RISCV_ISA_EXT_ZVE32F, "(Zve32f) Vector Extensions (f32)" }, + { RISCV_ISA_EXT_ZVE64X, "(Zve64x) Vector Extensions (i64)" }, + { RISCV_ISA_EXT_ZVE64F, "(Zve64f) Vector Extensions (f64)" }, + { RISCV_ISA_EXT_ZVE64D, "(Zve64d) Vector Extensions (???)" }, + { RISCV_ISA_EXT_ZIMOP, "(Zimop) " }, + { RISCV_ISA_EXT_ZCA, "(Zca) " }, + { RISCV_ISA_EXT_ZCB, "(Zcb) " }, + { RISCV_ISA_EXT_ZCD, "(Zcd) " }, + { RISCV_ISA_EXT_ZCF, "(Zcf) " }, + { RISCV_ISA_EXT_ZCMOP, "(Zcmop) " }, + { RISCV_ISA_EXT_ZAWRS, "(Zawrs) " }, + { RISCV_ISA_EXT_SVVPTC, "(Svvptc) " }, + { RISCV_ISA_EXT_SMMPM, "(Smmpm) " }, + { RISCV_ISA_EXT_SMNPM, "(Smnpm) " }, + { RISCV_ISA_EXT_SSNPM, "(Ssnpm) " }, + { RISCV_ISA_EXT_ZABHA, "(Zabha) " }, + { RISCV_ISA_EXT_ZICCRSE, "(Ziccrse) " }, + { RISCV_ISA_EXT_SVADE, "(Svade) " }, + { RISCV_ISA_EXT_SVADU, "(Svadu) " }, + { RISCV_ISA_EXT_ZFBFMIN, "(Zfbfmin) " }, + { RISCV_ISA_EXT_ZVFBFMIN, "(Zvfbfmin) " }, + { RISCV_ISA_EXT_ZVFBFWMA, "(Zvfbfwma) " }, + { RISCV_ISA_EXT_ZAAMO, "(Zaamo) " }, + { RISCV_ISA_EXT_ZALRSC, "(Zalrsc) " }, + { RISCV_ISA_EXT_ZICBOP, "(Zicbop) " }, + { RISCV_ISA_EXT_IME, "(Ime) Integrated Matrix Extension" }, }; struct cpuInfo* get_cpu_info(void);