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Fix #23. I tried fetching the cache topology in AMD but could not find a proper way, so the code fallback to two commits ago. cpufetch has to guess cache sizes except L3, which can be fetched. Since I have been trying many approaches and stuff, the code needs to be refactored

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Dr-Noob
2020-08-30 12:12:25 +02:00
parent 69cc08759a
commit dae0f678ad
5 changed files with 96 additions and 64 deletions
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src/apic.h
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@@ -14,7 +14,7 @@ struct apic {
uint32_t* cache_id_apic;
};
bool get_topology_from_apic(uint32_t cpuid_max_levels, struct topology** topo);
bool get_topology_from_apic(struct cpuInfo* cpu, struct topology** topo);
uint32_t is_smt_enabled(struct topology* topo);
#endif