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[v0.98] Use malloc/calloc wrapper that exits when alloc fails, as suggested by #90

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Dr-Noob
2021-08-04 09:58:00 +02:00
parent 3a636c101b
commit eac97bf721
15 changed files with 631 additions and 605 deletions
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100
src/arm/midr.c
View File

@@ -16,12 +16,12 @@
#define STRING_UNKNOWN "Unknown"
void init_cache_struct(struct cache* cach) {
cach->L1i = malloc(sizeof(struct cach));
cach->L1d = malloc(sizeof(struct cach));
cach->L2 = malloc(sizeof(struct cach));
cach->L3 = malloc(sizeof(struct cach));
cach->L1i = emalloc(sizeof(struct cach));
cach->L1d = emalloc(sizeof(struct cach));
cach->L2 = emalloc(sizeof(struct cach));
cach->L3 = emalloc(sizeof(struct cach));
cach->cach_arr = malloc(sizeof(struct cach*) * 4);
cach->cach_arr = emalloc(sizeof(struct cach*) * 4);
cach->cach_arr[0] = cach->L1i;
cach->cach_arr[1] = cach->L1d;
cach->cach_arr[2] = cach->L2;
@@ -34,8 +34,8 @@ void init_cache_struct(struct cache* cach) {
cach->L3->exists = false;
}
struct cache* get_cache_info(struct cpuInfo* cpu) {
struct cache* cach = malloc(sizeof(struct cache));
struct cache* get_cache_info(struct cpuInfo* cpu) {
struct cache* cach = emalloc(sizeof(struct cache));
init_cache_struct(cach);
cach->max_cache_level = 2;
@@ -49,7 +49,7 @@ struct cache* get_cache_info(struct cpuInfo* cpu) {
}
struct frequency* get_frequency_info(uint32_t core) {
struct frequency* freq = malloc(sizeof(struct frequency));
struct frequency* freq = emalloc(sizeof(struct frequency));
freq->base = UNKNOWN_FREQ;
freq->max = get_max_freq_from_file(core, false);
@@ -58,36 +58,36 @@ struct frequency* get_frequency_info(uint32_t core) {
}
struct topology* get_topology_info(struct cpuInfo* cpu, struct cache* cach, uint32_t* midr_array, int socket_idx, int ncores) {
struct topology* topo = malloc(sizeof(struct topology));
struct topology* topo = emalloc(sizeof(struct topology));
topo->cach = cach;
topo->total_cores = 0;
int sockets_seen = 0;
int first_core_idx = 0;
int currrent_core_idx = 0;
int cores_in_socket = 0;
while(socket_idx + 1 > sockets_seen) {
if(midr_array[first_core_idx] == midr_array[currrent_core_idx] && currrent_core_idx < ncores) {
currrent_core_idx++;
cores_in_socket++;
}
else {
topo->total_cores = cores_in_socket;
topo->total_cores = cores_in_socket;
cores_in_socket = 0;
first_core_idx = currrent_core_idx;
sockets_seen++;
}
}
return topo;
}
bool cores_are_equal(int c1pos, int c2pos, uint32_t* midr_array, int32_t* freq_array) {
return midr_array[c1pos] == midr_array[c2pos] && freq_array[c1pos] == freq_array[c2pos];
}
uint32_t fill_ids_from_midr(uint32_t* midr_array, int32_t* freq_array, uint32_t* ids_array, int len) {
uint32_t latest_id = 0;
bool found;
@@ -128,17 +128,17 @@ void init_cpu_info(struct cpuInfo* cpu) {
// ARM32 https://elixir.bootlin.com/linux/latest/source/arch/arm/include/uapi/asm/hwcap.h
// ARM64 https://elixir.bootlin.com/linux/latest/source/arch/arm64/include/uapi/asm/hwcap.h
struct features* get_features_info() {
struct features* feat = malloc(sizeof(struct features));
struct features* feat = emalloc(sizeof(struct features));
bool *ptr = &(feat->AES);
for(uint32_t i = 0; i < sizeof(struct features)/sizeof(bool); i++, ptr++) {
*ptr = false;
}
errno = 0;
long hwcaps = getauxval(AT_HWCAP);
if(errno == ENOENT) {
printWarn("Unable to retrieve AT_HWCAP using getauxval");
printWarn("Unable to retrieve AT_HWCAP using getauxval");
}
#ifdef __aarch64__
else {
@@ -152,7 +152,7 @@ struct features* get_features_info() {
else {
feat->NEON = hwcaps & HWCAP_NEON;
}
hwcaps = getauxval(AT_HWCAP2);
if(errno == ENOENT) {
printWarn("Unable to retrieve AT_HWCAP2 using getauxval");
@@ -169,77 +169,77 @@ struct features* get_features_info() {
}
struct cpuInfo* get_cpu_info() {
struct cpuInfo* cpu = malloc(sizeof(struct cpuInfo));
struct cpuInfo* cpu = emalloc(sizeof(struct cpuInfo));
init_cpu_info(cpu);
int ncores = get_ncores_from_cpuinfo();
bool success = false;
int32_t* freq_array = malloc(sizeof(uint32_t) * ncores);
uint32_t* midr_array = malloc(sizeof(uint32_t) * ncores);
uint32_t* ids_array = malloc(sizeof(uint32_t) * ncores);
int32_t* freq_array = emalloc(sizeof(uint32_t) * ncores);
uint32_t* midr_array = emalloc(sizeof(uint32_t) * ncores);
uint32_t* ids_array = emalloc(sizeof(uint32_t) * ncores);
for(int i=0; i < ncores; i++) {
midr_array[i] = get_midr_from_cpuinfo(i, &success);
if(!success) {
printWarn("Unable to fetch MIDR for core %d. This is probably because the core is offline", i);
midr_array[i] = midr_array[0];
}
freq_array[i] = get_max_freq_from_file(i, false);
if(freq_array[i] == UNKNOWN_FREQ) {
printWarn("Unable to fetch max frequency for core %d. This is probably because the core is offline", i);
freq_array[i] = freq_array[0];
}
}
}
uint32_t sockets = fill_ids_from_midr(midr_array, freq_array, ids_array, ncores);
struct cpuInfo* ptr = cpu;
int midr_idx = 0;
int tmp_midr_idx = 0;
for(uint32_t i=0; i < sockets; i++) {
if(i > 0) {
ptr->next_cpu = malloc(sizeof(struct cpuInfo));
ptr->next_cpu = emalloc(sizeof(struct cpuInfo));
ptr = ptr->next_cpu;
init_cpu_info(ptr);
tmp_midr_idx = midr_idx;
while(cores_are_equal(midr_idx, tmp_midr_idx, midr_array, freq_array)) tmp_midr_idx++;
midr_idx = tmp_midr_idx;
}
}
ptr->midr = midr_array[midr_idx];
ptr->arch = get_uarch_from_midr(ptr->midr, ptr);
ptr->feat = get_features_info();
ptr->freq = get_frequency_info(midr_idx);
ptr->cach = get_cache_info(ptr);
ptr->topo = get_topology_info(ptr, ptr->cach, midr_array, i, ncores);
}
cpu->num_cpus = sockets;
cpu->hv = malloc(sizeof(struct hypervisor));
cpu->hv = emalloc(sizeof(struct hypervisor));
cpu->hv->present = false;
cpu->soc = get_soc();
cpu->soc = get_soc();
return cpu;
}
char* get_str_topology(struct cpuInfo* cpu, struct topology* topo, bool dual_socket) {
uint32_t size = 3+7+1;
char* string = malloc(sizeof(char)*size);
char* string = emalloc(sizeof(char)*size);
snprintf(string, size, "%d cores", topo->total_cores);
return string;
}
char* get_str_peak_performance(struct cpuInfo* cpu) {
char* get_str_peak_performance(struct cpuInfo* cpu) {
//7 for GFLOP/s and 6 for digits,eg 412.14
uint32_t size = 7+6+1+1;
assert(strlen(STRING_UNKNOWN)+1 <= size);
char* string = malloc(sizeof(char)*size);
char* string = emalloc(sizeof(char)*size);
struct cpuInfo* ptr = cpu;
//First check we have consistent data
for(int i=0; i < cpu->num_cpus; ptr = ptr->next_cpu, i++) {
if(get_freq(ptr->freq) == UNKNOWN_FREQ) {
@@ -249,13 +249,13 @@ char* get_str_peak_performance(struct cpuInfo* cpu) {
}
double flops = 0.0;
ptr = cpu;
for(int i=0; i < cpu->num_cpus; ptr = ptr->next_cpu, i++) {
flops += ptr->topo->total_cores * (get_freq(ptr->freq) * 1000000);
}
if(cpu->feat->NEON) flops = flops * 4;
if(flops >= (double)1000000000000.0)
snprintf(string,size,"%.2f TFLOP/s",flops/1000000000000);
else if(flops >= 1000000000.0)
@@ -267,10 +267,10 @@ char* get_str_peak_performance(struct cpuInfo* cpu) {
}
char* get_str_features(struct cpuInfo* cpu) {
struct features* feat = cpu->feat;
char* string = malloc(sizeof(char) * 25);
struct features* feat = cpu->feat;
char* string = emalloc(sizeof(char) * 25);
uint32_t len = 0;
if(feat->NEON) {
strcat(string, "NEON,");
len += 5;
@@ -291,19 +291,19 @@ char* get_str_features(struct cpuInfo* cpu) {
strcat(string, "CRC32,");
len += 6;
}
if(len > 0) {
string[len-1] = '\0';
return string;
}
else
return NULL;
else
return NULL;
}
void print_debug(struct cpuInfo* cpu) {
int ncores = get_ncores_from_cpuinfo();
bool success = false;
for(int i=0; i < ncores; i++) {
printf("[Core %d] ", i);
long freq = get_max_freq_from_file(i, false);
@@ -313,16 +313,16 @@ void print_debug(struct cpuInfo* cpu) {
printf("0x%.8X ", get_midr_from_cpuinfo(0, &success));
}
else {
printf("0x%.8X ", midr);
printf("0x%.8X ", midr);
}
if(freq == UNKNOWN_FREQ) {
printWarn("Unable to fetch max frequency for core %d. This is probably because the core is offline", i);
printf("%ld MHz\n", get_max_freq_from_file(0, false));
}
else {
printf("%ld MHz\n", freq);
printf("%ld MHz\n", freq);
}
}
}
}
void free_topo_struct(struct topology* topo) {

167
src/arm/soc.c
View File

@@ -32,34 +32,34 @@ void fill_soc(struct system_on_chip* soc, char* soc_name, SOC soc_model, int32_t
soc->soc_vendor = get_soc_vendor_from_soc(soc_model);
soc->process = process;
int len = strlen(soc_name) + strlen(soc_trademark_string[soc->soc_vendor]) + 1;
soc->soc_name = malloc(sizeof(char) * len);
soc->soc_name = emalloc(sizeof(char) * len);
memset(soc->soc_name, 0, sizeof(char) * len);
sprintf(soc->soc_name, "%s%s", soc_trademark_string[soc->soc_vendor], soc_name);
sprintf(soc->soc_name, "%s%s", soc_trademark_string[soc->soc_vendor], soc_name);
}
bool match_soc(struct system_on_chip* soc, char* raw_name, char* expected_name, char* soc_name, SOC soc_model, int32_t process) {
if(strlen(raw_name) > strlen(expected_name))
return false;
int len = strlen(raw_name);
if(strncmp(raw_name, expected_name, len) != 0) {
return false;
}
else {
fill_soc(soc, soc_name, soc_model, process);
return true;
return true;
}
}
char* toupperstr(char* str) {
int len = strlen(str) + 1;
char* ret = malloc(sizeof(char) * len);
char* ret = emalloc(sizeof(char) * len);
memset(ret, 0, sizeof(char) * len);
for(int i=0; i < len; i++) {
ret[i] = toupper((unsigned char) str[i]);
ret[i] = toupper((unsigned char) str[i]);
}
return ret;
}
@@ -82,22 +82,22 @@ bool match_broadcom(char* soc_name, struct system_on_chip* soc) {
if((tmp = strstr(soc_name, "BCM")) == NULL)
return false;
SOC_START
SOC_EQ(tmp, "BCM2835", "2835", SOC_BCM_2835, soc, 65)
SOC_EQ(tmp, "BCM2836", "2836", SOC_BCM_2836, soc, 40)
SOC_EQ(tmp, "BCM2837", "2837", SOC_BCM_2837, soc, 40)
SOC_EQ(tmp, "BCM2837B0", "2837B0", SOC_BCM_2837B0, soc, 40)
SOC_EQ(tmp, "BCM2711", "2711", SOC_BCM_2711, soc, 28)
SOC_EQ(tmp, "BCM21553", "21553", SOC_BCM_21553, soc, 65)
SOC_EQ(tmp, "BCM21553-Thunderbird", "21553 Thunderbird", SOC_BCM_21553T, soc, 65)
SOC_EQ(tmp, "BCM21663", "21663", SOC_BCM_21663, soc, 40)
SOC_EQ(tmp, "BCM21664", "21664", SOC_BCM_21664, soc, 40)
SOC_EQ(tmp, "BCM28155", "28155", SOC_BCM_28155, soc, 40)
SOC_EQ(tmp, "BCM23550", "23550", SOC_BCM_23550, soc, 40)
SOC_EQ(tmp, "BCM28145", "28145", SOC_BCM_28145, soc, 40)
SOC_EQ(tmp, "BCM2157", "2157", SOC_BCM_2157, soc, 65)
SOC_EQ(tmp, "BCM21654", "21654", SOC_BCM_21654, soc, 40)
SOC_EQ(tmp, "BCM2835", "2835", SOC_BCM_2835, soc, 65)
SOC_EQ(tmp, "BCM2836", "2836", SOC_BCM_2836, soc, 40)
SOC_EQ(tmp, "BCM2837", "2837", SOC_BCM_2837, soc, 40)
SOC_EQ(tmp, "BCM2837B0", "2837B0", SOC_BCM_2837B0, soc, 40)
SOC_EQ(tmp, "BCM2711", "2711", SOC_BCM_2711, soc, 28)
SOC_EQ(tmp, "BCM21553", "21553", SOC_BCM_21553, soc, 65)
SOC_EQ(tmp, "BCM21553-Thunderbird", "21553 Thunderbird", SOC_BCM_21553T, soc, 65)
SOC_EQ(tmp, "BCM21663", "21663", SOC_BCM_21663, soc, 40)
SOC_EQ(tmp, "BCM21664", "21664", SOC_BCM_21664, soc, 40)
SOC_EQ(tmp, "BCM28155", "28155", SOC_BCM_28155, soc, 40)
SOC_EQ(tmp, "BCM23550", "23550", SOC_BCM_23550, soc, 40)
SOC_EQ(tmp, "BCM28145", "28145", SOC_BCM_28145, soc, 40)
SOC_EQ(tmp, "BCM2157", "2157", SOC_BCM_2157, soc, 65)
SOC_EQ(tmp, "BCM21654", "21654", SOC_BCM_21654, soc, 40)
SOC_END
}
@@ -108,7 +108,7 @@ bool match_hisilicon(char* soc_name, struct system_on_chip* soc) {
if((tmp = strstr(soc_name, "Hi")) == NULL)
return false;
SOC_START
SOC_EQ(tmp, "Hi3620GFC", "K3V2", SOC_HISILICON_3620, soc, 40)
//SOC_EQ(tmp, "?", "K3V2E", SOC_KIRIN, soc, ?)
@@ -200,16 +200,16 @@ bool match_mediatek(char* soc_name, struct system_on_chip* soc) {
if((tmp = strstr(soc_name, "MT")) == NULL)
return false;
SOC_START
// Dimensity //
SOC_EQ(tmp, "MT6889", "Dimensity 1000", SOC_MTK_MT6889, soc, 7)
SOC_EQ(tmp, "MT6885Z", "Dimensity 1000L", SOC_MTK_MT6885Z, soc, 7)
//SOC_EQ(tmp, "?", "Dimensity 700", SOC_MTK_, soc, 7)
SOC_EQ(tmp, "MT6853", "Dimensity 720", SOC_MTK_MT6853, soc, 7)
SOC_EQ(tmp, "MT6889", "Dimensity 1000", SOC_MTK_MT6889, soc, 7)
SOC_EQ(tmp, "MT6885Z", "Dimensity 1000L", SOC_MTK_MT6885Z, soc, 7)
//SOC_EQ(tmp, "?", "Dimensity 700", SOC_MTK_, soc, 7)
SOC_EQ(tmp, "MT6853", "Dimensity 720", SOC_MTK_MT6853, soc, 7)
SOC_EQ(tmp, "MT6873", "Dimensity 800", SOC_MTK_MT6873, soc, 7)
SOC_EQ(tmp, "MT6875", "Dimensity 820", SOC_MTK_MT6875, soc, 7)
// Helio //
// Helio //
SOC_EQ(tmp, "MT6761D", "Helio A20", SOC_MTK_MT6761D, soc, 12)
SOC_EQ(tmp, "MT6761", "Helio A22", SOC_MTK_MT6761, soc, 12)
SOC_EQ(tmp, "MT6762D", "Helio A25", SOC_MTK_MT6762D, soc, 12)
@@ -310,7 +310,7 @@ bool match_mediatek(char* soc_name, struct system_on_chip* soc) {
*
* If Qualcomm official website reports the SoC name without the initial two or three SKU name,
* we assume APQ if second number is 0, or MSM if second number is different than 0
*
*
* All SoC names here have been retrieved from official Qualcomm resources. However, Linux kernel
* and Android may report the SoC with slightly different. Therefore, this function needs some
* rework (e.g, debug with http://specdevice.com/unmoderated.php?lang=en)
@@ -322,11 +322,11 @@ bool match_qualcomm(char* soc_name, struct system_on_chip* soc) {
if((tmp = strstr(soc_name_upper, "MSM")) != NULL);
else if((tmp = strstr(soc_name_upper, "SDM")) != NULL);
else if((tmp = strstr(soc_name_upper, "APQ")) != NULL);
else if((tmp = strstr(soc_name_upper, "SM")) != NULL);
else if((tmp = strstr(soc_name_upper, "QM")) != NULL);
else if((tmp = strstr(soc_name_upper, "SM")) != NULL);
else if((tmp = strstr(soc_name_upper, "QM")) != NULL);
else if((tmp = strstr(soc_name_upper, "QSD")) != NULL);
else return false;
SOC_START
// Snapdragon S1 //
SOC_EQ(tmp, "QSD8650", "S1", SOC_SNAPD_QSD8650, soc, 65)
@@ -340,36 +340,36 @@ bool match_qualcomm(char* soc_name, struct system_on_chip* soc) {
SOC_EQ(tmp, "MSM7625A", "S1", SOC_SNAPD_MSM7625A, soc, 45)
SOC_EQ(tmp, "MSM7225A", "S1", SOC_SNAPD_MSM7225A, soc, 45)
// Snapdragon S2 //
SOC_EQ(tmp, "MSM8655", "S2", SOC_SNAPD_MSM8655, soc, 45)
SOC_EQ(tmp, "MSM8255", "S2", SOC_SNAPD_MSM8255, soc, 45)
SOC_EQ(tmp, "MSM8655", "S2", SOC_SNAPD_MSM8655, soc, 45)
SOC_EQ(tmp, "MSM8255", "S2", SOC_SNAPD_MSM8255, soc, 45)
SOC_EQ(tmp, "APQ8055", "S2", SOC_SNAPD_APQ8055, soc, 45)
SOC_EQ(tmp, "MSM7630", "S2", SOC_SNAPD_MSM7630, soc, 45)
SOC_EQ(tmp, "MSM7230", "S2", SOC_SNAPD_MSM7230, soc, 45)
SOC_EQ(tmp, "MSM7230", "S2", SOC_SNAPD_MSM7230, soc, 45)
// Snapdragon S3 //
SOC_EQ(tmp, "MSM8660", "S3", SOC_SNAPD_MSM8660, soc, 45)
SOC_EQ(tmp, "MSM8260", "S3", SOC_SNAPD_MSM8260, soc, 45)
SOC_EQ(tmp, "APQ8060", "S3", SOC_SNAPD_APQ8060, soc, 45)
SOC_EQ(tmp, "MSM8660", "S3", SOC_SNAPD_MSM8660, soc, 45)
SOC_EQ(tmp, "MSM8260", "S3", SOC_SNAPD_MSM8260, soc, 45)
SOC_EQ(tmp, "APQ8060", "S3", SOC_SNAPD_APQ8060, soc, 45)
// Snapdragon S4 //
SOC_EQ(tmp, "MSM8225", "S4 Play", SOC_SNAPD_MSM8225, soc, 45)
SOC_EQ(tmp, "MSM8625", "S4 Play", SOC_SNAPD_MSM8625, soc, 45)
SOC_EQ(tmp, "APQ8060A", "S4 Plus", SOC_SNAPD_APQ8060A, soc, 28)
SOC_EQ(tmp, "MSM8960", "S4 Plus", SOC_SNAPD_MSM8960, soc, 28)
SOC_EQ(tmp, "MSM8260A", "S4 Plus", SOC_SNAPD_MSM8260A, soc, 28)
SOC_EQ(tmp, "MSM8627", "S4 Plus", SOC_SNAPD_MSM8627, soc, 28)
SOC_EQ(tmp, "MSM8227", "S4 Plus", SOC_SNAPD_MSM8227, soc, 28)
SOC_EQ(tmp, "APQ8064", "S4 Pro", SOC_SNAPD_APQ8064, soc, 28)
SOC_EQ(tmp, "MSM8960T", "S4 Pro", SOC_SNAPD_MSM8960T, soc, 28)
SOC_EQ(tmp, "APQ8060A", "S4 Plus", SOC_SNAPD_APQ8060A, soc, 28)
SOC_EQ(tmp, "MSM8960", "S4 Plus", SOC_SNAPD_MSM8960, soc, 28)
SOC_EQ(tmp, "MSM8260A", "S4 Plus", SOC_SNAPD_MSM8260A, soc, 28)
SOC_EQ(tmp, "MSM8627", "S4 Plus", SOC_SNAPD_MSM8627, soc, 28)
SOC_EQ(tmp, "MSM8227", "S4 Plus", SOC_SNAPD_MSM8227, soc, 28)
SOC_EQ(tmp, "APQ8064", "S4 Pro", SOC_SNAPD_APQ8064, soc, 28)
SOC_EQ(tmp, "MSM8960T", "S4 Pro", SOC_SNAPD_MSM8960T, soc, 28)
// Snapdragon 2XX //
SOC_EQ(tmp, "MSM8110", "200", SOC_SNAPD_MSM8110, soc, 28)
SOC_EQ(tmp, "MSM8210", "200", SOC_SNAPD_MSM8210, soc, 28)
SOC_EQ(tmp, "MSM8610", "200", SOC_SNAPD_MSM8610, soc, 28)
SOC_EQ(tmp, "MSM8112", "200", SOC_SNAPD_MSM8112, soc, 28)
SOC_EQ(tmp, "MSM8212", "200", SOC_SNAPD_MSM8212, soc, 28)
SOC_EQ(tmp, "MSM8612", "200", SOC_SNAPD_MSM8612, soc, 28)
SOC_EQ(tmp, "MSM8225Q", "200", SOC_SNAPD_MSM8225Q, soc, 45)
SOC_EQ(tmp, "MSM8625Q", "200", SOC_SNAPD_MSM8625Q, soc, 45)
SOC_EQ(tmp, "MSM8208", "208", SOC_SNAPD_MSM8208, soc, 28)
SOC_EQ(tmp, "MSM8905", "205", SOC_SNAPD_MSM8905, soc, 28)
SOC_EQ(tmp, "MSM8110", "200", SOC_SNAPD_MSM8110, soc, 28)
SOC_EQ(tmp, "MSM8210", "200", SOC_SNAPD_MSM8210, soc, 28)
SOC_EQ(tmp, "MSM8610", "200", SOC_SNAPD_MSM8610, soc, 28)
SOC_EQ(tmp, "MSM8112", "200", SOC_SNAPD_MSM8112, soc, 28)
SOC_EQ(tmp, "MSM8212", "200", SOC_SNAPD_MSM8212, soc, 28)
SOC_EQ(tmp, "MSM8612", "200", SOC_SNAPD_MSM8612, soc, 28)
SOC_EQ(tmp, "MSM8225Q", "200", SOC_SNAPD_MSM8225Q, soc, 45)
SOC_EQ(tmp, "MSM8625Q", "200", SOC_SNAPD_MSM8625Q, soc, 45)
SOC_EQ(tmp, "MSM8208", "208", SOC_SNAPD_MSM8208, soc, 28)
SOC_EQ(tmp, "MSM8905", "205", SOC_SNAPD_MSM8905, soc, 28)
SOC_EQ(tmp, "MSM8909", "210 / 212", SOC_SNAPD_MSM8909, soc, 28) // In the future, we can differenciate them using frequency
SOC_EQ(tmp, "QM215", "215", SOC_SNAPD_QM215, soc, 28)
// Snapdragon 4XX //
@@ -473,21 +473,21 @@ struct system_on_chip* parse_soc_from_string(struct system_on_chip* soc) {
if(match_special(raw_name, soc))
return soc;
if (match_qualcomm(raw_name, soc))
return soc;
if(match_mediatek(raw_name, soc))
return soc;
if(match_exynos(raw_name, soc))
return soc;
if(match_hisilicon(raw_name, soc))
return soc;
match_broadcom(raw_name, soc);
return soc;
}
@@ -501,37 +501,37 @@ static inline int android_property_get(const char* key, char* value) {
struct system_on_chip* guess_soc_from_android(struct system_on_chip* soc) {
char tmp[100];
int property_len = 0;
property_len = android_property_get("ro.mediatek.platform", (char *) &tmp);
if(property_len > 0) {
soc->raw_name = malloc(sizeof(char) * (property_len + 1));
soc->raw_name = emalloc(sizeof(char) * (property_len + 1));
strncpy(soc->raw_name, tmp, property_len + 1);
soc->raw_name[property_len] = '\0';
soc->soc_vendor = SOC_VENDOR_UNKNOWN;
return parse_soc_from_string(soc);
}
property_len = android_property_get("ro.product.board", (char *) &tmp);
if(property_len > 0) {
soc->raw_name = malloc(sizeof(char) * (property_len + 1));
if(property_len > 0) {
soc->raw_name = emalloc(sizeof(char) * (property_len + 1));
strncpy(soc->raw_name, tmp, property_len + 1);
soc->raw_name[property_len] = '\0';
soc->soc_vendor = SOC_VENDOR_UNKNOWN;
return parse_soc_from_string(soc);
}
}
return soc;
}
#endif
struct system_on_chip* guess_soc_from_cpuinfo(struct system_on_chip* soc) {
char* tmp = get_hardware_from_cpuinfo();
if(tmp != NULL) {
soc->raw_name = tmp;
return parse_soc_from_string(soc);
}
return soc;
}
@@ -574,7 +574,7 @@ struct system_on_chip* guess_soc_raspbery_pi(struct system_on_chip* soc) {
char* soc_raw_name = soc_rpi_string[pppp];
/*int soc_len = strlen(soc_raw_name);
soc->raw_name = malloc(sizeof(char) * (soc_len + 1));
soc->raw_name = emalloc(sizeof(char) * (soc_len + 1));
strncpy(soc->raw_name, soc_raw_name, soc_len + 1);*/
match_broadcom(soc_raw_name, soc);
@@ -582,7 +582,7 @@ struct system_on_chip* guess_soc_raspbery_pi(struct system_on_chip* soc) {
}
struct system_on_chip* get_soc() {
struct system_on_chip* soc = malloc(sizeof(struct system_on_chip));
struct system_on_chip* soc = emalloc(sizeof(struct system_on_chip));
soc->raw_name = NULL;
soc->soc_vendor = SOC_VENDOR_UNKNOWN;
soc->process = UNKNOWN;
@@ -601,7 +601,7 @@ struct system_on_chip* get_soc() {
soc = guess_soc_from_cpuinfo(soc);
if(soc->soc_vendor == SOC_VENDOR_UNKNOWN) {
if(soc->raw_name != NULL)
printWarn("SoC detection failed using /proc/cpuinfo: Found '%s' string", soc->raw_name);
printWarn("SoC detection failed using /proc/cpuinfo: Found '%s' string", soc->raw_name);
else
printWarn("SoC detection failed using /proc/cpuinfo: No string found");
#ifdef __ANDROID__
@@ -609,16 +609,16 @@ struct system_on_chip* get_soc() {
if(soc->raw_name == NULL)
printWarn("SoC detection failed using Android: No string found");
else if(soc->soc_vendor == SOC_VENDOR_UNKNOWN)
printWarn("SoC detection failed using Android: Found '%s' string", soc->raw_name);
printWarn("SoC detection failed using Android: Found '%s' string", soc->raw_name);
#endif
}
if(soc->raw_name == NULL) {
soc->raw_name = malloc(sizeof(char) * (strlen(STRING_UNKNOWN)+1));
soc->raw_name = emalloc(sizeof(char) * (strlen(STRING_UNKNOWN)+1));
snprintf(soc->raw_name, strlen(STRING_UNKNOWN)+1, STRING_UNKNOWN);
}
return soc;
return soc;
}
char* get_soc_name(struct system_on_chip* soc) {
@@ -633,16 +633,15 @@ VENDOR get_soc_vendor(struct system_on_chip* soc) {
char* get_str_process(struct system_on_chip* soc) {
char* str;
if(soc->process == UNKNOWN) {
str = malloc(sizeof(char) * (strlen(STRING_UNKNOWN)+1));
str = emalloc(sizeof(char) * (strlen(STRING_UNKNOWN)+1));
snprintf(str, strlen(STRING_UNKNOWN)+1, STRING_UNKNOWN);
}
else {
str = malloc(sizeof(char) * 5);
str = emalloc(sizeof(char) * 5);
memset(str, 0, sizeof(char) * 5);
snprintf(str, 5, "%dnm", soc->process);
snprintf(str, 5, "%dnm", soc->process);
}
return str;
}

89
src/arm/uarch.c
View File

@@ -45,26 +45,26 @@ enum {
UARCH_ARM1156,
UARCH_ARM1176,
UARCH_ARM11MPCORE,
UARCH_CORTEX_A5,
UARCH_CORTEX_A7,
UARCH_CORTEX_A8,
UARCH_CORTEX_A9,
UARCH_CORTEX_A12,
UARCH_CORTEX_A15,
UARCH_CORTEX_A17,
UARCH_CORTEX_A32,
UARCH_CORTEX_A35,
UARCH_CORTEX_A53,
UARCH_CORTEX_A5,
UARCH_CORTEX_A7,
UARCH_CORTEX_A8,
UARCH_CORTEX_A9,
UARCH_CORTEX_A12,
UARCH_CORTEX_A15,
UARCH_CORTEX_A17,
UARCH_CORTEX_A32,
UARCH_CORTEX_A35,
UARCH_CORTEX_A53,
UARCH_CORTEX_A55r0, // ARM Cortex-A55 revision 0 (restricted dual-issue capabilities compared to revision 1+).
UARCH_CORTEX_A55,
UARCH_CORTEX_A57,
UARCH_CORTEX_A65,
UARCH_CORTEX_A72,
UARCH_CORTEX_A73,
UARCH_CORTEX_A75,
UARCH_CORTEX_A55,
UARCH_CORTEX_A57,
UARCH_CORTEX_A65,
UARCH_CORTEX_A72,
UARCH_CORTEX_A73,
UARCH_CORTEX_A75,
UARCH_CORTEX_A76,
UARCH_CORTEX_A77,
UARCH_CORTEX_A78,
UARCH_CORTEX_A78,
UARCH_NEOVERSE_N1,
UARCH_NEOVERSE_E1,
UARCH_SCORPION,
@@ -118,15 +118,15 @@ static const ISA isas_uarch[] = {
[UARCH_CORTEX_A17] = ISA_ARMv7_A,
[UARCH_CORTEX_A32] = ISA_ARMv8_A_AArch32,
[UARCH_CORTEX_A35] = ISA_ARMv8_A,
[UARCH_CORTEX_A53] = ISA_ARMv8_A,
[UARCH_CORTEX_A53] = ISA_ARMv8_A,
[UARCH_CORTEX_A55r0] = ISA_ARMv8_2_A,
[UARCH_CORTEX_A55] = ISA_ARMv8_2_A,
[UARCH_CORTEX_A57] = ISA_ARMv8_A,
[UARCH_CORTEX_A65] = ISA_ARMv8_2_A,
[UARCH_CORTEX_A65] = ISA_ARMv8_2_A,
[UARCH_CORTEX_A72] = ISA_ARMv8_A,
[UARCH_CORTEX_A73] = ISA_ARMv8_A,
[UARCH_CORTEX_A75] = ISA_ARMv8_2_A,
[UARCH_CORTEX_A76] = ISA_ARMv8_2_A,
[UARCH_CORTEX_A76] = ISA_ARMv8_2_A,
[UARCH_CORTEX_A77] = ISA_ARMv8_2_A,
[UARCH_CORTEX_A78] = ISA_ARMv8_2_A,
[UARCH_NEOVERSE_N1] = ISA_ARMv8_2_A,
@@ -170,18 +170,18 @@ static char* isas_string[] = {
#define CHECK_UARCH(arch, cpu, im_, p_, v_, r_, str, uarch, vendor) \
else if (im_ == im && p_ == p && (v_ == NA || v_ == v) && (r_ == NA || r_ == r)) fill_uarch(arch, cpu, str, uarch, vendor);
#define UARCH_END else { printBug("Unknown microarchitecture detected: IM=0x%.8X P=0x%.8X V=0x%.8X R=0x%.8X", im, p, v, r); fill_uarch(arch, cpu, "Unknown", UARCH_UNKNOWN, CPU_VENDOR_UNKNOWN); }
void fill_uarch(struct uarch* arch, struct cpuInfo* cpu, char* str, MICROARCH u, VENDOR vendor) {
arch->uarch = u;
arch->uarch = u;
arch->isa = isas_uarch[arch->uarch];
cpu->cpu_vendor = vendor;
arch->uarch_str = malloc(sizeof(char) * (strlen(str)+1));
arch->uarch_str = emalloc(sizeof(char) * (strlen(str)+1));
strcpy(arch->uarch_str, str);
arch->isa_str = malloc(sizeof(char) * (strlen(isas_string[arch->isa])+1));
strcpy(arch->isa_str, isas_string[arch->isa]);
}
arch->isa_str = emalloc(sizeof(char) * (strlen(isas_string[arch->isa])+1));
strcpy(arch->isa_str, isas_string[arch->isa]);
}
/*
* Codes are based on pytorch/cpuinfo, more precisely:
@@ -191,7 +191,7 @@ void fill_uarch(struct uarch* arch, struct cpuInfo* cpu, char* str, MICROARCH u,
* - https://elixir.bootlin.com/linux/latest/source/arch/arm/include/asm/cputype.h
*/
struct uarch* get_uarch_from_midr(uint32_t midr, struct cpuInfo* cpu) {
struct uarch* arch = malloc(sizeof(struct uarch));
struct uarch* arch = emalloc(sizeof(struct uarch));
uint32_t im = midr_get_implementer(midr);
uint32_t p = midr_get_part(midr);
uint32_t v = midr_get_variant(midr);
@@ -221,7 +221,7 @@ struct uarch* get_uarch_from_midr(uint32_t midr, struct cpuInfo* cpu) {
CHECK_UARCH(arch, cpu, 'A', 0xD03, NA, NA, "Cortex-A53", UARCH_CORTEX_A53, CPU_VENDOR_ARM)
CHECK_UARCH(arch, cpu, 'A', 0xD04, NA, NA, "Cortex-A35", UARCH_CORTEX_A35, CPU_VENDOR_ARM)
CHECK_UARCH(arch, cpu, 'A', 0xD05, NA, 0, "Cortex-A55", UARCH_CORTEX_A55r0, CPU_VENDOR_ARM)
CHECK_UARCH(arch, cpu, 'A', 0xD05, NA, NA, "Cortex-A55", UARCH_CORTEX_A55, CPU_VENDOR_ARM)
CHECK_UARCH(arch, cpu, 'A', 0xD05, NA, NA, "Cortex-A55", UARCH_CORTEX_A55, CPU_VENDOR_ARM)
CHECK_UARCH(arch, cpu, 'A', 0xD06, NA, NA, "Cortex-A65", UARCH_CORTEX_A65, CPU_VENDOR_ARM)
CHECK_UARCH(arch, cpu, 'A', 0xD07, NA, NA, "Cortex-A57", UARCH_CORTEX_A57, CPU_VENDOR_ARM)
CHECK_UARCH(arch, cpu, 'A', 0xD08, NA, NA, "Cortex-A72", UARCH_CORTEX_A72, CPU_VENDOR_ARM)
@@ -233,26 +233,26 @@ struct uarch* get_uarch_from_midr(uint32_t midr, struct cpuInfo* cpu) {
CHECK_UARCH(arch, cpu, 'A', 0xD0E, NA, NA, "Cortex-A76", UARCH_CORTEX_A76, CPU_VENDOR_ARM)
CHECK_UARCH(arch, cpu, 'A', 0xD41, NA, NA, "Cortex-A78", UARCH_CORTEX_A78, CPU_VENDOR_ARM)
CHECK_UARCH(arch, cpu, 'A', 0xD4A, NA, NA, "Neoverse E1", UARCH_NEOVERSE_E1, CPU_VENDOR_ARM)
CHECK_UARCH(arch, cpu, 'B', 0x00F, NA, NA, "Brahma B15", UARCH_BRAHMA_B15, CPU_VENDOR_BROADCOM)
CHECK_UARCH(arch, cpu, 'B', 0x100, NA, NA, "Brahma B53", UARCH_BRAHMA_B53, CPU_VENDOR_BROADCOM)
CHECK_UARCH(arch, cpu, 'B', 0x516, NA, NA, "ThunderX2", UARCH_THUNDERX2, CPU_VENDOR_CAVIUM)
CHECK_UARCH(arch, cpu, 'C', 0x0A0, NA, NA, "ThunderX", UARCH_THUNDERX, CPU_VENDOR_CAVIUM)
CHECK_UARCH(arch, cpu, 'C', 0x0A1, NA, NA, "ThunderX 88XX", UARCH_THUNDERX, CPU_VENDOR_CAVIUM)
CHECK_UARCH(arch, cpu, 'C', 0x0A2, NA, NA, "ThunderX 81XX", UARCH_THUNDERX, CPU_VENDOR_CAVIUM)
CHECK_UARCH(arch, cpu, 'C', 0x0A3, NA, NA, "ThunderX 81XX", UARCH_THUNDERX, CPU_VENDOR_CAVIUM)
CHECK_UARCH(arch, cpu, 'C', 0x0AF, NA, NA, "ThunderX2 99XX", UARCH_THUNDERX2, CPU_VENDOR_CAVIUM)
CHECK_UARCH(arch, cpu, 'H', 0xD01, NA, NA, "TaiShan v110", UARCH_TAISHAN_V110, CPU_VENDOR_HUAWUEI) // Kunpeng 920 series
CHECK_UARCH(arch, cpu, 'H', 0xD40, NA, NA, "Cortex-A76", UARCH_CORTEX_A76, CPU_VENDOR_ARM) // Kirin 980 Big/Medium cores -> Cortex-A76
CHECK_UARCH(arch, cpu, 'N', 0x000, NA, NA, "Denver", UARCH_DENVER, CPU_VENDOR_NVIDIA)
CHECK_UARCH(arch, cpu, 'N', 0x003, NA, NA, "Denver2", UARCH_DENVER2, CPU_VENDOR_NVIDIA)
CHECK_UARCH(arch, cpu, 'N', 0x004, NA, NA, "Carmel", UARCH_CARMEL, CPU_VENDOR_NVIDIA)
CHECK_UARCH(arch, cpu, 'P', 0x000, NA, NA, "Xgene", UARCH_XGENE, CPU_VENDOR_APM)
CHECK_UARCH(arch, cpu, 'Q', 0x00F, NA, NA, "Scorpion", UARCH_SCORPION, CPU_VENDOR_QUALCOMM)
CHECK_UARCH(arch, cpu, 'Q', 0x02D, NA, NA, "Scorpion", UARCH_KRAIT, CPU_VENDOR_QUALCOMM)
CHECK_UARCH(arch, cpu, 'Q', 0x04D, 1, 0, "Krait 200", UARCH_KRAIT, CPU_VENDOR_QUALCOMM)
@@ -273,29 +273,28 @@ struct uarch* get_uarch_from_midr(uint32_t midr, struct cpuInfo* cpu) {
CHECK_UARCH(arch, cpu, 'Q', 0x803, NA, NA, "Kryo 385 Silver", UARCH_CORTEX_A55r0, CPU_VENDOR_ARM) // Low-power Kryo 385 "Silver" -> Cortex-A55r0
CHECK_UARCH(arch, cpu, 'Q', 0x804, NA, NA, "Kryo 485 Gold", UARCH_CORTEX_A76, CPU_VENDOR_ARM) // High-performance Kryo 485 "Gold" / "Gold Prime" -> Cortex-A76
CHECK_UARCH(arch, cpu, 'Q', 0x805, NA, NA, "Kryo 485 Silver", UARCH_CORTEX_A55, CPU_VENDOR_ARM) // Low-performance Kryo 485 "Silver" -> Cortex-A55
CHECK_UARCH(arch, cpu, 'Q', 0xC00, NA, NA, "Falkor", UARCH_FALKOR, CPU_VENDOR_QUALCOMM)
CHECK_UARCH(arch, cpu, 'Q', 0xC01, NA, NA, "Saphira", UARCH_SAPHIRA, CPU_VENDOR_QUALCOMM)
CHECK_UARCH(arch, cpu, 'Q', 0xC00, NA, NA, "Falkor", UARCH_FALKOR, CPU_VENDOR_QUALCOMM)
CHECK_UARCH(arch, cpu, 'Q', 0xC01, NA, NA, "Saphira", UARCH_SAPHIRA, CPU_VENDOR_QUALCOMM)
CHECK_UARCH(arch, cpu, 'S', 0x001, 1, NA, "Exynos M1", UARCH_EXYNOS_M1, CPU_VENDOR_SAMSUNG) // Exynos 8890
CHECK_UARCH(arch, cpu, 'S', 0x001, 4, NA, "Exynos M2", UARCH_EXYNOS_M2, CPU_VENDOR_SAMSUNG) // Exynos 8895
CHECK_UARCH(arch, cpu, 'S', 0x002, 1, NA, "Exynos M3", UARCH_EXYNOS_M3, CPU_VENDOR_SAMSUNG) // Exynos 9810
CHECK_UARCH(arch, cpu, 'S', 0x003, 1, NA, "Exynos M4", UARCH_EXYNOS_M4, CPU_VENDOR_SAMSUNG) // Exynos 9820
CHECK_UARCH(arch, cpu, 'S', 0x004, 1, NA, "Exynos M5", UARCH_EXYNOS_M5, CPU_VENDOR_SAMSUNG) // Exynos 9820 (this one looks wrong at uarch.c ...)
CHECK_UARCH(arch, cpu, 'V', 0x581, NA, NA, "PJ4", UARCH_PJ4, CPU_VENDOR_MARVELL)
CHECK_UARCH(arch, cpu, 'V', 0x584, NA, NA, "PJ4B-MP", UARCH_PJ4, CPU_VENDOR_MARVELL)
UARCH_END
return arch;
}
char* get_str_uarch(struct cpuInfo* cpu) {
return cpu->arch->uarch_str;
return cpu->arch->uarch_str;
}
void free_uarch_struct(struct uarch* arch) {
void free_uarch_struct(struct uarch* arch) {
free(arch->uarch_str);
free(arch);
}

20
src/arm/udev.c
View File

@@ -81,8 +81,8 @@ uint32_t get_midr_from_cpuinfo(uint32_t core, bool* success) {
*success = true;
if((buf = read_file(_PATH_CPUINFO, &filelen)) == NULL) {
perror("open");
*success = false;
return 0;
*success = false;
return 0;
}
char* tmp = strstr(buf, CPUINFO_CPU_STRING);
@@ -92,9 +92,9 @@ uint32_t get_midr_from_cpuinfo(uint32_t core, bool* success) {
current_core++;
tmp = strstr(tmp, CPUINFO_CPU_STRING);
}
if(tmp == NULL) {
*success = false;
*success = false;
return 0;
}
@@ -108,35 +108,35 @@ uint32_t get_midr_from_cpuinfo(uint32_t core, bool* success) {
if ((ret = parse_cpuinfo_field(tmp, CPUINFO_CPU_IMPLEMENTER_STR, 16)) < 0) {
printf("Failed parsing cpu_implementer\n");
*success = false;
*success = false;
return 0;
}
cpu_implementer = (uint32_t) ret;
if ((ret = parse_cpuinfo_field(tmp, CPUINFO_CPU_ARCHITECTURE_STR, 10)) < 0) {
printf("Failed parsing cpu_architecture\n");
*success = false;
*success = false;
return 0;
}
cpu_architecture = (uint32_t) 0xF; // Why?
if ((ret = parse_cpuinfo_field(tmp, CPUINFO_CPU_VARIANT_STR, 16)) < 0) {
printf("Failed parsing cpu_variant\n");
*success = false;
*success = false;
return 0;
}
cpu_variant = (uint32_t) ret;
if ((ret = parse_cpuinfo_field(tmp, CPUINFO_CPU_PART_STR, 16)) < 0) {
printf("Failed parsing cpu_part\n");
*success = false;
*success = false;
return 0;
}
cpu_part = (uint32_t) ret;
if ((ret = parse_cpuinfo_field(tmp, CPUINFO_CPU_REVISION_STR, 10)) < 0) {
printf("Failed parsing cpu_revision\n");
*success = false;
*success = false;
return 0;
}
cpu_revision = (uint32_t) ret;
@@ -164,7 +164,7 @@ char* get_field_from_cpuinfo(char* CPUINFO_FIELD) {
char* tmp2 = strstr(tmp1, "\n");
int strlen = (1 + (tmp2-tmp1));
char* hardware = malloc(sizeof(char) * strlen);
char* hardware = emalloc(sizeof(char) * strlen);
memset(hardware, 0, sizeof(char) * strlen);
strncpy(hardware, tmp1, tmp2-tmp1);