mirror of
https://github.com/Dr-Noob/cpufetch.git
synced 2026-03-25 07:50:40 +01:00
[v0.98] Use malloc/calloc wrapper that exits when alloc fails, as suggested by #90
This commit is contained in:
Dr-Noob
328
src/x86/cpuid.c
328
src/x86/cpuid.c
@@ -58,22 +58,22 @@ void init_topology_struct(struct topology* topo, struct cache* cach) {
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topo->smt_available = 0;
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topo->smt_supported = 0;
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topo->sockets = 0;
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topo->apic = malloc(sizeof(struct apic));
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topo->apic = emalloc(sizeof(struct apic));
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topo->cach = cach;
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}
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void init_cache_struct(struct cache* cach) {
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cach->L1i = malloc(sizeof(struct cach));
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cach->L1d = malloc(sizeof(struct cach));
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cach->L2 = malloc(sizeof(struct cach));
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cach->L3 = malloc(sizeof(struct cach));
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cach->cach_arr = malloc(sizeof(struct cach*) * 4);
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cach->L1i = emalloc(sizeof(struct cach));
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cach->L1d = emalloc(sizeof(struct cach));
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cach->L2 = emalloc(sizeof(struct cach));
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cach->L3 = emalloc(sizeof(struct cach));
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cach->cach_arr = emalloc(sizeof(struct cach*) * 4);
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cach->cach_arr[0] = cach->L1i;
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cach->cach_arr[1] = cach->L1d;
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cach->cach_arr[2] = cach->L2;
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cach->cach_arr[3] = cach->L3;
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cach->max_cache_level = 0;
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cach->L1i->exists = false;
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cach->L1d->exists = false;
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@@ -83,7 +83,7 @@ void init_cache_struct(struct cache* cach) {
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void get_name_cpuid(char* name, uint32_t reg1, uint32_t reg2, uint32_t reg3) {
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uint32_t c = 0;
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name[c++] = reg1 & MASK;
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name[c++] = (reg1>>8) & MASK;
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name[c++] = (reg1>>16) & MASK;
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@@ -106,14 +106,14 @@ char* get_str_cpu_name_internal() {
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uint32_t ecx = 0;
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uint32_t edx = 0;
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uint32_t c = 0;
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char * name = malloc(sizeof(char) * CPU_NAME_MAX_LENGTH);
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char * name = emalloc(sizeof(char) * CPU_NAME_MAX_LENGTH);
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memset(name, 0, CPU_NAME_MAX_LENGTH);
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for(int i=0; i < 3; i++) {
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for(int i=0; i < 3; i++) {
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eax = 0x80000002 + i;
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cpuid(&eax, &ebx, &ecx, &edx);
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name[c++] = eax & MASK;
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name[c++] = (eax>>8) & MASK;
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name[c++] = (eax>>16) & MASK;
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@@ -129,22 +129,22 @@ char* get_str_cpu_name_internal() {
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name[c++] = edx & MASK;
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name[c++] = (edx>>8) & MASK;
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name[c++] = (edx>>16) & MASK;
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name[c++] = (edx>>24) & MASK;
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name[c++] = (edx>>24) & MASK;
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}
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name[c] = '\0';
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//Remove unused characters
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//Remove unused characters
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char *str = name;
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char *dest = name;
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// Remove spaces before name
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while (*str != '\0' && *str == ' ')str++;
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while (*str != '\0' && *str == ' ')str++;
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// Remove spaces between the name and after it
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while (*str != '\0') {
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while (*str == ' ' && *(str + 1) == ' ') str++;
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*dest++ = *str++;
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}
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*dest = '\0';
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return name;
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}
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@@ -153,27 +153,27 @@ struct uarch* get_cpu_uarch(struct cpuInfo* cpu) {
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uint32_t ebx = 0;
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uint32_t ecx = 0;
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uint32_t edx = 0;
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cpuid(&eax, &ebx, &ecx, &edx);
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uint32_t stepping = eax & 0xF;
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uint32_t model = (eax >> 4) & 0xF;
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uint32_t emodel = (eax >> 16) & 0xF;
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uint32_t family = (eax >> 8) & 0xF;
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uint32_t efamily = (eax >> 20) & 0xFF;
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return get_uarch_from_cpuid(cpu, efamily, family, emodel, model, (int)stepping);
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}
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struct hypervisor* get_hp_info(bool hv_present) {
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struct hypervisor* hv = malloc(sizeof(struct hypervisor));
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struct hypervisor* hv = emalloc(sizeof(struct hypervisor));
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if(!hv_present) {
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hv->present = false;
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return hv;
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return hv;
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}
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hv->present = true;
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hv->present = true;
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uint32_t eax = 0x40000000;
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uint32_t ebx = 0;
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uint32_t ecx = 0;
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@@ -184,37 +184,37 @@ struct hypervisor* get_hp_info(bool hv_present) {
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char name[13];
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memset(name, 0, 13);
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get_name_cpuid(name, ebx, ecx, edx);
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bool found = false;
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uint8_t len = sizeof(hv_vendors_string) / sizeof(hv_vendors_string[0]);
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for(uint8_t v=0; v < len && !found; v++) {
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if(strcmp(hv_vendors_string[v], name) == 0) {
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hv->hv_vendor = v;
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found = true;
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found = true;
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}
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}
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if(!found) {
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hv->hv_vendor = HV_VENDOR_INVALID;
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printWarn("Unknown hypervisor vendor: %s", name);
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printWarn("Unknown hypervisor vendor: %s", name);
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}
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hv->hv_name = hv_vendors_name[hv->hv_vendor];
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return hv;
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}
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struct cpuInfo* get_cpu_info() {
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struct cpuInfo* cpu = malloc(sizeof(struct cpuInfo));
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struct features* feat = malloc(sizeof(struct features));
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struct cpuInfo* cpu = emalloc(sizeof(struct cpuInfo));
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struct features* feat = emalloc(sizeof(struct features));
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cpu->feat = feat;
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bool *ptr = &(feat->AES);
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for(uint32_t i = 0; i < sizeof(struct features)/sizeof(bool); i++, ptr++) {
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*ptr = false;
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}
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uint32_t eax = 0;
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uint32_t ebx = 0;
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uint32_t ecx = 0;
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@@ -228,11 +228,11 @@ struct cpuInfo* get_cpu_info() {
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char name[13];
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memset(name,0,13);
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get_name_cpuid(name, ebx, edx, ecx);
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if(strcmp(CPU_VENDOR_INTEL_STRING,name) == 0)
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cpu->cpu_vendor = CPU_VENDOR_INTEL;
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else if (strcmp(CPU_VENDOR_AMD_STRING,name) == 0)
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cpu->cpu_vendor = CPU_VENDOR_AMD;
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cpu->cpu_vendor = CPU_VENDOR_AMD;
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else {
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cpu->cpu_vendor = CPU_VENDOR_INVALID;
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printErr("Unknown CPU vendor: %s", name);
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@@ -245,7 +245,7 @@ struct cpuInfo* get_cpu_info() {
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ecx = 0;
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edx = 0;
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cpuid(&eax, &ebx, &ecx, &edx);
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cpu->maxExtendedLevels = eax;
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cpu->maxExtendedLevels = eax;
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//Fill instructions support
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if (cpu->maxLevels >= 0x00000001){
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@@ -271,7 +271,7 @@ struct cpuInfo* get_cpu_info() {
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else {
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printWarn("Can't read features information from cpuid (needed level is 0x%.8X, max is 0x%.8X)", 0x00000001, cpu->maxLevels);
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}
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if (cpu->maxLevels >= 0x00000007){
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eax = 0x00000007;
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ecx = 0x00000000;
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@@ -288,9 +288,9 @@ struct cpuInfo* get_cpu_info() {
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((ebx & (1U << 21)) != 0));
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}
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else {
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printWarn("Can't read features information from cpuid (needed level is 0x%.8X, max is 0x%.8X)", 0x00000007, cpu->maxLevels);
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printWarn("Can't read features information from cpuid (needed level is 0x%.8X, max is 0x%.8X)", 0x00000007, cpu->maxLevels);
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}
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if (cpu->maxExtendedLevels >= 0x80000001){
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eax = 0x80000001;
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cpuid(&eax, &ebx, &ecx, &edx);
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@@ -298,25 +298,25 @@ struct cpuInfo* get_cpu_info() {
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feat->FMA4 = (ecx & (1U << 16)) != 0;
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}
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else {
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printWarn("Can't read features information from cpuid (needed extended level is 0x%.8X, max is 0x%.8X)", 0x80000001, cpu->maxExtendedLevels);
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printWarn("Can't read features information from cpuid (needed extended level is 0x%.8X, max is 0x%.8X)", 0x80000001, cpu->maxExtendedLevels);
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}
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if (cpu->maxExtendedLevels >= 0x80000004){
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cpu->cpu_name = get_str_cpu_name_internal();
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}
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else {
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cpu->cpu_name = malloc(sizeof(char)*8);
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else {
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cpu->cpu_name = emalloc(sizeof(char)*8);
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sprintf(cpu->cpu_name,"Unknown");
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printWarn("Can't read cpu name from cpuid (needed extended level is 0x%.8X, max is 0x%.8X)", 0x80000004, cpu->maxExtendedLevels);
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printWarn("Can't read cpu name from cpuid (needed extended level is 0x%.8X, max is 0x%.8X)", 0x80000004, cpu->maxExtendedLevels);
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}
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cpu->topology_extensions = false;
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if(cpu->cpu_vendor == CPU_VENDOR_AMD && cpu->maxExtendedLevels >= 0x80000001) {
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eax = 0x80000001;
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cpuid(&eax, &ebx, &ecx, &edx);
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cpuid(&eax, &ebx, &ecx, &edx);
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cpu->topology_extensions = (ecx >> 22) & 1;
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}
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cpu->arch = get_cpu_uarch(cpu);
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cpu->freq = get_frequency_info(cpu);
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cpu->cach = get_cache_info(cpu);
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@@ -328,26 +328,26 @@ struct cpuInfo* get_cpu_info() {
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return cpu;
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}
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bool get_cache_topology_amd(struct cpuInfo* cpu, struct topology* topo) {
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if(cpu->maxExtendedLevels >= 0x8000001D && cpu->topology_extensions) {
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bool get_cache_topology_amd(struct cpuInfo* cpu, struct topology* topo) {
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if(cpu->maxExtendedLevels >= 0x8000001D && cpu->topology_extensions) {
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uint32_t i, eax, ebx, ecx, edx, num_sharing_cache, cache_type, cache_level;
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i = 0;
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do {
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eax = 0x8000001D;
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ebx = 0;
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ecx = i; // cache id
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edx = 0;
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cpuid(&eax, &ebx, &ecx, &edx);
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cache_type = eax & 0x1F;
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cpuid(&eax, &ebx, &ecx, &edx);
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cache_type = eax & 0x1F;
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if(cache_type > 0) {
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num_sharing_cache = ((eax >> 14) & 0xFFF) + 1;
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cache_level = (eax >>= 5) & 0x7;
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switch (cache_type) {
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num_sharing_cache = ((eax >> 14) & 0xFFF) + 1;
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cache_level = (eax >>= 5) & 0x7;
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switch (cache_type) {
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case 1: // Data Cache (We assume this is L1d)
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if(cache_level != 1) {
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printBug("Found data cache at level %d (expected 1)", cache_level);
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@@ -355,7 +355,7 @@ bool get_cache_topology_amd(struct cpuInfo* cpu, struct topology* topo) {
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}
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topo->cach->L1d->num_caches = topo->logical_cores / num_sharing_cache;
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break;
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case 2: // Instruction Cache (We assume this is L1i)
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if(cache_level != 1) {
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printBug("Found instruction cache at level %d (expected 1)", cache_level);
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@@ -363,9 +363,9 @@ bool get_cache_topology_amd(struct cpuInfo* cpu, struct topology* topo) {
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}
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topo->cach->L1i->num_caches = topo->logical_cores / num_sharing_cache;
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break;
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case 3: // Unified Cache (This may be L2 or L3)
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if(cache_level == 2) {
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if(cache_level == 2) {
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topo->cach->L2->num_caches = topo->logical_cores / num_sharing_cache;
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}
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else if(cache_level == 3) {
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@@ -375,44 +375,44 @@ bool get_cache_topology_amd(struct cpuInfo* cpu, struct topology* topo) {
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printWarn("Found unknown unified cache at level %d", cache_level);
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}
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break;
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default: // Unknown cache type
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printBug("Unknown cache type %d with level %d found at i=%d", cache_type, cache_level, i);
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return false;
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}
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return false;
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}
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}
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i++;
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} while (cache_type > 0);
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} while (cache_type > 0);
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}
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else {
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printWarn("Can't read topology information from cpuid (needed extended level is 0x%.8X, max is 0x%.8X and topology_extensions=%s). Guessing cache topology", 0x8000001D, cpu->maxExtendedLevels, cpu->topology_extensions ? "true" : "false");
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printWarn("Can't read topology information from cpuid (needed extended level is 0x%.8X, max is 0x%.8X and topology_extensions=%s). Guessing cache topology", 0x8000001D, cpu->maxExtendedLevels, cpu->topology_extensions ? "true" : "false");
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topo->cach->L1i->num_caches = topo->physical_cores;
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topo->cach->L1d->num_caches = topo->physical_cores;
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if(topo->cach->L3->exists) {
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topo->cach->L2->num_caches = topo->physical_cores;
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topo->cach->L3->num_caches = 1;
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topo->cach->L3->num_caches = 1;
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}
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else {
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topo->cach->L2->num_caches = 1;
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topo->cach->L2->num_caches = 1;
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}
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}
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return true;
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}
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// Main reference: https://software.intel.com/content/www/us/en/develop/articles/intel-64-architecture-processor-topology-enumeration.html
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// Very interesting resource: https://wiki.osdev.org/Detecting_CPU_Topology_(80x86)
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struct topology* get_topology_info(struct cpuInfo* cpu, struct cache* cach) {
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struct topology* topo = malloc(sizeof(struct topology));
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struct topology* topo = emalloc(sizeof(struct topology));
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init_topology_struct(topo, cach);
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uint32_t eax = 0;
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uint32_t ebx = 0;
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uint32_t ecx = 0;
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uint32_t edx = 0;
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// Ask the OS the total number of cores it sees
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// If we have one socket, it will be same as the cpuid,
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// but in dual socket it will not!
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@@ -425,45 +425,45 @@ struct topology* get_topology_info(struct cpuInfo* cpu, struct cache* cach) {
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if((topo->total_cores = sysconf(_SC_NPROCESSORS_ONLN)) == -1) {
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perror("sysconf");
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topo->total_cores = topo->logical_cores; // fallback
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}
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#endif
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}
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#endif
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switch(cpu->cpu_vendor) {
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case CPU_VENDOR_INTEL:
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if (cpu->maxLevels >= 0x00000004) {
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if (cpu->maxLevels >= 0x00000004) {
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get_topology_from_apic(cpu, topo);
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}
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else {
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printWarn("Can't read topology information from cpuid (needed level is 0x%.8X, max is 0x%.8X)", 0x00000001, cpu->maxLevels);
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else {
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printWarn("Can't read topology information from cpuid (needed level is 0x%.8X, max is 0x%.8X)", 0x00000001, cpu->maxLevels);
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topo->physical_cores = 1;
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topo->logical_cores = 1;
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topo->smt_available = 1;
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topo->smt_supported = 1;
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}
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}
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break;
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case CPU_VENDOR_AMD:
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case CPU_VENDOR_AMD:
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if (cpu->maxExtendedLevels >= 0x80000008) {
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eax = 0x80000008;
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cpuid(&eax, &ebx, &ecx, &edx);
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eax = 0x80000008;
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cpuid(&eax, &ebx, &ecx, &edx);
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topo->logical_cores = (ecx & 0xFF) + 1;
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if (cpu->maxExtendedLevels >= 0x8000001E && cpu->topology_extensions) {
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eax = 0x8000001E;
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eax = 0x8000001E;
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cpuid(&eax, &ebx, &ecx, &edx);
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topo->smt_supported = ((ebx >> 8) & 0x03) + 1;
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topo->smt_supported = ((ebx >> 8) & 0x03) + 1;
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}
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else {
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printWarn("Can't read topology information from cpuid (needed extended level is 0x%.8X, max is 0x%.8X and topology_extensions=%s)", 0x8000001E, cpu->maxExtendedLevels, cpu->topology_extensions ? "true" : "false");
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topo->smt_supported = 1;
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}
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printWarn("Can't read topology information from cpuid (needed extended level is 0x%.8X, max is 0x%.8X and topology_extensions=%s)", 0x8000001E, cpu->maxExtendedLevels, cpu->topology_extensions ? "true" : "false");
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topo->smt_supported = 1;
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}
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}
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else {
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printWarn("Can't read topology information from cpuid (needed extended level is 0x%.8X, max is 0x%.8X)", 0x80000008, cpu->maxExtendedLevels);
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printWarn("Can't read topology information from cpuid (needed extended level is 0x%.8X, max is 0x%.8X)", 0x80000008, cpu->maxExtendedLevels);
|
||||
topo->physical_cores = 1;
|
||||
topo->logical_cores = 1;
|
||||
topo->smt_supported = 1;
|
||||
topo->smt_supported = 1;
|
||||
}
|
||||
|
||||
|
||||
if (cpu->maxLevels >= 0x00000001) {
|
||||
if(topo->smt_supported > 1)
|
||||
topo->smt_available = is_smt_enabled_amd(topo);
|
||||
@@ -471,25 +471,25 @@ struct topology* get_topology_info(struct cpuInfo* cpu, struct cache* cach) {
|
||||
topo->smt_available = 1;
|
||||
}
|
||||
else {
|
||||
printWarn("Can't read topology information from cpuid (needed level is 0x%.8X, max is 0x%.8X)", 0x0000000B, cpu->maxLevels);
|
||||
printWarn("Can't read topology information from cpuid (needed level is 0x%.8X, max is 0x%.8X)", 0x0000000B, cpu->maxLevels);
|
||||
topo->smt_available = 1;
|
||||
}
|
||||
topo->physical_cores = topo->logical_cores / topo->smt_available;
|
||||
|
||||
|
||||
if(topo->smt_supported > 1)
|
||||
topo->sockets = topo->total_cores / topo->smt_supported / topo->physical_cores; // Idea borrowed from lscpu
|
||||
else
|
||||
topo->sockets = topo->total_cores / topo->physical_cores;
|
||||
|
||||
get_cache_topology_amd(cpu, topo);
|
||||
|
||||
topo->sockets = topo->total_cores / topo->physical_cores;
|
||||
|
||||
get_cache_topology_amd(cpu, topo);
|
||||
|
||||
break;
|
||||
|
||||
|
||||
default:
|
||||
printBug("Cant get topology because VENDOR is empty");
|
||||
return NULL;
|
||||
}
|
||||
|
||||
|
||||
return topo;
|
||||
}
|
||||
|
||||
@@ -499,13 +499,13 @@ struct cache* get_cache_info_amd_fallback(struct cache* cach) {
|
||||
uint32_t ecx = 0;
|
||||
uint32_t edx = 0;
|
||||
cpuid(&eax, &ebx, &ecx, &edx);
|
||||
|
||||
|
||||
cach->L1d->size = (ecx >> 24) * 1024;
|
||||
cach->L1i->size = (edx >> 24) * 1024;
|
||||
|
||||
|
||||
eax = 0x80000006;
|
||||
cpuid(&eax, &ebx, &ecx, &edx);
|
||||
|
||||
|
||||
cach->L2->size = (ecx >> 16) * 1024;
|
||||
cach->L3->size = (edx >> 18) * 512 * 1024;
|
||||
|
||||
@@ -529,17 +529,17 @@ struct cache* get_cache_info_general(struct cache* cach, uint32_t level) {
|
||||
uint32_t edx = 0;
|
||||
int i=0;
|
||||
int32_t cache_type;
|
||||
|
||||
|
||||
do {
|
||||
eax = level; // get cache info
|
||||
ebx = 0;
|
||||
ecx = i; // cache id
|
||||
edx = 0;
|
||||
|
||||
cpuid(&eax, &ebx, &ecx, &edx);
|
||||
|
||||
|
||||
cpuid(&eax, &ebx, &ecx, &edx);
|
||||
|
||||
cache_type = eax & 0x1F;
|
||||
|
||||
|
||||
// If its 0, we tried fetching a non existing cache
|
||||
if (cache_type > 0) {
|
||||
int32_t cache_level = (eax >>= 5) & 0x7;
|
||||
@@ -547,11 +547,11 @@ struct cache* get_cache_info_general(struct cache* cach, uint32_t level) {
|
||||
uint32_t cache_coherency_line_size = (ebx & 0xFFF) + 1;
|
||||
uint32_t cache_physical_line_partitions = ((ebx >>= 12) & 0x3FF) + 1;
|
||||
uint32_t cache_ways_of_associativity = ((ebx >>= 10) & 0x3FF) + 1;
|
||||
|
||||
int32_t cache_total_size = cache_ways_of_associativity * cache_physical_line_partitions * cache_coherency_line_size * cache_sets;
|
||||
|
||||
int32_t cache_total_size = cache_ways_of_associativity * cache_physical_line_partitions * cache_coherency_line_size * cache_sets;
|
||||
cach->max_cache_level++;
|
||||
|
||||
switch (cache_type) {
|
||||
|
||||
switch (cache_type) {
|
||||
case 1: // Data Cache (We assume this is L1d)
|
||||
if(cache_level != 1) {
|
||||
printBug("Found data cache at level %d (expected 1)", cache_level);
|
||||
@@ -560,7 +560,7 @@ struct cache* get_cache_info_general(struct cache* cach, uint32_t level) {
|
||||
cach->L1d->size = cache_total_size;
|
||||
cach->L1d->exists = true;
|
||||
break;
|
||||
|
||||
|
||||
case 2: // Instruction Cache (We assume this is L1i)
|
||||
if(cache_level != 1) {
|
||||
printBug("Found instruction cache at level %d (expected 1)", cache_level);
|
||||
@@ -569,9 +569,9 @@ struct cache* get_cache_info_general(struct cache* cach, uint32_t level) {
|
||||
cach->L1i->size = cache_total_size;
|
||||
cach->L1i->exists = true;
|
||||
break;
|
||||
|
||||
|
||||
case 3: // Unified Cache (This may be L2 or L3)
|
||||
if(cache_level == 2) {
|
||||
if(cache_level == 2) {
|
||||
cach->L2->size = cache_total_size;
|
||||
cach->L2->exists = true;
|
||||
}
|
||||
@@ -584,21 +584,21 @@ struct cache* get_cache_info_general(struct cache* cach, uint32_t level) {
|
||||
cach->max_cache_level--;
|
||||
}
|
||||
break;
|
||||
|
||||
|
||||
default: // Unknown cache type
|
||||
printBug("Unknown cache type %d with level %d found at i=%d", cache_type, cache_level, i);
|
||||
return NULL;
|
||||
return NULL;
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
i++;
|
||||
} while (cache_type > 0);
|
||||
|
||||
|
||||
return cach;
|
||||
}
|
||||
|
||||
struct cache* get_cache_info(struct cpuInfo* cpu) {
|
||||
struct cache* cach = malloc(sizeof(struct cache));
|
||||
struct cache* get_cache_info(struct cpuInfo* cpu) {
|
||||
struct cache* cach = emalloc(sizeof(struct cache));
|
||||
init_cache_struct(cach);
|
||||
|
||||
uint32_t level;
|
||||
@@ -607,9 +607,9 @@ struct cache* get_cache_info(struct cpuInfo* cpu) {
|
||||
// We use extended 0x8000001D for AMD
|
||||
// or 0x80000005/6 for old AMD
|
||||
if(cpu->cpu_vendor == CPU_VENDOR_INTEL) {
|
||||
level = 0x00000004;
|
||||
level = 0x00000004;
|
||||
if(cpu->maxLevels < level) {
|
||||
printWarn("Can't read cache information from cpuid (needed level is 0x%.8X, max is 0x%.8X)", level, cpu->maxLevels);
|
||||
printWarn("Can't read cache information from cpuid (needed level is 0x%.8X, max is 0x%.8X)", level, cpu->maxLevels);
|
||||
return NULL;
|
||||
}
|
||||
else {
|
||||
@@ -619,7 +619,7 @@ struct cache* get_cache_info(struct cpuInfo* cpu) {
|
||||
else {
|
||||
level = 0x8000001D;
|
||||
if(cpu->maxExtendedLevels < level || !cpu->topology_extensions) {
|
||||
printWarn("Can't read cache information from cpuid (needed extended level is 0x%.8X, max is 0x%.8X and topology_extensions=%s)", level, cpu->maxExtendedLevels, cpu->topology_extensions ? "true" : "false");
|
||||
printWarn("Can't read cache information from cpuid (needed extended level is 0x%.8X, max is 0x%.8X and topology_extensions=%s)", level, cpu->maxExtendedLevels, cpu->topology_extensions ? "true" : "false");
|
||||
level = 0x80000006;
|
||||
if(cpu->maxExtendedLevels < level) {
|
||||
printWarn("Can't read cache information from cpuid using old method (needed extended level is 0x%.8X, max is 0x%.8X)", level, cpu->maxExtendedLevels);
|
||||
@@ -629,7 +629,7 @@ struct cache* get_cache_info(struct cpuInfo* cpu) {
|
||||
cach = get_cache_info_amd_fallback(cach);
|
||||
}
|
||||
else {
|
||||
cach = get_cache_info_general(cach, level);
|
||||
cach = get_cache_info_general(cach, level);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -637,8 +637,8 @@ struct cache* get_cache_info(struct cpuInfo* cpu) {
|
||||
}
|
||||
|
||||
struct frequency* get_frequency_info(struct cpuInfo* cpu) {
|
||||
struct frequency* freq = malloc(sizeof(struct frequency));
|
||||
|
||||
struct frequency* freq = emalloc(sizeof(struct frequency));
|
||||
|
||||
if(cpu->maxLevels < 0x00000016) {
|
||||
#if defined (_WIN32) || defined (__APPLE__)
|
||||
printWarn("Can't read frequency information from cpuid (needed level is 0x%.8X, max is 0x%.8X)", 0x00000016, cpu->maxLevels);
|
||||
@@ -703,7 +703,7 @@ char* get_str_peak_performance(struct cpuInfo* cpu, struct topology* topo, int64
|
||||
//7 for GFLOP/s and 6 for digits,eg 412.14
|
||||
uint32_t size = 7+6+1+1;
|
||||
assert(strlen(STRING_UNKNOWN)+1 <= size);
|
||||
char* string = malloc(sizeof(char)*size);
|
||||
char* string = emalloc(sizeof(char)*size);
|
||||
|
||||
//First check we have consistent data
|
||||
if(freq == UNKNOWN_FREQ) {
|
||||
@@ -714,8 +714,8 @@ char* get_str_peak_performance(struct cpuInfo* cpu, struct topology* topo, int64
|
||||
struct features* feat = cpu->feat;
|
||||
double flops = topo->physical_cores * topo->sockets * (freq*1000000);
|
||||
int vpus = get_number_of_vpus(cpu);
|
||||
|
||||
flops = flops * vpus;
|
||||
|
||||
flops = flops * vpus;
|
||||
|
||||
if(feat->FMA3 || feat->FMA4)
|
||||
flops = flops*2;
|
||||
@@ -729,11 +729,11 @@ char* get_str_peak_performance(struct cpuInfo* cpu, struct topology* topo, int64
|
||||
flops = flops*8;
|
||||
else if(feat->SSE)
|
||||
flops = flops*4;
|
||||
|
||||
|
||||
// See https://sites.utexas.edu/jdm4372/2018/01/22/a-peculiar-
|
||||
// throughput-limitation-on-intels-xeon-phi-x200-knights-landing/
|
||||
if(is_knights_landing(cpu))
|
||||
flops = flops * 6 / 7;
|
||||
flops = flops * 6 / 7;
|
||||
|
||||
if(flops >= (double)1000000000000.0)
|
||||
snprintf(string,size,"%.2f TFLOP/s",flops/1000000000000);
|
||||
@@ -741,7 +741,7 @@ char* get_str_peak_performance(struct cpuInfo* cpu, struct topology* topo, int64
|
||||
snprintf(string,size,"%.2f GFLOP/s",flops/1000000000);
|
||||
else
|
||||
snprintf(string,size,"%.2f MFLOP/s",flops/1000000);
|
||||
|
||||
|
||||
return string;
|
||||
}
|
||||
|
||||
@@ -751,7 +751,7 @@ char* get_str_topology(struct cpuInfo* cpu, struct topology* topo, bool dual_soc
|
||||
if(topo->smt_supported > 1) {
|
||||
//3 for digits, 21 for ' cores (SMT disabled)' which is the longest possible output
|
||||
uint32_t size = 3+21+1;
|
||||
string = malloc(sizeof(char)*size);
|
||||
string = emalloc(sizeof(char)*size);
|
||||
if(dual_socket) {
|
||||
if(topo->smt_available > 1)
|
||||
snprintf(string, size, "%d cores (%d threads)",topo->physical_cores * topo->sockets, topo->logical_cores * topo->sockets);
|
||||
@@ -775,7 +775,7 @@ char* get_str_topology(struct cpuInfo* cpu, struct topology* topo, bool dual_soc
|
||||
}
|
||||
else {
|
||||
uint32_t size = 3+7+1;
|
||||
string = malloc(sizeof(char)*size);
|
||||
string = emalloc(sizeof(char)*size);
|
||||
if(dual_socket)
|
||||
snprintf(string, size, "%d cores",topo->physical_cores * topo->sockets);
|
||||
else
|
||||
@@ -786,7 +786,7 @@ char* get_str_topology(struct cpuInfo* cpu, struct topology* topo, bool dual_soc
|
||||
|
||||
char* get_str_avx(struct cpuInfo* cpu) {
|
||||
//If all AVX are available, it will use up to 15
|
||||
char* string = malloc(sizeof(char)*17+1);
|
||||
char* string = emalloc(sizeof(char)*17+1);
|
||||
if(!cpu->feat->AVX)
|
||||
snprintf(string,2+1,"No");
|
||||
else if(!cpu->feat->AVX2)
|
||||
@@ -808,7 +808,7 @@ char* get_str_sse(struct cpuInfo* cpu) {
|
||||
uint32_t SSE4a_sl = 6;
|
||||
uint32_t SSE4_1_sl = 7;
|
||||
uint32_t SSE4_2_sl = 7;
|
||||
char* string = malloc(sizeof(char)*SSE_sl+SSE2_sl+SSE3_sl+SSSE3_sl+SSE4a_sl+SSE4_1_sl+SSE4_2_sl+1);
|
||||
char* string = emalloc(sizeof(char)*SSE_sl+SSE2_sl+SSE3_sl+SSSE3_sl+SSE4a_sl+SSE4_1_sl+SSE4_2_sl+1);
|
||||
|
||||
if(cpu->feat->SSE) {
|
||||
snprintf(string+last,SSE_sl+1,"SSE,");
|
||||
@@ -845,7 +845,7 @@ char* get_str_sse(struct cpuInfo* cpu) {
|
||||
}
|
||||
|
||||
char* get_str_fma(struct cpuInfo* cpu) {
|
||||
char* string = malloc(sizeof(char)*9+1);
|
||||
char* string = emalloc(sizeof(char)*9+1);
|
||||
if(!cpu->feat->FMA3)
|
||||
snprintf(string,2+1,"No");
|
||||
else if(!cpu->feat->FMA4)
|
||||
@@ -861,9 +861,9 @@ void print_debug(struct cpuInfo* cpu) {
|
||||
uint32_t ebx = 0;
|
||||
uint32_t ecx = 0;
|
||||
uint32_t edx = 0;
|
||||
|
||||
|
||||
cpuid(&eax, &ebx, &ecx, &edx);
|
||||
|
||||
|
||||
printf("%s\n", cpu->cpu_name);
|
||||
if(cpu->hv->present) {
|
||||
printf("- Hypervisor: %s\n", cpu->hv->hv_name);
|
||||
@@ -871,7 +871,7 @@ void print_debug(struct cpuInfo* cpu) {
|
||||
printf("- Max standard level: 0x%.8X\n", cpu->maxLevels);
|
||||
printf("- Max extended level: 0x%.8X\n", cpu->maxExtendedLevels);
|
||||
if(cpu->cpu_vendor == CPU_VENDOR_AMD) {
|
||||
printf("- AMD topology extensions: %d\n", cpu->topology_extensions);
|
||||
printf("- AMD topology extensions: %d\n", cpu->topology_extensions);
|
||||
}
|
||||
printf("- CPUID dump: 0x%.8X\n", eax);
|
||||
|
||||
@@ -887,7 +887,7 @@ void print_raw(struct cpuInfo* cpu) {
|
||||
printf("%s\n\n", cpu->cpu_name);
|
||||
printf(" CPUID leaf sub EAX EBX ECX EDX \n");
|
||||
printf("--------------------------------------------------------------\n");
|
||||
|
||||
|
||||
for(int c=0; c < cpu->topo->total_cores; c++) {
|
||||
#ifndef __APPLE__
|
||||
if(!bind_to_cpu(c)) {
|
||||
@@ -895,9 +895,9 @@ void print_raw(struct cpuInfo* cpu) {
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
||||
printf("CPU %d:\n", c);
|
||||
|
||||
|
||||
printf("CPU %d:\n", c);
|
||||
|
||||
for(uint32_t reg=0x00000000; reg <= cpu->maxLevels; reg++) {
|
||||
if(reg == 0x00000004) {
|
||||
for(uint32_t reg2=0x00000000; reg2 < cpu->cach->max_cache_level; reg2++) {
|
||||
@@ -905,9 +905,9 @@ void print_raw(struct cpuInfo* cpu) {
|
||||
ebx = 0;
|
||||
ecx = reg2;
|
||||
edx = 0;
|
||||
|
||||
|
||||
cpuid(&eax, &ebx, &ecx, &edx);
|
||||
|
||||
|
||||
printf(" 0x%.8X 0x%.2X: 0x%.8X 0x%.8X 0x%.8X 0x%.8X\n", reg, reg2, eax, ebx, ecx, edx);
|
||||
}
|
||||
}
|
||||
@@ -917,9 +917,9 @@ void print_raw(struct cpuInfo* cpu) {
|
||||
ebx = 0;
|
||||
ecx = reg2;
|
||||
edx = 0;
|
||||
|
||||
|
||||
cpuid(&eax, &ebx, &ecx, &edx);
|
||||
|
||||
|
||||
printf(" 0x%.8X 0x%.2X: 0x%.8X 0x%.8X 0x%.8X 0x%.8X\n", reg, reg2, eax, ebx, ecx, edx);
|
||||
}
|
||||
}
|
||||
@@ -928,10 +928,10 @@ void print_raw(struct cpuInfo* cpu) {
|
||||
ebx = 0;
|
||||
ecx = 0;
|
||||
edx = 0;
|
||||
|
||||
|
||||
cpuid(&eax, &ebx, &ecx, &edx);
|
||||
|
||||
printf(" 0x%.8X 0x%.2X: 0x%.8X 0x%.8X 0x%.8X 0x%.8X\n", reg, 0x00, eax, ebx, ecx, edx);
|
||||
|
||||
printf(" 0x%.8X 0x%.2X: 0x%.8X 0x%.8X 0x%.8X 0x%.8X\n", reg, 0x00, eax, ebx, ecx, edx);
|
||||
}
|
||||
}
|
||||
for(uint32_t reg=0x80000000; reg <= cpu->maxExtendedLevels; reg++) {
|
||||
@@ -941,9 +941,9 @@ void print_raw(struct cpuInfo* cpu) {
|
||||
ebx = 0;
|
||||
ecx = reg2;
|
||||
edx = 0;
|
||||
|
||||
|
||||
cpuid(&eax, &ebx, &ecx, &edx);
|
||||
|
||||
|
||||
printf(" 0x%.8X 0x%.2X: 0x%.8X 0x%.8X 0x%.8X 0x%.8X\n", reg, reg2, eax, ebx, ecx, edx);
|
||||
}
|
||||
}
|
||||
@@ -952,9 +952,9 @@ void print_raw(struct cpuInfo* cpu) {
|
||||
ebx = 0;
|
||||
ecx = 0;
|
||||
edx = 0;
|
||||
|
||||
|
||||
cpuid(&eax, &ebx, &ecx, &edx);
|
||||
|
||||
|
||||
printf(" 0x%.8X 0x%.2X: 0x%.8X 0x%.8X 0x%.8X 0x%.8X\n", reg, 0x00, eax, ebx, ecx, edx);
|
||||
}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user