Dr-Noob
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35efdd8f2c
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Fix #26. Guess number of VPUs according to microarchitecture
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2020-08-31 14:04:41 +02:00 |
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Dr-Noob
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5148962fa3
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Add code to detect CPU microarchitecture (Intel only, at the moment)
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2020-08-31 13:18:25 +02:00 |
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Dr-Noob
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d998acdcdf
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Fix #25: Compute PP taking into account the number of sockets
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2020-08-31 09:33:39 +02:00 |
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Dr-Noob
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81a45628f0
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Code refactoring. Forgot to add verbose option to help
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2020-08-30 13:55:37 +02:00 |
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Dr-Noob
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4f98a5bccf
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Refactor previous commit
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2020-08-30 12:42:38 +02:00 |
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Dr-Noob
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dae0f678ad
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Fix #23. I tried fetching the cache topology in AMD but could not find a proper way, so the code fallback to two commits ago. cpufetch has to guess cache sizes except L3, which can be fetched. Since I have been trying many approaches and stuff, the code needs to be refactored
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2020-08-30 12:12:25 +02:00 |
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Dr-Noob
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69cc08759a
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Fix #21 and #22: Obtain the number of caches of every level instead of guessing them. It is done by fetching cache topology from apic. It works, but it needs a big refactoring. Moreover, it currently works only on Intel CPUs, so this breaks the cache in AMD.
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2020-08-29 21:51:14 +02:00 |
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Dr-Noob
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d8dad29a57
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Fix SMT bug in AMD. I would like to improve it, since Intel can use APIC with 0x1 and 0xB (extended) while AMD does with 0x1 and extended seems to be 0x1E. Add support to detect more than one L3 cache. This is not a very elegant solution, since we still assume that we have the same number of caches as caches in a given level. To fix it, cpufetch should know how many caches are in a given level (hint, Linux knows using shared_cpu_map)
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2020-08-29 15:42:56 +02:00 |
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Dr-Noob
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ad6c3c88ce
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Small corrections in code and Makefile
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2020-07-12 15:39:34 +02:00 |
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Dr-Noob
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e114bde128
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Complete topology read in AMD
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2020-07-06 01:58:48 +02:00 |
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Dr-Noob
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7164409ca2
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Add legacy style (for Windows) and make it the default for Windows. Add verbose flag
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2020-07-06 01:30:14 +02:00 |
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Dr-Noob
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08f79bb914
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Fix compilation in Windows and add support for bind to specific cores. Separate APIC code in other file
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2020-07-06 01:16:59 +02:00 |
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Dr-Noob
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b457c86100
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Add support for obtaining topology in old processors (with CPUID less than 0xB)
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2020-07-05 19:59:55 +02:00 |
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Dr-Noob
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e5d86289b5
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Use APIC to obtain topology. This is interesting because this will allow us to obtain it even on older CPUs (without CPUID 0xB) (will be added in future commits)
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2020-07-05 16:52:41 +02:00 |
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Dr-Noob
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c6c4d8b6fd
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Fix spaces bug in CPU name
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2020-07-03 19:42:05 +02:00 |
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Dr-Noob
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c8fde107dd
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Fix ascii logo in AMD. Fix output on CPUs without L3
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2020-07-03 16:24:14 +02:00 |
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Dr-Noob
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b076189b32
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Add support to detect if HT/SMT is enabled or disabled
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2020-07-03 16:11:09 +02:00 |
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Dr-Noob
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d7b7e2b62d
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Support printing dual socket. Fix bug where cache sizes were not displayed correctly (they were truncated)
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2020-06-29 17:13:37 +02:00 |
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Dr-Noob
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941bf35d03
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Big refactoring. Move ascii managment to printer. Mix extended and standart cpuid functions in cpuid file. Old cpuid renamed to cpuid_asm. Store cpu name in cpuInfo struct
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2020-06-28 15:51:30 +02:00 |
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Dr-Noob
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a2dab8129c
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Use standart types instead of int/long in specific files. This fixes a problem in Windows, were PP was not computed correctly. Compiling with C99
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2020-06-22 12:47:14 +02:00 |
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Dr-Noob
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9f55672aa2
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Divide source code from other stuff
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2018-06-23 13:04:42 +02:00 |
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