Dr-Noob
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81a45628f0
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Code refactoring. Forgot to add verbose option to help
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2020-08-30 13:55:37 +02:00 |
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Dr-Noob
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4f98a5bccf
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Refactor previous commit
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2020-08-30 12:42:38 +02:00 |
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Dr-Noob
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dae0f678ad
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Fix #23. I tried fetching the cache topology in AMD but could not find a proper way, so the code fallback to two commits ago. cpufetch has to guess cache sizes except L3, which can be fetched. Since I have been trying many approaches and stuff, the code needs to be refactored
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2020-08-30 12:12:25 +02:00 |
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Dr-Noob
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69cc08759a
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Fix #21 and #22: Obtain the number of caches of every level instead of guessing them. It is done by fetching cache topology from apic. It works, but it needs a big refactoring. Moreover, it currently works only on Intel CPUs, so this breaks the cache in AMD.
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2020-08-29 21:51:14 +02:00 |
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Dr-Noob
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e114bde128
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Complete topology read in AMD
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2020-07-06 01:58:48 +02:00 |
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Dr-Noob
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08f79bb914
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Fix compilation in Windows and add support for bind to specific cores. Separate APIC code in other file
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2020-07-06 01:16:59 +02:00 |
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