Dr-Noob
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50931ee94d
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[v0.86][BUGFIX] Fix print format for hex values
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2020-11-21 16:45:51 +01:00 |
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Dr-Noob
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42ade63746
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[v0.86][BUGFIX] Add old AMD CPUs cache fix to master branch
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2020-11-21 16:41:08 +01:00 |
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Dr-Noob
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e4a4e13d56
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[v0.82][BUGFIX] Using 0x80000006 in new AMD CPUs outputs wrong L3 size since it reports the full size instead the size of a single L3. Use old method just when is necessary
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2020-11-21 16:37:51 +01:00 |
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Dr-Noob
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7d707916fb
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[v0.86][OPTIONS] Replace levels option with debug option, which does the same on x86, but also exists on ARM, which prints MIDR registers (need work to be properly implemented)
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2020-11-18 23:41:42 +01:00 |
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Dr-Noob
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b978ddc83d
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[v0.82][BUGFIX] Issue #33: Use 0x80000006 for cache fetching in AMD, instead of 0x8000001D. This means that a different approach in Intel and AMD CPUs
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2020-11-07 10:48:48 +01:00 |
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Dr-Noob
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4f1722ead6
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[v0.81][ARM][Refactoring] Refactoring and very basic ARM support
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2020-11-05 13:44:46 +01:00 |
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Dr-Noob
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f4f68287aa
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[v0.8][Refactoring] Refactoring ARM code and source code tree
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2020-11-05 11:01:46 +01:00 |
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Dr-Noob
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1fad4fd10b
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[v0.8][ARM] Building support in ARM
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2020-11-05 09:28:41 +01:00 |
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