Dr-Noob
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fba69daee0
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[v0.98][Refactoring] Simplify x86 get_str_topology
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2021-08-07 10:27:41 +02:00 |
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Dr-Noob
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a03f296390
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[v0.98] Fix bug in get_str_peak_performance and always show unknown pp when freq is also unknown
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2021-08-07 08:58:49 +02:00 |
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Dr-Noob
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2b21326167
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[v0.98][Refactoring] Use printWarn + strerror(errno) instead of perror. Use fallback in ppc in case total_cores cannot be retrieved
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2021-08-07 08:45:37 +02:00 |
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Dr-Noob
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c24dd7cbb6
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[v0.98][Refactoring] Use int for peak performance, which makes code cleaner
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2021-08-06 11:04:29 +02:00 |
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Dr-Noob
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6953d8dda5
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[v0.98][Refactoring] Unify the use of get_str_peak_performance
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2021-08-06 10:26:07 +02:00 |
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Dr-Noob
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44d4b3b553
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[v0.98][Refactoring] Unify the use of init_topology_struct and init_cache_struct
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2021-08-05 20:01:32 +02:00 |
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Dr-Noob
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6ab6afc974
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[v0.98][Refactoring] Unify the use of unknown string
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2021-08-05 19:07:09 +02:00 |
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Dr-Noob
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c4f6ba7c55
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[v0.98] Fix compilation in different platforms
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2021-08-04 23:33:44 +02:00 |
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Dr-Noob
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eac97bf721
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[v0.98] Use malloc/calloc wrapper that exits when alloc fails, as suggested by #90
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2021-08-04 10:01:32 +02:00 |
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Dr-Noob
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3a636c101b
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[v0.98] Use unsigned integers in bit operations as suggested by #76
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2021-08-03 23:54:49 +02:00 |
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Dr-Noob
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bb502250c6
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[v0.98] Update ryzen uarch table. Add bash script to decode CPUID
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2021-07-27 10:06:59 +02:00 |
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Dr-Noob
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5c3f49c580
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[v0.98] Patch to fix the compilation error reported by #93
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2021-06-19 00:03:13 +02:00 |
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Dr-Noob
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e22c2a8f3c
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[0.97] Do not count "L4" cache when computing the max cache level. Fixes #43
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2021-05-03 15:04:28 +02:00 |
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Dr-Noob
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fe7a99087d
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[v0.97] Merge branch bugfix2
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2021-04-24 23:24:32 +02:00 |
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Dr-Noob
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37eba4ba0c
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[v0.97] Do not consider CPUID freq == 0 as a bug. Check udev if CPUID freq is not supported
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2021-04-13 15:33:54 +02:00 |
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Dr-Noob
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9fa7b4ce7f
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[v0.97] Use DESTDIR instead of PREFIX in Makefile
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2021-04-12 15:47:59 +02:00 |
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Dr-Noob
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8f2f3d3a16
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[v0.97] Merge bugfix3 branch to support Rocket Lake processors
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2021-04-09 20:06:05 +02:00 |
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Dr-Noob
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ec5f80adc1
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[v0.97] Fix compilation in macOS
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2021-04-09 15:49:21 +02:00 |
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Dr-Noob
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ecca042d86
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[v0.97] Manually merge bugfix branch with latest fixes
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2021-04-09 15:37:17 +02:00 |
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Dr-Noob
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c718d83868
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[v0.96] Add Rocket Lake uarch detection as suggested by #68
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2021-04-09 11:26:34 +02:00 |
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Dr-Noob
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8bb65e0cc0
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[v0.96] Fix compilation issue in Windows
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2021-04-09 09:25:48 +02:00 |
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Dr-Noob
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e8d2898ae3
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[v0.96] Remove cache sizes check
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2021-04-08 13:18:35 +02:00 |
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Dr-Noob
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a67a605fb5
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[v0.96] Print "Unknown" string when manufacturing process is unkown
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2021-04-08 10:12:01 +02:00 |
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Dr-Noob
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044608f31f
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[v0.95] Add 0x8000001D sublevel query to --raw option
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2021-04-07 14:35:45 +02:00 |
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Dr-Noob
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2879876500
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[v0.96] Dont treat unknown unified cache as a bug, since there are some processors with eDRAM which supports this level, like #41
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2021-04-07 11:17:43 +02:00 |
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Dr-Noob
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c7cc8be712
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[v0.96] Use lower verbosity for some errors found in cpuid
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2021-04-07 10:37:17 +02:00 |
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Dr-Noob
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09cbb8874b
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[v0.96] Fix previous mistake: use level 0xB to check if the level is supported or not, according to Intel docs
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2021-04-06 20:37:49 +02:00 |
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Dr-Noob
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fe95ca3e10
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[v0.96] Fix bug where ebx returned 0 in apic.c when CPU max level >= 0xB but CPU does not support x2apic
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2021-04-06 16:56:26 +02:00 |
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Dr-Noob
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d56f7ffd14
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[v0.96] Fix segfault when invalid cache size is found
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2021-04-06 12:56:44 +02:00 |
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Dr-Noob
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7420792ef5
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[v0.95] Fetch topology extensions field in AMD processors
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2021-03-30 10:39:27 +02:00 |
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Dr-Noob
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db32cccd91
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[v0.95] Add --raw option
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2021-03-15 21:49:47 +01:00 |
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Dr-Noob
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a8d8ac2e91
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[v0.95] Temporarily disable cache sanity checks
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2021-03-06 22:13:32 +01:00 |
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Dr-Noob
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e21ca95da8
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[0.95][x86] Merge bugfix branch, which adds macOS support to cpufetch
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2021-01-14 18:46:41 +01:00 |
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Dr-Noob
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3bac5cbfe2
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[v0.95][x86] Print CPUID 0x1 EAX register with debug flag
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2021-01-10 22:03:25 +01:00 |
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Dr-Noob
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04f0bfcbde
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[v0.94][x86] Add uarch detection for Intel families derived from Kaby Lake
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2021-01-10 22:01:17 +01:00 |
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Dr-Noob
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697a921042
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[X86] Avoid checking /sys directory in macOS to find frequency
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2021-01-10 09:01:50 +01:00 |
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Dr-Noob
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3b624f3025
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[X86] Fix bug where unknown hypervisor caused a segfault. This should solve issue #38
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2021-01-05 17:37:26 +01:00 |
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Dr-Noob
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2494b56a49
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[X86] Fix compilation error in MacOS. MacOS does not provide any method to bin threads to cores, so its pretty hard to get apic ids. This first approach is really dark and I hope I can improve it in the future
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2021-01-05 17:35:57 +01:00 |
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Dr-Noob
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797c708f2d
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[v0.94][x86] Consider missing frequency file in x86_64 as a bug if no hypervisor is present. Took this idea from issue #37. Add if hypervisor is present to debug mode to prevent more confusions in the future
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2020-12-29 00:09:01 +01:00 |
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Dr-Noob
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56a1da3428
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[v0.94] Do not consider missing frequency file in x86_64 as a bug. Fix typos
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2020-12-26 08:52:14 +01:00 |
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Dr-Noob
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01e22b8090
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[v0.94] Fix compilation issues
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2020-12-01 16:13:38 +01:00 |
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Dr-Noob
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b1f3196e0d
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[v0.94] Refactor CPU features in a separate struct. Remove x86 debug functions
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2020-12-01 12:16:12 +01:00 |
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Dr-Noob
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89e5e30e53
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[v0.91][X86][BUGFIX] Fix annoying compilation issue
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2020-11-26 13:05:14 +01:00 |
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Dr-Noob
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fbea497740
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[v0.89] Change freq from int64 to int32, which fixes a compilation issue. Fix Makefile in Windows
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2020-11-24 12:52:42 +01:00 |
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Dr-Noob
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fcb2c716db
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[v0.87][FREQ] Frequency in udev is now fetched as a per core basis. Before this commit, freq was always fetched from core 0. This allows ARM do detect the max frequency of each of the cores (which may or may not be the same in all of them)
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2020-11-22 10:23:02 +01:00 |
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Dr-Noob
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0875c4d425
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[v0.87][ARM] cpuInfo now holds all the structs (freq, cache, etc), instead of having them separated. This allows ARM to represent a single CPU, because from its pointer, it is able to access the specific frequency, cache, etc
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2020-11-22 09:57:50 +01:00 |
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Dr-Noob
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50931ee94d
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[v0.86][BUGFIX] Fix print format for hex values
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2020-11-21 16:45:51 +01:00 |
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Dr-Noob
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42ade63746
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[v0.86][BUGFIX] Add old AMD CPUs cache fix to master branch
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2020-11-21 16:41:08 +01:00 |
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Dr-Noob
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e4a4e13d56
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[v0.82][BUGFIX] Using 0x80000006 in new AMD CPUs outputs wrong L3 size since it reports the full size instead the size of a single L3. Use old method just when is necessary
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2020-11-21 16:37:51 +01:00 |
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Dr-Noob
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7d707916fb
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[v0.86][OPTIONS] Replace levels option with debug option, which does the same on x86, but also exists on ARM, which prints MIDR registers (need work to be properly implemented)
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2020-11-18 23:41:42 +01:00 |
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