Add description for missign extensions

src/common/cpu.h

@@ -138,7 +138,7 @@ struct features {
 
 struct extensions {
   char* str;
-  uint64_t mask;
+  bool* mask; // allocated at runtime with size RISCV_ISA_EXT_ID_MAX-1
 };
 
 struct cpuInfo {

src/common/printer.c

@@ -949,14 +949,7 @@ bool print_cpufetch_arm(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
 #endif
 
 #ifdef ARCH_RISCV
-// https://stackoverflow.com/a/2709523
+void print_ascii_riscv(struct ascii* art, uint32_t la, int32_t termw, bool use_short, bool* extensions_mask) {
-uint64_t number_of_bits(uint64_t i) {
-  i = i - ((i >> 1) & 0x5555555555555555);
-  i = (i & 0x3333333333333333) + ((i >> 2) & 0x3333333333333333);
-  return (((i + (i >> 4)) & 0xF0F0F0F0F0F0F0F) * 0x101010101010101) >> 56;
-}
-
-void print_ascii_riscv(struct ascii* art, uint32_t la, int32_t termw, bool use_short, uint64_t extensions_mask) {
   struct ascii_logo* logo = art->art;
   int attr_to_print = 0;
   int attr_type;
@@ -966,7 +959,7 @@ void print_ascii_riscv(struct ascii* art, uint32_t la, int32_t termw, bool use_s
   int32_t ext_list_size = sizeof(extension_list)/sizeof(extension_list[0]);
   int32_t ext_num = 0;
   int32_t ext_to_print = 0;
-  int32_t num_extensions = number_of_bits(extensions_mask);
+  int32_t num_extensions = get_num_extensions(extensions_mask);
   int32_t space_up = ((int)logo->height - (int)(art->n_attributes_set + num_extensions))/2;
   int32_t space_down = (int)logo->height - (int)(art->n_attributes_set + num_extensions) - (int)space_up;
   uint32_t logo_pos = 0;
@@ -1012,7 +1005,9 @@ void print_ascii_riscv(struct ascii* art, uint32_t la, int32_t termw, bool use_s
       // Print extension
       if(attr_to_print > 0 && art->attributes[attr_to_print-1]->type == ATTRIBUTE_EXTENSIONS && ext_num != num_extensions) {
         // Search for the extension to print
-        while(ext_to_print < ext_list_size && !((extensions_mask >> extension_list[ext_to_print].id) & 1U)) ext_to_print++;
+        while (ext_to_print < ext_list_size && !((extensions_mask[extension_list[ext_to_print].id])))
+          ext_to_print++;
+
         if(ext_to_print == ext_list_size) {
           printBug("print_ascii_riscv: Unable to find the extension to print");
         }

src/riscv/riscv.c

@@ -12,7 +12,7 @@
 #define SET_ISA_EXT_MAP(name, bit)          \
   if(strncmp(multi_letter_extension, name,  \
         multi_letter_extension_len) == 0) { \
-    ext->mask |= 1UL << bit;                \
+    ext->mask[bit] = true;                  \
     maskset = true;                         \
   }                                         \
 
@@ -62,7 +62,6 @@ int parse_multi_letter_extension(struct extensions* ext, char* e) {
   SET_ISA_EXT_MAP("zicbom",      RISCV_ISA_EXT_ZICBOM)
   SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE)
   SET_ISA_EXT_MAP("svnapot",     RISCV_ISA_EXT_SVNAPOT)
-  SET_ISA_EXT_MAP("zicbop",      RISCV_ISA_EXT_ZICBOP)
   SET_ISA_EXT_MAP("zicboz",      RISCV_ISA_EXT_ZICBOZ)
   SET_ISA_EXT_MAP("smaia",       RISCV_ISA_EXT_SMAIA)
   SET_ISA_EXT_MAP("ssaia",       RISCV_ISA_EXT_SSAIA)
@@ -153,7 +152,7 @@ bool valid_extension(char ext) {
 
 struct extensions* get_extensions_from_str(char* str) {
   struct extensions* ext = emalloc(sizeof(struct extensions));
-  ext->mask = 0;
+  ext->mask = ecalloc(RISCV_ISA_EXT_ID_MAX, sizeof(bool));
   ext->str = NULL;
 
   if(str == NULL) {
@@ -166,6 +165,8 @@ struct extensions* get_extensions_from_str(char* str) {
 
   // Code inspired in Linux kernel (riscv_fill_hwcap):
   // https://elixir.bootlin.com/linux/v6.2.10/source/arch/riscv/kernel/cpufeature.c
+  // Now it seems to be here in riscv_parse_isa_string:
+  // https://elixir.bootlin.com/linux/v6.16/source/arch/riscv/kernel/cpufeature.c
   char* isa = str;
   if (!strncmp(isa, "rv32", 4))
     isa += 4;
@@ -197,7 +198,7 @@ struct extensions* get_extensions_from_str(char* str) {
       // adding it to the mask
       if(valid_extension(*e)) {
         int n = *e - 'a';
-        ext->mask |= 1UL << n;
+        ext->mask[n] = true;
       }
       else {
         printBug("get_extensions_from_str: Invalid extension: '%c'", *e);
@@ -208,6 +209,18 @@ struct extensions* get_extensions_from_str(char* str) {
   return ext;
 }
 
+uint32_t get_num_extensions(bool* mask) {
+  uint32_t num = 0;
+  for (int i=0; i < RISCV_ISA_EXT_ID_MAX; i++) {
+    if (mask[i]) num++;
+  }
+  return num;
+}
+
+bool is_mask_empty(bool* mask) {
+  return get_num_extensions(mask) == 0;
+}
+
 struct cpuInfo* get_cpu_info(void) {
   struct cpuInfo* cpu = malloc(sizeof(struct cpuInfo));
   //init_cpu_info(cpu);
@@ -220,7 +233,7 @@ struct cpuInfo* get_cpu_info(void) {
   cpu->hv = emalloc(sizeof(struct hypervisor));
   cpu->hv->present = false;
   cpu->ext = get_extensions_from_str(ext_str);
-  if(cpu->ext->str != NULL && cpu->ext->mask == 0) return NULL;
+  if(cpu->ext->str != NULL && is_mask_empty(cpu->ext->mask)) return NULL;
   cpu->arch = get_uarch(cpu);
   cpu->soc = get_soc(cpu);
   cpu->freq = get_frequency_info(0);

src/riscv/riscv.h

@@ -89,7 +89,7 @@ enum riscv_isa_ext_id {
   RISCV_ISA_EXT_ZAAMO,
   RISCV_ISA_EXT_ZALRSC,
   RISCV_ISA_EXT_ZICBOP,
-  RISCV_ISA_EXT_IME,
+  RISCV_ISA_EXT_IME,      // This is not in the kernel! but it was seen on a Muse Pi Pro board
   RISCV_ISA_EXT_ID_MAX
 };
 
@@ -97,6 +97,9 @@ enum riscv_isa_ext_id {
 // https://en.wikichip.org/wiki/risc-v/standard_extensions
 // (Zicbop) https://github.com/riscv/riscv-CMOs/blob/master/cmobase/Zicbop.adoc
 // https://raw.githubusercontent.com/riscv/riscv-CMOs/master/specifications/cmobase-v1.0.1.pdf
+// https://www.kernel.org/doc/Documentation/devicetree/bindings/riscv/extensions.yaml
+// https://gcc.gnu.org/onlinedocs/gcc/RISC-V-Options.html
+// (Ime) https://github.com/riscv/integrated-matrix-extension (not confirmed, just a guess...)
 // Included all except for G
 static const struct extension extension_list[] = {
   { 'i' - 'a', "(I) Integer Instruction Set" },
@@ -133,69 +136,70 @@ static const struct extension extension_list[] = {
   { RISCV_ISA_EXT_ZICSR,       "(Zicsr) Control and Status Register" },
   { RISCV_ISA_EXT_ZIFENCEI,    "(Zifencei) Instruction-Fetch Fence" },
   { RISCV_ISA_EXT_ZIHPM,       "(Zihpm) Hardware Performance Counters" },
-  { RISCV_ISA_EXT_SMSTATEEN,   "(smstateen) " },
+  { RISCV_ISA_EXT_SMSTATEEN,   "(Smstateen) Supervisor/Hypervisor State Enable" },
-  { RISCV_ISA_EXT_ZICOND,      "(zicond) " },
+  { RISCV_ISA_EXT_ZICOND,      "(Zicond) Integer Conditional Operations" },
-  { RISCV_ISA_EXT_ZBC,         "(zbc) " },
+  { RISCV_ISA_EXT_ZBC,         "(Zbc) Carry-Less Multiplication" },
-  { RISCV_ISA_EXT_ZBKB,        "(zbkb) " },
+  { RISCV_ISA_EXT_ZBKB,        "(Zbkb) Bit-Manipulation for Cryptography (Byte ops)" },
-  { RISCV_ISA_EXT_ZBKC,        "(zbkc) " },
+  { RISCV_ISA_EXT_ZBKC,        "(Zbkc) Bit-Manipulation for Cryptography (Carry-less ops)" },
-  { RISCV_ISA_EXT_ZBKX,        "(zbkx) " },
+  { RISCV_ISA_EXT_ZBKX,        "(Zbkx) Bit-Manipulation for Cryptography (Crossbar ops)" },
-  { RISCV_ISA_EXT_ZKND,        "(zknd) " },
+  { RISCV_ISA_EXT_ZKND,        "(Zknd) NIST AES Decryption Instructions" },
-  { RISCV_ISA_EXT_ZKNE,        "(zkne) " },
+  { RISCV_ISA_EXT_ZKNE,        "(Zkne) NIST AES Encryption Instructions" },
-  { RISCV_ISA_EXT_ZKNH,        "(zknh) " },
+  { RISCV_ISA_EXT_ZKNH,        "(Zknh) NIST Hash (SHA-2/SHA-3) Instructions" },
-  { RISCV_ISA_EXT_ZKR,         "(zkr) " },
+  { RISCV_ISA_EXT_ZKR,         "(Zkr) Entropy Source Reading (Random)" },
-  { RISCV_ISA_EXT_ZKSED,       "(zksed) " },
+  { RISCV_ISA_EXT_ZKSED,       "(Zksed) SM4 Block Cipher Decryption" },
-  { RISCV_ISA_EXT_ZKSH,        "(zksh) " },
+  { RISCV_ISA_EXT_ZKSH,        "(Zksh) SM3 Hash Instructions" },
-  { RISCV_ISA_EXT_ZKT,         "(zkt) " },
+  { RISCV_ISA_EXT_ZKT,         "(Zkt) Data-Independent Execution Latency" },
-  { RISCV_ISA_EXT_ZVBB,        "(zvbb) " },
+  { RISCV_ISA_EXT_ZVBB,        "(Zvbb) Vector Basic Bit-Manipulation" },
-  { RISCV_ISA_EXT_ZVBC,        "(zvbc) " },
+  { RISCV_ISA_EXT_ZVBC,        "(Zvbc) Vector Carry-Less Multiplication" },
-  { RISCV_ISA_EXT_ZVKB,        "(zvkb) " },
+  { RISCV_ISA_EXT_ZVKB,        "(Zvkb) Vector Cryptography (Byte ops)" },
-  { RISCV_ISA_EXT_ZVKG,        "(zvkg) " },
+  { RISCV_ISA_EXT_ZVKG,        "(Zvkg) Vector GCM/GMAC Instructions" },
-  { RISCV_ISA_EXT_ZVKNED,      "(zvkned) " },
+  { RISCV_ISA_EXT_ZVKNED,      "(Zvkned) Vector AES Decryption" },
-  { RISCV_ISA_EXT_ZVKNHA,      "(zvknha) " },
+  { RISCV_ISA_EXT_ZVKNHA,      "(Zvknha) Vector SHA-2 Hash (A variant)" },
-  { RISCV_ISA_EXT_ZVKNHB,      "(zvknhb) " },
+  { RISCV_ISA_EXT_ZVKNHB,      "(Zvknhb) Vector SHA-2 Hash (B variant)" },
-  { RISCV_ISA_EXT_ZVKSED,      "(zvksed) " },
+  { RISCV_ISA_EXT_ZVKSED,      "(Zvksed) Vector SM4 Block Cipher Decryption" },
-  { RISCV_ISA_EXT_ZVKSH,       "(zvksh) " },
+  { RISCV_ISA_EXT_ZVKSH,       "(Zvksh) Vector SM3 Hash Instructions" },
-  { RISCV_ISA_EXT_ZVKT,        "(zvkt) " },
+  { RISCV_ISA_EXT_ZVKT,        "(Zvkt) Vector Data-Independent Execution Latency" },
-  { RISCV_ISA_EXT_ZFH,         "(zfh) " },
+  { RISCV_ISA_EXT_ZFH,         "(Zfh) Half-Precision Floating Point" },
-  { RISCV_ISA_EXT_ZFHMIN,      "(zfhmin) " },
+  { RISCV_ISA_EXT_ZFHMIN,      "(Zfhmin) Minimal Half-Precision Floating Point" },
-  { RISCV_ISA_EXT_ZIHINTNTL,   "(zihintntl) " },
+  { RISCV_ISA_EXT_ZIHINTNTL,   "(Zihintntl) Non-Temporal Load/Store Hints" },
-  { RISCV_ISA_EXT_ZVFH,        "(zvfh) " },
+  { RISCV_ISA_EXT_ZVFH,        "(Zvfh) Vector Half-Precision Floating Point" },
-  { RISCV_ISA_EXT_ZVFHMIN,     "(zvfhmin) " },
+  { RISCV_ISA_EXT_ZVFHMIN,     "(Zvfhmin) Minimal Vector Half-Precision Floating Point" },
-  { RISCV_ISA_EXT_ZFA,         "(zfa) " },
+  { RISCV_ISA_EXT_ZFA,         "(Zfa) Additional Floating-Point Instructions" },
-  { RISCV_ISA_EXT_ZTSO,        "(ztso) " },
+  { RISCV_ISA_EXT_ZTSO,        "(Ztso) Total Store Ordering Memory Model" },
-  { RISCV_ISA_EXT_ZACAS,       "(zacas) " },
+  { RISCV_ISA_EXT_ZACAS,       "(Zacas) Atomic Compare-and-Swap" },
-  { RISCV_ISA_EXT_ZVE32X,      "(zve32x) " },
+  { RISCV_ISA_EXT_ZVE32X,      "(Zve32x) Embedded Vector Integer (32-bit elements)" },
-  { RISCV_ISA_EXT_ZVE32F,      "(zve32f) " },
+  { RISCV_ISA_EXT_ZVE32F,      "(Zve32f) Embedded Vector Floating Point (f32)" },
-  { RISCV_ISA_EXT_ZVE64X,      "(zve64x) " },
+  { RISCV_ISA_EXT_ZVE64X,      "(Zve64x) Embedded Vector Integer (64-bit elements)" },
-  { RISCV_ISA_EXT_ZVE64F,      "(zve64f) " },
+  { RISCV_ISA_EXT_ZVE64F,      "(Zve64f) Embedded Vector Floating Point (f64)" },
-  { RISCV_ISA_EXT_ZVE64D,      "(zve64d) " },
+  { RISCV_ISA_EXT_ZVE64D,      "(Zve64d) Embedded Vector Double-Precision FP (f64)" },
-  { RISCV_ISA_EXT_ZIMOP,       "(zimop) " },
+  { RISCV_ISA_EXT_ZIMOP,       "(Zimop) Integer Multiply-Only Instructions" },
-  { RISCV_ISA_EXT_ZCA,         "(zca) " },
+  { RISCV_ISA_EXT_ZCA,         "(Zca) Compressed Integer Instructions" },
-  { RISCV_ISA_EXT_ZCB,         "(zcb) " },
+  { RISCV_ISA_EXT_ZCB,         "(Zcb) Compressed Bit-Manipulation Instructions" },
-  { RISCV_ISA_EXT_ZCD,         "(zcd) " },
+  { RISCV_ISA_EXT_ZCD,         "(Zcd) Compressed Double-Precision FP Instructions" },
-  { RISCV_ISA_EXT_ZCF,         "(zcf) " },
+  { RISCV_ISA_EXT_ZCF,         "(Zcf) Compressed Single-Precision FP Instructions" },
-  { RISCV_ISA_EXT_ZCMOP,       "(zcmop) " },
+  { RISCV_ISA_EXT_ZCMOP,       "(Zcmop) Compressed Multiply-Only Instructions" },
-  { RISCV_ISA_EXT_ZAWRS,       "(zawrs) " },
+  { RISCV_ISA_EXT_ZAWRS,       "(Zawrs) Wait-on-Reservation-Set Instruction" },
-  { RISCV_ISA_EXT_SVVPTC,      "(svvptc) " },
+  { RISCV_ISA_EXT_SVVPTC,      "(Svvptc) Supervisor Virtual Page Table Cache Control" },
-  { RISCV_ISA_EXT_SMMPM,       "(smmpm) " },
+  { RISCV_ISA_EXT_SMMPM,       "(Smmpm) Supervisor Memory Protection Modification" },
-  { RISCV_ISA_EXT_SMNPM,       "(smnpm) " },
+  { RISCV_ISA_EXT_SMNPM,       "(Smnpm) Supervisor Non-Privileged Memory Access Control" },
-  { RISCV_ISA_EXT_SSNPM,       "(ssnpm) " },
+  { RISCV_ISA_EXT_SSNPM,       "(Ssnpm) Supervisor Secure Non-Privileged Memory" },
-  { RISCV_ISA_EXT_ZABHA,       "(zabha) " },
+  { RISCV_ISA_EXT_ZABHA,       "(Zabha) Atomic Byte/Halfword Operations" },
-  { RISCV_ISA_EXT_ZICCRSE,     "(ziccrse) " },
+  { RISCV_ISA_EXT_ZICCRSE,     "(Ziccrse) Cache Control Range Start/End Operations" },
-  { RISCV_ISA_EXT_SVADE,       "(svade) " },
+  { RISCV_ISA_EXT_SVADE,       "(Svade) Supervisor Virtual Address Deferred Exception" },
-  { RISCV_ISA_EXT_SVADU,       "(svadu) " },
+  { RISCV_ISA_EXT_SVADU,       "(Svadu) Supervisor Virtual Address Dirty Update" },
-  { RISCV_ISA_EXT_ZFBFMIN,     "(zfbfmin) " },
+  { RISCV_ISA_EXT_ZFBFMIN,     "(Zfbfmin) Minimal BFloat16 Floating Point" },
-  { RISCV_ISA_EXT_ZVFBFMIN,    "(zvfbfmin) " },
+  { RISCV_ISA_EXT_ZVFBFMIN,    "(Zvfbfmin) Vector Minimal BFloat16 Floating Point" },
-  { RISCV_ISA_EXT_ZVFBFWMA,    "(zvfbfwma) " },
+  { RISCV_ISA_EXT_ZVFBFWMA,    "(Zvfbfwma) Vector BFloat16 Widening Multiply-Accumulate" },
-  { RISCV_ISA_EXT_ZAAMO,       "(zaamo) " },
+  { RISCV_ISA_EXT_ZAAMO,       "(Zaamo) Atomic Memory Operation (AMO) Instructions" },
-  { RISCV_ISA_EXT_ZALRSC,      "(zalrsc) " },
+  { RISCV_ISA_EXT_ZALRSC,      "(Zalrsc) Atomic Load-Reserved/Store-Conditional" },
-  { RISCV_ISA_EXT_ZICBOP,      "(zicbop) " },
+  { RISCV_ISA_EXT_ZICBOP,      "(Zicbop) Cache Block Prefetch/Zero Operations" },
-  { RISCV_ISA_EXT_IME,         "(ime) Integrated Matrix Extension" },
+  { RISCV_ISA_EXT_IME,         "(Ime) Integrated Matrix Extension" },
 };
 
 struct cpuInfo* get_cpu_info(void);
 char* get_str_topology(struct cpuInfo* cpu, struct topology* topo);
 char* get_str_extensions(struct cpuInfo* cpu);
+uint32_t get_num_extensions(bool* mask);
 void print_debug(struct cpuInfo* cpu);
 
 #endif