[v1.04][X86] Fix incorrect free in AMD CPUs

[v1.04] Clarify how the unknown microarchitectures should be reported
[v1.04][X86] Add AMD uarchs
2026-03-25 16:00:39 +01:00 · 2023-12-22 22:53:42 +00:00 · 2023-12-03 20:23:15 +00:00 · 2023-12-02 18:18:43 +00:00 · 2023-11-18 20:25:57 +01:00 · 2023-11-11 09:36:12 +00:00
15 changed files with 352 additions and 87 deletions
--- a/README.md
+++ b/README.md
@@ -50,6 +50,8 @@ cpufetch is a command-line tool written in C that displays the CPU information i
  - [4.2 Specifying the colors in RGB format](#42-specifying-the-colors-in-rgb-format)
 - [5. Implementation](#5-implementation)
 - [6. Bugs or improvements](#6-bugs-or-improvements)
+  - [6.1 Unknown microarchitecture error](#61-unknown-microarchitecture-error)
+  - [6.2 Other situations](#62-other-situations)
 - [7. Acknowledgements](#7-acknowledgements)
 - [8. cpufetch for GPUs (gpufetch)](#8-cpufetch-for-gpus-gpufetch)

@@ -147,6 +149,21 @@ By default, `cpufetch` will print the CPU logo with the system colorscheme. Howe
 See [cpufetch programming documentation](https://github.com/Dr-Noob/cpufetch/tree/master/doc).

 ## 6. Bugs or improvements
+### 6.1 Unknown microarchitecture error
+If you get the `Unknown microarchitecture detected` error when running cpufetch, it might be caused by two possible reasons:
+
+1. You are running an old release of cpufetch (most likely)
+2. Your microarchitecture is not yet supported
+
+Download and compile the latest version (see https://github.com/Dr-Noob/cpufetch#22-building-from-source for instructions)
+and verify if the error persists.
+
+* __If the error dissapears__: It means that this is the first situation. In this case, just use the
+latest version of cpufetch which already has support for your hardware.
+* __If the error does not dissapear__: It means that this is the
+second situation. In this case, please create a new issue with the error message and the output of 'cpufetch --debug' on https://github.com/Dr-Noob/cpufetch/issues
+
+### 6.2 Other situations
 See [cpufetch contributing guidelines](https://github.com/Dr-Noob/cpufetch/blob/master/CONTRIBUTING.md).

 ## 7. Acknowledgements
--- a/src/arm/soc.c
+++ b/src/arm/soc.c
@@ -12,6 +12,7 @@
  #include "sysctl.h"
 #endif

+#define NA -1
 #define min(a,b) (((a)<(b))?(a):(b))
 #define ARRAY_SIZE(arr)     (sizeof(arr) / sizeof((arr)[0]))

@@ -126,6 +127,22 @@ bool match_broadcom(char* soc_name, struct system_on_chip* soc) {
  SOC_END
 }

+// https://en.wikipedia.org/wiki/Google_Tensor
+bool match_google(char* soc_name, struct system_on_chip* soc) {
+  char* tmp;
+
+  if((tmp = strstr(soc_name, "gs")) == NULL)
+    return false;
+
+  soc->soc_vendor = SOC_VENDOR_GOOGLE;
+
+  SOC_START
+  SOC_EQ(tmp, "gs101", "Tensor",    SOC_GOOGLE_TENSOR,    soc, 5)
+  SOC_EQ(tmp, "gs201", "Tensor G2", SOC_GOOGLE_TENSOR_G2, soc, 5)
+  SOC_EQ(tmp, "gs301", "Tensor G3", SOC_GOOGLE_TENSOR_G3, soc, 4)
+  SOC_END
+}
+
 // https://www.techinsights.com/
 // https://datasheetspdf.com/pdf-file/1316605/HiSilicon/Hi3660/1
 bool match_hisilicon(char* soc_name, struct system_on_chip* soc) {
@@ -224,6 +241,10 @@ bool match_exynos(char* soc_name, struct system_on_chip* soc) {
  SOC_END
 }

+// https://www.phonemore.com/processors/mediatek/
+// https://phonedb.net/
+// https://en.wikipedia.org/wiki/List_of_MediaTek_systems_on_chips
+// https://wikimovel.com/index.php/MediaTek
 bool match_mediatek(char* soc_name, struct system_on_chip* soc) {
  char* tmp;
  char* soc_name_upper = toupperstr(soc_name);
@@ -235,25 +256,38 @@ bool match_mediatek(char* soc_name, struct system_on_chip* soc) {

  SOC_START
  // Dimensity //
+  SOC_EQ(tmp, "MT6893Z",  "Dimensity 1300",  SOC_MTK_MT6893Z,  soc, 6)
  SOC_EQ(tmp, "MT6893",   "Dimensity 1200",  SOC_MTK_MT6893,   soc, 6)
  SOC_EQ(tmp, "MT6891",   "Dimensity 1100",  SOC_MTK_MT6891,   soc, 6)
+  //SOC_EQ(tmp, "MT6877V",  "Dimensity 1080",  SOC_MTK_MT6877V   soc, 7) // There is a clash between this and another chip
+  SOC_EQ(tmp, "MT6879",   "Dimensity 1050",  SOC_MTK_MT6879,   soc, 6)
  SOC_EQ(tmp, "MT6889",   "Dimensity 1000",  SOC_MTK_MT6889,   soc, 7)
  SOC_EQ(tmp, "MT6885Z",  "Dimensity 1000L", SOC_MTK_MT6885Z,  soc, 7)
-  //SOC_EQ(tmp, "?",      "Dimensity 700",   SOC_MTK_,         soc, 7)
+  SOC_EQ(tmp, "MT6889Z",  "Dimensity 1000+", SOC_MTK_MT6889Z,  soc, 7)
+  SOC_EQ(tmp, "MT6883Z",  "Dimensity 1000C", SOC_MTK_MT6883Z,  soc, 7)
+  SOC_EQ(tmp, "MT6833",   "Dimensity 700",   SOC_MTK_MT6833,   soc, 7)
  SOC_EQ(tmp, "MT6853",   "Dimensity 720",   SOC_MTK_MT6853,   soc, 7)
  SOC_EQ(tmp, "MT6873",   "Dimensity 800",   SOC_MTK_MT6873,   soc, 7)
+  SOC_EQ(tmp, "MT6853V",  "Dimensity 800U",  SOC_MTK_MT6853V,  soc, 7)
+  SOC_EQ(tmp, "MT6833",   "Dimensity 810",   SOC_MTK_MT6833,   soc, 6)
  SOC_EQ(tmp, "MT6875",   "Dimensity 820",   SOC_MTK_MT6875,   soc, 7)
  // Helio //
  SOC_EQ(tmp, "MT6761D",  "Helio A20",       SOC_MTK_MT6761D,  soc, 12)
  SOC_EQ(tmp, "MT6761",   "Helio A22",       SOC_MTK_MT6761,   soc, 12)
  SOC_EQ(tmp, "MT6762D",  "Helio A25",       SOC_MTK_MT6762D,  soc, 12)
-  //SOC_EQ(tmp, "?",      "Helio G25",       SOC_MTK_,         soc, 12)
-  //SOC_EQ(tmp, "?",      "Helio G35",       SOC_MTK_,         soc, 12)
-  //SOC_EQ(tmp, "?",      "Helio G70",       SOC_MTK_,         soc, 12)
-  //SOC_EQ(tmp, "?",      "Helio G80",       SOC_MTK_,         soc, 12)
-  //SOC_EQ(tmp, "?",      "Helio G90",       SOC_MTK_,         soc, 12)
-  //SOC_EQ(tmp, "?",      "Helio G90T",      SOC_MTK_,         soc, 12)
-  //SOC_EQ(tmp, "?",      "Helio G95",       SOC_MTK_,         soc, 12)
+  SOC_EQ(tmp, "MT6762G",  "Helio G25",       SOC_MTK_MT6762G,  soc, 12)
+  SOC_EQ(tmp, "MT6765G",  "Helio G35",       SOC_MTK_MT6765G,  soc, 12)
+  //SOC_EQ(tmp, "???",    "Helio G36",       SOC_MTK_MT6765G,  soc,  ?)
+  SOC_EQ(tmp, "MT6765H",  "Helio G37",       SOC_MTK_MT6765H,  soc, 12)
+  SOC_EQ(tmp, "MT6769V",  "Helio G70",       SOC_MTK_MT6769V,  soc, 12)
+  SOC_EQ(tmp, "MT6769T",  "Helio G80",       SOC_MTK_MT6769T,  soc, 12)
+  SOC_EQ(tmp, "MT6769Z",  "Helio G85",       SOC_MTK_MT6769Z,  soc, 12)
+  SOC_EQ(tmp, "MT6769H",  "Helio G88",       SOC_MTK_MT6769H,  soc, 12)
+  //SOC_EQ(tmp, "MT6785V/CD", "Helio G90",   SOC_MTK_MT6785V_CD, soc, 12) // How to distingish between this and G95?
+  SOC_EQ(tmp, "MT6785V/CC", "Helio G90T",    SOC_MTK_MT6785V_CC, soc, 12)
+  SOC_EQ(tmp, "MT6785V/CD", "Helio G95",     SOC_MTK_MT6785V_CD, soc, 12)
+  SOC_EQ(tmp, "MT6789",   "Helio G99",       SOC_MTK_MT6789,   soc,  6)
+  SOC_EQ(tmp, "MT8781V",  "Helio G99",       SOC_MTK_MT8781V,  soc,  6) // Same as MT6789
  SOC_EQ(tmp, "MT6755",   "Helio P10",       SOC_MTK_MT6755M,  soc, 28)
  SOC_EQ(tmp, "MT6755M",  "Helio P10 M",     SOC_MTK_MT6755M,  soc, 28)
  SOC_EQ(tmp, "MT6755T",  "Helio P15",       SOC_MTK_MT6755T,  soc, 28)
@@ -268,8 +302,8 @@ bool match_mediatek(char* soc_name, struct system_on_chip* soc) {
  SOC_EQ(tmp, "MT6768",   "Helio P65",       SOC_MTK_MT6768,   soc, 12)
  SOC_EQ(tmp, "MT6771T",  "Helio P70",       SOC_MTK_MT6771,   soc, 12)
  SOC_EQ(tmp, "MT6771V",  "Helio P70",       SOC_MTK_MT6771,   soc, 12)
-  SOC_EQ(tmp, "MT6779",   "Helio P90",       SOC_MTK_MT6779,   soc, 12)
-  //SOC_EQ(tmp, "?",      "Helio P95",       SOC_MTK_,         soc, 12)
+  SOC_EQ(tmp, "MT6779V/CU", "Helio P90",     SOC_MTK_MT6779V_CU, soc, 12)
+  SOC_EQ(tmp, "MT6779V/CV", "Helio P95",     SOC_MTK_MT6779V_CV, soc, 12)
  SOC_EQ(tmp, "MT6795",   "Helio X10",       SOC_MTK_MT6795,   soc, 28)
  SOC_EQ(tmp, "MT6795T",  "Helio X10 T",     SOC_MTK_MT6795,   soc, 28)
  SOC_EQ(tmp, "MT6797",   "Helio X20",       SOC_MTK_MT6797,   soc, 20)
@@ -278,7 +312,31 @@ bool match_mediatek(char* soc_name, struct system_on_chip* soc) {
  SOC_EQ(tmp, "MT6797T",  "Helio X25",       SOC_MTK_MT6797T,  soc, 20)
  SOC_EQ(tmp, "MT6797X",  "Helio X27",       SOC_MTK_MT6797X,  soc, 20)
  SOC_EQ(tmp, "MT6799",   "Helio X30",       SOC_MTK_MT6799,   soc, 10)
+  // Pentonic
+  SOC_EQ(tmp, "MT9618",   "Pentonic  700",   SOC_MTK_MT9618,   soc,  7)
+  SOC_EQ(tmp, "MT9653",   "Pentonic  700",   SOC_MTK_MT9653,   soc,  7)
+  SOC_EQ(tmp, "MT9689",   "Pentonic  700",   SOC_MTK_MT9689,   soc,  7) // !! Assumption only, needs confirmation
+  SOC_EQ(tmp, "MT9972",   "Pentonic 1000",   SOC_MTK_MT9972,   soc,  7) // !! Assumption only, needs confirmation
+  SOC_EQ(tmp, "MT9902",   "Pentonic 2000",   SOC_MTK_MT9902,   soc,  7)
+  SOC_EQ(tmp, "MT9982",   "Pentonic 2000",   SOC_MTK_MT9982,   soc,  7)
  // MT XXXX //
+  SOC_EQ(tmp, "MT5327",   "MT5327",          SOC_MTK_MT5327,   soc, NA)
+  SOC_EQ(tmp, "MT5329",   "MT5329",          SOC_MTK_MT5329,   soc, NA)
+  SOC_EQ(tmp, "MT5366",   "MT5366",          SOC_MTK_MT5366,   soc, NA)
+  SOC_EQ(tmp, "MT5389",   "MT5389",          SOC_MTK_MT5389,   soc, NA)
+  SOC_EQ(tmp, "MT5395",   "MT5395",          SOC_MTK_MT5395,   soc, NA)
+  SOC_EQ(tmp, "MT5396",   "MT5396",          SOC_MTK_MT5396,   soc, NA)
+  SOC_EQ(tmp, "MT5398",   "MT5398",          SOC_MTK_MT5398,   soc, NA)
+  SOC_EQ(tmp, "MT5505",   "MT5505",          SOC_MTK_MT5505,   soc, NA)
+  SOC_EQ(tmp, "MT5561",   "MT5561",          SOC_MTK_MT5561,   soc, NA)
+  SOC_EQ(tmp, "MT5580",   "MT5580",          SOC_MTK_MT5580,   soc, NA)
+  SOC_EQ(tmp, "MT5582",   "MT5582",          SOC_MTK_MT5582,   soc, NA)
+  SOC_EQ(tmp, "MT5592",   "MT5592",          SOC_MTK_MT5592,   soc, NA)
+  SOC_EQ(tmp, "MT5595",   "MT5595",          SOC_MTK_MT5595,   soc, NA)
+  SOC_EQ(tmp, "MT5596",   "MT5596",          SOC_MTK_MT5596,   soc, 28) // !! Assumption only, needs confirmation
+  SOC_EQ(tmp, "MT5597",   "MT5597",          SOC_MTK_MT5597,   soc, 28) // !! Assumption only, needs confirmation
+  SOC_EQ(tmp, "MT5895",   "MT5895",          SOC_MTK_MT5895,   soc, 28) // Same as MT9950*
+  SOC_EQ(tmp, "MT5889",   "MT5889",          SOC_MTK_MT5889,   soc, 28) // Same as MT9615 (https://www.displayspecifications.com/en/model/97272c1f)
  SOC_EQ(tmp, "MT6515",   "MT6515",          SOC_MTK_MT6515,   soc, 40)
  SOC_EQ(tmp, "MT6516",   "MT6516",          SOC_MTK_MT6516,   soc, 65)
  SOC_EQ(tmp, "MT6517",   "MT6517",          SOC_MTK_MT6517,   soc, 40)
@@ -324,6 +382,19 @@ bool match_mediatek(char* soc_name, struct system_on_chip* soc) {
  SOC_EQ(tmp, "MT8735",   "MT8735",          SOC_MTK_MT8735,   soc, 28)
  SOC_EQ(tmp, "MT8765B",  "MT8765B",         SOC_MTK_MT8765B,  soc, 28)
  SOC_EQ(tmp, "MT8783",   "MT8783",          SOC_MTK_MT8783,   soc, 28)
+  SOC_EQ(tmp, "MT9602",   "MT9602",          SOC_MTK_MT9602,   soc, 28) // Same as MT9675*
+  SOC_EQ(tmp, "MT9612",   "MT9612",          SOC_MTK_MT9612,   soc, 28) // Same as MT9685*
+  SOC_EQ(tmp, "MT9613",   "MT9613",          SOC_MTK_MT9613,   soc, 28) // !! Assumption only, needs confirmation
+  SOC_EQ(tmp, "MT9615",   "MT9615",          SOC_MTK_MT9615,   soc, 28) // https://gadgetversus.com/processor/mediatek-mt9615-specs/
+  SOC_EQ(tmp, "MT9632",   "MT9632",          SOC_MTK_MT9632,   soc, 28) // Same as MT9675*
+  SOC_EQ(tmp, "MT9638",   "MT9638",          SOC_MTK_MT9638,   soc, 28) // !! Assumption only, needs confirmation
+  SOC_EQ(tmp, "MT9652",   "MT9652",          SOC_MTK_MT9652,   soc, 28) // Same as MT9613*
+  SOC_EQ(tmp, "MT9675",   "MT9675",          SOC_MTK_MT9675,   soc, 28) // !! Assumption only, needs confirmation
+  SOC_EQ(tmp, "MT9685",   "MT9685",          SOC_MTK_MT9685,   soc, 28) // https://gadgetversus.com/processor/mediatek-mt9685-specs/
+  SOC_EQ(tmp, "MT9950",   "MT9950",          SOC_MTK_MT9950,   soc, 28) // https://gadgetversus.com/processor/mediatek-mt9950-specs/
+  SOC_EQ(tmp, "MT9686",   "MT9686",          SOC_MTK_MT9686,   soc, 28) // Same as MT9613*
+  // (*) Many SoCs are reported with different names but they are the same chip.
+  // Source: https://en.wikipedia.org/wiki/List_of_MediaTek_systems_on_chips#Digital_television_SoCs
  SOC_END
 }

@@ -537,6 +608,21 @@ bool match_special(char* soc_name, struct system_on_chip* soc) {
    return true;
  }

+  // Google Pixel 6
+  // https://github.com/Dr-Noob/cpufetch/issues/134
+  if(strcmp(soc_name, "oriole") == 0) {
+    fill_soc(soc, "Tensor", SOC_GOOGLE_TENSOR, 5);
+    return true;
+  }
+
+  // Google Pixel 8
+  // https://github.com/Dr-Noob/cpufetch/issues/198
+  if(strcmp(soc_name, "husky") == 0 ||
+     strcmp(soc_name, "zuma") == 0) {
+    fill_soc(soc, "Tensor G3", SOC_GOOGLE_TENSOR_G3, 4);
+    return true;
+  }
+
  return false;
 }

@@ -561,6 +647,9 @@ struct system_on_chip* parse_soc_from_string(struct system_on_chip* soc) {
  if(match_allwinner(raw_name, soc))
    return soc;

+  if(match_google(raw_name, soc))
+    return soc;
+
  match_broadcom(raw_name, soc);
  return soc;
 }
--- a/src/arm/socs.h
+++ b/src/arm/socs.h
@@ -64,39 +64,23 @@ enum {
  SOC_EXYNOS_980,
  SOC_EXYNOS_880,
  // Mediatek //
-  SOC_MTK_MT6893,
-  SOC_MTK_MT6891,
-  SOC_MTK_MT6889,
-  SOC_MTK_MT6885Z,
-  SOC_MTK_MT6853,
-  SOC_MTK_MT6873,
-  SOC_MTK_MT6875,
-  SOC_MTK_MT6761D,
-  SOC_MTK_MT6761,
-  SOC_MTK_MT6762D,
-  SOC_MTK_MT6755,
-  SOC_MTK_MT6755M,
-  SOC_MTK_MT6755T,
-  SOC_MTK_MT6757,
-  SOC_MTK_MT6762,
-  SOC_MTK_MT6763V,
-  SOC_MTK_MT6763T,
-  SOC_MTK_MT6757CD,
-  SOC_MTK_MT6758,
-  SOC_MTK_MT6765,
-  SOC_MTK_MT6771,
-  SOC_MTK_MT6768,
-  SOC_MTK_MT6771T,
-  SOC_MTK_MT6771V,
-  SOC_MTK_MT6779,
-  SOC_MTK_MT6795,
-  SOC_MTK_MT6795T,
-  SOC_MTK_MT6797,
-  SOC_MTK_MT6797M,
-  SOC_MTK_MT6797D,
-  SOC_MTK_MT6797T,
-  SOC_MTK_MT6797X,
-  SOC_MTK_MT6799,
+  SOC_MTK_MT5327,
+  SOC_MTK_MT5329,
+  SOC_MTK_MT5366,
+  SOC_MTK_MT5389,
+  SOC_MTK_MT5395,
+  SOC_MTK_MT5396,
+  SOC_MTK_MT5398,
+  SOC_MTK_MT5505,
+  SOC_MTK_MT5561,
+  SOC_MTK_MT5580,
+  SOC_MTK_MT5582,
+  SOC_MTK_MT5592,
+  SOC_MTK_MT5595,
+  SOC_MTK_MT5596,
+  SOC_MTK_MT5597,
+  SOC_MTK_MT5889,
+  SOC_MTK_MT5895,
  SOC_MTK_MT6515,
  SOC_MTK_MT6516,
  SOC_MTK_MT6517,
@@ -126,7 +110,51 @@ enum {
  SOC_MTK_MT6750T,
  SOC_MTK_MT6752,
  SOC_MTK_MT6753,
+  SOC_MTK_MT6755M,
+  SOC_MTK_MT6755T,
+  SOC_MTK_MT6757,
+  SOC_MTK_MT6757CD,
+  SOC_MTK_MT6758,
+  SOC_MTK_MT6761,
+  SOC_MTK_MT6761D,
+  SOC_MTK_MT6762,
+  SOC_MTK_MT6762D,
+  SOC_MTK_MT6762G,
+  SOC_MTK_MT6763T,
+  SOC_MTK_MT6763V,
+  SOC_MTK_MT6765,
+  SOC_MTK_MT6765G,
+  SOC_MTK_MT6765H,
+  SOC_MTK_MT6768,
+  SOC_MTK_MT6769H,
+  SOC_MTK_MT6769T,
+  SOC_MTK_MT6769V,
+  SOC_MTK_MT6769Z,
+  SOC_MTK_MT6771,
+  SOC_MTK_MT6779V_CU,
+  SOC_MTK_MT6779V_CV,
+  SOC_MTK_MT6785V_CC,
+  SOC_MTK_MT6785V_CD,
+  SOC_MTK_MT6789,
+  SOC_MTK_MT6795,
+  SOC_MTK_MT6797,
+  SOC_MTK_MT6797T,
+  SOC_MTK_MT6797X,
+  SOC_MTK_MT6799,
+  SOC_MTK_MT6833,
  SOC_MTK_MT6850,
+  SOC_MTK_MT6853,
+  SOC_MTK_MT6853V,
+  SOC_MTK_MT6873,
+  SOC_MTK_MT6875,
+  SOC_MTK_MT6879,
+  SOC_MTK_MT6883Z,
+  SOC_MTK_MT6885Z,
+  SOC_MTK_MT6889,
+  SOC_MTK_MT6889Z,
+  SOC_MTK_MT6891,
+  SOC_MTK_MT6893,
+  SOC_MTK_MT6893Z,
  SOC_MTK_MT8121,
  SOC_MTK_MT8125,
  SOC_MTK_MT8127,
@@ -141,7 +169,25 @@ enum {
  SOC_MTK_MT8581,
  SOC_MTK_MT8735,
  SOC_MTK_MT8765B,
+  SOC_MTK_MT8781V,
  SOC_MTK_MT8783,
+  SOC_MTK_MT9602,
+  SOC_MTK_MT9612,
+  SOC_MTK_MT9613,
+  SOC_MTK_MT9615,
+  SOC_MTK_MT9618,
+  SOC_MTK_MT9632,
+  SOC_MTK_MT9638,
+  SOC_MTK_MT9652,
+  SOC_MTK_MT9653,
+  SOC_MTK_MT9675,
+  SOC_MTK_MT9685,
+  SOC_MTK_MT9686,
+  SOC_MTK_MT9689,
+  SOC_MTK_MT9902,
+  SOC_MTK_MT9950,
+  SOC_MTK_MT9972,
+  SOC_MTK_MT9982,
  // Snapdragon //
  SOC_SNAPD_QSD8650,
  SOC_SNAPD_QSD8250,
@@ -304,6 +350,10 @@ enum {
  SOC_ROCKCHIP_3568,
  SOC_ROCKCHIP_3588,
  SOC_ROCKCHIP_3588S,
+  // GOOGLE
+  SOC_GOOGLE_TENSOR,
+  SOC_GOOGLE_TENSOR_G2,
+  SOC_GOOGLE_TENSOR_G3,
  // UNKNOWN
  SOC_MODEL_UNKNOWN
 };
@@ -317,6 +367,7 @@ inline static VENDOR get_soc_vendor_from_soc(SOC soc) {
  else if(soc >= SOC_APPLE_M1 && soc <= SOC_APPLE_M2_ULTRA) return SOC_VENDOR_APPLE;
  else if(soc >= SOC_ALLWINNER_A10 && soc <= SOC_ALLWINNER_R328) return SOC_VENDOR_ALLWINNER;
  else if(soc >= SOC_ROCKCHIP_3288 && soc <= SOC_ROCKCHIP_3588S) return SOC_VENDOR_ROCKCHIP;
+  else if(soc >= SOC_GOOGLE_TENSOR && soc <= SOC_GOOGLE_TENSOR_G3) return SOC_VENDOR_GOOGLE;
  return SOC_VENDOR_UNKNOWN;
 }

--- a/src/arm/uarch.c
+++ b/src/arm/uarch.c
@@ -68,8 +68,10 @@ enum {
  UARCH_CORTEX_A78,
  UARCH_CORTEX_A510,
  UARCH_CORTEX_A710,
+  UARCH_CORTEX_A715,
  UARCH_CORTEX_X1,
  UARCH_CORTEX_X2,
+  UARCH_CORTEX_X3,
  UARCH_NEOVERSE_N1,
  UARCH_NEOVERSE_E1,
  UARCH_NEOVERSE_V1,
@@ -143,8 +145,10 @@ static const ISA isas_uarch[] = {
  [UARCH_CORTEX_A78]   = ISA_ARMv8_2_A,
  [UARCH_CORTEX_A510]   = ISA_ARMv9_A,
  [UARCH_CORTEX_A710]   = ISA_ARMv9_A,
+  [UARCH_CORTEX_A715]  = ISA_ARMv9_A,
  [UARCH_CORTEX_X1]    = ISA_ARMv8_2_A,
  [UARCH_CORTEX_X2]    = ISA_ARMv9_A,
+  [UARCH_CORTEX_X3]    = ISA_ARMv9_A,
  [UARCH_NEOVERSE_N1]  = ISA_ARMv8_2_A,
  [UARCH_NEOVERSE_E1]  = ISA_ARMv8_2_A,
  [UARCH_NEOVERSE_V1]  = ISA_ARMv8_4_A,
@@ -194,7 +198,9 @@ static char* isas_string[] = {
 #define UARCH_START if (false) {}
 #define CHECK_UARCH(arch, cpu, im_, p_, v_, r_, str, uarch, vendor) \
   else if (im_ == im && p_ == p && (v_ == NA || v_ == v) && (r_ == NA || r_ == r)) fill_uarch(arch, cpu, str, uarch, vendor);
-#define UARCH_END else { printBug("Unknown microarchitecture detected: IM=0x%.8X P=0x%.8X V=0x%.8X R=0x%.8X", im, p, v, r); fill_uarch(arch, cpu, "Unknown", UARCH_UNKNOWN, CPU_VENDOR_UNKNOWN); }
+#define UARCH_END else { printErr("Unknown microarchitecture detected: IM=0x%X P=0x%X V=0x%X R=0x%X", im, p, v, r); \
+fprintf(stderr, "Please see https://github.com/Dr-Noob/cpufetch#61-unknown-microarchitecture-error to know how to report this error\n"); \
+fill_uarch(arch, cpu, "Unknown", UARCH_UNKNOWN, CPU_VENDOR_UNKNOWN); }

 void fill_uarch(struct uarch* arch, struct cpuInfo* cpu, char* str, MICROARCH u, VENDOR vendor) {
  arch->uarch = u;
@@ -210,7 +216,7 @@ void fill_uarch(struct uarch* arch, struct cpuInfo* cpu, char* str, MICROARCH u,

 /*
 * Codes are based on pytorch/cpuinfo, more precisely:
- * - https://github.com/pytorch/cpuinfo/blob/master/src/arm/uarch.c
+ * - https://github.com/pytorch/cpuinfo/blob/main/src/arm/uarch.c
 * Other sources:
 * - https://elixir.bootlin.com/linux/latest/source/arch/arm64/include/asm/cputype.h
 * - https://elixir.bootlin.com/linux/latest/source/arch/arm/include/asm/cputype.h
@@ -263,6 +269,8 @@ struct uarch* get_uarch_from_midr(uint32_t midr, struct cpuInfo* cpu) {
  CHECK_UARCH(arch, cpu, 'A', 0xD47, NA, NA, "Cortex‑A710",           UARCH_CORTEX_A710,  CPU_VENDOR_ARM)
  CHECK_UARCH(arch, cpu, 'A', 0xD48, NA, NA, "Cortex-X2",             UARCH_CORTEX_X2,    CPU_VENDOR_ARM)
  CHECK_UARCH(arch, cpu, 'A', 0xD4A, NA, NA, "Neoverse E1",           UARCH_NEOVERSE_E1,  CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xD4D, NA, NA, "Cortex-A715",           UARCH_CORTEX_A715,  CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xD4E, NA, NA, "Cortex-X3",             UARCH_CORTEX_X3,    CPU_VENDOR_ARM)

  CHECK_UARCH(arch, cpu, 'B', 0x00F, NA, NA, "Brahma B15",            UARCH_BRAHMA_B15,   CPU_VENDOR_BROADCOM)
  CHECK_UARCH(arch, cpu, 'B', 0x100, NA, NA, "Brahma B53",            UARCH_BRAHMA_B53,   CPU_VENDOR_BROADCOM)
@@ -383,6 +391,7 @@ int get_number_of_vpus(struct cpuInfo* cpu) {
    case UARCH_AVALANCHE:   // [https://en.wikipedia.org/wiki/Comparison_of_ARM_processors]
    case UARCH_CORTEX_X1:   // [https://www.anandtech.com/show/15813/arm-cortex-a78-cortex-x1-cpu-ip-diverging/3]
    case UARCH_CORTEX_X2:   // [https://www.anandtech.com/show/16693/arm-announces-mobile-armv9-cpu-microarchitectures-cortexx2-cortexa710-cortexa510/2]
+    case UARCH_CORTEX_X3:   // [https://www.hwcooling.net/en/cortex-x3-the-new-fastest-arm-core-architecture-analysis: "The FPU and SIMD unit of the core still has four pipelines"]
    case UARCH_NEOVERSE_V1: // [https://en.wikichip.org/wiki/arm_holdings/microarchitectures/neoverse_v1]
      return 4;
    case UARCH_EXYNOS_M3:   // [https://www.anandtech.com/show/12361/samsung-exynos-m3-architecture]
@@ -401,13 +410,13 @@ int get_number_of_vpus(struct cpuInfo* cpu) {
    case UARCH_EXYNOS_M1:   // [https://www.anandtech.com/show/12361/samsung-exynos-m3-architecture]
    case UARCH_EXYNOS_M2:   // [https://www.anandtech.com/show/12361/samsung-exynos-m3-architecture]
    case UARCH_NEOVERSE_N1: // [https://en.wikichip.org/wiki/arm_holdings/microarchitectures/neoverse_n1#Individual_Core]
+    case UARCH_CORTEX_A710: // [https://chipsandcheese.com/2023/08/11/arms-cortex-a710-winning-by-default/]: Fig in Core Overview. Table in Instruction Scheduling and Execution
+    case UARCH_CORTEX_A715: // [https://www.hwcooling.net/en/arm-introduces-new-cortex-a715-core-architecture-analysis/]: "the numbers of ALU and FPU execution units themselves >
      return 2;
    case UARCH_NEOVERSE_E1: // [https://www.anandtech.com/show/13959/arm-announces-neoverse-n1-platform/5]
    // A510 is integrated as part of a Complex. Normally, each complex would incorporate two Cortex-A510 cores.
    // Each complex incorporates a single VPU with 2 ports, so for each A510 there is theoretically 1 port.
    case UARCH_CORTEX_A510: // [https://en.wikichip.org/wiki/arm_holdings/microarchitectures/cortex-a510#Vector_Processing_Unit_.28VPU.29]
-    // Not sure about this one since there is no explicit information saying it has one, but they never state it has more either.
-    case UARCH_CORTEX_A710: // [Arm Cortex‑A710 Core Technical Reference Manual]
      return 1;
    default:
      // ARMv6
--- a/src/common/ascii.h
+++ b/src/common/ascii.h
@@ -33,7 +33,7 @@ struct ascii_logo {
  uint32_t width;
  uint32_t height;
  bool replace_blocks;
-  char color_ascii[3][100];
+  char color_ascii[4][100];
  char color_text[2][100];
 };

@@ -218,6 +218,23 @@ $C1    kMMMMMMMMMMMMMMMMMMMMMMd    \
 $C1     'KMMMMMMMWXXWMMMMMMMk.     \
 $C1       \"cooc\"*    \"*coo'\"       "

+#define ASCII_GOOGLE \
+"$C1            aaaaaaaa               \
+$C1        .MMMMMMMMMMMMMMMM.         \
+$C1     .MMMMMMMMMMMMMMMMMMMMM*       \
+$C1   .MMMMMMMM**        *MM*         \
+$C2  MM$C1MMMMM.                         \
+$C2 *MMM$C1MM.                           \
+$C2*MMMMMM          $C4lMMMMMMMMMMMMMMM* \
+$C2MMMMMMM          $C4lMMMMMMMMMMMMMMMM \
+$C2*MMMMMM          $C4lMMMMMMMMMMMMMMMd \
+$C2 MMMM$C3MMM.                  $C4*MMMMM. \
+$C2  MM$C3MMMMMM.              $C4.MMMMMM.  \
+$C3   *MMMMMMMMM*.......MMM$C4MMMMMM*    \
+$C3     *MMMMMMMMMMMMMMMMMMMM$C4MM*      \
+$C3         *MMMMMMMMMMMMMM*          \
+$C3              ******               "
+
 #define ASCII_ALLWINNER \
 "$C1                                               \
 $C1                #################              \
@@ -306,6 +323,24 @@ $C1    ########   ########          \
 $C1         #########               \
 $C1             #                   "

+#define ASCII_SIPEED \
+"$C1  ####################################   \
+$C1######@@################################ \
+$C1####@@##@@####@@@@@@@@@@@@@@@@########## \
+$C1######@@####@@@@@@@@@@@@@@@@@@########## \
+$C1#########@@@@########################### \
+$C1#######@@@@@@########################### \
+$C1#########@@@@########################### \
+$C1###########@@@@@@@@@@@@@@@############## \
+$C1##############@@@@@@@@@@@@@@@########### \
+$C1###########################@@@@@######## \
+$C1###########################@@@@@@####### \
+$C1###########################@@@@@######## \
+$C1##########@@@@@@@@@@@@@@@@@@@########### \
+$C1##########@@@@@@@@@@@@@@@@############## \
+$C1######################################## \
+$C1  ####################################   "
+
 // --------------------- LONG LOGOS ------------------------- //
 #define ASCII_AMD_L \
 "$C1                                                              \
@@ -440,9 +475,9 @@ $C1                 #######                          "

 typedef struct ascii_logo asciiL;

-//                        +-----------------------------------------------------------------------------------------------------+
+//                        +-----------------------------------------------------------------------------------------------------------------+
 //                        | LOGO             | W | H | REPLACE | COLORS LOGO (>0 && <10)                      | COLORS TEXT (=2)            |
-//                        +-----------------------------------------------------------------------------------------------------+
+//                        +-----------------------------------------------------------------------------------------------------------------+
 asciiL logo_amd         = { ASCII_AMD,         39, 15, false, {C_FG_WHITE, C_FG_GREEN},                       {C_FG_WHITE,   C_FG_GREEN}   };
 asciiL logo_intel       = { ASCII_INTEL,       48, 14, false, {C_FG_CYAN},                                    {C_FG_CYAN,    C_FG_WHITE}   };
 asciiL logo_intel_new   = { ASCII_INTEL_NEW,   51,  9, false, {C_FG_CYAN},                                    {C_FG_CYAN,    C_FG_WHITE}   };
@@ -454,13 +489,15 @@ asciiL logo_broadcom    = { ASCII_BROADCOM,    44, 19, false, {C_FG_WHITE, C_FG_
 asciiL logo_arm         = { ASCII_ARM,         42,  5, false, {C_FG_CYAN},                                    {C_FG_WHITE,   C_FG_CYAN}    };
 asciiL logo_ibm         = { ASCII_IBM,         42,  9, false, {C_FG_CYAN, C_FG_WHITE},                        {C_FG_CYAN,    C_FG_WHITE}   };
 asciiL logo_apple       = { ASCII_APPLE,       32, 17, false, {C_FG_WHITE},                                   {C_FG_CYAN,    C_FG_B_WHITE} };
+asciiL logo_google      = { ASCII_GOOGLE,      35, 15, false, {C_FG_RED, C_FG_YELLOW, C_FG_GREEN, C_FG_BLUE}, {C_FG_BLUE,    C_FG_B_WHITE} };
 asciiL logo_allwinner   = { ASCII_ALLWINNER,   47, 16, false, {C_FG_CYAN},                                    {C_FG_B_BLACK, C_FG_B_CYAN } };
 asciiL logo_rockchip    = { ASCII_ROCKCHIP,    58,  8, false, {C_FG_CYAN, C_FG_YELLOW},                       {C_FG_CYAN,    C_FG_YELLOW}  };
 asciiL logo_riscv       = { ASCII_RISCV,       63, 18, false, {C_FG_CYAN, C_FG_YELLOW},                       {C_FG_CYAN,    C_FG_YELLOW}  };
 asciiL logo_sifive      = { ASCII_SIFIVE,      48, 19, true,  {C_BG_WHITE, C_BG_BLACK},                       {C_FG_WHITE,   C_FG_BLUE}    };
 asciiL logo_starfive    = { ASCII_STARFIVE,    33, 17, false, {C_FG_WHITE},                                   {C_FG_WHITE,   C_FG_BLUE}    };
+asciiL logo_sipeed      = { ASCII_SIPEED,      41, 16, true,  {C_BG_RED, C_BG_WHITE},                         {C_FG_RED,     C_FG_WHITE}   };

-// Long variants          | ----------------------------------------------------------------------------------------------------|
+// Long variants          | ----------------------------------------------------------------------------------------------------------------|
 asciiL logo_amd_l       = { ASCII_AMD_L,       62, 19, true,  {C_BG_WHITE, C_BG_GREEN},                       {C_FG_WHITE, C_FG_GREEN}     };
 asciiL logo_intel_l     = { ASCII_INTEL_L,     62, 19, true,  {C_BG_CYAN, C_BG_WHITE},                        {C_FG_CYAN,  C_FG_WHITE}     };
 asciiL logo_intel_l_new = { ASCII_INTEL_L_NEW, 57, 14, true,  {C_BG_CYAN, C_BG_WHITE, C_BG_BLUE},             {C_FG_CYAN,  C_FG_WHITE}     };
--- a/src/common/cpu.c
+++ b/src/common/cpu.c
@@ -194,7 +194,7 @@ void init_topology_struct(struct topology* topo, struct cache* cach) {
  topo->sockets = 0;
 #ifdef ARCH_X86
  topo->smt_available = 0;
-  topo->apic = emalloc(sizeof(struct apic));
+  topo->apic = ecalloc(1, sizeof(struct apic));
 #endif
 #endif
 }
--- a/src/common/printer.c
+++ b/src/common/printer.c
@@ -368,6 +368,8 @@ void choose_ascii_art(struct ascii* art, struct color** cs, struct terminal* ter
    art->art = &logo_broadcom;
  else if(art->vendor == SOC_VENDOR_APPLE)
    art->art = &logo_apple;
+  else if(art->vendor == SOC_VENDOR_GOOGLE)
+    art->art = &logo_google;
  else if(art->vendor == SOC_VENDOR_ALLWINNER)
    art->art = &logo_allwinner;
  else if(art->vendor == SOC_VENDOR_ROCKCHIP)
@@ -382,6 +384,8 @@ void choose_ascii_art(struct ascii* art, struct color** cs, struct terminal* ter
    art->art = choose_ascii_art_aux(&logo_starfive_l, &logo_starfive, term, lf);
  else if(art->vendor == SOC_VENDOR_ALLWINNER)
    art->art = &logo_allwinner;
+  else if(art->vendor == SOC_VENDOR_SIPEED)
+    art->art = &logo_sipeed;
  else
    art->art = &logo_riscv;
 #endif
--- a/src/common/soc.c
+++ b/src/common/soc.c
@@ -18,9 +18,11 @@ static char* soc_trademark_string[] = {
  [SOC_VENDOR_BROADCOM]   = "Broadcom BCM",
  [SOC_VENDOR_APPLE]      = "Apple ",
  [SOC_VENDOR_ROCKCHIP]   = "Rockchip ",
+  [SOC_VENDOR_GOOGLE]     = "Google ",
  // RISC-V
  [SOC_VENDOR_SIFIVE]     = "SiFive ",
  [SOC_VENDOR_STARFIVE]   = "StarFive ",
+  [SOC_VENDOR_SIPEED]     = "Sipeed ",
  // ARM & RISC-V
  [SOC_VENDOR_ALLWINNER]  = "Allwinner "
 };
--- a/src/common/soc.h
+++ b/src/common/soc.h
@@ -22,9 +22,11 @@ enum {
  SOC_VENDOR_BROADCOM,
  SOC_VENDOR_APPLE,
  SOC_VENDOR_ROCKCHIP,
+  SOC_VENDOR_GOOGLE,
  // RISC-V
  SOC_VENDOR_SIFIVE,
  SOC_VENDOR_STARFIVE,
+  SOC_VENDOR_SIPEED,
  // ARM & RISC-V
  SOC_VENDOR_ALLWINNER
 };
--- a/src/riscv/riscv.c
+++ b/src/riscv/riscv.c
@@ -78,6 +78,18 @@ int parse_multi_letter_extension(struct extensions* ext, char* e) {
  return multi_letter_extension_len;
 }

+bool valid_extension(char ext) {
+  bool found = false;
+  uint64_t idx = 0;
+
+  while(idx < sizeof(extension_list)/sizeof(extension_list[0]) && !found) {
+    found = (extension_list[idx].id == (ext - 'a'));
+    if(!found) idx++;
+  }
+
+  return found;
+}
+
 struct extensions* get_extensions_from_str(char* str) {
  struct extensions* ext = emalloc(sizeof(struct extensions));
  ext->mask = 0;
@@ -114,9 +126,23 @@ struct extensions* get_extensions_from_str(char* str) {
      e += multi_letter_extension_len;
    }
    else {
+      // Single-letter extensions 's' and 'u' are invalid
+      // according to Linux kernel (arch/riscv/kernel/cpufeature.c:
+      // riscv_fill_hwcap). Optionally, we could opt for using
+      // hwcap instead of cpuinfo to avoid this
+      if (*e == 's' || *e == 'u') {
+        continue;
+      }
+      // Make sure that the extension is valid before
+      // adding it to the mask
+      if(valid_extension(*e)) {
        int n = *e - 'a';
        ext->mask |= 1UL << n;
      }
+      else {
+        printBug("get_extensions_from_str: Invalid extension: '%c'", *e);
+      }
+    }
  }

  return ext;
--- a/src/riscv/riscv.h
+++ b/src/riscv/riscv.h
@@ -54,7 +54,6 @@ static const struct extension extension_list[] = {
  { 'v' - 'a', "(V) Vector Operations" },
  { 'n' - 'a', "(N) User-Level Interrupts" },
  { 'h' - 'a', "(H) Hypervisor" },
-  { 's' - 'a', "(S) Supervisor-level Instructions" },
  // multi-letter extensions
  { RISCV_ISA_EXT_SSCOFPMF,    "(Sscofpmf) Count OverFlow and Privilege Mode Filtering" },
  { RISCV_ISA_EXT_SSTC,        "(Sstc) S and VS level Time Compare" },
--- a/src/riscv/soc.c
+++ b/src/riscv/soc.c
@@ -32,6 +32,12 @@ bool match_allwinner(char* soc_name, struct system_on_chip* soc) {
  SOC_END
 }

+bool match_sipeed(char* soc_name, struct system_on_chip* soc) {
+  SOC_START
+  SOC_EQ(soc_name, "light", "Lichee Pi 4A", SOC_SIPEED_LICHEEPI4A, soc, 12) // https://github.com/Dr-Noob/cpufetch/issues/200, https://sipeed.com/licheepi4a
+  SOC_END
+}
+
 struct system_on_chip* parse_soc_from_string(struct system_on_chip* soc) {
  char* raw_name = soc->raw_name;

@@ -41,7 +47,10 @@ struct system_on_chip* parse_soc_from_string(struct system_on_chip* soc) {
  if(match_allwinner(raw_name, soc))
    return soc;

-  match_sifive(raw_name, soc);
+  if(match_sifive(raw_name, soc))
+    return soc;
+
+  match_sipeed(raw_name, soc);
  return soc;
 }

--- a/src/riscv/socs.h
+++ b/src/riscv/socs.h
@@ -11,6 +11,8 @@ enum {
  SOC_STARFIVE_VF2,
  // ALLWINNER
  SOC_ALLWINNER_D1H,
+  // SIPEED
+  SOC_SIPEED_LICHEEPI4A,
  // UNKNOWN
  SOC_MODEL_UNKNOWN
 };
@@ -19,6 +21,7 @@ inline static VENDOR get_soc_vendor_from_soc(SOC soc) {
  if(soc >= SOC_SIFIVE_U740 && soc <= SOC_SIFIVE_U740) return SOC_VENDOR_SIFIVE;
  if(soc >= SOC_STARFIVE_VF2 && soc <= SOC_STARFIVE_VF2) return SOC_VENDOR_STARFIVE;
  if(soc >= SOC_ALLWINNER_D1H && soc <= SOC_ALLWINNER_D1H) return SOC_VENDOR_ALLWINNER;
+  if(soc >= SOC_SIPEED_LICHEEPI4A && soc <= SOC_SIPEED_LICHEEPI4A) return SOC_VENDOR_SIPEED;
  return SOC_VENDOR_UNKNOWN;
 }

--- a/src/x86/cpuid.c
+++ b/src/x86/cpuid.c
@@ -1170,7 +1170,9 @@ void print_raw(struct cpuInfo* cpu) {
 }

 void free_topo_struct(struct topology* topo) {
+  if(topo->apic->cache_select_mask != NULL)
    free(topo->apic->cache_select_mask);
+  if(topo->apic->cache_id_apic != NULL)
    free(topo->apic->cache_id_apic);
  free(topo->apic);
  free(topo);
--- a/src/x86/uarch.c
+++ b/src/x86/uarch.c
@@ -112,7 +112,8 @@ enum {
  UARCH_ZEN2,
  UARCH_ZEN3,
  UARCH_ZEN3_PLUS,
-  UARCH_ZEN4
+  UARCH_ZEN4,
+  UARCH_ZEN4C
 };

 struct uarch {
@@ -124,7 +125,9 @@ struct uarch {
 #define UARCH_START if (false) {}
 #define CHECK_UARCH(arch, ef_, f_, em_, m_, s_, str, uarch, process) \
   else if (ef_ == ef && f_ == f && (em_ == NA || em_ == em) && (m_ == NA || m_ == m) && (s_ == NA || s_ == s)) fill_uarch(arch, str, uarch, process);
-#define UARCH_END else { printBug("Unknown microarchitecture detected: M=0x%.8X EM=0x%.8X F=0x%.8X EF=0x%.8X S=0x%.8X", m, em, f, ef, s); fill_uarch(arch, STRING_UNKNOWN, UARCH_UNKNOWN, 0); }
+#define UARCH_END else { printErr("Unknown microarchitecture detected: M=0x%X EM=0x%X F=0x%X EF=0x%X S=0x%X", m, em, f, ef, s); \
+fprintf(stderr, "Please see https://github.com/Dr-Noob/cpufetch#61-unknown-microarchitecture-error to know how to report this error\n"); \
+fill_uarch(arch, STRING_UNKNOWN, UARCH_UNKNOWN, UNK); }

 void fill_uarch(struct uarch* arch, char* str, MICROARCH u, uint32_t process) {
  arch->uarch_str = emalloc(sizeof(char) * (strlen(str)+1));
@@ -350,6 +353,7 @@ struct uarch* get_uarch_from_cpuid_amd(uint32_t ef, uint32_t f, uint32_t em, uin
  CHECK_UARCH(arch,  6, 15,  6,  5, NA, "Excavator",   UARCH_EXCAVATOR,   28) // undocumented, but sample from Alexandros Couloumbis
  CHECK_UARCH(arch,  6, 15,  7,  0, NA, "Excavator",   UARCH_EXCAVATOR,   28)
  CHECK_UARCH(arch,  7, 15,  0,  0, NA, "Jaguar",      UARCH_JAGUAR,      28)
+  CHECK_UARCH(arch,  7, 15,  1, NA, NA, "Jaguar",      UARCH_JAGUAR,      14) // instlatx64 (PS4) Normal PS4 is 28nm, Slim and Pro are 16nm
  CHECK_UARCH(arch,  7, 15,  2,  6, NA, "Jaguar",      UARCH_JAGUAR,      28) // AMD Cato (Xbox One?)
  CHECK_UARCH(arch,  7, 15,  3,  0, NA, "Puma 2014",   UARCH_PUMA_2014,   28)
  CHECK_UARCH(arch,  8, 15,  0,  0, NA, "Zen",         UARCH_ZEN,         14) // instlatx64 engr sample
@@ -364,14 +368,23 @@ struct uarch* get_uarch_from_cpuid_amd(uint32_t ef, uint32_t f, uint32_t em, uin
  CHECK_UARCH(arch,  8, 15,  6,  0, NA, "Zen 2",       UARCH_ZEN2,         7) // undocumented, geekbench.com example
  CHECK_UARCH(arch,  8, 15,  6,  8, NA, "Zen 2",       UARCH_ZEN2,         7) // found on instlatx64
  CHECK_UARCH(arch,  8, 15,  7,  1, NA, "Zen 2",       UARCH_ZEN2,         7) // samples from Steven Noonan and instlatx64
+  CHECK_UARCH(arch,  8, 15,  8,  4, NA, "Zen 2",       UARCH_ZEN2,         7) // instlatx64 (Xbox Series X?)
  CHECK_UARCH(arch,  8, 15,  9,  0,  2, "Zen 2",       UARCH_ZEN2,         7) // Steam Deck (instlatx64)
+  CHECK_UARCH(arch,  8, 15,  10, 0, NA, "Zen 2",       UARCH_ZEN2,         6) // instlatx64
  CHECK_UARCH(arch, 10, 15,  0,  1, NA, "Zen 3",       UARCH_ZEN3,         7) // instlatx64
+  CHECK_UARCH(arch, 10, 15,  0,  8, NA, "Zen 3",       UARCH_ZEN3,         7) // instlatx64
+  CHECK_UARCH(arch, 10, 15,  1,  1, NA, "Zen 4",       UARCH_ZEN4,         5) // instlatx64
+  CHECK_UARCH(arch, 10, 15,  1,  8, NA, "Zen 4",       UARCH_ZEN4,         5) // instlatx64
  CHECK_UARCH(arch, 10, 15,  2,  1, NA, "Zen 3",       UARCH_ZEN3,         7) // instlatx64
+  CHECK_UARCH(arch, 10, 15,  3, NA, NA, "Zen 3",       UARCH_ZEN3,         7) // instlatx64
  CHECK_UARCH(arch, 10, 15,  4,  4, NA, "Zen 3+",      UARCH_ZEN3_PLUS,    6) // instlatx64 (they say it is Zen3...)
  CHECK_UARCH(arch, 10, 15,  5,  0, NA, "Zen 3",       UARCH_ZEN3,         7) // instlatx64
-  CHECK_UARCH(arch, 10, 15,  1,  1, NA, "Zen 4",       UARCH_ZEN4,         5) // instlatx64
  CHECK_UARCH(arch, 10, 15,  6,  1,  2, "Zen 4",       UARCH_ZEN4,         5) // instlatx64
  CHECK_UARCH(arch, 10, 15,  7,  4,  1, "Zen 4",       UARCH_ZEN4,         4) // instlatx64
+  CHECK_UARCH(arch, 10, 15,  7,  8,  0, "Zen 4",       UARCH_ZEN4,         4) // instlatx64
+  CHECK_UARCH(arch, 10, 15,  8, NA, NA, "Zen 4",       UARCH_ZEN4,         5) // instlatx64 (AMD MI300C)
+  CHECK_UARCH(arch, 10, 15,  9, NA, NA, "Zen 4",       UARCH_ZEN4,         5) // instlatx64 (AMD MI300A)
+  CHECK_UARCH(arch, 10, 15, 10, NA, NA, "Zen 4c",      UARCH_ZEN4C,        5) // instlatx64
  UARCH_END

  return arch;
@@ -419,7 +432,8 @@ struct uarch* get_uarch_from_cpuid(struct cpuInfo* cpu, uint32_t dump, uint32_t
 bool vpus_are_AVX512(struct cpuInfo* cpu) {
  return cpu->arch->uarch != UARCH_ICE_LAKE &&
         cpu->arch->uarch != UARCH_TIGER_LAKE &&
-         cpu->arch->uarch != UARCH_ZEN4;
+         cpu->arch->uarch != UARCH_ZEN4 &&
+         cpu->arch->uarch != UARCH_ZEN4C;
 }

 bool is_knights_landing(struct cpuInfo* cpu) {
@@ -455,6 +469,7 @@ int get_number_of_vpus(struct cpuInfo* cpu) {
      case UARCH_ZEN3:
      case UARCH_ZEN3_PLUS:
      case UARCH_ZEN4:
+      case UARCH_ZEN4C:
        return 2;
      default:
        return 1;
Author	SHA1	Message	Date
Dr-Noob	4ba128ad33	[v1.04][X86] Fix incorrect free in AMD CPUs	2023-12-22 22:53:42 +00:00
Dr-Noob	2feee25659	[v1.04] Clarify how the unknown microarchitectures should be reported	2023-12-03 20:23:15 +00:00
Dr-Noob	8335bd004d	[v1.04][X86] Add AMD uarchs	2023-12-02 18:18:43 +00:00
Dr-Noob	a172b4b281	[v1.04][ARM] Add more Mediatek SoCs	2023-11-18 20:25:57 +01:00
Dr-Noob	d88a6bf763	[v1.04][X86] Fixed bhyve matcher (#193 )	2023-11-11 09:36:12 +00:00
Dr-Noob	8870a0ca0c	[v1.04][RISCV] Add Sipeed ASCII logo	2023-11-01 20:50:05 +00:00
Dr-Noob	a43b700540	[v1.04][RISCV] Add Lichee PI 4a SoC (#200 )	2023-11-01 20:48:25 +00:00
Dr-Noob	9a578d3670	[v1.04][RISCV] Make single-letter extension detection more robust. s and u are invalid but might appear (#200 ), so just skip them	2023-10-29 17:14:47 +00:00
Dr-Noob	bf890965a3	[v1.04] Add colors to Google logo	2023-10-17 09:19:05 +02:00
Dr-Noob	530207aee0	[v1.04] Added Google ascii logo	2023-10-17 08:56:20 +02:00
Dr-Noob	f64ff0d4cf	[v1.04] Added Google Tensor SoCs	2023-10-17 08:55:38 +02:00
Dr-Noob	4b7600d49e	[v1.04][ARM] Add Cortex-A715/X3 uarchs	2023-10-16 09:04:59 +02:00