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1 Commits
d36123a363 ... bugfix

Author SHA1 Message Date
Dr-Noob
67a9975aa8 [v1.03] Experimental fix to distinguish between Gen8/Gen8+ Snapdragon SoCs 2023-01-17 19:14:05 +01:00
62 changed files with 1117 additions and 5095 deletions
Expand all files Collapse all files

76
Makefile
View File

@@ -1,7 +1,7 @@
CC ?= gcc
CFLAGS+=-Wall -Wextra -pedantic
SANITY_FLAGS=-Wfloat-equal -Wshadow -Wpointer-arith -Wstrict-prototypes
SANITY_FLAGS=-Wfloat-equal -Wshadow -Wpointer-arith
PREFIX ?= /usr
@@ -11,29 +11,18 @@ COMMON_SRC = $(SRC_COMMON)main.c $(SRC_COMMON)cpu.c $(SRC_COMMON)udev.c $(SRC_CO
COMMON_HDR = $(SRC_COMMON)ascii.h $(SRC_COMMON)cpu.h $(SRC_COMMON)udev.h $(SRC_COMMON)printer.h $(SRC_COMMON)args.h $(SRC_COMMON)global.h
ifneq ($(OS),Windows_NT)
GIT_VERSION := "$(shell git describe --abbrev=4 --dirty --always --tags)"
arch := $(shell uname -m)
os := $(shell uname -s)
ifeq ($(os), Linux)
COMMON_SRC += $(SRC_COMMON)freq.c
COMMON_HDR += $(SRC_COMMON)freq.h
endif
ifeq ($(arch), $(filter $(arch), x86_64 amd64 i386 i486 i586 i686))
SRC_DIR=src/x86/
SOURCE += $(COMMON_SRC) $(SRC_DIR)cpuid.c $(SRC_DIR)apic.c $(SRC_DIR)cpuid_asm.c $(SRC_DIR)uarch.c
HEADERS += $(COMMON_HDR) $(SRC_DIR)cpuid.h $(SRC_DIR)apic.h $(SRC_DIR)cpuid_asm.h $(SRC_DIR)uarch.h $(SRC_DIR)freq/freq.h
ifeq ($(os), Linux)
os := $(shell uname -s)
ifeq ($(os), Linux)
SOURCE += $(SRC_DIR)freq/freq.c freq_nov.o freq_avx.o freq_avx512.o
HEADERS += $(SRC_DIR)freq/freq.h
CFLAGS += -pthread
endif
ifeq ($(os), FreeBSD)
SOURCE += $(SRC_COMMON)sysctl.c
HEADERS += $(SRC_COMMON)sysctl.h
endif
endif
CFLAGS += -DARCH_X86 -std=c99 -fstack-protector-all
else ifeq ($(arch), $(filter $(arch), ppc64le ppc64 ppcle ppc))
SRC_DIR=src/ppc/
@@ -42,25 +31,15 @@ ifneq ($(OS),Windows_NT)
CFLAGS += -DARCH_PPC -std=gnu99 -fstack-protector-all -Wno-language-extension-token
else ifeq ($(arch), $(filter $(arch), arm aarch64_be aarch64 arm64 armv8b armv8l armv7l armv6l))
SRC_DIR=src/arm/
SOURCE += $(COMMON_SRC) $(SRC_DIR)midr.c $(SRC_DIR)uarch.c $(SRC_COMMON)soc.c $(SRC_DIR)soc.c $(SRC_COMMON)pci.c $(SRC_DIR)udev.c sve.o
HEADERS += $(COMMON_HDR) $(SRC_DIR)midr.h $(SRC_DIR)uarch.h $(SRC_COMMON)soc.h $(SRC_DIR)soc.h $(SRC_COMMON)pci.h $(SRC_DIR)udev.c $(SRC_DIR)socs.h
SOURCE += $(COMMON_SRC) $(SRC_DIR)midr.c $(SRC_DIR)uarch.c $(SRC_DIR)soc.c $(SRC_DIR)udev.c
HEADERS += $(COMMON_HDR) $(SRC_DIR)midr.h $(SRC_DIR)uarch.h $(SRC_DIR)soc.h $(SRC_DIR)udev.c $(SRC_DIR)socs.h
CFLAGS += -DARCH_ARM -Wno-unused-parameter -std=c99 -fstack-protector-all
# Check if the compiler supports -march=armv8-a+sve. We will use it (if supported) to compile SVE detection code later
is_sve_flag_supported := $(shell $(CC) -march=armv8-a+sve -c $(SRC_DIR)sve.c -o sve_test.o 2> /dev/null && echo 'yes'; rm -f sve_test.o)
ifeq ($(is_sve_flag_supported), yes)
SVE_FLAGS += -march=armv8-a+sve
endif
os := $(shell uname -s)
ifeq ($(os), Darwin)
SOURCE += $(SRC_COMMON)sysctl.c
HEADERS += $(SRC_COMMON)sysctl.h
SOURCE += $(SRC_DIR)sysctl.c
HEADERS += $(SRC_DIR)sysctl.h
endif
else ifeq ($(arch), $(filter $(arch), riscv64 riscv32))
SRC_DIR=src/riscv/
SOURCE += $(COMMON_SRC) $(SRC_DIR)riscv.c $(SRC_DIR)uarch.c $(SRC_COMMON)soc.c $(SRC_DIR)soc.c $(SRC_DIR)udev.c
HEADERS += $(COMMON_HDR) $(SRC_DIR)riscv.h $(SRC_DIR)uarch.h $(SRC_COMMON)soc.h $(SRC_DIR)soc.h $(SRC_DIR)udev.h $(SRC_DIR)socs.h
CFLAGS += -DARCH_RISCV -Wno-unused-parameter -std=c99 -fstack-protector-all
else
# Error lines should not be tabulated because Makefile complains about it
$(warning Unsupported arch detected: $(arch). See https://github.com/Dr-Noob/cpufetch#1-support)
@@ -70,27 +49,11 @@ $(error Aborting compilation)
OUTPUT=cpufetch
else
arch := $(shell cc -dumpmachine)
arch := $(firstword $(subst -, ,$(arch)))
ifeq ($(arch), $(filter $(arch), x86_64 amd64 i386 i486 i586 i686))
SRC_DIR=src/x86/
SOURCE += $(COMMON_SRC) $(SRC_DIR)cpuid.c $(SRC_DIR)apic.c $(SRC_DIR)cpuid_asm.c $(SRC_DIR)uarch.c
HEADERS += $(COMMON_HDR) $(SRC_DIR)cpuid.h $(SRC_DIR)apic.h $(SRC_DIR)cpuid_asm.h $(SRC_DIR)uarch.h
CFLAGS += -DARCH_X86 -std=c99
else ifeq ($(arch), $(filter $(arch), arm aarch64_be aarch64 arm64 armv8b armv8l armv7l armv6l))
SRC_DIR=src/arm/
SOURCE += $(COMMON_SRC) $(SRC_DIR)midr.c $(SRC_DIR)uarch.c $(SRC_COMMON)soc.c $(SRC_DIR)soc.c $(SRC_COMMON)pci.c $(SRC_DIR)udev.c sve.o
HEADERS += $(COMMON_HDR) $(SRC_DIR)midr.h $(SRC_DIR)uarch.h $(SRC_COMMON)soc.h $(SRC_DIR)soc.h $(SRC_COMMON)pci.h $(SRC_DIR)udev.c $(SRC_DIR)socs.h
CFLAGS += -DARCH_ARM -std=c99
else
# Error lines should not be tabulated because Makefile complains about it
$(warning Unsupported arch detected: $(arch). See https://github.com/Dr-Noob/cpufetch#1-support)
$(warning If your architecture is supported but the compilation fails, please open an issue in https://github.com/Dr-Noob/cpufetch/issues)
$(error Aborting compilation)
endif
GIT_VERSION := ""
# Assume x86_64
SRC_DIR=src/x86/
SOURCE += $(COMMON_SRC) $(SRC_DIR)cpuid.c $(SRC_DIR)apic.c $(SRC_DIR)cpuid_asm.c $(SRC_DIR)uarch.c
HEADERS += $(COMMON_HDR) $(SRC_DIR)cpuid.h $(SRC_DIR)apic.h $(SRC_DIR)cpuid_asm.h $(SRC_DIR)uarch.h
CFLAGS += -DARCH_X86 -std=c99
SANITY_FLAGS += -Wno-pedantic-ms-format
OUTPUT=cpufetch.exe
endif
@@ -116,15 +79,8 @@ freq_avx.o: Makefile $(SRC_DIR)freq/freq_avx.c $(SRC_DIR)freq/freq_avx.h $(SRC_D
freq_avx512.o: Makefile $(SRC_DIR)freq/freq_avx512.c $(SRC_DIR)freq/freq_avx512.h $(SRC_DIR)freq/freq.h
$(CC) $(CFLAGS) $(SANITY_FLAGS) -c -mavx512f -pthread $(SRC_DIR)freq/freq_avx512.c -o $@
sve.o: Makefile $(SRC_DIR)sve.c $(SRC_DIR)sve.h
$(CC) $(CFLAGS) $(SANITY_FLAGS) $(SVE_FLAGS) -c $(SRC_DIR)sve.c -o $@
$(OUTPUT): Makefile $(SOURCE) $(HEADERS)
ifeq ($(GIT_VERSION),"")
$(CC) $(CFLAGS) $(SANITY_FLAGS) $(SOURCE) -o $(OUTPUT)
else
$(CC) $(CFLAGS) $(SANITY_FLAGS) -DGIT_FULL_VERSION=\"$(GIT_VERSION)\" $(SOURCE) -o $(OUTPUT)
endif
run: $(OUTPUT)
./$(OUTPUT)
@@ -135,9 +91,9 @@ clean:
install: $(OUTPUT)
install -Dm755 "cpufetch" "$(DESTDIR)$(PREFIX)/bin/cpufetch"
install -Dm644 "LICENSE" "$(DESTDIR)$(PREFIX)/share/licenses/cpufetch-git/LICENSE"
install -Dm644 "cpufetch.1" "$(DESTDIR)$(PREFIX)/share/man/man1/cpufetch.1"
install -Dm644 "cpufetch.1" "$(DESTDIR)$(PREFIX)/share/man/man1/cpufetch.1.gz"
uninstall:
rm -f "$(DESTDIR)$(PREFIX)/bin/cpufetch"
rm -f "$(DESTDIR)$(PREFIX)/share/licenses/cpufetch-git/LICENSE"
rm -f "$(DESTDIR)$(PREFIX)/share/man/man1/cpufetch.1"
rm -f "$(DESTDIR)$(PREFIX)/share/man/man1/cpufetch.1.gz"

49
README.md
View File

@@ -45,14 +45,11 @@ cpufetch is a command-line tool written in C that displays the CPU information i
- [3.1 x86_64](#31-x86_64)
- [3.2 ARM](#32-arm)
- [3.3 PowerPC](#33-powerpc)
- [3.4 RISC-V](#34-risc-v)
- [4. Colors](#4-colors)
- [4.1 Specifying a name](#41-specifying-a-name)
- [4.2 Specifying the colors in RGB format](#42-specifying-the-colors-in-rgb-format)
- [5. Implementation](#5-implementation)
- [6. Bugs or improvements](#6-bugs-or-improvements)
- [6.1 Unknown microarchitecture error](#61-unknown-microarchitecture-error)
- [6.2 Other situations](#62-other-situations)
- [7. Acknowledgements](#7-acknowledgements)
- [8. cpufetch for GPUs (gpufetch)](#8-cpufetch-for-gpus-gpufetch)
@@ -60,17 +57,17 @@ cpufetch is a command-line tool written in C that displays the CPU information i
## 1. Support
| OS | x86_64 / x86 | ARM | RISC-V | PowerPC |
|:-----------:|:------------------:|:------------------:|:------------------:|:------------------:|
| GNU / Linux | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
| Windows | :heavy_check_mark: | :heavy_check_mark: | :x: | :x: |
| Android | :heavy_check_mark: | :heavy_check_mark: | :x: | :x: |
| macOS | :heavy_check_mark: | :heavy_check_mark: | :x: | :heavy_check_mark: |
| FreeBSD | :heavy_check_mark: | :x: | :x: | :x: |
| OS | x86_64 / x86 | ARM | PowerPC |
|:-----------:|:------------------:|:------------------:|:------------------:|
| GNU / Linux | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
| Windows | :heavy_check_mark: | :x: | :x: |
| Android | :heavy_check_mark: | :heavy_check_mark: | :x: |
| macOS | :heavy_check_mark: | :heavy_check_mark: | :x: |
| FreeBSD | :heavy_check_mark: | :x: | :x: |
**NOTES:**
- Colors will be used in Windows only if the terminal supports it.
- Support in macOS ARM is limited to Apple chips only
- Support in macOS ARM is limited to Apple M1 only
## 2. Installation
### 2.1 Installing from a package
@@ -121,11 +118,6 @@ make
<p align="center"><img width=90% src="pictures/ibm.png"></p>
<p align="center">Talos II</p>
## 3.4 RISC-V
<p align="center"><img width=80% src="pictures/starfive.png"></p>
<p align="center">StarFive VisionFive 2</p>
## 4. Colors
By default, `cpufetch` will print the CPU logo with the system colorscheme. However, you can set a custom color scheme in two different ways:
@@ -155,33 +147,14 @@ By default, `cpufetch` will print the CPU logo with the system colorscheme. Howe
See [cpufetch programming documentation](https://github.com/Dr-Noob/cpufetch/tree/master/doc).
## 6. Bugs or improvements
### 6.1 Unknown microarchitecture error
If you get the `Unknown microarchitecture detected` error when running cpufetch, it might be caused by two possible reasons:
1. You are running an old release of cpufetch (most likely)
2. Your microarchitecture is not yet supported
Download and compile the latest version (see https://github.com/Dr-Noob/cpufetch#22-building-from-source for instructions)
and verify if the error persists.
* __If the error dissapears__: It means that this is the first situation. In this case, just use the
latest version of cpufetch which already has support for your hardware.
* __If the error does not dissapear__: It means that this is the
second situation. In this case, please create a new issue with the error message and the output of 'cpufetch --debug' on https://github.com/Dr-Noob/cpufetch/issues
### 6.2 Other situations
See [cpufetch contributing guidelines](https://github.com/Dr-Noob/cpufetch/blob/master/CONTRIBUTING.md).
## 7. Acknowledgements
Thanks to the fellow contributors and interested people in the project. Special thanks to:
- [Gonzalocl](https://github.com/Gonzalocl) and [OdnetninI](https://github.com/OdnetninI): Tested cpufetch in the earlier versions of the project in many different CPUs.
- [Gonzalocl](https://github.com/Gonzalocl), [OdnetninI](https://github.com/OdnetninI): Tested cpufetch in the earlier versions of the project in many different CPUs.
- [Kyngo](https://github.com/Kyngo): Tested cpufetch in the Apple M1 CPU.
- [avollmerhaus](https://github.com/avollmerhaus): Helped with PowerPC port giving ssh access to a PowerPC machine.
- [bbonev](https://github.com/bbonev) and [stephan-cr](https://github.com/stephan-cr): Reviewed the source code.
- [mdoksa76](https://github.com/mdoksa76) and [exkc](https://github.com/exkc): Excellent ideas and feedback for supporting Allwinner SoCs.
- [Sakura286](https://github.com/Sakura286), [exkc](https://github.com/exkc) and [Patola](https://github.com/Patola): Helped with RISC-V port with ssh access, ideas, testing, etc.
- [ThomasKaiser](https://github.com/ThomasKaiser): Very valuable feedback on improving ARM SoC detection (Apple, Allwinner, Rockchip).
- [zerkerX](https://github.com/zerkerX): Helped with feedback for supporting old (e.g., Pentium III) Intel CPUs.
- [avollmerhaus](https://github.com/avollmerhaus): Gave me ssh acess to a PowerPC machine, allowing me to develop the PowerPC port.
- [bbonev](https://github.com/bbonev), [stephan-cr](https://github.com/stephan-cr): Reviewed the source code.
## 8. cpufetch for GPUs (gpufetch)
See [gpufetch](https://github.com/Dr-Noob/gpufetch) project!

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358
src/arm/midr.c
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@@ -8,76 +8,15 @@
#ifdef __linux__
#include <sys/auxv.h>
#include <asm/hwcap.h>
#include "../common/freq.h"
#elif defined __APPLE__ || __MACH__
#include "../common/sysctl.h"
#elif defined _WIN32
#define WIN32_LEAN_AND_MEAN
#define NOMINMAX
#include <windows.h>
#include "sysctl.h"
#endif
#include "../common/global.h"
#include "../common/soc.h"
#include "../common/args.h"
#include "udev.h"
#include "midr.h"
#include "uarch.h"
#include "sve.h"
#if defined _WIN32
// Windows stores processor information in registery at:
// "HKEY_LOCAL_MACHINE\HARDWARE\DESCRIPTION\System\CentralProcessor"
// Within this directory, each core will get its own folder with
// registery entries named `CP ####` that map to ARM system registers.
// Ex. the MIDR register for core 0 is the `REG_QWORD` at:
// "HKEY_LOCAL_MACHINE\HARDWARE\DESCRIPTION\System\CentralProcessor\0\CP 4000"
// The name of these `CP ####`-registers follow their register ID encoding in hexadecimal
// (op0&1):op1:crn:crm:op2.
// More registers can be found here:
// https://developer.arm.com/documentation/ddi0601/2024-06/AArch64-Registers
// Some important ones:
// CP 4000: MIDR_EL1
// CP 4020: ID_AA64PFR0_EL1
// CP 4021: ID_AA64PFR1_EL1
// CP 4028: ID_AA64DFR0_EL1
// CP 4029: ID_AA64DFR1_EL1
// CP 402C: ID_AA64AFR0_EL1
// CP 402D: ID_AA64AFR1_EL1
// CP 4030: ID_AA64ISAR0_EL1
// CP 4031: ID_AA64ISAR1_EL1
// CP 4038: ID_AA64MMFR0_EL1
// CP 4039: ID_AA64MMFR1_EL1
// CP 403A: ID_AA64MMFR2_EL1
bool read_registry_hklm_int(char* path, char* name, void* value, bool is64) {
DWORD value_len;
int reg_type;
if (is64) {
value_len = sizeof(int64_t);
reg_type = RRF_RT_REG_QWORD;
}
else {
value_len = sizeof(int32_t);
reg_type = RRF_RT_REG_DWORD;
}
if(RegGetValueA(HKEY_LOCAL_MACHINE, path, name, reg_type, NULL, value, &value_len) != ERROR_SUCCESS) {
printBug("Error reading registry entry \"%s\\%s\"", path, name);
return false;
}
return true;
}
bool get_win32_core_info_int(uint32_t core_index, char* name, void* value, bool is64) {
// path + digits
uint32_t max_path_size = 45+3+1;
char* path = ecalloc(sizeof(char) * max_path_size, sizeof(char));
snprintf(path, max_path_size, "HARDWARE\\DESCRIPTION\\System\\CentralProcessor\\%u", core_index);
return read_registry_hklm_int(path, name, value, is64);
}
#endif
#include "soc.h"
bool cores_are_equal(int c1pos, int c2pos, uint32_t* midr_array, int32_t* freq_array) {
return midr_array[c1pos] == midr_array[c2pos] && freq_array[c1pos] == freq_array[c2pos];
@@ -100,17 +39,8 @@ struct cache* get_cache_info(struct cpuInfo* cpu) {
struct frequency* get_frequency_info(uint32_t core) {
struct frequency* freq = emalloc(sizeof(struct frequency));
freq->measured = false;
freq->base = UNKNOWN_DATA;
freq->max = get_max_freq_from_file(core);
#ifdef __linux__
if (freq->max == UNKNOWN_DATA || measure_max_frequency_flag()) {
if (freq->max == UNKNOWN_DATA)
printWarn("Unable to find max frequency from udev, measuring CPU frequency");
freq->max = measure_max_frequency(core);
freq->measured = true;
}
#endif
return freq;
}
@@ -150,21 +80,26 @@ int64_t get_peak_performance(struct cpuInfo* cpu) {
}
}
int64_t total_flops = 0;
int64_t flops = 0;
ptr = cpu;
for(int i=0; i < cpu->num_cpus; ptr = ptr->next_cpu, i++) {
int vpus = get_number_of_vpus(ptr);
int vpus_width = get_vpus_width(ptr);
bool has_fma = has_fma_support(ptr);
int64_t flops = ptr->topo->total_cores * get_freq(ptr->freq) * 1000000 * vpus * (vpus_width/32);
if(has_fma) flops = flops * 2;
total_flops += flops;
if(cpu->soc->soc_vendor == SOC_VENDOR_APPLE) {
// Special case for M1/M2
// First we find the E cores, then the P
// M1 have 2 (E cores) or 4 (P cores) FMA units
// Source: https://dougallj.github.io/applecpu/firestorm-simd.html
flops += ptr->topo->total_cores * (get_freq(ptr->freq) * 1000000) * 2 * 4 * 2;
ptr = ptr->next_cpu;
flops += ptr->topo->total_cores * (get_freq(ptr->freq) * 1000000) * 2 * 4 * 4;
}
else {
for(int i=0; i < cpu->num_cpus; ptr = ptr->next_cpu, i++) {
flops += ptr->topo->total_cores * (get_freq(ptr->freq) * 1000000);
}
if(cpu->feat->NEON) flops = flops * 4;
}
return total_flops;
return flops;
}
uint32_t fill_ids_from_midr(uint32_t* midr_array, int32_t* freq_array, uint32_t* ids_array, int len) {
@@ -206,7 +141,7 @@ void init_cpu_info(struct cpuInfo* cpu) {
// true...
// ARM32 https://elixir.bootlin.com/linux/latest/source/arch/arm/include/uapi/asm/hwcap.h
// ARM64 https://elixir.bootlin.com/linux/latest/source/arch/arm64/include/uapi/asm/hwcap.h
struct features* get_features_info(void) {
struct features* get_features_info() {
struct features* feat = emalloc(sizeof(struct features));
bool *ptr = &(feat->AES);
for(uint32_t i = 0; i < sizeof(struct features)/sizeof(bool); i++, ptr++) {
@@ -227,17 +162,6 @@ struct features* get_features_info(void) {
feat->SHA1 = hwcaps & HWCAP_SHA1;
feat->SHA2 = hwcaps & HWCAP_SHA2;
feat->NEON = hwcaps & HWCAP_ASIMD;
feat->SVE = hwcaps & HWCAP_SVE;
hwcaps = getauxval(AT_HWCAP2);
if (errno == ENOENT) {
printWarn("Unable to retrieve AT_HWCAP2 using getauxval");
}
else {
#ifdef HWCAP2_SVE2
feat->SVE2 = hwcaps & HWCAP2_SVE2;
#endif
}
}
#else
else {
@@ -253,8 +177,6 @@ struct features* get_features_info(void) {
feat->CRC32 = hwcaps & HWCAP2_CRC32;
feat->SHA1 = hwcaps & HWCAP2_SHA1;
feat->SHA2 = hwcaps & HWCAP2_SHA2;
feat->SVE = false;
feat->SVE2 = false;
}
#endif // ifdef __aarch64__
#elif defined __APPLE__ || __MACH__
@@ -264,54 +186,8 @@ struct features* get_features_info(void) {
feat->SHA1 = true;
feat->SHA2 = true;
feat->NEON = true;
feat->SVE = false;
feat->SVE2 = false;
#elif defined _WIN32
// CP 4020 maps to the ID_AA64PFR0_EL1 register on Windows
// https://developer.arm.com/documentation/ddi0601/2024-06/AArch64-Registers/ID-AA64PFR0-EL1--AArch64-Processor-Feature-Register-0
int64_t pfr0 = 0;
if(!get_win32_core_info_int(0, "CP 4020", &pfr0, true)) {
printWarn("Unable to retrieve PFR0 via registry");
}
else {
// AdvSimd[23:20]
// -1: Not available
// 0: AdvSimd support
// 1: AdvSimd support + FP16
int8_t adv_simd = ((int64_t)(pfr0 << (60 - 20)) >> 60);
feat->NEON = (adv_simd >= 0);
// SVE[35:32]
feat->SVE = (pfr0 >> 32) & 0xF ? true : false;
}
// Windoes does not expose a registry entry for the ID_AA64ZFR0_EL1 register
// this would have mapped to "CP 4024".
feat->SVE2 = false;
// CP 4030 maps to the ID_AA64ISAR0_EL1 register on Windows
// https://developer.arm.com/documentation/ddi0601/2024-06/AArch64-Registers/ID-AA64ISAR0-EL1--AArch64-Instruction-Set-Attribute-Register-0
int64_t isar0 = 0;
if(!get_win32_core_info_int(0, "CP 4030", &isar0, true)) {
printWarn("Unable to retrieve ISAR0 via registry");
}
else {
// AES[7:4]
feat->AES = (isar0 >> 4) & 0xF ? true : false;
// SHA1[11:8]
feat->SHA1 = (isar0 >> 8) & 0xF ? true : false;
// SHA2[15:12]
feat->SHA2 = (isar0 >> 12) & 0xF ? true : false;
// CRC32[19:16]
feat->CRC32 = (isar0 >> 16) & 0xF ? true : false;
}
#endif // ifdef __linux__
if (feat->SVE || feat->SVE2) {
feat->cntb = sve_cntb();
}
return feat;
}
@@ -418,7 +294,7 @@ void fill_cpu_info_avalanche_blizzard(struct cpuInfo* cpu, uint32_t pcores, uint
bli->feat = get_features_info();
bli->topo = malloc(sizeof(struct topology));
bli->topo->cach = bli->cach;
bli->topo->total_cores = ecores;
bli->topo->total_cores = pcores;
bli->freq = malloc(sizeof(struct frequency));
bli->freq->base = UNKNOWN_DATA;
bli->freq->max = 2800;
@@ -434,7 +310,7 @@ void fill_cpu_info_avalanche_blizzard(struct cpuInfo* cpu, uint32_t pcores, uint
ava->feat = get_features_info();
ava->topo = malloc(sizeof(struct topology));
ava->topo->cach = ava->cach;
ava->topo->total_cores = pcores;
ava->topo->total_cores = ecores;
ava->freq = malloc(sizeof(struct frequency));
ava->freq->base = UNKNOWN_DATA;
ava->freq->max = 3500;
@@ -443,154 +319,59 @@ void fill_cpu_info_avalanche_blizzard(struct cpuInfo* cpu, uint32_t pcores, uint
ava->next_cpu = NULL;
}
void fill_cpu_info_everest_sawtooth(struct cpuInfo* cpu, uint32_t pcores, uint32_t ecores) {
// 1. Fill SAWTOOTH
struct cpuInfo* saw = cpu;
saw->midr = MIDR_APPLE_M3_SAWTOOTH;
saw->arch = get_uarch_from_midr(saw->midr, saw);
saw->cach = get_cache_info(saw);
saw->feat = get_features_info();
saw->topo = malloc(sizeof(struct topology));
saw->topo->cach = saw->cach;
saw->topo->total_cores = ecores;
saw->freq = malloc(sizeof(struct frequency));
saw->freq->base = UNKNOWN_DATA;
saw->freq->max = 2750;
saw->hv = malloc(sizeof(struct hypervisor));
saw->hv->present = false;
saw->next_cpu = malloc(sizeof(struct cpuInfo));
// 2. Fill EVEREST
struct cpuInfo* eve = saw->next_cpu;
eve->midr = MIDR_APPLE_M3_EVEREST;
eve->arch = get_uarch_from_midr(eve->midr, eve);
eve->cach = get_cache_info(eve);
eve->feat = get_features_info();
eve->topo = malloc(sizeof(struct topology));
eve->topo->cach = eve->cach;
eve->topo->total_cores = pcores;
eve->freq = malloc(sizeof(struct frequency));
eve->freq->base = UNKNOWN_DATA;
eve->freq->max = 4050;
eve->hv = malloc(sizeof(struct hypervisor));
eve->hv->present = false;
eve->next_cpu = NULL;
}
struct cpuInfo* get_cpu_info_mach(struct cpuInfo* cpu) {
// https://developer.apple.com/documentation/kernel/1387446-sysctlbyname/determining_system_capabilities
uint32_t nperflevels = get_sys_info_by_name("hw.nperflevels");
if((cpu->num_cpus = nperflevels) != 2) {
printBug("Expected to find SoC with 2 perf levels, found: %d", cpu->num_cpus);
return NULL;
}
uint32_t pcores = get_sys_info_by_name("hw.perflevel0.physicalcpu");
uint32_t ecores = get_sys_info_by_name("hw.perflevel1.physicalcpu");
if(ecores <= 0) {
printBug("Expected to find a numer of ecores > 0, found: %d", ecores);
return NULL;
}
if(pcores <= 0) {
printBug("Expected to find a numer of pcores > 0, found: %d", pcores);
return NULL;
}
uint32_t cpu_family = get_sys_info_by_name("hw.cpufamily");
// Manually fill the cpuInfo assuming that
// the CPU is an Apple SoC
// the CPU is an Apple M1/M2
if(cpu_family == CPUFAMILY_ARM_FIRESTORM_ICESTORM) {
fill_cpu_info_firestorm_icestorm(cpu, pcores, ecores);
cpu->soc = get_soc(cpu);
cpu->num_cpus = 2;
// Now detect the M1 version
uint32_t cpu_subfamily = get_sys_info_by_name("hw.cpusubfamily");
if(cpu_subfamily == CPUSUBFAMILY_ARM_HG) {
// Apple M1
fill_cpu_info_firestorm_icestorm(cpu, 4, 4);
}
else if(cpu_subfamily == CPUSUBFAMILY_ARM_HS || cpu_subfamily == CPUSUBFAMILY_ARM_HC_HD) {
// Apple M1 Pro/Max/Ultra. Detect number of cores
uint32_t physicalcpu = get_sys_info_by_name("hw.physicalcpu");
if(physicalcpu == 20) {
// M1 Ultra
fill_cpu_info_firestorm_icestorm(cpu, 16, 4);
}
else if(physicalcpu == 8 || physicalcpu == 10) {
// M1 Pro/Max
fill_cpu_info_firestorm_icestorm(cpu, physicalcpu-2, 2);
}
else {
printBug("Found invalid physical cpu number: %d", physicalcpu);
return NULL;
}
}
else {
printBug("Found invalid cpu_subfamily: 0x%.8X", cpu_subfamily);
return NULL;
}
cpu->soc = get_soc();
cpu->peak_performance = get_peak_performance(cpu);
}
else if(cpu_family == CPUFAMILY_ARM_AVALANCHE_BLIZZARD) {
fill_cpu_info_avalanche_blizzard(cpu, pcores, ecores);
cpu->soc = get_soc(cpu);
cpu->peak_performance = get_peak_performance(cpu);
}
else if(cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH ||
cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH_2 ||
cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH_PRO ||
cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH_MAX) {
fill_cpu_info_everest_sawtooth(cpu, pcores, ecores);
cpu->soc = get_soc(cpu);
// Just the "normal" M2 exists for now
cpu->num_cpus = 2;
fill_cpu_info_avalanche_blizzard(cpu, 4, 4);
cpu->soc = get_soc();
cpu->peak_performance = get_peak_performance(cpu);
}
else {
printBugCheckRelease("Found invalid cpu_family: 0x%.8X", cpu_family);
printBug("Found invalid cpu_family: 0x%.8X", cpu_family);
return NULL;
}
return cpu;
}
#elif defined _WIN32
struct cpuInfo* get_cpu_info_windows(struct cpuInfo* cpu) {
init_cpu_info(cpu);
SYSTEM_INFO sys_info;
GetSystemInfo(&sys_info);
int ncores = sys_info.dwNumberOfProcessors;
uint32_t* midr_array = emalloc(sizeof(uint32_t) * ncores);
int32_t* freq_array = emalloc(sizeof(uint32_t) * ncores);
uint32_t* ids_array = emalloc(sizeof(uint32_t) * ncores);
for(int i=0; i < ncores; i++) {
// Cast from 64 to 32 bit to be able to re-use the pre-existing
// functions such as fill_ids_from_midr and cores_are_equal
int64_t midr_64;
if(!get_win32_core_info_int(i, "CP 4000", &midr_64, true)) {
return NULL;
}
midr_array[i] = midr_64;
if(!get_win32_core_info_int(i, "~MHz", &freq_array[i], false)) {
return NULL;
}
}
uint32_t sockets = fill_ids_from_midr(midr_array, freq_array, ids_array, ncores);
struct cpuInfo* ptr = cpu;
int midr_idx = 0;
int tmp_midr_idx = 0;
for(uint32_t i=0; i < sockets; i++) {
if(i > 0) {
ptr->next_cpu = emalloc(sizeof(struct cpuInfo));
ptr = ptr->next_cpu;
init_cpu_info(ptr);
tmp_midr_idx = midr_idx;
while(cores_are_equal(midr_idx, tmp_midr_idx, midr_array, freq_array)) tmp_midr_idx++;
midr_idx = tmp_midr_idx;
}
ptr->midr = midr_array[midr_idx];
ptr->arch = get_uarch_from_midr(ptr->midr, ptr);
ptr->feat = get_features_info();
ptr->freq = emalloc(sizeof(struct frequency));
ptr->freq->measured = false;
ptr->freq->base = freq_array[midr_idx];
ptr->freq->max = UNKNOWN_DATA;
ptr->cach = get_cache_info(ptr);
ptr->topo = get_topology_info(ptr, ptr->cach, midr_array, freq_array, i, ncores);
}
cpu->num_cpus = sockets;
cpu->hv = emalloc(sizeof(struct hypervisor));
cpu->hv->present = false;
cpu->soc = get_soc(cpu);
cpu->peak_performance = get_peak_performance(cpu);
return cpu;
}
#endif
struct cpuInfo* get_cpu_info(void) {
struct cpuInfo* get_cpu_info() {
struct cpuInfo* cpu = malloc(sizeof(struct cpuInfo));
init_cpu_info(cpu);
@@ -598,8 +379,6 @@ struct cpuInfo* get_cpu_info(void) {
return get_cpu_info_linux(cpu);
#elif defined __APPLE__ || __MACH__
return get_cpu_info_mach(cpu);
#elif defined _WIN32
return get_cpu_info_windows(cpu);
#endif
}
@@ -613,7 +392,7 @@ char* get_str_topology(struct cpuInfo* cpu, struct topology* topo, bool dual_soc
char* get_str_features(struct cpuInfo* cpu) {
struct features* feat = cpu->feat;
uint32_t max_len = strlen("NEON,SHA1,SHA2,AES,CRC32,SVE,SVE2,") + 1;
uint32_t max_len = strlen("NEON,SHA1,SHA2,AES,CRC32,") + 1;
uint32_t len = 0;
char* string = ecalloc(max_len, sizeof(char));
@@ -621,14 +400,6 @@ char* get_str_features(struct cpuInfo* cpu) {
strcat(string, "NEON,");
len += 5;
}
if(feat->SVE) {
strcat(string, "SVE,");
len += 4;
}
if(feat->SVE2) {
strcat(string, "SVE2,");
len += 5;
}
if(feat->SHA1) {
strcat(string, "SHA1,");
len += 5;
@@ -677,19 +448,6 @@ void print_debug(struct cpuInfo* cpu) {
printf("%ld MHz\n", freq);
}
}
if (cpu->feat->SVE || cpu->feat->SVE2) {
printf("- cntb: %d\n", (int) cpu->feat->cntb);
}
#if defined(__APPLE__) || defined(__MACH__)
printf("hw.cpufamily: 0x%.8X\n", get_sys_info_by_name("hw.cpufamily"));
printf("hw.cpusubfamily: 0x%.8X\n", get_sys_info_by_name("hw.cpusubfamily"));
printf("hw.nperflevels: %d\n", get_sys_info_by_name("hw.nperflevels"));
printf("hw.physicalcpu: %d\n", get_sys_info_by_name("hw.physicalcpu"));
printf("hw.perflevel0.physicalcpu: %d\n", get_sys_info_by_name("hw.perflevel0.physicalcpu"));
printf("hw.perflevel1.physicalcpu: %d\n", get_sys_info_by_name("hw.perflevel1.physicalcpu"));
#endif
}
void free_topo_struct(struct topology* topo) {

2
src/arm/midr.h
View File

@@ -3,7 +3,7 @@
#include "../common/cpu.h"
struct cpuInfo* get_cpu_info(void);
struct cpuInfo* get_cpu_info();
uint32_t get_nsockets(struct topology* topo);
char* get_str_topology(struct cpuInfo* cpu, struct topology* topo, bool dual_socket);

982
src/arm/soc.c
View File

File diff suppressed because it is too large Load Diff

29
src/arm/soc.h
View File

@@ -1,10 +1,33 @@
#ifndef __SOC_ARM__
#define __SOC_ARM__
#ifndef __SOC__
#define __SOC__
#include "../common/cpu.h"
#include "../common/soc.h"
#include <stdint.h>
typedef int32_t SOC;
enum {
SOC_VENDOR_UNKNOWN,
SOC_VENDOR_SNAPDRAGON,
SOC_VENDOR_MEDIATEK,
SOC_VENDOR_EXYNOS,
SOC_VENDOR_KIRIN,
SOC_VENDOR_BROADCOM,
SOC_VENDOR_APPLE,
SOC_VENDOR_ALLWINNER
};
struct system_on_chip {
SOC soc_model;
VENDOR soc_vendor;
int32_t process;
char* soc_name;
char* raw_name;
};
struct system_on_chip* get_soc(struct cpuInfo* cpu);
char* get_soc_name(struct system_on_chip* soc);
VENDOR get_soc_vendor(struct system_on_chip* soc);
char* get_str_process(struct system_on_chip* soc);
#endif

240
src/arm/socs.h
View File

@@ -10,6 +10,7 @@ enum {
SOC_BCM_2836,
SOC_BCM_2837,
SOC_BCM_2837B0,
SOC_BCM_2711,
SOC_BCM_21553,
SOC_BCM_21553T,
SOC_BCM_21663,
@@ -19,8 +20,6 @@ enum {
SOC_BCM_28145,
SOC_BCM_2157,
SOC_BCM_21654,
SOC_BCM_2711,
SOC_BCM_2712,
// Hisilicon //
SOC_HISILICON_3620,
SOC_HISILICON_3630,
@@ -29,10 +28,6 @@ enum {
SOC_HISILICON_3670,
SOC_HISILICON_3680,
SOC_HISILICON_3690,
SOC_HISILICON_9000S,
// Kunpeng //
SOC_KUNPENG_920,
SOC_KUNPENG_930,
// Exynos //
SOC_EXYNOS_3475,
SOC_EXYNOS_4210,
@@ -68,23 +63,39 @@ enum {
SOC_EXYNOS_980,
SOC_EXYNOS_880,
// Mediatek //
SOC_MTK_MT5327,
SOC_MTK_MT5329,
SOC_MTK_MT5366,
SOC_MTK_MT5389,
SOC_MTK_MT5395,
SOC_MTK_MT5396,
SOC_MTK_MT5398,
SOC_MTK_MT5505,
SOC_MTK_MT5561,
SOC_MTK_MT5580,
SOC_MTK_MT5582,
SOC_MTK_MT5592,
SOC_MTK_MT5595,
SOC_MTK_MT5596,
SOC_MTK_MT5597,
SOC_MTK_MT5889,
SOC_MTK_MT5895,
SOC_MTK_MT6893,
SOC_MTK_MT6891,
SOC_MTK_MT6889,
SOC_MTK_MT6885Z,
SOC_MTK_MT6853,
SOC_MTK_MT6873,
SOC_MTK_MT6875,
SOC_MTK_MT6761D,
SOC_MTK_MT6761,
SOC_MTK_MT6762D,
SOC_MTK_MT6755,
SOC_MTK_MT6755M,
SOC_MTK_MT6755T,
SOC_MTK_MT6757,
SOC_MTK_MT6762,
SOC_MTK_MT6763V,
SOC_MTK_MT6763T,
SOC_MTK_MT6757CD,
SOC_MTK_MT6758,
SOC_MTK_MT6765,
SOC_MTK_MT6771,
SOC_MTK_MT6768,
SOC_MTK_MT6771T,
SOC_MTK_MT6771V,
SOC_MTK_MT6779,
SOC_MTK_MT6795,
SOC_MTK_MT6795T,
SOC_MTK_MT6797,
SOC_MTK_MT6797M,
SOC_MTK_MT6797D,
SOC_MTK_MT6797T,
SOC_MTK_MT6797X,
SOC_MTK_MT6799,
SOC_MTK_MT6515,
SOC_MTK_MT6516,
SOC_MTK_MT6517,
@@ -114,51 +125,7 @@ enum {
SOC_MTK_MT6750T,
SOC_MTK_MT6752,
SOC_MTK_MT6753,
SOC_MTK_MT6755M,
SOC_MTK_MT6755T,
SOC_MTK_MT6757,
SOC_MTK_MT6757CD,
SOC_MTK_MT6758,
SOC_MTK_MT6761,
SOC_MTK_MT6761D,
SOC_MTK_MT6762,
SOC_MTK_MT6762D,
SOC_MTK_MT6762G,
SOC_MTK_MT6763T,
SOC_MTK_MT6763V,
SOC_MTK_MT6765,
SOC_MTK_MT6765G,
SOC_MTK_MT6765H,
SOC_MTK_MT6768,
SOC_MTK_MT6769H,
SOC_MTK_MT6769T,
SOC_MTK_MT6769V,
SOC_MTK_MT6769Z,
SOC_MTK_MT6771,
SOC_MTK_MT6779V_CU,
SOC_MTK_MT6779V_CV,
SOC_MTK_MT6785V_CC,
SOC_MTK_MT6785V_CD,
SOC_MTK_MT6789,
SOC_MTK_MT6795,
SOC_MTK_MT6797,
SOC_MTK_MT6797T,
SOC_MTK_MT6797X,
SOC_MTK_MT6799,
SOC_MTK_MT6833,
SOC_MTK_MT6850,
SOC_MTK_MT6853,
SOC_MTK_MT6853V,
SOC_MTK_MT6873,
SOC_MTK_MT6875,
SOC_MTK_MT6879,
SOC_MTK_MT6883Z,
SOC_MTK_MT6885Z,
SOC_MTK_MT6889,
SOC_MTK_MT6889Z,
SOC_MTK_MT6891,
SOC_MTK_MT6893,
SOC_MTK_MT6893Z,
SOC_MTK_MT8121,
SOC_MTK_MT8125,
SOC_MTK_MT8127,
@@ -173,41 +140,7 @@ enum {
SOC_MTK_MT8581,
SOC_MTK_MT8735,
SOC_MTK_MT8765B,
SOC_MTK_MT8781V,
SOC_MTK_MT8783,
SOC_MTK_MT9602,
SOC_MTK_MT9612,
SOC_MTK_MT9613,
SOC_MTK_MT9615,
SOC_MTK_MT9618,
SOC_MTK_MT9632,
SOC_MTK_MT9638,
SOC_MTK_MT9652,
SOC_MTK_MT9653,
SOC_MTK_MT9675,
SOC_MTK_MT9685,
SOC_MTK_MT9686,
SOC_MTK_MT9689,
SOC_MTK_MT9902,
SOC_MTK_MT9950,
SOC_MTK_MT9972,
SOC_MTK_MT9982,
SOC_MTK_MT6983Z,
SOC_MTK_MT8798ZC,
SOC_MTK_MT6983W,
SOC_MTK_MT8798ZT,
SOC_MTK_MT6985W,
SOC_MTK_MT6985,
SOC_MTK_MT6989,
SOC_MTK_MT8796,
SOC_MTK_MT6877VZ,
SOC_MTK_MT6877T,
SOC_MTK_MT6855,
SOC_MTK_MT6853VT,
SOC_MTK_MT6853T,
SOC_MTK_MT6833P,
SOC_MTK_MT6833GP,
SOC_MTK_MT6833V,
// Snapdragon //
SOC_SNAPD_QSD8650,
SOC_SNAPD_QSD8250,
@@ -287,16 +220,11 @@ enum {
SOC_SNAPD_SDM660,
SOC_SNAPD_SM6115,
SOC_SNAPD_SM6125,
SOC_SNAPD_SM6375_AC,
SOC_SNAPD_SM6450,
SOC_SNAPD_SDM670,
SOC_SNAPD_SM6150,
SOC_SNAPD_SM6350,
SOC_SNAPD_SDM710,
SOC_SNAPD_SDM712,
SOC_SNAPD_SM4375,
SOC_SNAPD_SM4450,
SOC_SNAPD_SM4635,
SOC_SNAPD_SM7125,
SOC_SNAPD_SM7150_AA,
SOC_SNAPD_SM7150_AB,
@@ -305,11 +233,6 @@ enum {
SOC_SNAPD_SM7250_AA,
SOC_SNAPD_SM7250_AB,
SOC_SNAPD_SM7250_AC,
SOC_SNAPD_SM7435_AB,
SOC_SNAPD_SM7450,
SOC_SNAPD_SM7475,
SOC_SNAPD_SM7550_AB,
SOC_SNAPD_SM7675_AB,
SOC_SNAPD_MSM8974AA,
SOC_SNAPD_MSM8974AB,
SOC_SNAPD_MSM8974AC,
@@ -331,22 +254,12 @@ enum {
SOC_SNAPD_SM8350,
SOC_SNAPD_SM8450,
SOC_SNAPD_SM8475,
SOC_SNAPD_SM8550_AB,
SOC_SNAPD_SM8635,
SOC_SNAPD_SM8650_AB,
SOC_SNAPD_SC8280XP,
// APPLE
SOC_APPLE_M1,
SOC_APPLE_M1_PRO,
SOC_APPLE_M1_MAX,
SOC_APPLE_M1_ULTRA,
SOC_APPLE_M2,
SOC_APPLE_M2_PRO,
SOC_APPLE_M2_MAX,
SOC_APPLE_M2_ULTRA,
SOC_APPLE_M3,
SOC_APPLE_M3_PRO,
SOC_APPLE_M3_MAX,
// ALLWINNER
SOC_ALLWINNER_A10,
SOC_ALLWINNER_A13,
@@ -358,102 +271,29 @@ enum {
SOC_ALLWINNER_A33,
SOC_ALLWINNER_A40,
SOC_ALLWINNER_A50,
SOC_ALLWINNER_A64,
SOC_ALLWINNER_A80,
SOC_ALLWINNER_A83T,
SOC_ALLWINNER_V3S,
SOC_ALLWINNER_HZP,
SOC_ALLWINNER_H2PLUS,
SOC_ALLWINNER_S3,
SOC_ALLWINNER_H3,
SOC_ALLWINNER_H8,
SOC_ALLWINNER_H5,
SOC_ALLWINNER_H6,
SOC_ALLWINNER_H64,
SOC_ALLWINNER_H616,
SOC_ALLWINNER_H618,
SOC_ALLWINNER_R8,
SOC_ALLWINNER_R16,
SOC_ALLWINNER_R40,
SOC_ALLWINNER_R58,
SOC_ALLWINNER_R328,
// ROCKCHIP
SOC_ROCKCHIP_3288,
SOC_ROCKCHIP_3229,
SOC_ROCKCHIP_3308,
SOC_ROCKCHIP_3318,
SOC_ROCKCHIP_3326,
SOC_ROCKCHIP_3328,
SOC_ROCKCHIP_3368,
SOC_ROCKCHIP_3399,
SOC_ROCKCHIP_3528,
SOC_ROCKCHIP_3562,
SOC_ROCKCHIP_3566,
SOC_ROCKCHIP_3568,
SOC_ROCKCHIP_3588,
// GOOGLE
SOC_GOOGLE_TENSOR,
SOC_GOOGLE_TENSOR_G2,
SOC_GOOGLE_TENSOR_G3,
// NVIDIA,
SOC_TEGRA_2,
SOC_TEGRA_3,
SOC_TEGRA_4,
SOC_TEGRA_K1,
SOC_TEGRA_K2,
SOC_TEGRA_X1,
SOC_TEGRA_X2,
SOC_TEGRA_XAVIER,
SOC_TEGRA_ORIN,
// ALTRA
SOC_AMPERE_ALTRA,
// NXP
SOC_NXP_IMX8QM,
SOC_NXP_IMX8QP,
SOC_NXP_IMX8MP,
SOC_NXP_IMX8MN,
SOC_NXP_IMX8MM,
SOC_NXP_IMX8DXP,
SOC_NXP_IMX8QXP,
SOC_NXP_IMX93,
// AMLOGIC
SOC_AMLOGIC_A311D,
SOC_AMLOGIC_A311D2,
SOC_AMLOGIC_S905W,
SOC_AMLOGIC_S905D,
SOC_AMLOGIC_S905X,
SOC_AMLOGIC_S805X,
// MARVELL
SOC_MARVELL_A3700,
SOC_MARVELL_A3710,
SOC_MARVELL_A3720,
SOC_MARVELL_A7200,
SOC_MARVELL_A7400,
SOC_MARVELL_A8020,
SOC_MARVELL_A8040,
SOC_MARVELL_CN9130,
SOC_MARVELL_CN9131,
SOC_MARVELL_CN9132,
// UNKNOWN
SOC_MODEL_UNKNOWN
SOC_ALLWINNER_R328
};
inline static VENDOR get_soc_vendor_from_soc(SOC soc) {
if(soc >= SOC_BCM_2835 && soc <= SOC_BCM_2712) return SOC_VENDOR_BROADCOM;
else if(soc >= SOC_HISILICON_3620 && soc <= SOC_HISILICON_9000S) return SOC_VENDOR_KIRIN;
else if(soc >= SOC_KUNPENG_920 && soc <= SOC_KUNPENG_930) return SOC_VENDOR_KUNPENG;
if(soc >= SOC_BCM_2835 && soc <= SOC_BCM_21654) return SOC_VENDOR_BROADCOM;
else if(soc >= SOC_HISILICON_3620 && soc <= SOC_HISILICON_3690) return SOC_VENDOR_KIRIN;
else if(soc >= SOC_EXYNOS_3475 && soc <= SOC_EXYNOS_880) return SOC_VENDOR_EXYNOS;
else if(soc >= SOC_MTK_MT5327 && soc <= SOC_MTK_MT6833V) return SOC_VENDOR_MEDIATEK;
else if(soc >= SOC_SNAPD_QSD8650 && soc <= SOC_SNAPD_SC8280XP) return SOC_VENDOR_SNAPDRAGON;
else if(soc >= SOC_APPLE_M1 && soc <= SOC_APPLE_M3_MAX) return SOC_VENDOR_APPLE;
else if(soc >= SOC_MTK_MT6893 && soc <= SOC_MTK_MT8783) return SOC_VENDOR_MEDIATEK;
else if(soc >= SOC_SNAPD_QSD8650 && soc <= SOC_SNAPD_SM8475) return SOC_VENDOR_SNAPDRAGON;
else if(soc >= SOC_APPLE_M1 && soc <= SOC_APPLE_M2) return SOC_VENDOR_APPLE;
else if(soc >= SOC_ALLWINNER_A10 && soc <= SOC_ALLWINNER_R328) return SOC_VENDOR_ALLWINNER;
else if(soc >= SOC_ROCKCHIP_3288 && soc <= SOC_ROCKCHIP_3588) return SOC_VENDOR_ROCKCHIP;
else if(soc >= SOC_GOOGLE_TENSOR && soc <= SOC_GOOGLE_TENSOR_G3) return SOC_VENDOR_GOOGLE;
else if(soc >= SOC_TEGRA_2 && soc <= SOC_TEGRA_ORIN) return SOC_VENDOR_NVIDIA;
else if(soc >= SOC_AMPERE_ALTRA && soc <= SOC_AMPERE_ALTRA) return SOC_VENDOR_AMPERE;
else if(soc >= SOC_NXP_IMX8QM && soc <= SOC_NXP_IMX93) return SOC_VENDOR_NXP;
else if(soc >= SOC_AMLOGIC_A311D && soc <= SOC_AMLOGIC_S805X) return SOC_VENDOR_AMLOGIC;
else if(soc >= SOC_MARVELL_A3700 && soc <= SOC_MARVELL_CN9132) return SOC_VENDOR_MARVELL;
return SOC_VENDOR_UNKNOWN;
}

15
src/arm/sve.c
View File

@@ -1,15 +0,0 @@
#include <stdint.h>
#include "../common/global.h"
// https://learn.arm.com/learning-paths/servers-and-cloud-computing/sve/sve_basics/#:~:text=Using%20a%20text%20editor%20of%20your%20choice%2C%20copy,svcntb%28%29%29%3B%20%7D%20This%20program%20prints%20the%20vector%20length
uint64_t sve_cntb(void) {
#ifdef __ARM_FEATURE_SVE
uint64_t x0 = 0;
__asm volatile("cntb %0"
: "=r"(x0));
return x0;
#else
printWarn("sve_cntb: Hardware supports SVE, but it was not enabled by the compiler");
return 0;
#endif
}

6
src/arm/sve.h
View File

@@ -1,6 +0,0 @@
#ifndef __SVE_DETECTION__
#define __SVE_DETECTION__
uint64_t sve_cntb(void);
#endif

4
src/common/sysctl.c → src/arm/sysctl.c
View File

@@ -4,8 +4,8 @@
#include <string.h>
#include <errno.h>
#include "global.h"
#include "cpu.h"
#include "../common/global.h"
#include "../common/cpu.h"
uint32_t get_sys_info_by_name(char* name) {
size_t size = 0;

20
src/common/sysctl.h → src/arm/sysctl.h
View File

@@ -8,9 +8,6 @@
// APPLE_CPU_PART_M2_BLIZZARD=0x30,M2_AVALANCHE=0x31
#define MIDR_APPLE_M2_BLIZZARD 0x610F0300
#define MIDR_APPLE_M2_AVALANCHE 0x610F0310
// https://github.com/AsahiLinux/m1n1/blob/main/src/chickens.c
#define MIDR_APPLE_M3_SAWTOOTH 0x610F0480
#define MIDR_APPLE_M3_EVEREST 0x610F0490
// M1 / A14
#ifndef CPUFAMILY_ARM_FIRESTORM_ICESTORM
@@ -20,15 +17,6 @@
#ifndef CPUFAMILY_ARM_AVALANCHE_BLIZZARD
#define CPUFAMILY_ARM_AVALANCHE_BLIZZARD 0xDA33D83D
#endif
// M3 / A16 / A17
// M3: https://ratfactor.com/zig/stdlib-browseable2/c/darwin.zig.html
// M3_2: https://github.com/Dr-Noob/cpufetch/issues/230
// PRO: https://github.com/Dr-Noob/cpufetch/issues/225
// MAX: https://github.com/Dr-Noob/cpufetch/issues/210
#define CPUFAMILY_ARM_EVEREST_SAWTOOTH 0x8765EDEA
#define CPUFAMILY_ARM_EVEREST_SAWTOOTH_2 0xFA33415E
#define CPUFAMILY_ARM_EVEREST_SAWTOOTH_PRO 0x5F4DEA93
#define CPUFAMILY_ARM_EVEREST_SAWTOOTH_MAX 0x72015832
// For detecting different M1 types
// NOTE: Could also be achieved detecting different
@@ -43,14 +31,6 @@
#define CPUSUBFAMILY_ARM_HC_HD 5
#endif
// For alternative way to get CPU frequency on macOS and *BSD
#ifdef __APPLE__
#define CPUFREQUENCY_SYSCTL "hw.cpufrequency_max"
#else
// For FreeBSD, not sure about other *BSD
#define CPUFREQUENCY_SYSCTL "dev.cpu.0.freq"
#endif
uint32_t get_sys_info_by_name(char* name);
#endif

246
src/arm/uarch.c
View File

@@ -10,6 +10,7 @@
// Data not available
#define NA -1
typedef uint32_t MICROARCH;
typedef uint32_t ISA;
struct uarch {
@@ -33,9 +34,85 @@ enum {
ISA_ARMv8_3_A,
ISA_ARMv8_4_A,
ISA_ARMv8_5_A,
ISA_ARMv8_6_A,
ISA_ARMv9_A,
ISA_ARMv9_2_A
ISA_ARMv9_A
};
enum {
UARCH_UNKNOWN,
// ARM
UARCH_ARM7,
UARCH_ARM9,
UARCH_ARM1136,
UARCH_ARM1156,
UARCH_ARM1176,
UARCH_ARM11MPCORE,
UARCH_CORTEX_A5,
UARCH_CORTEX_A7,
UARCH_CORTEX_A8,
UARCH_CORTEX_A9,
UARCH_CORTEX_A12,
UARCH_CORTEX_A15,
UARCH_CORTEX_A17,
UARCH_CORTEX_A32,
UARCH_CORTEX_A35,
UARCH_CORTEX_A53,
UARCH_CORTEX_A55r0, // ARM Cortex-A55 revision 0 (restricted dual-issue capabilities compared to revision 1+).
UARCH_CORTEX_A55,
UARCH_CORTEX_A57,
UARCH_CORTEX_A65,
UARCH_CORTEX_A72,
UARCH_CORTEX_A73,
UARCH_CORTEX_A75,
UARCH_CORTEX_A76,
UARCH_CORTEX_A77,
UARCH_CORTEX_A78,
UARCH_CORTEX_A510,
UARCH_CORTEX_A710,
UARCH_CORTEX_X1,
UARCH_CORTEX_X2,
UARCH_NEOVERSE_N1,
UARCH_NEOVERSE_E1,
UARCH_SCORPION,
UARCH_KRAIT,
UARCH_KYRO,
UARCH_FALKOR,
UARCH_SAPHIRA,
UARCH_DENVER,
UARCH_DENVER2,
UARCH_CARMEL,
// SAMSUNG
UARCH_EXYNOS_M1, // Samsung Exynos M1 (Exynos 8890 big cores)
UARCH_EXYNOS_M2, // Samsung Exynos M2 (Exynos 8895 big cores)
UARCH_EXYNOS_M3, // Samsung Exynos M3 (Exynos 9810 big cores)
UARCH_EXYNOS_M4, // Samsung Exynos M4 (Exynos 9820 big cores)
UARCH_EXYNOS_M5, // Samsung Exynos M5 (Exynos 9830 big cores)
// APPLE
UARCH_SWIFT, // Apple A6 and A6X processors.
UARCH_CYCLONE, // Apple A7 processor.
UARCH_TYPHOON, // Apple A8 and A8X processor
UARCH_TWISTER, // Apple A9 and A9X processor.
UARCH_HURRICANE, // Apple A10 and A10X processor.
UARCH_MONSOON, // Apple A11 processor (big cores).
UARCH_MISTRAL, // Apple A11 processor (little cores).
UARCH_VORTEX, // Apple A12 processor (big cores).
UARCH_TEMPEST, // Apple A12 processor (big cores).
UARCH_LIGHTNING, // Apple A13 processor (big cores).
UARCH_THUNDER, // Apple A13 processor (little cores).
UARCH_ICESTORM, // Apple M1 processor (little cores).
UARCH_FIRESTORM, // Apple M1 processor (big cores).
UARCH_BLIZZARD, // Apple M2 processor (little cores).
UARCH_AVALANCHE, // Apple M2 processor (big cores).
// CAVIUM
UARCH_THUNDERX, // Cavium ThunderX
UARCH_THUNDERX2, // Cavium ThunderX2 (originally Broadcom Vulkan).
// MARVELL
UARCH_PJ4,
UARCH_BRAHMA_B15,
UARCH_BRAHMA_B53,
UARCH_XGENE, // Applied Micro X-Gene.
UARCH_TAISHAN_V110, // HiSilicon TaiShan v110 (Huawei Kunpeng 920 series processors).
// PHYTIUM
UARCH_XIAOMI, // Not to be confused with Xiaomi Inc
};
static const ISA isas_uarch[] = {
@@ -63,33 +140,17 @@ static const ISA isas_uarch[] = {
[UARCH_CORTEX_A76] = ISA_ARMv8_2_A,
[UARCH_CORTEX_A77] = ISA_ARMv8_2_A,
[UARCH_CORTEX_A78] = ISA_ARMv8_2_A,
[UARCH_CORTEX_A78C] = ISA_ARMv8_2_A,
[UARCH_CORTEX_A78AE] = ISA_ARMv8_2_A,
[UARCH_CORTEX_A510] = ISA_ARMv9_A,
[UARCH_CORTEX_A520] = ISA_ARMv9_2_A,
[UARCH_CORTEX_A710] = ISA_ARMv9_A,
[UARCH_CORTEX_A715] = ISA_ARMv9_A,
[UARCH_CORTEX_A720] = ISA_ARMv9_2_A,
[UARCH_CORTEX_A725] = ISA_ARMv9_2_A,
[UARCH_CORTEX_X1] = ISA_ARMv8_2_A,
[UARCH_CORTEX_X1C] = ISA_ARMv8_2_A, // Assuming same as X1
[UARCH_CORTEX_X2] = ISA_ARMv9_A,
[UARCH_CORTEX_X3] = ISA_ARMv9_A,
[UARCH_CORTEX_X4] = ISA_ARMv9_2_A,
[UARCH_CORTEX_X925] = ISA_ARMv9_2_A,
[UARCH_NEOVERSE_N1] = ISA_ARMv8_2_A,
[UARCH_NEOVERSE_N2] = ISA_ARMv9_A,
[UARCH_NEOVERSE_E1] = ISA_ARMv8_2_A,
[UARCH_NEOVERSE_V1] = ISA_ARMv8_4_A,
[UARCH_NEOVERSE_V2] = ISA_ARMv9_A,
[UARCH_NEOVERSE_V3] = ISA_ARMv9_2_A,
[UARCH_BRAHMA_B15] = ISA_ARMv7_A, // Same as Cortex-A15
[UARCH_BRAHMA_B53] = ISA_ARMv8_A, // Same as Cortex-A53
[UARCH_THUNDERX] = ISA_ARMv8_A,
[UARCH_THUNDERX2] = ISA_ARMv8_1_A,
[UARCH_TAISHAN_V110] = ISA_ARMv8_2_A,
[UARCH_TAISHAN_V120] = ISA_ARMv8_2_A, // Not confirmed
[UARCH_TAISHAN_V200] = ISA_ARMv8_2_A, // Not confirmed
[UARCH_DENVER] = ISA_ARMv8_A,
[UARCH_DENVER2] = ISA_ARMv8_A,
[UARCH_CARMEL] = ISA_ARMv8_A,
@@ -106,10 +167,8 @@ static const ISA isas_uarch[] = {
[UARCH_EXYNOS_M5] = ISA_ARMv8_2_A,
[UARCH_ICESTORM] = ISA_ARMv8_5_A, // https://github.com/llvm/llvm-project/blob/main/llvm/include/llvm/Support/AArch64TargetParser.def
[UARCH_FIRESTORM] = ISA_ARMv8_5_A,
[UARCH_BLIZZARD] = ISA_ARMv8_6_A, // https://github.com/llvm/llvm-project/blob/main/llvm/unittests/TargetParser/TargetParserTest.cpp
[UARCH_AVALANCHE] = ISA_ARMv8_6_A, // https://github.com/llvm/llvm-project/blob/main/llvm/unittests/TargetParser/TargetParserTest.cpp
[UARCH_SAWTOOTH] = ISA_ARMv8_6_A, // https://github.com/llvm/llvm-project/blob/main/llvm/unittests/TargetParser/TargetParserTest.cpp
[UARCH_EVEREST] = ISA_ARMv8_6_A, // https://github.com/llvm/llvm-project/blob/main/llvm/unittests/TargetParser/TargetParserTest.cpp
[UARCH_BLIZZARD] = ISA_ARMv8_5_A, // Not confirmed
[UARCH_AVALANCHE] = ISA_ARMv8_5_A,
[UARCH_PJ4] = ISA_ARMv7_A,
[UARCH_XIAOMI] = ISA_ARMv8_A,
};
@@ -127,16 +186,13 @@ static char* isas_string[] = {
[ISA_ARMv8_3_A] = "ARMv8.3",
[ISA_ARMv8_4_A] = "ARMv8.4",
[ISA_ARMv8_5_A] = "ARMv8.5",
[ISA_ARMv8_6_A] = "ARMv8.6",
[ISA_ARMv9_A] = "ARMv9",
[ISA_ARMv9_2_A] = "ARMv9.2",
[ISA_ARMv9_A] = "ARMv9"
};
#define UARCH_START if (false) {}
#define CHECK_UARCH(arch, cpu, im_, p_, v_, r_, str, uarch, vendor) \
else if (im_ == im && p_ == p && (v_ == NA || v_ == v) && (r_ == NA || r_ == r)) fill_uarch(arch, cpu, str, uarch, vendor);
#define UARCH_END else { printBugCheckRelease("Unknown microarchitecture detected: IM=0x%X P=0x%X V=0x%X R=0x%X", im, p, v, r); \
fill_uarch(arch, cpu, "Unknown", UARCH_UNKNOWN, CPU_VENDOR_UNKNOWN); }
#define UARCH_END else { printBug("Unknown microarchitecture detected: IM=0x%.8X P=0x%.8X V=0x%.8X R=0x%.8X", im, p, v, r); fill_uarch(arch, cpu, "Unknown", UARCH_UNKNOWN, CPU_VENDOR_UNKNOWN); }
void fill_uarch(struct uarch* arch, struct cpuInfo* cpu, char* str, MICROARCH u, VENDOR vendor) {
arch->uarch = u;
@@ -152,11 +208,10 @@ void fill_uarch(struct uarch* arch, struct cpuInfo* cpu, char* str, MICROARCH u,
/*
* Codes are based on pytorch/cpuinfo, more precisely:
* - https://github.com/pytorch/cpuinfo/blob/main/src/arm/uarch.c
* - https://github.com/pytorch/cpuinfo/blob/master/src/arm/uarch.c
* Other sources:
* - https://elixir.bootlin.com/linux/latest/source/arch/arm64/include/asm/cputype.h
* - https://elixir.bootlin.com/linux/latest/source/arch/arm/include/asm/cputype.h
* - https://github.com/AsahiLinux/m1n1/blob/main/src/chickens.c
*/
struct uarch* get_uarch_from_midr(uint32_t midr, struct cpuInfo* cpu) {
struct uarch* arch = emalloc(sizeof(struct uarch));
@@ -199,26 +254,12 @@ struct uarch* get_uarch_from_midr(uint32_t midr, struct cpuInfo* cpu) {
CHECK_UARCH(arch, cpu, 'A', 0xD0C, NA, NA, "Neoverse N1", UARCH_NEOVERSE_N1, CPU_VENDOR_ARM)
CHECK_UARCH(arch, cpu, 'A', 0xD0D, NA, NA, "Cortex-A77", UARCH_CORTEX_A77, CPU_VENDOR_ARM)
CHECK_UARCH(arch, cpu, 'A', 0xD0E, NA, NA, "Cortex-A76", UARCH_CORTEX_A76, CPU_VENDOR_ARM)
CHECK_UARCH(arch, cpu, 'A', 0xD40, NA, NA, "Neoverse V1", UARCH_NEOVERSE_V1, CPU_VENDOR_ARM)
CHECK_UARCH(arch, cpu, 'A', 0xD41, NA, NA, "Cortex-A78", UARCH_CORTEX_A78, CPU_VENDOR_ARM)
CHECK_UARCH(arch, cpu, 'A', 0xD42, NA, NA, "Cortex-A78AE", UARCH_CORTEX_A78AE, CPU_VENDOR_ARM)
CHECK_UARCH(arch, cpu, 'A', 0xD44, NA, NA, "Cortex-X1", UARCH_CORTEX_X1, CPU_VENDOR_ARM)
CHECK_UARCH(arch, cpu, 'A', 0xD46, NA, NA, "Cortex‑A510", UARCH_CORTEX_A510, CPU_VENDOR_ARM)
CHECK_UARCH(arch, cpu, 'A', 0xD47, NA, NA, "Cortex‑A710", UARCH_CORTEX_A710, CPU_VENDOR_ARM)
CHECK_UARCH(arch, cpu, 'A', 0xD48, NA, NA, "Cortex-X2", UARCH_CORTEX_X2, CPU_VENDOR_ARM)
CHECK_UARCH(arch, cpu, 'A', 0xD49, NA, NA, "Neoverse N2", UARCH_NEOVERSE_N2, CPU_VENDOR_ARM)
CHECK_UARCH(arch, cpu, 'A', 0xD4A, NA, NA, "Neoverse E1", UARCH_NEOVERSE_E1, CPU_VENDOR_ARM)
CHECK_UARCH(arch, cpu, 'A', 0xD4B, NA, NA, "Cortex-A78C", UARCH_CORTEX_A78C, CPU_VENDOR_ARM)
CHECK_UARCH(arch, cpu, 'A', 0xD4C, NA, NA, "Cortex-X1C", UARCH_CORTEX_X1C, CPU_VENDOR_ARM)
CHECK_UARCH(arch, cpu, 'A', 0xD4D, NA, NA, "Cortex-A715", UARCH_CORTEX_A715, CPU_VENDOR_ARM)
CHECK_UARCH(arch, cpu, 'A', 0xD4E, NA, NA, "Cortex-X3", UARCH_CORTEX_X3, CPU_VENDOR_ARM)
CHECK_UARCH(arch, cpu, 'A', 0xD4F, NA, NA, "Neoverse V2", UARCH_NEOVERSE_V2, CPU_VENDOR_ARM)
CHECK_UARCH(arch, cpu, 'A', 0xD80, NA, NA, "Cortex-A520", UARCH_CORTEX_A520, CPU_VENDOR_ARM)
CHECK_UARCH(arch, cpu, 'A', 0xD81, NA, NA, "Cortex-A720", UARCH_CORTEX_A720, CPU_VENDOR_ARM)
CHECK_UARCH(arch, cpu, 'A', 0xD82, NA, NA, "Cortex-X4", UARCH_CORTEX_X4, CPU_VENDOR_ARM)
CHECK_UARCH(arch, cpu, 'A', 0xD84, NA, NA, "Neoverse V3", UARCH_NEOVERSE_V3, CPU_VENDOR_ARM)
CHECK_UARCH(arch, cpu, 'A', 0xD85, NA, NA, "Cortex-X925", UARCH_CORTEX_X925, CPU_VENDOR_ARM)
CHECK_UARCH(arch, cpu, 'A', 0xD87, NA, NA, "Cortex-A725", UARCH_CORTEX_A725, CPU_VENDOR_ARM)
CHECK_UARCH(arch, cpu, 'B', 0x00F, NA, NA, "Brahma B15", UARCH_BRAHMA_B15, CPU_VENDOR_BROADCOM)
CHECK_UARCH(arch, cpu, 'B', 0x100, NA, NA, "Brahma B53", UARCH_BRAHMA_B53, CPU_VENDOR_BROADCOM)
@@ -230,11 +271,8 @@ struct uarch* get_uarch_from_midr(uint32_t midr, struct cpuInfo* cpu) {
CHECK_UARCH(arch, cpu, 'C', 0x0A3, NA, NA, "ThunderX 81XX", UARCH_THUNDERX, CPU_VENDOR_CAVIUM)
CHECK_UARCH(arch, cpu, 'C', 0x0AF, NA, NA, "ThunderX2 99XX", UARCH_THUNDERX2, CPU_VENDOR_CAVIUM)
CHECK_UARCH(arch, cpu, 'H', 0xD01, NA, NA, "TaiShan v110", UARCH_TAISHAN_V110, CPU_VENDOR_HUAWEI) // Kunpeng 920 series
CHECK_UARCH(arch, cpu, 'H', 0xD02, 2, 2, "TaiShan v120", UARCH_TAISHAN_V120, CPU_VENDOR_HUAWEI) // Kiring 9000S Big cores (https://github.com/Dr-Noob/cpufetch/issues/259)
CHECK_UARCH(arch, cpu, 'H', 0xD02, NA, NA, "TaiShan v200", UARCH_TAISHAN_V200, CPU_VENDOR_HUAWEI) // Kunpeng 930 series (found in openeuler: https://mailweb.openeuler.org/hyperkitty/list/kernel@openeuler.org/message/XQCV7NX2UKRIUWUFKRF4PO3QENCOUFR3)
CHECK_UARCH(arch, cpu, 'H', 0xD40, NA, NA, "Cortex-A76", UARCH_CORTEX_A76, CPU_VENDOR_ARM) // Kirin 980 Big/Medium cores -> Cortex-A76
CHECK_UARCH(arch, cpu, 'H', 0xD42, NA, NA, "TaiShan v120", UARCH_TAISHAN_V120, CPU_VENDOR_HUAWEI) // Kiring 9000S Small Cores (https://github.com/Dr-Noob/cpufetch/issues/259)
CHECK_UARCH(arch, cpu, 'H', 0xD01, NA, NA, "TaiShan v110", UARCH_TAISHAN_V110, CPU_VENDOR_HUAWUEI) // Kunpeng 920 series
CHECK_UARCH(arch, cpu, 'H', 0xD40, NA, NA, "Cortex-A76", UARCH_CORTEX_A76, CPU_VENDOR_ARM) // Kirin 980 Big/Medium cores -> Cortex-A76
CHECK_UARCH(arch, cpu, 'N', 0x000, NA, NA, "Denver", UARCH_DENVER, CPU_VENDOR_NVIDIA)
CHECK_UARCH(arch, cpu, 'N', 0x003, NA, NA, "Denver2", UARCH_DENVER2, CPU_VENDOR_NVIDIA)
@@ -276,12 +314,8 @@ struct uarch* get_uarch_from_midr(uint32_t midr, struct cpuInfo* cpu) {
CHECK_UARCH(arch, cpu, 'a', 0x022, NA, NA, "Icestorm", UARCH_ICESTORM, CPU_VENDOR_APPLE)
CHECK_UARCH(arch, cpu, 'a', 0x023, NA, NA, "Firestorm", UARCH_FIRESTORM, CPU_VENDOR_APPLE)
CHECK_UARCH(arch, cpu, 'a', 0x024, NA, NA, "Icestorm", UARCH_ICESTORM, CPU_VENDOR_APPLE) // https://github.com/Dr-Noob/cpufetch/issues/263
CHECK_UARCH(arch, cpu, 'a', 0x025, NA, NA, "Firestorm", UARCH_FIRESTORM, CPU_VENDOR_APPLE) // https://github.com/Dr-Noob/cpufetch/issues/263
CHECK_UARCH(arch, cpu, 'a', 0x030, NA, NA, "Blizzard", UARCH_BLIZZARD, CPU_VENDOR_APPLE)
CHECK_UARCH(arch, cpu, 'a', 0x031, NA, NA, "Avalanche", UARCH_AVALANCHE, CPU_VENDOR_APPLE)
CHECK_UARCH(arch, cpu, 'a', 0x048, NA, NA, "Sawtooth", UARCH_SAWTOOTH, CPU_VENDOR_APPLE)
CHECK_UARCH(arch, cpu, 'a', 0x049, NA, NA, "Everest", UARCH_EVEREST, CPU_VENDOR_APPLE)
CHECK_UARCH(arch, cpu, 'V', 0x581, NA, NA, "PJ4", UARCH_PJ4, CPU_VENDOR_MARVELL)
CHECK_UARCH(arch, cpu, 'V', 0x584, NA, NA, "PJ4B-MP", UARCH_PJ4, CPU_VENDOR_MARVELL)
@@ -291,113 +325,15 @@ struct uarch* get_uarch_from_midr(uint32_t midr, struct cpuInfo* cpu) {
return arch;
}
bool is_ARMv8_or_newer(struct cpuInfo* cpu) {
return cpu->arch->isa >= ISA_ARMv8_A;
}
bool has_fma_support(struct cpuInfo* cpu) {
// Arm A64 Instruction Set Architecture
// https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions
return is_ARMv8_or_newer(cpu);
}
int get_vpus_width(struct cpuInfo* cpu) {
// If the CPU has NEON, width can be 64 or 128 [1].
// In >= ARMv8, NEON are 128 bits width [2]
// If the CPU has SVE/SVE2, width can be between 128-2048 [3],
// so we get the exact value from cntb [4]
//
// [1] https://en.wikipedia.org/wiki/ARM_architecture_family#Advanced_SIMD_(Neon)
// [2] https://developer.arm.com/documentation/102474/0100/Fundamentals-of-Armv8-Neon-technology
// [3] https://www.anandtech.com/show/16640/arm-announces-neoverse-v1-n2-platforms-cpus-cmn700-mesh/5
// [4] https://developer.arm.com/documentation/ddi0596/2020-12/SVE-Instructions/CNTB--CNTD--CNTH--CNTW--Set-scalar-to-multiple-of-predicate-constraint-element-count-
if (cpu->feat->SVE && cpu->feat->cntb > 0) {
return cpu->feat->cntb * 8;
}
else if (cpu->feat->NEON) {
if(is_ARMv8_or_newer(cpu)) {
return 128;
}
else {
return 64;
}
}
else {
return 32;
}
}
int get_number_of_vpus(struct cpuInfo* cpu) {
MICROARCH ua = cpu->arch->uarch;
switch(ua) {
case UARCH_CORTEX_X925: // [https://www.anandtech.com/show/21399/arm-unveils-2024-cpu-core-designs-cortex-x925-a725-and-a520-arm-v9-2-redefined-for-3nm-/2]
return 6;
case UARCH_EVEREST: // Just a guess, needs confirmation.
case UARCH_FIRESTORM: // [https://dougallj.github.io/applecpu/firestorm-simd.html]
case UARCH_AVALANCHE: // [https://en.wikipedia.org/wiki/Comparison_of_ARM_processors]
case UARCH_CORTEX_X1: // [https://www.anandtech.com/show/15813/arm-cortex-a78-cortex-x1-cpu-ip-diverging/3]
case UARCH_CORTEX_X1C: // Assuming same as X1
case UARCH_CORTEX_X2: // [https://www.anandtech.com/show/16693/arm-announces-mobile-armv9-cpu-microarchitectures-cortexx2-cortexa710-cortexa510/2]
case UARCH_CORTEX_X3: // [https://www.hwcooling.net/en/cortex-x3-the-new-fastest-arm-core-architecture-analysis: "The FPU and SIMD unit of the core still has four pipelines"]
case UARCH_CORTEX_X4: // [https://www.anandtech.com/show/18871/arm-unveils-armv92-mobile-architecture-cortex-x4-a720-and-a520-64bit-exclusive/2]: "Cortex-X4: Out-of-Order Core"
case UARCH_NEOVERSE_V1: // [https://en.wikichip.org/wiki/arm_holdings/microarchitectures/neoverse_v1]
case UARCH_NEOVERSE_V2: // [https://chipsandcheese.com/2023/09/11/hot-chips-2023-arms-neoverse-v2/]
case UARCH_NEOVERSE_V3: // Assuming same as V2
return 4;
case UARCH_SAWTOOTH: // Needs confirmation, rn this is the best we know: https://mastodon.social/@dougall/111118317031041336
case UARCH_EXYNOS_M3: // [https://www.anandtech.com/show/12361/samsung-exynos-m3-architecture]
case UARCH_EXYNOS_M4: // [https://en.wikichip.org/wiki/samsung/microarchitectures/m4#Block_Diagram]
case UARCH_EXYNOS_M5: // [https://en.wikichip.org/wiki/samsung/microarchitectures/m5]
return 3;
case UARCH_ICESTORM: // [https://dougallj.github.io/applecpu/icestorm-simd.html]
case UARCH_BLIZZARD: // [https://en.wikipedia.org/wiki/Comparison_of_ARM_processors]
case UARCH_TAISHAN_V110:// [https://www-file.huawei.com/-/media/corp2020/pdf/publications/huawei-research/2022/huawei-research-issue1-en.pdf]: "128-bit x 2 for single precision"
case UARCH_TAISHAN_V120:// Not confirmed, asssuming same as v110
case UARCH_TAISHAN_V200:// Not confirmed, asssuming same as v110
case UARCH_CORTEX_A57: // [https://www.anandtech.com/show/8718/the-samsung-galaxy-note-4-exynos-review/5]
case UARCH_CORTEX_A72: // [https://www.anandtech.com/show/10347/arm-cortex-a73-artemis-unveiled/2]
case UARCH_CORTEX_A73: // [https://www.anandtech.com/show/10347/arm-cortex-a73-artemis-unveiled/2]
case UARCH_CORTEX_A75: // [https://www.anandtech.com/show/11441/dynamiq-and-arms-new-cpus-cortex-a75-a55/3]
case UARCH_CORTEX_A76: // [https://www.anandtech.com/show/12785/arm-cortex-a76-cpu-unveiled-7nm-powerhouse/3]
case UARCH_CORTEX_A77: // [https://fuse.wikichip.org/news/2339/arm-unveils-cortex-a77-emphasizes-single-thread-performance]
case UARCH_CORTEX_A78: // [https://fuse.wikichip.org/news/3536/arm-unveils-the-cortex-a78-when-less-is-more]
case UARCH_CORTEX_A78C: // Assuming same as A78
case UARCH_CORTEX_A78AE:// Assuming same as A78
case UARCH_EXYNOS_M1: // [https://www.anandtech.com/show/12361/samsung-exynos-m3-architecture]
case UARCH_EXYNOS_M2: // [https://www.anandtech.com/show/12361/samsung-exynos-m3-architecture]
case UARCH_NEOVERSE_N1: // [https://en.wikichip.org/wiki/arm_holdings/microarchitectures/neoverse_n1#Individual_Core]
case UARCH_NEOVERSE_N2: // [https://chipsandcheese.com/2023/08/18/arms-neoverse-n2-cortex-a710-for-servers/]
case UARCH_CORTEX_A710: // [https://chipsandcheese.com/2023/08/11/arms-cortex-a710-winning-by-default/]: Fig in Core Overview. Table in Instruction Scheduling and Execution
case UARCH_CORTEX_A715: // [https://www.hwcooling.net/en/arm-introduces-new-cortex-a715-core-architecture-analysis/]: "the numbers of ALU and FPU execution units themselves >
case UARCH_CORTEX_A720: // Assuming same as A715: https://www.anandtech.com/show/18871/arm-unveils-armv92-mobile-architecture-cortex-x4-a720-and-a520-64bit-exclusive/3
case UARCH_CORTEX_A725: // Assuming same as A720
return 2;
case UARCH_NEOVERSE_E1: // [https://www.anandtech.com/show/13959/arm-announces-neoverse-n1-platform/5]
// A510 is integrated as part of a Complex. Normally, each complex would incorporate two Cortex-A510 cores.
// Each complex incorporates a single VPU with 2 ports, so for each A510 there is theoretically 1 port.
case UARCH_CORTEX_A510: // [https://en.wikichip.org/wiki/arm_holdings/microarchitectures/cortex-a510#Vector_Processing_Unit_.28VPU.29]
case UARCH_CORTEX_A520: // Assuming same as A50: https://www.anandtech.com/show/18871/arm-unveils-armv92-mobile-architecture-cortex-x4-a720-and-a520-64bit-exclusive/4
return 1;
default:
// ARMv6
// ARMv7
// Remaining UARCH_CORTEX_AXX
// Old Snapdragon (e.g., Scorpion, Krait, etc)
return 1;
}
}
char* get_str_uarch(struct cpuInfo* cpu) {
return cpu->arch->uarch_str;
}
MICROARCH get_uarch(struct uarch* arch) {
return arch->uarch;
}
void free_uarch_struct(struct uarch* arch) {
free(arch->uarch_str);
free(arch);
}
bool is_cortex_x2(struct uarch* arch) {
return arch->uarch == UARCH_CORTEX_X2;
}

104
src/arm/uarch.h
View File

@@ -5,111 +5,9 @@
#include "midr.h"
enum {
UARCH_UNKNOWN,
// ARM
UARCH_ARM7,
UARCH_ARM9,
UARCH_ARM1136,
UARCH_ARM1156,
UARCH_ARM1176,
UARCH_ARM11MPCORE,
UARCH_CORTEX_A5,
UARCH_CORTEX_A7,
UARCH_CORTEX_A8,
UARCH_CORTEX_A9,
UARCH_CORTEX_A12,
UARCH_CORTEX_A15,
UARCH_CORTEX_A17,
UARCH_CORTEX_A32,
UARCH_CORTEX_A35,
UARCH_CORTEX_A53,
UARCH_CORTEX_A55r0, // ARM Cortex-A55 revision 0 (restricted dual-issue capabilities compared to revision 1+).
UARCH_CORTEX_A55,
UARCH_CORTEX_A57,
UARCH_CORTEX_A65,
UARCH_CORTEX_A72,
UARCH_CORTEX_A73,
UARCH_CORTEX_A75,
UARCH_CORTEX_A76,
UARCH_CORTEX_A77,
UARCH_CORTEX_A78,
UARCH_CORTEX_A78AE,
UARCH_CORTEX_A78C,
UARCH_CORTEX_A510,
UARCH_CORTEX_A520,
UARCH_CORTEX_A710,
UARCH_CORTEX_A715,
UARCH_CORTEX_A720,
UARCH_CORTEX_A725,
UARCH_CORTEX_X1,
UARCH_CORTEX_X1C,
UARCH_CORTEX_X2,
UARCH_CORTEX_X3,
UARCH_CORTEX_X4,
UARCH_CORTEX_X925,
UARCH_NEOVERSE_N1,
UARCH_NEOVERSE_N2,
UARCH_NEOVERSE_E1,
UARCH_NEOVERSE_V1,
UARCH_NEOVERSE_V2,
UARCH_NEOVERSE_V3,
UARCH_SCORPION,
UARCH_KRAIT,
UARCH_KYRO,
UARCH_FALKOR,
UARCH_SAPHIRA,
UARCH_DENVER,
UARCH_DENVER2,
UARCH_CARMEL,
// SAMSUNG
UARCH_EXYNOS_M1, // Samsung Exynos M1 (Exynos 8890 big cores)
UARCH_EXYNOS_M2, // Samsung Exynos M2 (Exynos 8895 big cores)
UARCH_EXYNOS_M3, // Samsung Exynos M3 (Exynos 9810 big cores)
UARCH_EXYNOS_M4, // Samsung Exynos M4 (Exynos 9820 big cores)
UARCH_EXYNOS_M5, // Samsung Exynos M5 (Exynos 9830 big cores)
// APPLE
UARCH_SWIFT, // Apple A6 and A6X processors.
UARCH_CYCLONE, // Apple A7 processor.
UARCH_TYPHOON, // Apple A8 and A8X processor
UARCH_TWISTER, // Apple A9 and A9X processor.
UARCH_HURRICANE, // Apple A10 and A10X processor.
UARCH_MONSOON, // Apple A11 processor (big cores).
UARCH_MISTRAL, // Apple A11 processor (little cores).
UARCH_VORTEX, // Apple A12 processor (big cores).
UARCH_TEMPEST, // Apple A12 processor (big cores).
UARCH_LIGHTNING, // Apple A13 processor (big cores).
UARCH_THUNDER, // Apple A13 processor (little cores).
UARCH_ICESTORM, // Apple M1 processor (little cores).
UARCH_FIRESTORM, // Apple M1 processor (big cores).
UARCH_BLIZZARD, // Apple M2 processor (little cores).
UARCH_AVALANCHE, // Apple M2 processor (big cores).
UARCH_SAWTOOTH, // Apple M3 processor (little cores).
UARCH_EVEREST, // Apple M3 processor (big cores).
// CAVIUM
UARCH_THUNDERX, // Cavium ThunderX
UARCH_THUNDERX2, // Cavium ThunderX2 (originally Broadcom Vulkan).
// MARVELL
UARCH_PJ4,
UARCH_BRAHMA_B15,
UARCH_BRAHMA_B53,
UARCH_XGENE, // Applied Micro X-Gene.
// HUAWEI
UARCH_TAISHAN_V110, // HiSilicon TaiShan v110
UARCH_TAISHAN_V120, // HiSilicon TaiShan v120
UARCH_TAISHAN_V200, // HiSilicon TaiShan v200
// PHYTIUM
UARCH_XIAOMI, // Not to be confused with Xiaomi Inc
};
typedef uint32_t MICROARCH;
struct uarch* get_uarch_from_midr(uint32_t midr, struct cpuInfo* cpu);
int get_number_of_vpus(struct cpuInfo* cpu);
int get_vpus_width(struct cpuInfo* cpu);
bool has_fma_support(struct cpuInfo* cpu);
char* get_str_uarch(struct cpuInfo* cpu);
void free_uarch_struct(struct uarch* arch);
MICROARCH get_uarch(struct uarch* arch);
bool is_cortex_x2(struct uarch* arch);
#endif

29
src/arm/udev.c
View File

@@ -3,6 +3,8 @@
#include "midr.h"
#define _PATH_DEVICETREE_MODEL "/sys/firmware/devicetree/base/model"
#define _PATH_CPUINFO "/proc/cpuinfo"
//#define _PATH_CPUINFO "cpuinfo_debug"
#define CPUINFO_CPU_IMPLEMENTER_STR "CPU implementer\t: "
#define CPUINFO_CPU_ARCHITECTURE_STR "CPU architecture: "
@@ -106,15 +108,36 @@ uint32_t get_midr_from_cpuinfo(uint32_t core, bool* success) {
return midr;
}
char* get_hardware_from_cpuinfo(void) {
char* get_field_from_cpuinfo(char* CPUINFO_FIELD) {
int filelen;
char* buf;
if((buf = read_file(_PATH_CPUINFO, &filelen)) == NULL) {
printWarn("read_file: %s: %s:\n", _PATH_CPUINFO, strerror(errno));
return NULL;
}
char* tmp1 = strstr(buf, CPUINFO_FIELD);
if(tmp1 == NULL) return NULL;
tmp1 = tmp1 + strlen(CPUINFO_FIELD);
char* tmp2 = strstr(tmp1, "\n");
int strlen = (1 + (tmp2-tmp1));
char* hardware = emalloc(sizeof(char) * strlen);
memset(hardware, 0, sizeof(char) * strlen);
strncpy(hardware, tmp1, tmp2-tmp1);
return hardware;
}
char* get_hardware_from_cpuinfo() {
return get_field_from_cpuinfo(CPUINFO_HARDWARE_STR);
}
char* get_revision_from_cpuinfo(void) {
char* get_revision_from_cpuinfo() {
return get_field_from_cpuinfo(CPUINFO_REVISION_STR);
}
bool is_raspberry_pi(void) {
bool is_raspberry_pi() {
int filelen;
char* buf;
if((buf = read_file(_PATH_DEVICETREE_MODEL, &filelen)) == NULL) {

12
src/arm/udev.h
View File

@@ -3,16 +3,12 @@
#include "../common/udev.h"
#define _PATH_SUNXI_NVMEM "/sys/bus/nvmem/devices/sunxi-sid0/nvmem"
#define _PATH_RK_EFUSE0 "/sys/bus/nvmem/devices/rockchip-efuse0/nvmem"
#define _PATH_RK_OTP0 "/sys/bus/nvmem/devices/rockchip-otp0/nvmem"
#define UNKNOWN -1
int get_ncores_from_cpuinfo(void);
int get_ncores_from_cpuinfo();
uint32_t get_midr_from_cpuinfo(uint32_t core, bool* success);
char* get_hardware_from_cpuinfo(void);
char* get_revision_from_cpuinfo(void);
bool is_raspberry_pi(void);
char* get_hardware_from_cpuinfo();
char* get_revision_from_cpuinfo();
bool is_raspberry_pi();
#endif

140
src/common/args.c
View File

@@ -12,8 +12,6 @@
#define COLOR_STR_AMD "amd"
#define COLOR_STR_IBM "ibm"
#define COLOR_STR_ARM "arm"
#define COLOR_STR_ROCKCHIP "rockchip"
#define COLOR_STR_SIFIVE "sifive"
static const char *SYTLES_STR_LIST[] = {
[STYLE_EMPTY] = NULL,
@@ -28,7 +26,6 @@ struct args_struct {
bool help_flag;
bool raw_flag;
bool accurate_pp;
bool measure_max_frequency_flag;
bool full_cpu_name_flag;
bool logo_long;
bool logo_short;
@@ -41,98 +38,92 @@ struct args_struct {
};
const char args_chr[] = {
/* [ARG_STYLE] = */ 's',
/* [ARG_COLOR] = */ 'c',
/* [ARG_HELP] = */ 'h',
/* [ARG_RAW] = */ 'r',
/* [ARG_FULLCPUNAME] = */ 'F',
/* [ARG_LOGO_LONG] = */ 1,
/* [ARG_LOGO_SHORT] = */ 2,
/* [ARG_LOGO_INTEL_NEW] = */ 3,
/* [ARG_LOGO_INTEL_OLD] = */ 4,
/* [ARG_ACCURATE_PP] = */ 5,
/* [ARG_MEASURE_MAX_FREQ] = */ 6,
/* [ARG_DEBUG] = */ 'd',
/* [ARG_VERBOSE] = */ 'v',
/* [ARG_VERSION] = */ 'V',
/* [ARG_STYLE] = */ 's',
/* [ARG_COLOR] = */ 'c',
/* [ARG_HELP] = */ 'h',
/* [ARG_RAW] = */ 'r',
/* [ARG_FULLCPUNAME] = */ 'F',
/* [ARG_LOGO_LONG] = */ 1,
/* [ARG_LOGO_SHORT] = */ 2,
/* [ARG_LOGO_INTEL_NEW] = */ 3,
/* [ARG_LOGO_INTEL_OLD] = */ 4,
/* [ARG_ACCURATE_PP] = */ 5,
/* [ARG_DEBUG] = */ 'd',
/* [ARG_VERBOSE] = */ 'v',
/* [ARG_VERSION] = */ 'V',
};
const char *args_str[] = {
/* [ARG_STYLE] = */ "style",
/* [ARG_COLOR] = */ "color",
/* [ARG_HELP] = */ "help",
/* [ARG_RAW] = */ "raw",
/* [ARG_FULLCPUNAME] = */ "full-cpu-name",
/* [ARG_LOGO_LONG] = */ "logo-long",
/* [ARG_LOGO_SHORT] = */ "logo-short",
/* [ARG_LOGO_INTEL_NEW] = */ "logo-intel-new",
/* [ARG_LOGO_INTEL_OLD] = */ "logo-intel-old",
/* [ARG_ACCURATE_PP] = */ "accurate-pp",
/* [ARG_MEASURE_MAX_FREQ] = */ "measure-max-freq",
/* [ARG_DEBUG] = */ "debug",
/* [ARG_VERBOSE] = */ "verbose",
/* [ARG_VERSION] = */ "version",
/* [ARG_STYLE] = */ "style",
/* [ARG_COLOR] = */ "color",
/* [ARG_HELP] = */ "help",
/* [ARG_RAW] = */ "raw",
/* [ARG_FULLCPUNAME] = */ "full-cpu-name",
/* [ARG_LOGO_LONG] = */ "logo-long",
/* [ARG_LOGO_SHORT] = */ "logo-short",
/* [ARG_LOGO_INTEL_NEW] = */ "logo-intel-new",
/* [ARG_LOGO_INTEL_OLD] = */ "logo-intel-old",
/* [ARG_ACCURATE_PP] = */ "accurate-pp",
/* [ARG_DEBUG] = */ "debug",
/* [ARG_VERBOSE] = */ "verbose",
/* [ARG_VERSION] = */ "version",
};
static struct args_struct args;
STYLE get_style(void) {
STYLE get_style() {
return args.style;
}
struct color** get_colors(void) {
struct color** get_colors() {
return args.colors;
}
bool show_help(void) {
bool show_help() {
return args.help_flag;
}
bool show_version(void) {
bool show_version() {
return args.version_flag;
}
bool show_debug(void) {
bool show_debug() {
return args.debug_flag;
}
bool show_raw(void) {
bool show_raw() {
return args.raw_flag;
}
bool accurate_pp(void) {
bool accurate_pp() {
return args.accurate_pp;
}
bool measure_max_frequency_flag(void) {
return args.measure_max_frequency_flag;
}
bool show_full_cpu_name(void) {
bool show_full_cpu_name() {
return args.full_cpu_name_flag;
}
bool show_logo_long(void) {
bool show_logo_long() {
return args.logo_long;
}
bool show_logo_short(void) {
bool show_logo_short() {
return args.logo_short;
}
bool show_logo_intel_new(void) {
bool show_logo_intel_new() {
return args.logo_intel_new;
}
bool show_logo_intel_old(void) {
bool show_logo_intel_old() {
return args.logo_intel_old;
}
bool verbose_enabled(void) {
bool verbose_enabled() {
return args.verbose_flag;
}
int max_arg_str_length(void) {
int max_arg_str_length() {
int max_len = -1;
int len = sizeof(args_str) / sizeof(args_str[0]);
for(int i=0; i < len; i++) {
@@ -177,8 +168,6 @@ bool parse_color(char* optarg_str, struct color*** cs) {
else if(strcmp(optarg_str, COLOR_STR_AMD) == 0) color_to_copy = COLOR_DEFAULT_AMD;
else if(strcmp(optarg_str, COLOR_STR_IBM) == 0) color_to_copy = COLOR_DEFAULT_IBM;
else if(strcmp(optarg_str, COLOR_STR_ARM) == 0) color_to_copy = COLOR_DEFAULT_ARM;
else if(strcmp(optarg_str, COLOR_STR_ROCKCHIP) == 0) color_to_copy = COLOR_DEFAULT_ROCKCHIP;
else if(strcmp(optarg_str, COLOR_STR_SIFIVE) == 0) color_to_copy = COLOR_DEFAULT_SIFIVE;
else {
str_to_parse = optarg_str;
free_ptr = false;
@@ -222,26 +211,19 @@ bool parse_color(char* optarg_str, struct color*** cs) {
return true;
}
char* build_short_options(void) {
char* build_short_options() {
const char *c = args_chr;
int len = sizeof(args_chr) / sizeof(args_chr[0]);
char* str = (char *) ecalloc(len*2 + 1, sizeof(char));
char* str = (char *) emalloc(sizeof(char) * (len*2 + 1));
memset(str, 0, sizeof(char) * (len*2 + 1));
#ifdef ARCH_X86
sprintf(str, "%c:%c:%c%c%c%c%c%c%c%c%c%c%c%c",
sprintf(str, "%c:%c:%c%c%c%c%c%c%c%c%c%c%c",
c[ARG_STYLE], c[ARG_COLOR], c[ARG_HELP],
c[ARG_RAW], c[ARG_FULLCPUNAME],
c[ARG_LOGO_SHORT], c[ARG_LOGO_LONG],
c[ARG_LOGO_INTEL_NEW], c[ARG_LOGO_INTEL_OLD],
c[ARG_ACCURATE_PP], c[ARG_MEASURE_MAX_FREQ],
c[ARG_DEBUG], c[ARG_VERBOSE],
c[ARG_VERSION]);
#elif ARCH_ARM
sprintf(str, "%c:%c:%c%c%c%c%c%c%c",
c[ARG_STYLE], c[ARG_COLOR], c[ARG_HELP],
c[ARG_LOGO_SHORT], c[ARG_LOGO_LONG],
c[ARG_MEASURE_MAX_FREQ],
c[ARG_DEBUG], c[ARG_VERBOSE],
c[ARG_ACCURATE_PP], c[ARG_DEBUG], c[ARG_VERBOSE],
c[ARG_VERSION]);
#else
sprintf(str, "%c:%c:%c%c%c%c%c%c",
@@ -277,24 +259,21 @@ bool parse_args(int argc, char* argv[]) {
set_log_level(true);
const struct option long_options[] = {
{args_str[ARG_STYLE], required_argument, 0, args_chr[ARG_STYLE] },
{args_str[ARG_COLOR], required_argument, 0, args_chr[ARG_COLOR] },
{args_str[ARG_HELP], no_argument, 0, args_chr[ARG_HELP] },
{args_str[ARG_STYLE], required_argument, 0, args_chr[ARG_STYLE] },
{args_str[ARG_COLOR], required_argument, 0, args_chr[ARG_COLOR] },
{args_str[ARG_HELP], no_argument, 0, args_chr[ARG_HELP] },
#ifdef ARCH_X86
{args_str[ARG_LOGO_INTEL_NEW], no_argument, 0, args_chr[ARG_LOGO_INTEL_NEW] },
{args_str[ARG_LOGO_INTEL_OLD], no_argument, 0, args_chr[ARG_LOGO_INTEL_OLD] },
{args_str[ARG_ACCURATE_PP], no_argument, 0, args_chr[ARG_ACCURATE_PP] },
{args_str[ARG_MEASURE_MAX_FREQ], no_argument, 0, args_chr[ARG_MEASURE_MAX_FREQ] },
{args_str[ARG_FULLCPUNAME], no_argument, 0, args_chr[ARG_FULLCPUNAME] },
{args_str[ARG_RAW], no_argument, 0, args_chr[ARG_RAW] },
#elif ARCH_ARM
{args_str[ARG_MEASURE_MAX_FREQ], no_argument, 0, args_chr[ARG_MEASURE_MAX_FREQ] },
{args_str[ARG_LOGO_INTEL_NEW], no_argument, 0, args_chr[ARG_LOGO_INTEL_NEW] },
{args_str[ARG_LOGO_INTEL_OLD], no_argument, 0, args_chr[ARG_LOGO_INTEL_OLD] },
{args_str[ARG_ACCURATE_PP], no_argument, 0, args_chr[ARG_ACCURATE_PP] },
{args_str[ARG_FULLCPUNAME], no_argument, 0, args_chr[ARG_FULLCPUNAME] },
{args_str[ARG_RAW], no_argument, 0, args_chr[ARG_RAW] },
#endif
{args_str[ARG_LOGO_SHORT], no_argument, 0, args_chr[ARG_LOGO_SHORT] },
{args_str[ARG_LOGO_LONG], no_argument, 0, args_chr[ARG_LOGO_LONG] },
{args_str[ARG_DEBUG], no_argument, 0, args_chr[ARG_DEBUG] },
{args_str[ARG_VERBOSE], no_argument, 0, args_chr[ARG_VERBOSE] },
{args_str[ARG_VERSION], no_argument, 0, args_chr[ARG_VERSION] },
{args_str[ARG_LOGO_SHORT], no_argument, 0, args_chr[ARG_LOGO_SHORT] },
{args_str[ARG_LOGO_LONG], no_argument, 0, args_chr[ARG_LOGO_LONG] },
{args_str[ARG_DEBUG], no_argument, 0, args_chr[ARG_DEBUG] },
{args_str[ARG_VERBOSE], no_argument, 0, args_chr[ARG_VERBOSE] },
{args_str[ARG_VERSION], no_argument, 0, args_chr[ARG_VERSION] },
{0, 0, 0, 0}
};
@@ -330,9 +309,6 @@ bool parse_args(int argc, char* argv[]) {
else if(opt == args_chr[ARG_ACCURATE_PP]) {
args.accurate_pp = true;
}
else if(opt == args_chr[ARG_MEASURE_MAX_FREQ]) {
args.measure_max_frequency_flag = true;
}
else if(opt == args_chr[ARG_FULLCPUNAME]) {
args.full_cpu_name_flag = true;
}

30
src/common/args.h
View File

@@ -29,7 +29,6 @@ enum {
ARG_LOGO_INTEL_NEW,
ARG_LOGO_INTEL_OLD,
ARG_ACCURATE_PP,
ARG_MEASURE_MAX_FREQ,
ARG_DEBUG,
ARG_VERBOSE,
ARG_VERSION
@@ -40,22 +39,21 @@ extern const char *args_str[];
#include "printer.h"
int max_arg_str_length(void);
int max_arg_str_length();
bool parse_args(int argc, char* argv[]);
bool show_help(void);
bool accurate_pp(void);
bool measure_max_frequency_flag(void);
bool show_full_cpu_name(void);
bool show_logo_long(void);
bool show_logo_short(void);
bool show_logo_intel_new(void);
bool show_logo_intel_old(void);
bool show_raw(void);
bool show_debug(void);
bool show_version(void);
bool verbose_enabled(void);
bool show_help();
bool accurate_pp();
bool show_full_cpu_name();
bool show_logo_long();
bool show_logo_short();
bool show_logo_intel_new();
bool show_logo_intel_old();
bool show_raw();
bool show_debug();
bool show_version();
bool verbose_enabled();
void free_colors_struct(struct color** cs);
struct color** get_colors(void);
STYLE get_style(void);
struct color** get_colors();
STYLE get_style();
#endif

357
src/common/ascii.h
View File

@@ -33,7 +33,7 @@ struct ascii_logo {
uint32_t width;
uint32_t height;
bool replace_blocks;
char color_ascii[4][100];
char color_ascii[3][100];
char color_text[2][100];
};
@@ -105,19 +105,6 @@ $C1 MMM :MMM NMM dMMK dMMX MMN \
$C1 MMM :MMM NMM dMMMoo OMM0....:Nx. MMN \
$C1 MMM :WWW XWW lONMM 'xXMMMMNOc MMN "
#define ASCII_HYGON \
"$C1 \
$C1 \
$C1 \
$C1 ## ## ## ## ###### ###### ## # \
$C1 ##....## ## ## ## ## ## #### # \
$C1 ######## ## ## ##. ## ## # #### \
$C1 ## ## ## *######. ###### # ## \
$C1 \
$C1 \
$C1 \
$C1 "
#define ASCII_SNAPD \
" $C1@@$C2######## \
$C1@@@@@$C2########### \
@@ -158,25 +145,6 @@ $C2 Exynos \
$C2 \
$C2 "
#define ASCII_KUNPENG \
"$C2 . \
$C2 .. \
$C2 .## \
$C1 .$CR $C2.###. \
$C1 ..$CR $C2#####. \
$C1 .#.$CR $C2.#######. \
$C1 .####.$CR $C2.#######. \
$C1 ..######*$CR $C2.#######. . \
$C1 .#########*$CR $C2.#######* . \
$C1 ######*$CR $C2.#######. .#. \
$C1*#######*$CR $C2.#######. *##. \
$C1 ##*$CR $C2.#######. ####### \
$C2 ###.$CR $C1#####$C2 *### \
$C1 *########## \
$C1 *######## \
$C1 #####. \
$C1 *###. "
#define ASCII_KIRIN \
"$C1 ####### \
$C1 ##### #################### \
@@ -250,23 +218,6 @@ $C1 kMMMMMMMMMMMMMMMMMMMMMMd \
$C1 'KMMMMMMMWXXWMMMMMMMk. \
$C1 \"cooc\"* \"*coo'\" "
#define ASCII_GOOGLE \
"$C1 aaaaaaaa \
$C1 .MMMMMMMMMMMMMMMM. \
$C1 .MMMMMMMMMMMMMMMMMMMMM* \
$C1 .MMMMMMMM** *MM* \
$C2 MM$C1MMMMM. \
$C2 *MMM$C1MM. \
$C2*MMMMMM $C4lMMMMMMMMMMMMMMM* \
$C2MMMMMMM $C4lMMMMMMMMMMMMMMMM \
$C2*MMMMMM $C4lMMMMMMMMMMMMMMMd \
$C2 MMMM$C3MMM. $C4*MMMMM. \
$C2 MM$C3MMMMMM. $C4.MMMMMM. \
$C3 *MMMMMMMMM*.......MMM$C4MMMMMM* \
$C3 *MMMMMMMMMMMMMMMMMMMM$C4MM* \
$C3 *MMMMMMMMMMMMMM* \
$C3 ****** "
#define ASCII_ALLWINNER \
"$C1 \
$C1 ################# \
@@ -285,186 +236,6 @@ $C1 ##### ##. \
$C1 ###########. \
$C1 "
#define ASCII_ROCKCHIP \
"$C1 \
$C1 $C2## \
$C1 ###### ## ## \
$C1 ##. ### ##### ##### ## .## ##### ######. ## ##### \
$C1 #######. ##. # #. ##### ##. ### ### # .## \
$C1##. ###. ####. #### ### .## #### ### ### #.##### \
$C1 ## \
$C1 "
#define ASCII_RISCV \
"$C1 \
$C1 ************ \
$C1 %%%%%%%%% *********** \
$C1 %%%%%%%%%% ********** \
$C1 %%%%%%%%% ********* \
$C1 % ******** \
$C1 %% .********* % \
$C1 %%%% ******* %%% \
$C1 %%%%%%. **** %%%%% \
$C1 %%%%%%%%. %%%%%%% \
$C1 \
$C1 \
$C1 ########### ## .######### ######### .## ## \
$C1 ## ## ## ## ## ### ### \
$C1 ########### ## ##########. ## #### .## ## \
$C1 ## ### ## ##. ## ### ### \
$C1 ## ### ## ##########. ########## ### \
$C1 "
#define ASCII_SIFIVE \
"$C1 ############################################## \
$C1 ###########@@@@@@@@@@@@@@@@@@@@@@@@########### \
$C1 #########@@@@@@@@@@@@@@@@@@@@@@@@@@@@######### \
$C1 ########@@@@######################@@@@######## \
$C1 #######@@@@########################@@@@####### \
$C1 ######@@@@##########################@@@@###### \
$C1 #####@@@@#######@@@@@@@@@@@@@@@@@@@@@@@@@##### \
$C1 ####@@@@#######@@@@@@@@@@@@@@@@@@@@@@@@@@@#### \
$C1 ###@@@@################################@@@@### \
$C1 ##@@@@##################################@@@@## \
$C1 #@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@#########@@@@# \
$C1 #@@@@@@@@@@@@@@@@@@@@@@@@@@@@@###########@@@@# \
$C1 ##@@@@@@############@@@@@@############@@@@@@## \
$C1 ######@@@@@###########@@###########@@@@@###### \
$C1 #########@@@@@@################@@@@@@######### \
$C1 #############@@@@@##########@@@@@############# \
$C1 ################@@@@@@##@@@@@@################ \
$C1 ####################@@@@@@#################### \
$C1 ############################################## "
#define ASCII_STARFIVE \
"$C1 # \
$C1 ########## \
$C1 ######## ######## \
$C1 ######## #### \
$C1 ####### #### \
$C1 #### ####### \
$C1 #### ##### ####### \
$C1 ####### ######## .## \
$C1 ######## ######## \
$C1 ### ########. ####### \
$C1 ####### ##### #### \
$C1 ######## #. #### \
$C1 # #### ####### \
$C1 ##### ####### \
$C1 ######## ######## \
$C1 ######### \
$C1 # "
#define ASCII_SIPEED \
"$C1 #################################### \
$C1######@@################################ \
$C1####@@##@@####@@@@@@@@@@@@@@@@########## \
$C1######@@####@@@@@@@@@@@@@@@@@@########## \
$C1#########@@@@########################### \
$C1#######@@@@@@########################### \
$C1#########@@@@########################### \
$C1###########@@@@@@@@@@@@@@@############## \
$C1##############@@@@@@@@@@@@@@@########### \
$C1###########################@@@@@######## \
$C1###########################@@@@@@####### \
$C1###########################@@@@@######## \
$C1##########@@@@@@@@@@@@@@@@@@@########### \
$C1##########@@@@@@@@@@@@@@@@############## \
$C1######################################## \
$C1 #################################### "
#define ASCII_NVIDIA \
"$C1 'cccccccccccccccccccccccccc \
$C1 ;oooooooooooooooooooooooool \
$C1 .:::. .oooooooooooooooooool \
$C1 .:cll; ,c:::. cooooooooooooool \
$C1 ,clo' ;. oolc: ooooooooooool \
$C1.cloo ;cclo . .olc. coooooooool \
$C1oooo :lo, ;ll; looc :oooooooool \
$C1 oooc ool. ;oooc;clol :looooooooool \
$C1 :ooc ,ol; ;oooooo. .cloo; loool \
$C1 ool; .olc. ,:lool .lool \
$C1 ool:. ,::::ccloo. :clooool \
$C1 oolc::. ':cclooooooool \
$C1 ;oooooooooooooooooooooooool \
$C1 \
$C1 \
$C2######. ## ## ## ###### ## ### \
$C2## ## ## ## ## ## ## ## #: :# \
$C2## ## ## ## ## ## ## ## ####### \
$C2## ## ### ## ###### ## ## ## "
#define ASCII_AMPERE \
"$C1 \
$C1 \
$C1 ## \
$C1 #### \
$C1 ### ## \
$C1 ### ### \
$C1 ### ### \
$C1 ### ### \
$C1 ## ### \
$C1 ####### ### ### \
$C1 ###### ## ###### ### \
$C1 #### ### ######## \
$C1 #### ### #### \
$C1 ### ### #### \
$C1 ## ### ### \
$C1 \
$C1 "
#define ASCII_NXP \
"$C1##### # $C2####### ####### $C3########## \
$C1####### ## $C2####### ####### $C3############### \
$C1########## #### $C2###### ###### $C3### ###### \
$C1############ ##### $C2############ $C3##### ##### \
$C1##### ####### ##### $C2########## $C3################### \
$C1##### ######### $C2############## $C3############### \
$C1##### ###### $C2###### ###### $C3#### \
$C1##### ## $C2###### ###### $C3## "
#define ASCII_AMLOGIC \
"$C1 .#####. ### ### \
$C1 ######## ### \
$C1 ####..### ########## ### ### ##### ### ### \
$C1 .## #. ### ## ## ## ### ## ## ## ## ### ## \
$C1 #### #.# ### ## ## ## ### ## ## ## ## ### ## \
$C1#########.### ## ## ## ## ### ###### ## ### \
$C1 ### \
$C1 ### "
#define ASCII_MARVELL \
"$C1 ........... ........... \
$C1 .### . .## . \
$C1 .##### . #### . \
$C1 ####### . ####### . \
$C1 .#########__________. #########__________. \
$C1 .###########|__________|#########|__________| \
$C1 ############ ______############ __________ \
$C1 .######### |__________|###### |__________| \
$C1 ########### ___########### __________ \
$C1.########## |__________| |__________| "
#define ASCII_SPACEMIT \
"$C1 :#: \
$C1 :####: \
$C1 :#######: \
$C1 :#########: \
$C1 :#########: \
$C1 :#######: \
$C1 :####: \
$C1 :#: \
$C1:##: :#: \
$C1:####: :###: \
$C1:#######: :####: \
$C1:##########: :###: \
$C1:###########: :#: \
$C1:###########: \
$C1 :##########: \
$C1 :#######: \
$C1 :####: \
$C1 :##: "
// --------------------- LONG LOGOS ------------------------- //
#define ASCII_AMD_L \
"$C1 \
@@ -549,112 +320,30 @@ $C1 ############ ################## ######### #### ######### \
$C1 \
$C1 ############ ################ ######### ## ######### "
#define ASCII_SIFIVE_L \
"$C1 ################################################### \
$C1 ###########@@@@@@@@@@@@@@@@@@@@@@@@@@@@############ \
$C1 ##########@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@########### \
$C1 #########@@@@@#######################@@@@########## \
$C1 ########@@@@@#########################@@@@######### \
$C1 #######@@@@@###########################@@@@######## \
$C1 ######@@@@@########@@@@@@@@@@@@@@@@@@@@@@@@@####### \
$C1 #####@@@@@########@@@@@@@@@@@@@@@@@@@@@@@@@@@###### \
$C1 ####@@@@@################################@@@@@##### \
$C1 ###@@@@@##################################@@@@@#### \
$C1 ##@@@@@####################################@@@@@### \
$C1 ##@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@#########@@@@### \
$C1 ##@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@############@@@@### \
$C1 ####@@@@@#############@@@@@@@############@@@@@##### \
$C1 #######@@@@@@############@############@@@@@@####### \
$C1 ##########@@@@@@###################@@@@@@########## \
$C1 ##############@@@@@@###########@@@@@@############## \
$C1 #################@@@@@@#####@@@@@@################# \
$C1 ####################@@@@@@@@@@@#################### \
$C1 ########################@@@######################## \
$C1 ################################################### "
#define ASCII_STARFIVE_L \
"$C1 ####### \
$C1 ################. \
$C1 ############ ########### \
$C1 ############ ##########. \
$C1 ############ # ###### \
$C1 ########### ##### ## \
$C1 #######. ########## \
$C1 ###### ### *########### \
$C1 ###### #######. ########## \
$C1 ######### ############ ###### \
$C1 ###########. ###########* # \
$C1 ############ ############ \
$C1 # ############. .########### \
$C1 ###### ########### ######### \
$C1 ########## .######, ##### \
$C1 ############ ##. #####. \
$C1 ######### ######## \
$C1 ## ##### ##########. \
$C1 ####### # ############ \
$C1 ########### ###########. \
$C1 ###########. ############ \
$C1 ################ \
$C1 ####### "
#define ASCII_NVIDIA_L \
"$C1 MMMMMMMMMMMMMMMMMMMMMMMMMMMMMM \
$C1 MMMMMMMMMMMMMMMMMMMMMMMMMMMMMM \
$C1 .:: 'MMMMMMMMMMMMMMMMMMMMMMMMM \
$C1 ccllooo;:;. ;MMMMMMMMMMMMMMMMMM \
$C1 cloc :ooollcc: :MMMMMMMMMMMMMMM \
$C1 cloc :ccl; lolc, ;MMMMMMMMMMMM \
$C1.cloo: :clo ;c: .ool; MMMMMMMMMMM \
$C1 ooo: ooo :ool, .cloo. ;lMMMMMMMMMMM \
$C1 ooo: ooc :ooooccooo. :MMMM lMMMMMMM \
$C1 ooc. ool: :oooooo' ,cloo. MMMM \
$C1 ool:. olc: .:cloo. :MMMM \
$C1 olc, ;:::cccloo. :MMMMMMMM \
$C1 olcc::; ,:ccloMMMMMMMMM \
$C1 :......oMMMMMMMMMMMMMMMMMMMMMM \
$C1 :lllMMMMMMMMMMMMMMMMMMMMMMMMMM "
typedef struct ascii_logo asciiL;
// +-----------------------------------------------------------------------------------------------------------------+
// | LOGO | W | H | REPLACE | COLORS LOGO (>0 && <10) | COLORS TEXT (=2) |
// +-----------------------------------------------------------------------------------------------------------------+
asciiL logo_amd = { ASCII_AMD, 39, 15, false, {C_FG_WHITE, C_FG_GREEN}, {C_FG_WHITE, C_FG_GREEN} };
asciiL logo_intel = { ASCII_INTEL, 48, 14, false, {C_FG_CYAN}, {C_FG_CYAN, C_FG_WHITE} };
asciiL logo_intel_new = { ASCII_INTEL_NEW, 51, 9, false, {C_FG_CYAN}, {C_FG_CYAN, C_FG_WHITE} };
asciiL logo_hygon = { ASCII_HYGON, 51, 11, false, {C_FG_RED}, {C_FG_RED, C_FG_WHITE} };
asciiL logo_snapd = { ASCII_SNAPD, 39, 16, false, {C_FG_RED, C_FG_WHITE}, {C_FG_RED, C_FG_WHITE} };
asciiL logo_mtk = { ASCII_MTK, 59, 5, false, {C_FG_BLUE, C_FG_YELLOW}, {C_FG_BLUE, C_FG_YELLOW} };
asciiL logo_exynos = { ASCII_EXYNOS, 22, 13, true, {C_BG_BLUE, C_FG_WHITE}, {C_FG_BLUE, C_FG_WHITE} };
asciiL logo_kirin = { ASCII_KIRIN, 53, 12, false, {C_FG_RED}, {C_FG_WHITE, C_FG_RED} };
asciiL logo_kunpeng = { ASCII_KUNPENG, 48, 17, false, {C_FG_RED, C_FG_WHITE}, {C_FG_WHITE, C_FG_RED} };
asciiL logo_broadcom = { ASCII_BROADCOM, 44, 19, false, {C_FG_WHITE, C_FG_RED}, {C_FG_WHITE, C_FG_RED} };
asciiL logo_arm = { ASCII_ARM, 42, 5, false, {C_FG_CYAN}, {C_FG_WHITE, C_FG_CYAN} };
asciiL logo_ibm = { ASCII_IBM, 42, 9, false, {C_FG_CYAN, C_FG_WHITE}, {C_FG_CYAN, C_FG_WHITE} };
asciiL logo_apple = { ASCII_APPLE, 32, 17, false, {C_FG_WHITE}, {C_FG_CYAN, C_FG_B_WHITE} };
asciiL logo_google = { ASCII_GOOGLE, 35, 15, false, {C_FG_RED, C_FG_YELLOW, C_FG_GREEN, C_FG_BLUE}, {C_FG_BLUE, C_FG_B_WHITE} };
asciiL logo_allwinner = { ASCII_ALLWINNER, 47, 16, false, {C_FG_CYAN}, {C_FG_B_BLACK, C_FG_B_CYAN } };
asciiL logo_rockchip = { ASCII_ROCKCHIP, 58, 8, false, {C_FG_CYAN, C_FG_YELLOW}, {C_FG_CYAN, C_FG_YELLOW} };
asciiL logo_riscv = { ASCII_RISCV, 63, 18, false, {C_FG_CYAN, C_FG_YELLOW}, {C_FG_CYAN, C_FG_YELLOW} };
asciiL logo_sifive = { ASCII_SIFIVE, 48, 19, true, {C_BG_WHITE, C_BG_BLACK}, {C_FG_WHITE, C_FG_BLUE} };
asciiL logo_starfive = { ASCII_STARFIVE, 33, 17, false, {C_FG_WHITE}, {C_FG_WHITE, C_FG_BLUE} };
asciiL logo_sipeed = { ASCII_SIPEED, 41, 16, true, {C_BG_RED, C_BG_WHITE}, {C_FG_RED, C_FG_WHITE} };
asciiL logo_nvidia = { ASCII_NVIDIA, 45, 19, false, {C_FG_GREEN, C_FG_WHITE}, {C_FG_WHITE, C_FG_GREEN} };
asciiL logo_ampere = { ASCII_AMPERE, 50, 17, false, {C_FG_RED}, {C_FG_WHITE, C_FG_RED} };
asciiL logo_nxp = { ASCII_NXP, 55, 8, false, {C_FG_YELLOW, C_FG_CYAN, C_FG_GREEN}, {C_FG_CYAN, C_FG_WHITE} };
asciiL logo_amlogic = { ASCII_AMLOGIC, 58, 8, false, {C_FG_BLUE}, {C_FG_BLUE, C_FG_B_WHITE} };
asciiL logo_marvell = { ASCII_MARVELL, 56, 10, false, {C_FG_B_BLACK}, {C_FG_B_BLACK, C_FG_B_WHITE} };
asciiL logo_spacemit = { ASCII_SPACEMIT, 27, 18, false, {C_FG_B_GREEN}, {C_FG_B_GREEN, C_FG_B_WHITE} };
// ------------------------------------------------------------------------------------------------------+
// | LOGO | W | H | REPLACE | COLORS LOGO (>0 && <10) | COLORS TEXT (=2) |
// ------------------------------------------------------------------------------------------------------+
asciiL logo_amd = { ASCII_AMD, 39, 15, false, {C_FG_WHITE, C_FG_GREEN}, {C_FG_WHITE, C_FG_GREEN} };
asciiL logo_intel = { ASCII_INTEL, 48, 14, false, {C_FG_CYAN}, {C_FG_CYAN, C_FG_WHITE} };
asciiL logo_intel_new = { ASCII_INTEL_NEW, 51, 9, false, {C_FG_CYAN}, {C_FG_CYAN, C_FG_WHITE} };
asciiL logo_snapd = { ASCII_SNAPD, 39, 16, false, {C_FG_RED, C_FG_WHITE}, {C_FG_RED, C_FG_WHITE} };
asciiL logo_mtk = { ASCII_MTK, 59, 5, false, {C_FG_BLUE, C_FG_YELLOW}, {C_FG_BLUE, C_FG_YELLOW} };
asciiL logo_exynos = { ASCII_EXYNOS, 22, 13, true, {C_BG_BLUE, C_FG_WHITE}, {C_FG_BLUE, C_FG_WHITE} };
asciiL logo_kirin = { ASCII_KIRIN, 53, 12, false, {C_FG_RED}, {C_FG_WHITE, C_FG_RED} };
asciiL logo_broadcom = { ASCII_BROADCOM, 44, 19, false, {C_FG_WHITE, C_FG_RED}, {C_FG_WHITE, C_FG_RED} };
asciiL logo_arm = { ASCII_ARM, 42, 5, false, {C_FG_CYAN}, {C_FG_WHITE, C_FG_CYAN} };
asciiL logo_ibm = { ASCII_IBM, 42, 9, false, {C_FG_CYAN, C_FG_WHITE}, {C_FG_CYAN, C_FG_WHITE} };
asciiL logo_apple = { ASCII_APPLE, 32, 17, false, {C_FG_WHITE}, {C_FG_CYAN, C_FG_B_WHITE} };
asciiL logo_allwinner = { ASCII_ALLWINNER, 47, 16, false, {C_FG_CYAN}, {C_FG_B_BLACK, C_FG_B_CYAN } };
// Long variants | ----------------------------------------------------------------------------------------------------------------|
asciiL logo_amd_l = { ASCII_AMD_L, 62, 19, true, {C_BG_WHITE, C_BG_GREEN}, {C_FG_WHITE, C_FG_GREEN} };
asciiL logo_intel_l = { ASCII_INTEL_L, 62, 19, true, {C_BG_CYAN, C_BG_WHITE}, {C_FG_CYAN, C_FG_WHITE} };
asciiL logo_intel_l_new = { ASCII_INTEL_L_NEW, 57, 14, true, {C_BG_CYAN, C_BG_WHITE, C_BG_BLUE}, {C_FG_CYAN, C_FG_WHITE} };
asciiL logo_arm_l = { ASCII_ARM_L, 60, 8, true, {C_BG_CYAN}, {C_FG_WHITE, C_FG_CYAN} };
asciiL logo_ibm_l = { ASCII_IBM_L, 62, 13, true, {C_BG_CYAN, C_FG_WHITE}, {C_FG_CYAN, C_FG_WHITE} };
asciiL logo_starfive_l = { ASCII_STARFIVE_L, 50, 22, false, {C_FG_WHITE}, {C_FG_WHITE, C_FG_BLUE} };
asciiL logo_sifive_l = { ASCII_SIFIVE_L, 53, 21, true, {C_BG_WHITE, C_BG_BLACK}, {C_FG_WHITE, C_FG_CYAN} };
asciiL logo_nvidia_l = { ASCII_NVIDIA_L, 50, 15, false, {C_FG_GREEN, C_FG_WHITE}, {C_FG_WHITE, C_FG_GREEN} };
asciiL logo_unknown = { NULL, 0, 0, false, {COLOR_NONE}, {COLOR_NONE, COLOR_NONE} };
// Long variants | ----------------------------------------------------------------------------------------------------|
asciiL logo_amd_l = { ASCII_AMD_L, 62, 19, true, {C_BG_WHITE, C_BG_GREEN}, {C_FG_WHITE, C_FG_GREEN} };
asciiL logo_intel_l = { ASCII_INTEL_L, 62, 19, true, {C_BG_CYAN, C_BG_WHITE}, {C_FG_CYAN, C_FG_WHITE} };
asciiL logo_intel_l_new = { ASCII_INTEL_L_NEW, 57, 14, true, {C_BG_CYAN, C_BG_WHITE, C_BG_BLUE}, {C_FG_CYAN, C_FG_WHITE} };
asciiL logo_arm_l = { ASCII_ARM_L, 60, 8, true, {C_BG_CYAN}, {C_FG_WHITE, C_FG_CYAN} };
asciiL logo_ibm_l = { ASCII_IBM_L, 62, 13, true, {C_BG_CYAN, C_FG_WHITE}, {C_FG_CYAN, C_FG_WHITE} };
asciiL logo_unknown = { NULL, 0, 0, false, {COLOR_NONE}, {COLOR_NONE, COLOR_NONE} };
#endif

34
src/common/cpu.c
View File

@@ -14,8 +14,6 @@
#include "../ppc/uarch.h"
#elif ARCH_ARM
#include "../arm/uarch.h"
#elif ARCH_RISCV
#include "../riscv/uarch.h"
#endif
#define STRING_YES "Yes"
@@ -34,12 +32,6 @@ int64_t get_freq(struct frequency* freq) {
return freq->max;
}
#ifdef ARCH_X86
int64_t get_freq_pp(struct frequency* freq) {
return freq->max_pp;
}
#endif
#if defined(ARCH_X86) || defined(ARCH_PPC)
char* get_str_cpu_name(struct cpuInfo* cpu, bool fcpuname) {
#ifdef ARCH_X86
@@ -151,25 +143,17 @@ char* get_str_l3(struct cache* cach) {
char* get_str_freq(struct frequency* freq) {
//Max 3 digits and 3 for '(M/G)Hz' plus 1 for '\0'
uint32_t size = (1+5+1+3+1);
uint32_t size = (5+1+3+1);
assert(strlen(STRING_UNKNOWN)+1 <= size);
char* string = ecalloc(size, sizeof(char));
char* string = emalloc(sizeof(char)*size);
memset(string, 0, sizeof(char)*size);
if(freq->max == UNKNOWN_DATA || freq->max < 0) {
if(freq->max == UNKNOWN_DATA || freq->max < 0)
snprintf(string,strlen(STRING_UNKNOWN)+1,STRING_UNKNOWN);
}
else if(freq->max >= 1000) {
if (freq->measured)
snprintf(string,size,"~%.3f "STRING_GIGAHERZ,(float)(freq->max)/1000);
else
snprintf(string,size,"%.3f "STRING_GIGAHERZ,(float)(freq->max)/1000);
}
else {
if (freq->measured)
snprintf(string,size,"~%d "STRING_MEGAHERZ,freq->max);
else
snprintf(string,size,"%d "STRING_MEGAHERZ,freq->max);
}
else if(freq->max >= 1000)
snprintf(string,size,"%.3f "STRING_GIGAHERZ,(float)(freq->max)/1000);
else
snprintf(string,size,"%d "STRING_MEGAHERZ,freq->max);
return string;
}
@@ -208,7 +192,7 @@ void init_topology_struct(struct topology* topo, struct cache* cach) {
topo->sockets = 0;
#ifdef ARCH_X86
topo->smt_available = 0;
topo->apic = ecalloc(1, sizeof(struct apic));
topo->apic = emalloc(sizeof(struct apic));
#endif
#endif
}

45
src/common/cpu.h
View File

@@ -8,7 +8,6 @@ enum {
// ARCH_X86
CPU_VENDOR_INTEL,
CPU_VENDOR_AMD,
CPU_VENDOR_HYGON,
// ARCH_ARM
CPU_VENDOR_ARM,
CPU_VENDOR_APPLE,
@@ -17,15 +16,10 @@ enum {
CPU_VENDOR_NVIDIA,
CPU_VENDOR_APM,
CPU_VENDOR_QUALCOMM,
CPU_VENDOR_HUAWEI,
CPU_VENDOR_HUAWUEI,
CPU_VENDOR_SAMSUNG,
CPU_VENDOR_MARVELL,
CPU_VENDOR_PHYTIUM,
// ARCH_RISCV
CPU_VENDOR_RISCV,
CPU_VENDOR_SIFIVE,
CPU_VENDOR_THEAD,
CPU_VENDOR_SPACEMIT,
// OTHERS
CPU_VENDOR_UNKNOWN,
CPU_VENDOR_INVALID
@@ -34,14 +28,10 @@ enum {
enum {
HV_VENDOR_KVM,
HV_VENDOR_QEMU,
HV_VENDOR_VBOX,
HV_VENDOR_HYPERV,
HV_VENDOR_VMWARE,
HV_VENDOR_XEN,
HV_VENDOR_PARALLELS,
HV_VENDOR_PHYP,
HV_VENDOR_BHYVE,
HV_VENDOR_APPLEVZ,
HV_VENDOR_INVALID
};
@@ -59,13 +49,6 @@ typedef int32_t VENDOR;
struct frequency {
int32_t base;
int32_t max;
// Indicates if max frequency was measured
bool measured;
#ifdef ARCH_X86
// Max frequency when running vectorized code.
// Used only for peak performance computation.
int32_t max_pp;
#endif
};
struct hypervisor {
@@ -130,33 +113,18 @@ struct features {
bool SHA1;
bool SHA2;
bool CRC32;
bool SVE;
bool SVE2;
uint64_t cntb;
#endif
};
struct extensions {
char* str;
bool* mask; // allocated at runtime with size RISCV_ISA_EXT_ID_MAX-1
};
struct cpuInfo {
VENDOR cpu_vendor;
VENDOR cpu_vendor;
struct uarch* arch;
struct hypervisor* hv;
struct frequency* freq;
struct cache* cach;
struct topology* topo;
int64_t peak_performance;
// Similar but not exactly equal
// to struct features
#ifdef ARCH_RISCV
struct extensions* ext;
#else
struct features* feat;
#endif
int64_t peak_performance;
#if defined(ARCH_X86) || defined(ARCH_PPC)
// CPU name from model
@@ -181,7 +149,7 @@ struct cpuInfo {
uint32_t midr;
#endif
#if defined(ARCH_ARM) || defined(ARCH_RISCV)
#ifdef ARCH_ARM
struct system_on_chip* soc;
#endif
@@ -194,8 +162,6 @@ struct cpuInfo {
#ifdef ARCH_X86
// The index of the first core in the module
uint32_t first_core_id;
// The index of this module
uint32_t module_id;
#endif
#endif
};
@@ -208,9 +174,6 @@ uint32_t get_nsockets(struct topology* topo);
VENDOR get_cpu_vendor(struct cpuInfo* cpu);
int64_t get_freq(struct frequency* freq);
#ifdef ARCH_X86
int64_t get_freq_pp(struct frequency* freq);
#endif
char* get_str_aes(struct cpuInfo* cpu);
char* get_str_sha(struct cpuInfo* cpu);

195
src/common/freq.c
View File

@@ -1,195 +0,0 @@
#ifdef __linux__
#define _GNU_SOURCE
#include <time.h>
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <errno.h>
#include <unistd.h>
#include <asm/unistd.h>
#include <sys/ioctl.h>
#include <linux/perf_event.h>
#include "global.h"
#include "cpu.h"
static long
perf_event_open(struct perf_event_attr *hw_event, pid_t pid,
int cpu, int group_fd, unsigned long flags) {
int ret;
ret = syscall(__NR_perf_event_open, hw_event, pid, cpu,
group_fd, flags);
return ret;
}
#define INSERT_ASM_ONCE __asm volatile("nop");
#define INSERT_ASM_10_TIMES \
INSERT_ASM_ONCE \
INSERT_ASM_ONCE \
INSERT_ASM_ONCE \
INSERT_ASM_ONCE \
INSERT_ASM_ONCE \
INSERT_ASM_ONCE \
INSERT_ASM_ONCE \
INSERT_ASM_ONCE \
INSERT_ASM_ONCE \
INSERT_ASM_ONCE \
#define INSERT_ASM_100_TIMES \
INSERT_ASM_10_TIMES \
INSERT_ASM_10_TIMES \
INSERT_ASM_10_TIMES \
INSERT_ASM_10_TIMES \
INSERT_ASM_10_TIMES \
INSERT_ASM_10_TIMES \
INSERT_ASM_10_TIMES \
INSERT_ASM_10_TIMES \
INSERT_ASM_10_TIMES \
INSERT_ASM_10_TIMES
#define INSERT_ASM_1000_TIMES \
INSERT_ASM_100_TIMES \
INSERT_ASM_100_TIMES \
INSERT_ASM_100_TIMES \
INSERT_ASM_100_TIMES \
INSERT_ASM_100_TIMES \
INSERT_ASM_100_TIMES \
INSERT_ASM_100_TIMES \
INSERT_ASM_100_TIMES \
INSERT_ASM_100_TIMES \
INSERT_ASM_100_TIMES \
void nop_function(uint64_t iters) {
for (uint64_t i = 0; i < iters; i++) {
INSERT_ASM_1000_TIMES
INSERT_ASM_1000_TIMES
INSERT_ASM_1000_TIMES
INSERT_ASM_1000_TIMES
}
}
// Run the nop_function with the number of iterations specified and
// measure both the time and number of cycles
int measure_freq_iters(uint64_t iters, uint32_t core, double* freq) {
clockid_t clock = CLOCK_PROCESS_CPUTIME_ID;
struct timespec start, end;
struct perf_event_attr pe;
uint64_t cycles;
int fd;
int pid = 0;
memset(&pe, 0, sizeof(struct perf_event_attr));
pe.type = PERF_TYPE_HARDWARE;
pe.size = sizeof(struct perf_event_attr);
pe.config = PERF_COUNT_HW_CPU_CYCLES;
pe.disabled = 1;
pe.exclude_kernel = 1;
pe.exclude_hv = 1;
fd = perf_event_open(&pe, pid, core, -1, 0);
if (fd == -1) {
perror("perf_event_open");
if (errno == EPERM || errno == EACCES) {
printErr("You may not have permission to collect stats.\n"\
"Consider tweaking /proc/sys/kernel/perf_event_paranoid or running as root");
}
return -1;
}
if (clock_gettime(clock, &start) == -1) {
perror("clock_gettime");
return -1;
}
if(ioctl(fd, PERF_EVENT_IOC_RESET, 0) == -1) {
perror("ioctl");
return -1;
}
if(ioctl(fd, PERF_EVENT_IOC_ENABLE, 0) == -1) {
perror("ioctl");
return -1;
}
nop_function(iters);
ssize_t ret = read(fd, &cycles, sizeof(uint64_t));
if (ret == -1) {
perror("read");
return -1;
}
if (ret != sizeof(uint64_t)) {
printErr("Read returned %d, expected %d", ret, sizeof(uint64_t));
return -1;
}
if(ioctl(fd, PERF_EVENT_IOC_DISABLE, 0) == -1) {
perror("ioctl");
return -1;
}
if (clock_gettime(clock, &end) == -1) {
perror("clock_gettime");
return -1;
}
uint64_t nsecs = (end.tv_sec*1e9 + end.tv_nsec) - (start.tv_sec*1e9 + start.tv_nsec);
uint64_t usecs = nsecs/1000;
*freq = cycles/((double)usecs);
return 0;
}
// Return a good number of iterations to run the nop_function in
// order to get a precise measurement of the frequency without taking
// too much time.
uint64_t get_num_iters_from_freq(double frequency) {
// Truncate to reduce variability
uint64_t freq_trunc = ((uint64_t) frequency / 100) * 100;
uint64_t osp_per_iter = 4 * 1000;
return freq_trunc * 1e7 * 1/osp_per_iter;
}
// Differences between x86 measure_frequency and this measure_max_frequency:
// - measure_frequency employs all cores simultaneously whereas
// measure_max_frequency only employs 1.
// - measure_frequency runs the computation and checks /proc/cpuinfo whereas
// measure_max_frequency does not rely on /proc/cpuinfo and simply
// counts cpu cycles to measure frequency.
// - measure_frequency uses actual computation while measuring the frequency
// whereas measure_max_frequency uses nop instructions. This makes the former
// x86 dependant whereas the latter is architecture independant.
int64_t measure_max_frequency(uint32_t core) {
if (!bind_to_cpu(core)) {
printErr("Failed binding the process to CPU %d", core);
return UNKNOWN_DATA;
}
// First, get very rough estimation of clock cycle to
// compute a reasonable value for the iterations
double estimation_freq, frequency;
uint64_t iters = 100000;
if (measure_freq_iters(iters, core, &estimation_freq) == -1)
return UNKNOWN_DATA;
if (estimation_freq <= 0.0) {
printErr("First frequency measurement yielded an invalid value: %f", estimation_freq);
return UNKNOWN_DATA;
}
iters = get_num_iters_from_freq(estimation_freq);
printWarn("Running frequency measurement with %ld iterations on core %d...", iters, core);
// Now perform actual measurement
const char* frequency_banner = "cpufetch is measuring the max frequency...";
printf("%s", frequency_banner);
fflush(stdout);
if (measure_freq_iters(iters, core, &frequency) == -1)
return UNKNOWN_DATA;
// Clean screen once measurement is finished
printf("\r%*c\r", (int) strlen(frequency_banner), ' ');
// Discard last digit in the frequency, which should help providing
// more reliable and predictable values.
return (((int) frequency + 5)/10) * 10;
}
#endif // #ifdef __linux__

6
src/common/freq.h
View File

@@ -1,6 +0,0 @@
#ifndef __COMMON_FREQ__
#define __COMMON_FREQ__
int64_t measure_max_frequency(uint32_t core);
#endif

130
src/common/global.c
View File

@@ -1,14 +1,3 @@
#ifdef _WIN32
#define NOMINMAX
#include <windows.h>
#elif defined __linux__
#define _GNU_SOURCE
#include <sched.h>
#elif defined __FreeBSD__
#include <sys/param.h>
#include <sys/cpuset.h>
#endif
#include <stdarg.h>
#include <stdio.h>
#include <stdlib.h>
@@ -31,40 +20,6 @@
#endif
#ifdef ARCH_X86
static const char* ARCH_STR = "x86 / x86_64 build";
#include "../x86/cpuid.h"
#elif ARCH_PPC
static const char* ARCH_STR = "PowerPC build";
#include "../ppc/ppc.h"
#elif ARCH_ARM
static const char* ARCH_STR = "ARM build";
#include "../arm/midr.h"
#elif ARCH_RISCV
static const char* ARCH_STR = "RISC-V build";
#include "../riscv/riscv.h"
#endif
#ifdef __linux__
#ifdef __ANDROID__
static const char* OS_STR = "Android";
#else
static const char* OS_STR = "Linux";
#endif
#elif __FreeBSD__
static const char* OS_STR = "FreeBSD";
#elif _WIN32
static const char* OS_STR = "Windows";
#elif defined __APPLE__ || __MACH__
static const char* OS_STR = "macOS";
#else
static const char* OS_STR = "Unknown OS";
#endif
#ifndef GIT_FULL_VERSION
static const char* VERSION = "1.06";
#endif
enum {
LOG_LEVEL_NORMAL,
LOG_LEVEL_VERBOSE
@@ -72,14 +27,6 @@ enum {
int LOG_LEVEL;
void printBugMessage(FILE *restrict stream) {
#if defined(ARCH_X86) || defined(ARCH_PPC)
fprintf(stream, "Please, create a new issue with this error message, the output of 'cpufetch' and 'cpufetch --debug' on https://github.com/Dr-Noob/cpufetch/issues\n");
#elif ARCH_ARM
fprintf(stream, "Please, create a new issue with this error message, your smartphone/computer model, the output of 'cpufetch --verbose' and 'cpufetch --debug' on https://github.com/Dr-Noob/cpufetch/issues\n");
#endif
}
void printWarn(const char *fmt, ...) {
if(LOG_LEVEL == LOG_LEVEL_VERBOSE) {
int buffer_size = 4096;
@@ -100,8 +47,6 @@ void printErr(const char *fmt, ...) {
vsnprintf(buffer,buffer_size, fmt, args);
va_end(args);
fprintf(stderr,RED "[ERROR]: "RESET "%s\n",buffer);
fprintf(stderr,"[VERSION]: ");
print_version(stderr);
}
void printBug(const char *fmt, ...) {
@@ -112,42 +57,10 @@ void printBug(const char *fmt, ...) {
vsnprintf(buffer,buffer_size, fmt, args);
va_end(args);
fprintf(stderr,RED "[ERROR]: "RESET "%s\n",buffer);
fprintf(stderr,"[VERSION]: ");
print_version(stderr);
printBugMessage(stderr);
}
bool isReleaseVersion(char *git_full_version) {
return strstr(git_full_version, "-") == NULL;
}
/// The unknown uarch errors are by far the most common error a user will encounter.
/// Rather than using the generic printBug function, which asks the user to report
/// the problem on the issues webpage, this function will check if the program is
/// the release version. In such case, support for this feature is most likely already
/// in the last version, so just tell the user to compile that one and not report this
/// in github.
void printBugCheckRelease(const char *fmt, ...) {
int buffer_size = 4096;
char buffer[buffer_size];
va_list args;
va_start(args, fmt);
vsnprintf(buffer,buffer_size, fmt, args);
va_end(args);
fprintf(stderr, RED "[ERROR]: "RESET "%s\n", buffer);
fprintf(stderr, "[VERSION]: ");
print_version(stderr);
#ifdef GIT_FULL_VERSION
if (isReleaseVersion(GIT_FULL_VERSION)) {
fprintf(stderr, RED "[ERROR]: "RESET "You are using an outdated version of cpufetch. Please compile cpufetch from source (see https://github.com/Dr-Noob/cpufetch?tab=readme-ov-file#22-building-from-source)");
}
else {
printBugMessage(stderr);
}
#else
printBugMessage(stderr);
#if defined(ARCH_X86) || defined(ARCH_PPC)
fprintf(stderr, "Please, create a new issue with this error message, the output of 'cpufetch' and 'cpufetch --debug' on https://github.com/Dr-Noob/cpufetch/issues\n");
#elif ARCH_ARM
fprintf(stderr, "Please, create a new issue with this error message, your smartphone/computer model, the output of 'cpufetch --verbose' and 'cpufetch --debug' on https://github.com/Dr-Noob/cpufetch/issues\n");
#endif
}
@@ -210,38 +123,3 @@ void* erealloc(void *ptr, size_t size) {
return newptr;
}
#ifndef __APPLE__
bool bind_to_cpu(int cpu_id) {
#ifdef _WIN32
HANDLE process = GetCurrentProcess();
DWORD_PTR processAffinityMask = 1 << cpu_id;
return SetProcessAffinityMask(process, processAffinityMask);
#elif defined __linux__
cpu_set_t currentCPU;
CPU_ZERO(&currentCPU);
CPU_SET(cpu_id, &currentCPU);
if (sched_setaffinity (0, sizeof(currentCPU), &currentCPU) == -1) {
printWarn("sched_setaffinity: %s", strerror(errno));
return false;
}
return true;
#elif defined __FreeBSD__
cpuset_t currentCPU;
CPU_ZERO(&currentCPU);
CPU_SET(cpu_id, &currentCPU);
if(cpuset_setaffinity(CPU_LEVEL_WHICH, CPU_WHICH_TID, -1, sizeof(cpuset_t), &currentCPU) == -1) {
printWarn("cpuset_setaffinity: %s", strerror(errno));
return false;
}
return true;
#endif
}
#endif
void print_version(FILE *restrict stream) {
#ifdef GIT_FULL_VERSION
fprintf(stream, "cpufetch %s (%s %s)\n", GIT_FULL_VERSION, OS_STR, ARCH_STR);
#else
fprintf(stream, "cpufetch v%s (%s %s)\n", VERSION, OS_STR, ARCH_STR);
#endif
}

6
src/common/global.h
View File

@@ -1,7 +1,6 @@
#ifndef __GLOBAL__
#define __GLOBAL__
#include <stdio.h>
#include <stdbool.h>
#include <stddef.h>
@@ -12,16 +11,11 @@ void set_log_level(bool verbose);
void printWarn(const char *fmt, ...);
void printErr(const char *fmt, ...);
void printBug(const char *fmt, ...);
void printBugCheckRelease(const char *fmt, ...);
int min(int a, int b);
int max(int a, int b);
char *strremove(char *str, const char *sub);
void* emalloc(size_t size);
void* ecalloc(size_t nmemb, size_t size);
void* erealloc(void *ptr, size_t size);
#ifndef __APPLE__
bool bind_to_cpu(int cpu_id);
#endif
void print_version(FILE *restrict stream);
#endif

75
src/common/main.c
View File

@@ -6,6 +6,35 @@
#include "printer.h"
#include "global.h"
#ifdef ARCH_X86
static const char* ARCH_STR = "x86_64 build";
#include "../x86/cpuid.h"
#elif ARCH_PPC
static const char* ARCH_STR = "PowerPC build";
#include "../ppc/ppc.h"
#elif ARCH_ARM
static const char* ARCH_STR = "ARM build";
#include "../arm/midr.h"
#endif
#ifdef __linux__
#ifdef __ANDROID__
static const char* OS_STR = "Android";
#else
static const char* OS_STR = "Linux";
#endif
#elif __FreeBSD__
static const char* OS_STR = "FreeBSD";
#elif _WIN32
static const char* OS_STR = "Windows";
#elif defined __APPLE__ || __MACH__
static const char* OS_STR = "macOS";
#else
static const char* OS_STR = "Unknown OS";
#endif
static const char* VERSION = "1.03";
void print_help(char *argv[]) {
const char **t = args_str;
const char *c = args_chr;
@@ -30,29 +59,20 @@ void print_help(char *argv[]) {
#ifdef ARCH_X86
#ifdef __linux__
printf(" --%s %*s Compute the peak performance accurately (measure the CPU frequency instead of using the maximum)\n", t[ARG_ACCURATE_PP], (int) (max_len-strlen(t[ARG_ACCURATE_PP])), "");
printf(" --%s %*s Measure the max CPU frequency instead of reading it\n", t[ARG_MEASURE_MAX_FREQ], (int) (max_len-strlen(t[ARG_MEASURE_MAX_FREQ])), "");
#endif // __linux__
#endif
printf(" --%s %*s Show the old Intel logo\n", t[ARG_LOGO_INTEL_OLD], (int) (max_len-strlen(t[ARG_LOGO_INTEL_OLD])), "");
printf(" --%s %*s Show the new Intel logo\n", t[ARG_LOGO_INTEL_NEW], (int) (max_len-strlen(t[ARG_LOGO_INTEL_NEW])), "");
printf(" -%c, --%s %*s Show the full CPU name (do not abbreviate it)\n", c[ARG_FULLCPUNAME], t[ARG_FULLCPUNAME], (int) (max_len-strlen(t[ARG_FULLCPUNAME])), "");
printf(" -%c, --%s %*s Print raw cpuid data (debug purposes)\n", c[ARG_RAW], t[ARG_RAW], (int) (max_len-strlen(t[ARG_RAW])), "");
#endif // ARCH_X86
#ifdef ARCH_ARM
#ifdef __linux__
printf(" --%s %*s Measure the max CPU frequency instead of reading it\n", t[ARG_MEASURE_MAX_FREQ], (int) (max_len-strlen(t[ARG_MEASURE_MAX_FREQ])), "");
#endif
#endif
printf(" -%c, --%s %*s Print this help and exit\n", c[ARG_HELP], t[ARG_HELP], (int) (max_len-strlen(t[ARG_HELP])), "");
printf(" -%c, --%s %*s Print cpufetch version and exit\n", c[ARG_VERSION], t[ARG_VERSION], (int) (max_len-strlen(t[ARG_VERSION])), "");
printf("\nCOLORS: \n");
printf(" * \"intel\": Use Intel color scheme \n");
printf(" * \"intel-new\": Use Intel (new logo) color scheme \n");
printf(" * \"amd\": Use AMD color scheme \n");
printf(" * \"ibm\", Use IBM color scheme \n");
printf(" * \"arm\": Use ARM color scheme \n");
printf(" * \"rockchip\": Use Rockchip color scheme \n");
printf(" * \"sifive\": Use SiFive color scheme \n");
printf(" * \"intel\": Use Intel default color scheme \n");
printf(" * \"amd\": Use AMD default color scheme \n");
printf(" * \"ibm\", Use IBM default color scheme \n");
printf(" * \"arm\": Use ARM default color scheme \n");
printf(" * custom: If the argument of --color does not match any of the previous strings, a custom scheme can be specified.\n");
printf(" 5 colors must be given in RGB with the format: R,G,B:R,G,B:...\n");
printf(" The first 3 colors are the CPU art color and the next 2 colors are the text colors\n");
@@ -82,15 +102,12 @@ void print_help(char *argv[]) {
printf("\nNOTE: \n");
printf(" Peak performance information is NOT accurate. cpufetch computes peak performance using the max\n");
printf(" frequency of the CPU. However, to compute the peak performance, you need to know the frequency of the\n");
printf(" CPU running AVX code. By default, this value is not fetched by cpufetch, but you can use the\n");
printf(" --accurate-pp option, which will measure the AVX frequency and show a more precise estimation\n");
printf(" (this option is only available in x86 architectures).\n");
printf(" To precisely measure peak performance, see: https://github.com/Dr-Noob/peakperf\n");
printf("\n");
printf(" Both --accurate-pp and --measure-max-freq measure the actual frequency of the CPU. However,\n");
printf(" they differ slightly. The former measures the max frequency while running vectorized SSE/AVX\n");
printf(" instructions and it is thus x86 only, whereas the latter simply measures the max clock cycle\n");
printf(" and is architecture independent.\n");
printf(" CPU running AVX code. This value is not be fetched by cpufetch since it depends on each specific CPU.\n");
printf(" To correctly measure peak performance, see: https://github.com/Dr-Noob/peakperf\n");
}
void print_version() {
printf("cpufetch v%s (%s %s)\n",VERSION, OS_STR, ARCH_STR);
}
int main(int argc, char* argv[]) {
@@ -103,7 +120,7 @@ int main(int argc, char* argv[]) {
}
if(show_version()) {
print_version(stdout);
print_version();
return EXIT_SUCCESS;
}
@@ -114,7 +131,7 @@ int main(int argc, char* argv[]) {
return EXIT_FAILURE;
if(show_debug()) {
print_version(stdout);
print_version();
print_debug(cpu);
return EXIT_SUCCESS;
}
@@ -122,7 +139,7 @@ int main(int argc, char* argv[]) {
// TODO: This should be moved to the end of args.c
if(show_raw()) {
#ifdef ARCH_X86
print_version(stdout);
print_version();
print_raw(cpu);
return EXIT_SUCCESS;
#else
@@ -131,10 +148,8 @@ int main(int argc, char* argv[]) {
#endif
}
if(print_cpufetch(cpu, get_style(), get_colors(), show_full_cpu_name())) {
if(print_cpufetch(cpu, get_style(), get_colors(), show_full_cpu_name()))
return EXIT_SUCCESS;
}
else {
else
return EXIT_FAILURE;
}
}

133
src/common/pci.c
View File

@@ -1,133 +0,0 @@
#define _GNU_SOURCE
#include <sys/stat.h>
#include <dirent.h>
#include "udev.h"
#include "global.h"
#include "pci.h"
#ifndef PATH_MAX
#define PATH_MAX 1024
#endif
#define PCI_PATH "/sys/bus/pci/devices/"
#define MAX_LENGTH_PCI_DIR_NAME 1024
// Return a list of PCI devices containing only
// the sysfs path
struct pci_devices * get_pci_paths(void) {
DIR *dirp;
if ((dirp = opendir(PCI_PATH)) == NULL) {
perror("opendir");
return NULL;
}
struct dirent *dp;
int numDirs = 0;
errno = 0;
while ((dp = readdir(dirp)) != NULL) {
if (strcmp(dp->d_name, ".") != 0 && strcmp(dp->d_name, "..") != 0)
numDirs++;
}
if (errno != 0) {
perror("readdir");
return NULL;
}
rewinddir(dirp);
struct pci_devices * pci = emalloc(sizeof(struct pci_devices));
pci->num_devices = numDirs;
pci->devices = emalloc(sizeof(struct pci_device) * pci->num_devices);
char * full_path = emalloc(PATH_MAX * sizeof(char));
struct stat stbuf;
int i = 0;
while ((dp = readdir(dirp)) != NULL) {
if (strcmp(dp->d_name, ".") == 0 || strcmp(dp->d_name, "..") == 0)
continue;
if (strlen(dp->d_name) > MAX_LENGTH_PCI_DIR_NAME) {
printErr("Directory name is too long: %s", dp->d_name);
return NULL;
}
memset(full_path, 0, PATH_MAX * sizeof(char));
snprintf(full_path, min(strlen(PCI_PATH) + strlen(dp->d_name) + 1, PATH_MAX), "%s%s", PCI_PATH, dp->d_name);
if (stat(full_path, &stbuf) == -1) {
perror("stat");
return NULL;
}
if ((stbuf.st_mode & S_IFMT) == S_IFDIR) {
int strLen = min(MAX_LENGTH_PCI_DIR_NAME, strlen(dp->d_name)) + 1;
pci->devices[i] = emalloc(sizeof(struct pci_device));
pci->devices[i]->path = ecalloc(strLen, sizeof(char));
strncpy(pci->devices[i]->path, dp->d_name, strLen);
i++;
}
}
if (errno != 0) {
perror("readdir");
return NULL;
}
return pci;
}
// For each PCI device in the list pci, fetch its vendor and
// device id using sysfs (e.g., /sys/bus/pci/devices/XXX/{vendor/device})
void populate_pci_devices(struct pci_devices * pci) {
int filelen;
char* buf;
for (int i=0; i < pci->num_devices; i++) {
struct pci_device* dev = pci->devices[i];
int path_size = strlen(PCI_PATH) + strlen(dev->path) + 2;
// Read vendor_id
char *vendor_id_path = emalloc(sizeof(char) * (path_size + strlen("vendor") + 1));
sprintf(vendor_id_path, "%s/%s/%s", PCI_PATH, dev->path, "vendor");
if ((buf = read_file(vendor_id_path, &filelen)) == NULL) {
printWarn("read_file: %s: %s\n", vendor_id_path, strerror(errno));
dev->vendor_id = 0;
}
else {
dev->vendor_id = strtol(buf, NULL, 16);
}
// Read device_id
char *device_id_path = emalloc(sizeof(char) * (path_size + strlen("device") + 1));
sprintf(device_id_path, "%s/%s/%s", PCI_PATH, dev->path, "device");
if ((buf = read_file(device_id_path, &filelen)) == NULL) {
printWarn("read_file: %s: %s\n", device_id_path, strerror(errno));
dev->device_id = 0;
}
else {
dev->device_id = strtol(buf, NULL, 16);
}
free(vendor_id_path);
free(device_id_path);
}
}
// Return a list of PCI devices that could be used to infer the SoC.
// The criteria to determine which devices are suitable for this task
// is decided in filter_pci_devices.
struct pci_devices * get_pci_devices(void) {
struct pci_devices * pci = get_pci_paths();
if (pci == NULL)
return NULL;
populate_pci_devices(pci);
return pci;
}

23
src/common/pci.h
View File

@@ -1,23 +0,0 @@
#ifndef __PCI__
#define __PCI__
#define PCI_VENDOR_NVIDIA 0x10de
#define PCI_VENDOR_AMPERE 0x1def
#define PCI_DEVICE_TEGRA_X1 0x0faf
#define PCI_DEVICE_ALTRA 0xe100
struct pci_device {
char * path;
uint16_t vendor_id;
uint16_t device_id;
};
struct pci_devices {
struct pci_device ** devices;
int num_devices;
};
struct pci_devices * get_pci_devices(void);
#endif

422
src/common/printer.c
View File

@@ -16,16 +16,10 @@
#elif ARCH_PPC
#include "../ppc/uarch.h"
#include "../ppc/ppc.h"
#elif ARCH_ARM
#else
#include "../arm/uarch.h"
#include "../arm/midr.h"
#include "../arm/soc.h"
#include "../arm/socs.h"
#include "../common/soc.h"
#elif ARCH_RISCV
#include "../riscv/riscv.h"
#include "../riscv/uarch.h"
#include "../riscv/soc.h"
#endif
#ifdef _WIN32
@@ -45,18 +39,10 @@
#define MAX_ATTRIBUTES 100
#define MAX_TERM_SIZE 1024
typedef struct {
int id;
const char *name;
const char *shortname;
} AttributeField;
enum {
#if defined(ARCH_X86)
#if defined(ARCH_X86) || defined(ARCH_PPC)
ATTRIBUTE_NAME,
#elif defined(ARCH_PPC)
ATTRIBUTE_PART_NUMBER,
#elif defined(ARCH_ARM) || defined(ARCH_RISCV)
#elif ARCH_ARM
ATTRIBUTE_SOC,
#endif
#if defined(ARCH_X86) || defined(ARCH_ARM)
@@ -70,15 +56,12 @@ enum {
ATTRIBUTE_NCORES,
ATTRIBUTE_NCORES_DUAL,
#ifdef ARCH_X86
ATTRIBUTE_SSE,
ATTRIBUTE_AVX,
ATTRIBUTE_FMA,
#elif ARCH_PPC
ATTRIBUTE_ALTIVEC,
#elif ARCH_ARM
ATTRIBUTE_FEATURES,
#elif ARCH_RISCV
ATTRIBUTE_EXTENSIONS,
#endif
ATTRIBUTE_L1i,
ATTRIBUTE_L1d,
@@ -87,40 +70,70 @@ enum {
ATTRIBUTE_PEAK
};
static const AttributeField ATTRIBUTE_INFO[] = {
#if defined(ARCH_X86)
{ ATTRIBUTE_NAME, "Name:", "Name:" },
#elif defined(ARCH_PPC)
{ ATTRIBUTE_PART_NUMBER, "Part Number:", "P/N:" },
#elif defined(ARCH_ARM) || defined(ARCH_RISCV)
{ ATTRIBUTE_SOC, "SoC:", "SoC:" },
static const char* ATTRIBUTE_FIELDS [] = {
#ifdef ARCH_X86
"Name:",
#elif ARCH_PPC
"Part Number:",
#elif ARCH_ARM
"SoC:",
#endif
#if defined(ARCH_X86) || defined(ARCH_ARM)
{ ATTRIBUTE_CPU_NUM, "", "" },
"",
#endif
{ ATTRIBUTE_HYPERVISOR, "Hypervisor:", "Hypervisor:" },
{ ATTRIBUTE_UARCH, "Microarchitecture:", "uArch:" },
{ ATTRIBUTE_TECHNOLOGY, "Technology:", "Technology:" },
{ ATTRIBUTE_FREQUENCY, "Max Frequency:", "Max Freq:" },
{ ATTRIBUTE_SOCKETS, "Sockets:", "Sockets:" },
{ ATTRIBUTE_NCORES, "Cores:", "Cores:" },
{ ATTRIBUTE_NCORES_DUAL, "Cores (Total):", "Cores (Total):" },
"Hypervisor:",
"Microarchitecture:",
"Technology:",
"Max Frequency:",
"Sockets:",
"Cores:",
"Cores (Total):",
#ifdef ARCH_X86
{ ATTRIBUTE_SSE, "SSE:", "SSE:" },
{ ATTRIBUTE_AVX, "AVX:", "AVX:" },
{ ATTRIBUTE_FMA, "FMA:", "FMA:" },
"AVX:",
"FMA:",
#elif ARCH_PPC
{ ATTRIBUTE_ALTIVEC, "Altivec: ", "Altivec: " },
#elif ARCH_ARM
{ ATTRIBUTE_FEATURES, "Features: ", "Features: " },
#elif ARCH_RISCV
{ ATTRIBUTE_EXTENSIONS, "Extensions: ", "Extensions: " },
"Altivec: ",
#elif defined(ARCH_ARM)
"Features: ",
#endif
{ ATTRIBUTE_L1i, "L1i Size:", "L1i Size:" },
{ ATTRIBUTE_L1d, "L1d Size:", "L1d Size:" },
{ ATTRIBUTE_L2, "L2 Size:", "L2 Size:" },
{ ATTRIBUTE_L3, "L3 Size:", "L3 Size:" },
{ ATTRIBUTE_PEAK, "Peak Performance:", "Peak Perf.:" },
"L1i Size:",
"L1d Size:",
"L2 Size:",
"L3 Size:",
"Peak Performance:",
};
static const char* ATTRIBUTE_FIELDS_SHORT [] = {
#if defined(ARCH_X86)
"Name:",
#elif ARCH_PPC
"P/N:",
#elif ARCH_ARM
"SoC:",
#endif
#if defined(ARCH_X86) || defined(ARCH_ARM)
"",
#endif
"Hypervisor:",
"uArch:",
"Technology:",
"Max Freq:",
"Sockets:",
"Cores:",
"Cores (Total):",
#ifdef ARCH_X86
"AVX:",
"FMA:",
#elif ARCH_PPC
"Altivec: ",
#elif defined(ARCH_ARM)
"Features: ",
#endif
"L1i Size:",
"L1d Size:",
"L2 Size:",
"L3 Size:",
"Peak Perf.:",
};
struct terminal {
@@ -312,13 +325,6 @@ struct ascii_logo* choose_ascii_art_aux(struct ascii_logo* logo_long, struct asc
}
}
// https://no-color.org/
bool is_color_enabled(void) {
const char *var_name = "NO_COLOR";
char *no_color = getenv(var_name);
return no_color == NULL || no_color[0] == '\0';
}
void choose_ascii_art(struct ascii* art, struct color** cs, struct terminal* term, int lf) {
// 1. Choose logo
#ifdef ARCH_X86
@@ -333,9 +339,6 @@ void choose_ascii_art(struct ascii* art, struct color** cs, struct terminal* ter
else if(art->vendor == CPU_VENDOR_AMD) {
art->art = choose_ascii_art_aux(&logo_amd_l, &logo_amd, term, lf);
}
else if(art->vendor == CPU_VENDOR_HYGON) {
art->art = &logo_hygon;
}
else {
art->art = &logo_unknown;
}
@@ -350,51 +353,19 @@ void choose_ascii_art(struct ascii* art, struct color** cs, struct terminal* ter
art->art = &logo_exynos;
else if(art->vendor == SOC_VENDOR_KIRIN)
art->art = &logo_kirin;
else if(art->vendor == SOC_VENDOR_KUNPENG)
art->art = &logo_kunpeng;
else if(art->vendor == SOC_VENDOR_BROADCOM)
art->art = &logo_broadcom;
else if(art->vendor == SOC_VENDOR_APPLE)
art->art = &logo_apple;
else if(art->vendor == SOC_VENDOR_GOOGLE)
art->art = &logo_google;
else if(art->vendor == SOC_VENDOR_ALLWINNER)
art->art = &logo_allwinner;
else if(art->vendor == SOC_VENDOR_ROCKCHIP)
art->art = &logo_rockchip;
else if(art->vendor == SOC_VENDOR_AMPERE)
art->art = &logo_ampere;
else if(art->vendor == SOC_VENDOR_NXP)
art->art = &logo_nxp;
else if(art->vendor == SOC_VENDOR_AMLOGIC)
art->art = &logo_amlogic;
else if(art->vendor == SOC_VENDOR_MARVELL)
art->art = &logo_marvell;
else if(art->vendor == SOC_VENDOR_NVIDIA)
art->art = choose_ascii_art_aux(&logo_nvidia_l, &logo_nvidia, term, lf);
else {
art->art = choose_ascii_art_aux(&logo_arm_l, &logo_arm, term, lf);
}
#elif ARCH_RISCV
if(art->vendor == SOC_VENDOR_SIFIVE)
art->art = choose_ascii_art_aux(&logo_sifive_l, &logo_sifive, term, lf);
else if(art->vendor == SOC_VENDOR_STARFIVE)
art->art = choose_ascii_art_aux(&logo_starfive_l, &logo_starfive, term, lf);
else if(art->vendor == SOC_VENDOR_ALLWINNER)
art->art = &logo_allwinner;
else if(art->vendor == SOC_VENDOR_SIPEED)
art->art = &logo_sipeed;
else if(art->vendor == SOC_VENDOR_SPACEMIT)
art->art = &logo_spacemit;
else
art->art = &logo_riscv;
#endif
// 2. Choose colors
struct ascii_logo* logo = art->art;
bool color = is_color_enabled();
if (!color)
art->style = STYLE_LEGACY;
switch(art->style) {
case STYLE_LEGACY:
@@ -426,14 +397,13 @@ void choose_ascii_art(struct ascii* art, struct color** cs, struct terminal* ter
}
}
uint32_t longest_attribute_length(struct ascii* art, bool use_short) {
uint32_t longest_attribute_length(struct ascii* art, const char** attribute_fields) {
uint32_t max = 0;
uint64_t len = 0;
for(uint32_t i=0; i < art->n_attributes_set; i++) {
if(art->attributes[i]->value != NULL) {
const char* str = use_short ? ATTRIBUTE_INFO[art->attributes[i]->type].shortname : ATTRIBUTE_INFO[art->attributes[i]->type].name;
len = strlen(str);
len = strlen(attribute_fields[art->attributes[i]->type]);
if(len > max) max = len;
}
}
@@ -458,7 +428,7 @@ uint32_t longest_field_length(struct ascii* art, int la) {
}
#if defined(ARCH_X86) || defined(ARCH_PPC)
void print_ascii_generic(struct ascii* art, uint32_t la, int32_t termw, bool use_short, bool hybrid_architecture) {
void print_ascii_generic(struct ascii* art, uint32_t la, int32_t termw, const char** attribute_fields, bool hybrid_architecture) {
struct ascii_logo* logo = art->art;
int attr_to_print = 0;
int attr_type;
@@ -520,15 +490,14 @@ void print_ascii_generic(struct ascii* art, uint32_t la, int32_t termw, bool use
else {
#endif
beg_space = 0;
const char* attr_str = use_short ? ATTRIBUTE_INFO[attr_type].shortname : ATTRIBUTE_INFO[attr_type].name;
space_right = 2 + 1 + (la - strlen(attr_str));
space_right = 2 + 1 + (la - strlen(attribute_fields[attr_type]));
if(hybrid_architecture && add_space) {
beg_space = 2;
space_right -= 2;
}
printOut(lbuf, beg_space + strlen(attr_str) + space_right + strlen(attr_value),
"%*s%s%s%s%*s%s%s%s", beg_space, "", logo->color_text[0], attr_str, art->reset, space_right, "", logo->color_text[1], attr_value, art->reset);
printOut(lbuf, beg_space + strlen(attribute_fields[attr_type]) + space_right + strlen(attr_value),
"%*s%s%s%s%*s%s%s%s", beg_space, "", logo->color_text[0], attribute_fields[attr_type], art->reset, space_right, "", logo->color_text[1], attr_value, art->reset);
#ifdef ARCH_X86
}
#endif
@@ -582,7 +551,6 @@ bool print_cpufetch_x86(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
for(int i = 0; i < cpu->num_cpus; ptr = ptr->next_cpu, i++) {
char* max_frequency = get_str_freq(ptr->freq);
char* avx = get_str_avx(ptr);
char* sse = get_str_sse(ptr);
char* fma = get_str_fma(ptr);
char* cpu_num = emalloc(sizeof(char) * 9);
@@ -617,18 +585,8 @@ bool print_cpufetch_x86(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
setAttribute(art, ATTRIBUTE_NCORES, n_cores);
}
}
// Show the most modern vector instructions.
if (strcmp(avx, "No") == 0) {
if (strcmp(sse, "No") != 0) {
setAttribute(art, ATTRIBUTE_SSE, sse);
}
}
else {
setAttribute(art, ATTRIBUTE_AVX, avx);
setAttribute(art, ATTRIBUTE_FMA, fma);
}
setAttribute(art, ATTRIBUTE_AVX, avx);
setAttribute(art, ATTRIBUTE_FMA, fma);
if(l1i != NULL) setAttribute(art, ATTRIBUTE_L1i, l1i);
if(l1d != NULL) setAttribute(art, ATTRIBUTE_L1d, l1d);
if(l2 != NULL) setAttribute(art, ATTRIBUTE_L2, l2);
@@ -637,19 +595,19 @@ bool print_cpufetch_x86(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
setAttribute(art, ATTRIBUTE_PEAK, pp);
// Step 3. Print output
bool use_short = false;
uint32_t longest_attribute = longest_attribute_length(art, use_short);
const char** attribute_fields = ATTRIBUTE_FIELDS;
uint32_t longest_attribute = longest_attribute_length(art, attribute_fields);
uint32_t longest_field = longest_field_length(art, longest_attribute);
choose_ascii_art(art, cs, term, longest_field);
if(!ascii_fits_screen(term->w, *art->art, longest_field)) {
// Despite of choosing the smallest logo, the output does not fit
// Choose the shorter field names and recalculate the longest attr
use_short = true;
longest_attribute = longest_attribute_length(art, use_short);
attribute_fields = ATTRIBUTE_FIELDS_SHORT;
longest_attribute = longest_attribute_length(art, attribute_fields);
}
print_ascii_generic(art, longest_attribute, term->w, use_short, hybrid_architecture);
print_ascii_generic(art, longest_attribute, term->w, attribute_fields, hybrid_architecture);
free(manufacturing_process);
free(sockets);
@@ -698,14 +656,11 @@ bool print_cpufetch_ppc(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
// Step 2. Set attributes
if(cpu_name != NULL) {
setAttribute(art, ATTRIBUTE_PART_NUMBER, cpu_name);
setAttribute(art,ATTRIBUTE_NAME,cpu_name);
}
setAttribute(art, ATTRIBUTE_UARCH, uarch);
if(cpu->hv->present) {
setAttribute(art, ATTRIBUTE_HYPERVISOR, cpu->hv->hv_name);
}
setAttribute(art, ATTRIBUTE_TECHNOLOGY, manufacturing_process);
setAttribute(art, ATTRIBUTE_FREQUENCY, max_frequency);
setAttribute(art,ATTRIBUTE_UARCH,uarch);
setAttribute(art,ATTRIBUTE_TECHNOLOGY,manufacturing_process);
setAttribute(art,ATTRIBUTE_FREQUENCY,max_frequency);
uint32_t socket_num = get_nsockets(cpu->topo);
if (socket_num > 1) {
setAttribute(art, ATTRIBUTE_SOCKETS, sockets);
@@ -713,31 +668,31 @@ bool print_cpufetch_ppc(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
setAttribute(art, ATTRIBUTE_NCORES_DUAL, n_cores_dual);
}
else {
setAttribute(art, ATTRIBUTE_NCORES, n_cores);
setAttribute(art,ATTRIBUTE_NCORES, n_cores);
}
setAttribute(art, ATTRIBUTE_ALTIVEC, altivec);
setAttribute(art, ATTRIBUTE_L1i, l1i);
setAttribute(art, ATTRIBUTE_L1d, l1d);
setAttribute(art, ATTRIBUTE_L2, l2);
setAttribute(art,ATTRIBUTE_ALTIVEC, altivec);
setAttribute(art,ATTRIBUTE_L1i,l1i);
setAttribute(art,ATTRIBUTE_L1d,l1d);
setAttribute(art,ATTRIBUTE_L2,l2);
if(l3 != NULL) {
setAttribute(art, ATTRIBUTE_L3, l3);
setAttribute(art,ATTRIBUTE_L3,l3);
}
setAttribute(art, ATTRIBUTE_PEAK, pp);
setAttribute(art,ATTRIBUTE_PEAK,pp);
// Step 3. Print output
bool use_short = false;
uint32_t longest_attribute = longest_attribute_length(art, use_short);
const char** attribute_fields = ATTRIBUTE_FIELDS;
uint32_t longest_attribute = longest_attribute_length(art, attribute_fields);
uint32_t longest_field = longest_field_length(art, longest_attribute);
choose_ascii_art(art, cs, term, longest_field);
if(!ascii_fits_screen(term->w, *art->art, longest_field)) {
// Despite of choosing the smallest logo, the output does not fit
// Choose the shorter field names and recalculate the longest attr
use_short = true;
longest_attribute = longest_attribute_length(art, use_short);
attribute_fields = ATTRIBUTE_FIELDS_SHORT;
longest_attribute = longest_attribute_length(art, attribute_fields);
}
print_ascii_generic(art, longest_attribute, term->w, use_short, false);
print_ascii_generic(art, longest_attribute, term->w, attribute_fields, false);
return true;
}
@@ -765,7 +720,7 @@ uint32_t longest_field_length_arm(struct ascii* art, int la) {
return max;
}
void print_ascii_arm(struct ascii* art, uint32_t la, int32_t termw, bool use_short) {
void print_ascii_arm(struct ascii* art, uint32_t la, int32_t termw, const char** attribute_fields) {
struct ascii_logo* logo = art->art;
int attr_to_print = 0;
int attr_type;
@@ -836,15 +791,14 @@ void print_ascii_arm(struct ascii* art, uint32_t la, int32_t termw, bool use_sho
}
else {
beg_space = 0;
const char* attr_str = use_short ? ATTRIBUTE_INFO[attr_type].shortname : ATTRIBUTE_INFO[attr_type].name;
space_right = 2 + 1 + (la - strlen(attr_str));
space_right = 2 + 1 + (la - strlen(attribute_fields[attr_type]));
if(add_space) {
beg_space = 2;
space_right -= 2;
}
printOut(lbuf, beg_space + strlen(attr_str) + space_right + strlen(attr_value),
"%*s%s%s%s%*s%s%s%s", beg_space, "", logo->color_text[0], attr_str, art->reset, space_right, "", logo->color_text[1], attr_value, art->reset);
printOut(lbuf, beg_space + strlen(attribute_fields[attr_type]) + space_right + strlen(attr_value),
"%*s%s%s%s%*s%s%s%s", beg_space, "", logo->color_text[0], attribute_fields[attr_type], art->reset, space_right, "", logo->color_text[1], attr_value, art->reset);
}
}
printOutLine(lbuf, art, termw);
@@ -864,28 +818,26 @@ bool print_cpufetch_arm(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
char* manufacturing_process = get_str_process(cpu->soc);
char* soc_name = get_soc_name(cpu->soc);
char* features = get_str_features(cpu);
setAttribute(art, ATTRIBUTE_SOC, soc_name);
// Currently no reliable way to identify the specific SoC on Windows
// https://github.com/Dr-Noob/cpufetch/pull/273
// Hide manufacturing process
#if !defined(_WIN32)
// In the case that the model is unknown but the vendor isn't (this is, when
// guess_raw_soc_from_devtree succeeded), do not show the manufacturing process
// (as it will be unknown)
if (cpu->soc->model != SOC_MODEL_UNKNOWN ||
(cpu->soc->model == SOC_MODEL_UNKNOWN && cpu->soc->vendor == SOC_VENDOR_UNKNOWN))
setAttribute(art, ATTRIBUTE_TECHNOLOGY, manufacturing_process);
#endif
setAttribute(art,ATTRIBUTE_SOC,soc_name);
setAttribute(art,ATTRIBUTE_TECHNOLOGY,manufacturing_process);
if(cpu->num_cpus == 1) {
char* uarch = get_str_uarch(cpu);
char* max_frequency = get_str_freq(cpu->freq);
char* n_cores = get_str_topology(cpu, cpu->topo, false);
/*
* char* l1i = get_str_l1i(cpu->cach);
* char* l1d = get_str_l1d(cpu->cach);
* char* l2 = get_str_l2(cpu->cach);
* char* l3 = get_str_l3(cpu->cach);
* Do not setAttribute for caches.
* Cache functionality may be implemented
* in the future
*/
setAttribute(art, ATTRIBUTE_UARCH, uarch);
setAttribute(art, ATTRIBUTE_FREQUENCY, max_frequency);
setAttribute(art, ATTRIBUTE_NCORES, n_cores);
setAttribute(art,ATTRIBUTE_UARCH,uarch);
setAttribute(art,ATTRIBUTE_FREQUENCY,max_frequency);
setAttribute(art,ATTRIBUTE_NCORES,n_cores);
if(features != NULL) {
setAttribute(art, ATTRIBUTE_FEATURES, features);
}
@@ -896,8 +848,17 @@ bool print_cpufetch_arm(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
char* uarch = get_str_uarch(ptr);
char* max_frequency = get_str_freq(ptr->freq);
char* n_cores = get_str_topology(ptr, ptr->topo, false);
char* cpu_num = emalloc(sizeof(char) * 9);
/*
* char* l1i = get_str_l1i(cpu->cach);
* char* l1d = get_str_l1d(cpu->cach);
* char* l2 = get_str_l2(cpu->cach);
* char* l3 = get_str_l3(cpu->cach);
* Do not setAttribute for caches.
* Cache functionality may be implemented
* in the future
*/
char* cpu_num = emalloc(sizeof(char) * 9);
sprintf(cpu_num, "CPU %d:", i+1);
setAttribute(art, ATTRIBUTE_CPU_NUM, cpu_num);
setAttribute(art, ATTRIBUTE_UARCH, uarch);
@@ -909,13 +870,13 @@ bool print_cpufetch_arm(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
}
}
char* pp = get_str_peak_performance(cpu->peak_performance);
setAttribute(art, ATTRIBUTE_PEAK, pp);
setAttribute(art,ATTRIBUTE_PEAK,pp);
if(cpu->hv->present) {
setAttribute(art, ATTRIBUTE_HYPERVISOR, cpu->hv->hv_name);
}
bool use_short = false;
uint32_t longest_attribute = longest_attribute_length(art, use_short);
const char** attribute_fields = ATTRIBUTE_FIELDS;
uint32_t longest_attribute = longest_attribute_length(art, attribute_fields);
uint32_t longest_field = longest_field_length_arm(art, longest_attribute);
choose_ascii_art(art, cs, term, longest_field);
@@ -927,11 +888,11 @@ bool print_cpufetch_arm(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
if(!ascii_fits_screen(term->w, *art->art, longest_field)) {
// Despite of choosing the smallest logo, the output does not fit
// Choose the shorter field names and recalculate the longest attr
use_short = true;
longest_attribute = longest_attribute_length(art, use_short);
attribute_fields = ATTRIBUTE_FIELDS_SHORT;
longest_attribute = longest_attribute_length(art, attribute_fields);
}
print_ascii_arm(art, longest_attribute, term->w, use_short);
print_ascii_arm(art, longest_attribute, term->w, attribute_fields);
free(manufacturing_process);
free(pp);
@@ -948,138 +909,7 @@ bool print_cpufetch_arm(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
}
#endif
#ifdef ARCH_RISCV
void print_ascii_riscv(struct ascii* art, uint32_t la, int32_t termw, bool use_short, bool* extensions_mask) {
struct ascii_logo* logo = art->art;
int attr_to_print = 0;
int attr_type;
char* attr_value;
int32_t beg_space;
int32_t space_right;
int32_t ext_list_size = sizeof(extension_list)/sizeof(extension_list[0]);
int32_t ext_num = 0;
int32_t ext_to_print = 0;
int32_t num_extensions = get_num_extensions(extensions_mask);
int32_t space_up = ((int)logo->height - (int)(art->n_attributes_set + num_extensions))/2;
int32_t space_down = (int)logo->height - (int)(art->n_attributes_set + num_extensions) - (int)space_up;
uint32_t logo_pos = 0;
int32_t iters = max(logo->height, art->n_attributes_set + num_extensions);
struct line_buffer* lbuf = emalloc(sizeof(struct line_buffer));
lbuf->buf = emalloc(sizeof(char) * LINE_BUFFER_SIZE);
lbuf->pos = 0;
lbuf->chars = 0;
printf("\n");
for(int32_t n=0; n < iters; n++) {
// 1. Print logo
if(space_up > 0 || (space_up + n >= 0 && space_up + n < (int)logo->height)) {
for(uint32_t i=0; i < logo->width; i++) {
if(logo->art[logo_pos] == '$') {
if(logo->replace_blocks) logo_pos += 3;
else parse_print_color(art, lbuf, &logo_pos);
}
if(logo->replace_blocks && logo->art[logo_pos] != ' ') {
if(logo->art[logo_pos] == '#') printOut(lbuf, 1, "%s%c%s", logo->color_ascii[0], ' ', art->reset);
else if(logo->art[logo_pos] == '@') printOut(lbuf, 1, "%s%c%s", logo->color_ascii[1], ' ', art->reset);
else if(logo->art[logo_pos] == '%') printOut(lbuf, 1, "%s%c%s", logo->color_ascii[2], ' ', art->reset);
else printOut(lbuf, 1, "%c", logo->art[logo_pos]);
}
else
printOut(lbuf, 1, "%c", logo->art[logo_pos]);
logo_pos++;
}
printOut(lbuf, 0, "%s", art->reset);
}
else {
// If logo should not be printed, fill with spaces
printOut(lbuf, logo->width, "%*c", logo->width, ' ');
}
// 2. Print text
if(space_up < 0 || (n > space_up-1 && n < (int)logo->height - space_down)) {
attr_type = art->attributes[attr_to_print]->type;
attr_value = art->attributes[attr_to_print]->value;
// Print extension
if(attr_to_print > 0 && art->attributes[attr_to_print-1]->type == ATTRIBUTE_EXTENSIONS && ext_num != num_extensions) {
// Search for the extension to print
while (ext_to_print < ext_list_size && !((extensions_mask[extension_list[ext_to_print].id])))
ext_to_print++;
if(ext_to_print == ext_list_size) {
printBug("print_ascii_riscv: Unable to find the extension to print");
}
printOut(lbuf, 3 + strlen(extension_list[ext_to_print].str), "%s - %s%s", logo->color_text[0], extension_list[ext_to_print].str, art->reset);
ext_num++;
ext_to_print++;
}
else {
attr_to_print++;
beg_space = 0;
const char* attr_str = use_short ? ATTRIBUTE_INFO[attr_type].shortname : ATTRIBUTE_INFO[attr_type].name;
space_right = 2 + 1 + (la - strlen(attr_str));
printOut(lbuf, beg_space + strlen(attr_str) + space_right + strlen(attr_value),
"%*s%s%s%s%*s%s%s%s", beg_space, "", logo->color_text[0], attr_str, art->reset, space_right, "", logo->color_text[1], attr_value, art->reset);
}
}
printOutLine(lbuf, art, termw);
printf("\n");
}
printf("\n");
free(lbuf->buf);
free(lbuf);
}
bool print_cpufetch_riscv(struct cpuInfo* cpu, STYLE s, struct color** cs, struct terminal* term) {
struct ascii* art = set_ascii(get_soc_vendor(cpu->soc), s);
if(art == NULL)
return false;
// Step 1. Retrieve attributes
char* uarch = get_str_uarch(cpu);
char* manufacturing_process = get_str_process(cpu->soc);
char* soc_name = get_soc_name(cpu->soc);
char* extensions = get_str_extensions(cpu);
char* max_frequency = get_str_freq(cpu->freq);
char* n_cores = get_str_topology(cpu, cpu->topo);
char* pp = get_str_peak_performance(cpu->peak_performance);
// Step 2. Set attributes
setAttribute(art, ATTRIBUTE_SOC, soc_name);
setAttribute(art, ATTRIBUTE_TECHNOLOGY, manufacturing_process);
setAttribute(art, ATTRIBUTE_UARCH, uarch);
setAttribute(art, ATTRIBUTE_NCORES, n_cores);
setAttribute(art, ATTRIBUTE_FREQUENCY, max_frequency);
if(extensions != NULL) {
setAttribute(art, ATTRIBUTE_EXTENSIONS, extensions);
}
setAttribute(art, ATTRIBUTE_PEAK, pp);
// Step 3. Print output
bool use_short = false;
uint32_t longest_attribute = longest_attribute_length(art, use_short);
uint32_t longest_field = longest_field_length(art, longest_attribute);
choose_ascii_art(art, cs, term, longest_field);
if(!ascii_fits_screen(term->w, *art->art, longest_field)) {
// Despite of choosing the smallest logo, the output does not fit
// Choose the shorter field names and recalculate the longest attr
use_short = true;
longest_attribute = longest_attribute_length(art, use_short);
}
print_ascii_riscv(art, longest_attribute, term->w, use_short, cpu->ext->mask);
return true;
}
#endif
struct terminal* get_terminal_size(void) {
struct terminal* get_terminal_size() {
struct terminal* term = emalloc(sizeof(struct terminal));
#ifdef _WIN32
@@ -1116,7 +946,5 @@ bool print_cpufetch(struct cpuInfo* cpu, STYLE s, struct color** cs, bool show_f
return print_cpufetch_ppc(cpu, s, cs, term, show_full_cpu_name);
#elif ARCH_ARM
return print_cpufetch_arm(cpu, s, cs, term);
#elif ARCH_RISCV
return print_cpufetch_riscv(cpu, s, cs, term);
#endif
}

4
src/common/printer.h
View File

@@ -11,8 +11,6 @@ typedef int STYLE;
#include "../ppc/ppc.h"
#elif ARCH_ARM
#include "../arm/midr.h"
#elif ARCH_RISCV
#include "../riscv/riscv.h"
#endif
// +-----------------------------------+-----------------------+
@@ -23,8 +21,6 @@ typedef int STYLE;
#define COLOR_DEFAULT_AMD "250,250,250:000,154,102:000,000,000:250,250,250:000,154,102"
#define COLOR_DEFAULT_IBM "092,119,172:092,119,172:000,000,000:240,240,240:092,119,172"
#define COLOR_DEFAULT_ARM "000,145,189:000,145,189:000,000,000:240,240,240:000,145,189"
#define COLOR_DEFAULT_ROCKCHIP "114,159,207:229,195,000:000,000,000:240,240,240:114,159,207"
#define COLOR_DEFAULT_SIFIVE "255,255,255:000,000,000:000,000,000:255,255,255:000,000,000"
#ifdef ARCH_X86
void print_levels(struct cpuInfo* cpu);

117
src/common/soc.c
View File

@@ -1,117 +0,0 @@
#include "soc.h"
#ifdef ARCH_ARM
#include "../arm/socs.h"
#elif ARCH_RISCV
#include "../riscv/socs.h"
#endif
#include "udev.h"
#include "../common/global.h"
#include <string.h>
static char* soc_trademark_string[] = {
// ARM
[SOC_VENDOR_SNAPDRAGON] = "Snapdragon ",
[SOC_VENDOR_MEDIATEK] = "MediaTek ",
[SOC_VENDOR_EXYNOS] = "Exynos ",
[SOC_VENDOR_KIRIN] = "Kirin ",
[SOC_VENDOR_KUNPENG] = "Kunpeng ",
[SOC_VENDOR_BROADCOM] = "Broadcom ",
[SOC_VENDOR_APPLE] = "Apple ",
[SOC_VENDOR_ROCKCHIP] = "Rockchip ",
[SOC_VENDOR_GOOGLE] = "Google ",
[SOC_VENDOR_NVIDIA] = "NVIDIA ",
[SOC_VENDOR_AMPERE] = "Ampere ",
[SOC_VENDOR_NXP] = "NXP ",
[SOC_VENDOR_AMLOGIC] = "Amlogic ",
[SOC_VENDOR_MARVELL] = "Marvell",
// RISC-V
[SOC_VENDOR_SIFIVE] = "SiFive ",
[SOC_VENDOR_STARFIVE] = "StarFive ",
[SOC_VENDOR_SIPEED] = "Sipeed ",
[SOC_VENDOR_SPACEMIT] = "SpacemiT ",
// ARM & RISC-V
[SOC_VENDOR_ALLWINNER] = "Allwinner "
};
VENDOR get_soc_vendor(struct system_on_chip* soc) {
return soc->vendor;
}
char* get_str_process(struct system_on_chip* soc) {
char* str;
if(soc->process == UNKNOWN) {
str = emalloc(sizeof(char) * (strlen(STRING_UNKNOWN)+1));
snprintf(str, strlen(STRING_UNKNOWN)+1, STRING_UNKNOWN);
}
else {
int max_process_len = 5 + 1;
str = ecalloc(max_process_len, sizeof(char));
snprintf(str, max_process_len, "%dnm", soc->process);
}
return str;
}
char* get_soc_name(struct system_on_chip* soc) {
if(soc->model == SOC_MODEL_UNKNOWN)
return soc->raw_name;
return soc->name;
}
void fill_soc(struct system_on_chip* soc, char* soc_name, SOC soc_model, int32_t process) {
soc->model = soc_model;
soc->vendor = get_soc_vendor_from_soc(soc_model);
soc->process = process;
if(soc->vendor == SOC_VENDOR_UNKNOWN) {
printBug("fill_soc: soc->vendor == SOC_VENDOR_UNKOWN");
// If we fall here there is a bug in socs.h
// Reset everything to avoid segfault
soc->vendor = SOC_VENDOR_UNKNOWN;
soc->model = SOC_MODEL_UNKNOWN;
soc->process = UNKNOWN;
soc->raw_name = emalloc(sizeof(char) * (strlen(STRING_UNKNOWN)+1));
snprintf(soc->raw_name, strlen(STRING_UNKNOWN)+1, STRING_UNKNOWN);
}
else {
int len = strlen(soc_name) + strlen(soc_trademark_string[soc->vendor]) + 1;
soc->name = emalloc(sizeof(char) * len);
sprintf(soc->name, "%s%s", soc_trademark_string[soc->vendor], soc_name);
}
}
void fill_soc_raw(struct system_on_chip* soc, char* soc_name, VENDOR vendor) {
soc->model = SOC_MODEL_UNKNOWN;
soc->vendor = vendor;
soc->process = UNKNOWN;
int len = strlen(soc_name) + strlen(soc_trademark_string[soc->vendor]) + 1;
soc->raw_name = emalloc(sizeof(char) * len);
sprintf(soc->raw_name, "%s%s", soc_trademark_string[soc->vendor], soc_name);
}
#ifdef _WIN32
VENDOR try_match_soc_vendor_name(char* vendor_name)
{
for(size_t i=1; i < sizeof(soc_trademark_string)/sizeof(soc_trademark_string[0]); i++) {
if(strstr(vendor_name, soc_trademark_string[i]) != NULL) {
return i;
}
}
return SOC_VENDOR_UNKNOWN;
}
#endif
bool match_soc(struct system_on_chip* soc, char* raw_name, char* expected_name, char* soc_name, SOC soc_model, int32_t process) {
int len1 = strlen(raw_name);
int len2 = strlen(expected_name);
int len = min(len1, len2);
if(strncmp(raw_name, expected_name, len) != 0) {
return false;
}
else {
fill_soc(soc, soc_name, soc_model, process);
return true;
}
}

65
src/common/soc.h
View File

@@ -1,65 +0,0 @@
#ifndef __SOC__
#define __SOC__
// NOTE:
// soc.c/soc.h are used by
// ARM and RISC-V backends
#include "../common/cpu.h"
#include <stdint.h>
#define UNKNOWN -1
typedef int32_t SOC;
enum {
SOC_VENDOR_UNKNOWN,
// ARM
SOC_VENDOR_SNAPDRAGON,
SOC_VENDOR_MEDIATEK,
SOC_VENDOR_EXYNOS,
SOC_VENDOR_KIRIN,
SOC_VENDOR_KUNPENG,
SOC_VENDOR_BROADCOM,
SOC_VENDOR_APPLE,
SOC_VENDOR_ROCKCHIP,
SOC_VENDOR_GOOGLE,
SOC_VENDOR_NVIDIA,
SOC_VENDOR_AMPERE,
SOC_VENDOR_NXP,
SOC_VENDOR_AMLOGIC,
SOC_VENDOR_MARVELL,
// RISC-V
SOC_VENDOR_SIFIVE,
SOC_VENDOR_STARFIVE,
SOC_VENDOR_SIPEED,
SOC_VENDOR_SPACEMIT,
// ARM & RISC-V
SOC_VENDOR_ALLWINNER
};
struct system_on_chip {
SOC model;
VENDOR vendor;
int32_t process;
char* name;
char* raw_name;
};
struct system_on_chip* get_soc(struct cpuInfo* cpu);
char* get_soc_name(struct system_on_chip* soc);
VENDOR get_soc_vendor(struct system_on_chip* soc);
bool match_soc(struct system_on_chip* soc, char* raw_name, char* expected_name, char* soc_name, SOC soc_model, int32_t process);
char* get_str_process(struct system_on_chip* soc);
void fill_soc(struct system_on_chip* soc, char* soc_name, SOC soc_model, int32_t process);
void fill_soc_raw(struct system_on_chip* soc, char* soc_name, VENDOR vendor);
#ifdef _WIN32
VENDOR try_match_soc_vendor_name(char* vendor_name);
#endif
#define SOC_START if (false) {}
#define SOC_EQ(raw_name, expected_name, soc_name, soc_model, soc, process) \
else if (match_soc(soc, raw_name, expected_name, soc_name, soc_model, process)) return true;
#define SOC_END else { return false; }
#endif

179
src/common/udev.c
View File

@@ -1,12 +1,9 @@
#include "../common/global.h"
#include "udev.h"
#include "global.h"
#include "cpu.h"
#define _PATH_DEVTREE "/proc/device-tree/compatible"
// https://www.kernel.org/doc/html/latest/core-api/cpu_hotplug.html
int get_ncores_from_cpuinfo(void) {
int get_ncores_from_cpuinfo() {
// Examples:
// 0-271
// 0-7
@@ -132,26 +129,6 @@ long get_cache_size_from_file(char* path) {
return ret * 1024;
}
char* get_field_from_cpuinfo(char* CPUINFO_FIELD) {
int filelen;
char* buf;
if((buf = read_file(_PATH_CPUINFO, &filelen)) == NULL) {
printWarn("read_file: %s: %s:\n", _PATH_CPUINFO, strerror(errno));
return NULL;
}
char* tmp1 = strstr(buf, CPUINFO_FIELD);
if(tmp1 == NULL) return NULL;
tmp1 = tmp1 + strlen(CPUINFO_FIELD);
char* tmp2 = strstr(tmp1, "\n");
int strlen = (1 + (tmp2-tmp1));
char* hardware = ecalloc(strlen, sizeof(char));
strncpy(hardware, tmp1, tmp2-tmp1);
return hardware;
}
long get_max_freq_from_file(uint32_t core) {
char path[_PATH_FREQUENCY_MAX_LEN];
sprintf(path, "%s%s/cpu%d%s%s", _PATH_SYS_SYSTEM, _PATH_SYS_CPU, core, _PATH_FREQUENCY, _PATH_FREQUENCY_MAX);
@@ -201,13 +178,7 @@ bool maps_equal(uint32_t* map1, uint32_t* map2, int n) {
return true;
}
// Generic function to count the number of distinct
// elements in the list of files passed in char** paths.
// An element can be potentially anything.
// We use this function to count:
// - The number of caches
// - The number of sockets
int get_num_elements_from_files(char** paths, int num_paths) {
int get_num_caches_from_files(char** paths, int num_paths) {
int filelen;
char* buf;
char* tmpbuf;
@@ -222,10 +193,10 @@ int get_num_elements_from_files(char** paths, int num_paths) {
num_bitmasks += (buf[i] == ',');
}
// 2. Read map from every core
uint32_t** maps = emalloc(sizeof(uint32_t *) * num_paths);
// 2. Read cpu_shared_map from every core
uint32_t** shared_maps = emalloc(sizeof(uint32_t *) * num_paths);
for(int i=0; i < num_paths; i++) {
maps[i] = emalloc(sizeof(uint32_t) * num_bitmasks);
shared_maps[i] = emalloc(sizeof(uint32_t) * num_bitmasks);
if((buf = read_file(paths[i], &filelen)) == NULL) {
printWarn("Could not open '%s'", paths[i]);
@@ -235,7 +206,6 @@ int get_num_elements_from_files(char** paths, int num_paths) {
for(int j=0; j < num_bitmasks; j++) {
char* end;
tmpbuf = emalloc(sizeof(char) * (strlen(buf) + 1));
memset(tmpbuf, 0, sizeof(char) * (strlen(buf) + 1));
char* commaend = strstr(buf, ",");
if(commaend == NULL) {
strcpy(tmpbuf, buf);
@@ -251,43 +221,35 @@ int get_num_elements_from_files(char** paths, int num_paths) {
return -1;
}
maps[i][j] = (uint32_t) ret;
shared_maps[i][j] = (uint32_t) ret;
buf = commaend + 1;
free(tmpbuf);
}
}
// 2. Count number of different masks; this is the number of elements
int num_elements = 0;
// 2. Count number of different masks; this is the number of caches
int num_caches = 0;
bool found = false;
uint32_t** unique_maps = emalloc(sizeof(uint32_t *) * num_paths);
uint32_t** unique_shared_maps = emalloc(sizeof(uint32_t *) * num_paths);
for(int i=0; i < num_paths; i++) {
unique_maps[i] = emalloc(sizeof(uint32_t) * num_bitmasks);
unique_shared_maps[i] = emalloc(sizeof(uint32_t) * num_bitmasks);
for(int j=0; j < num_bitmasks; j++) {
unique_maps[i][j] = 0;
unique_shared_maps[i][j] = 0;
}
}
for(int i=0; i < num_paths; i++) {
for(int j=0; j < num_paths && !found; j++) {
if(maps_equal(maps[i], unique_maps[j], num_bitmasks)) found = true;
if(maps_equal(shared_maps[i], unique_shared_maps[j], num_bitmasks)) found = true;
}
if(!found) {
add_shared_map(maps, i, unique_maps, num_elements, num_bitmasks);
num_elements++;
add_shared_map(shared_maps, i, unique_shared_maps, num_caches, num_bitmasks);
num_caches++;
}
found = false;
}
return num_elements;
}
int get_num_caches_from_files(char** paths, int num_paths) {
return get_num_elements_from_files(paths, num_paths);
}
int get_num_sockets_from_files(char** paths, int num_paths) {
return get_num_elements_from_files(paths, num_paths);
return num_caches;
}
int get_num_caches_by_level(struct cpuInfo* cpu, uint32_t level) {
@@ -316,114 +278,3 @@ int get_num_caches_by_level(struct cpuInfo* cpu, uint32_t level) {
return ret;
}
int get_num_sockets_package_cpus(struct topology* topo) {
// Get number of sockets using
// /sys/devices/system/cpu/cpu*/topology/package_cpus
char** paths = emalloc(sizeof(char *) * topo->total_cores);
for(int i=0; i < topo->total_cores; i++) {
paths[i] = emalloc(sizeof(char) * _PATH_PACKAGE_MAX_LEN);
sprintf(paths[i], "%s%s/cpu%d%s", _PATH_SYS_SYSTEM, _PATH_SYS_CPU, i, _PATH_TOPO_PACKAGE_CPUS);
}
int ret = get_num_sockets_from_files(paths, topo->total_cores);
for(int i=0; i < topo->total_cores; i++)
free(paths[i]);
free(paths);
return ret;
}
// Inspired in is_devtree_compatible from lscpu
bool is_devtree_compatible(char* str) {
int filelen;
char* buf;
if((buf = read_file("/proc/device-tree/compatible", &filelen)) == NULL) {
return false;
}
char* tmp;
if((tmp = strstr(buf, str)) == NULL) {
return false;
}
return true;
}
char* get_devtree_compatible(int *filelen) {
char* buf;
if ((buf = read_file(_PATH_DEVTREE, filelen)) == NULL) {
printWarn("read_file: %s: %s", _PATH_DEVTREE, strerror(errno));
}
return buf;
}
// Returns a list of structs devtree, each containing both the vendor and the
// model, coming from the compatible file from the device tree. In this
// context, vendor refers to the first string of every entry and the model to
// the second. For instance, given a compatible file with:
// "str1,foo1.str2,foo2" (where . denotes the NULL byte, i.e., the separator),
// then this function will return a list with two structs, the first one
// containing str1 and foo1 and the other containing str2 and foo2.
struct devtree** get_devtree_compatible_struct(int *num_vendors_ptr) {
int len;
char* dt = get_devtree_compatible(&len);
if (dt == NULL) {
return NULL;
}
int num_vendors = 0;
char* ptr = dt;
for (int ptrpos = 0; ptrpos < len; ptrpos = (ptr-dt)) {
ptr = memchr(ptr, '\0', len);
if (ptr == NULL) {
printBug("get_devtree_compatible_struct: Unable to find delimiter (1) (num_vendors=%d)", num_vendors);
return NULL;
}
ptr++;
num_vendors++;
}
struct devtree** vendors = emalloc(sizeof(struct devtree *) * num_vendors);
ptr = dt;
for (int ptrpos = 0, i = 0; ptrpos < len; ptrpos = (ptr-dt), i++) {
char* comma_ptr = strstr(ptr, ",");
if (comma_ptr == NULL) {
printBug("get_devtree_compatible_struct: Unable to find comma (num_vendors=%d)", num_vendors);
return NULL;
}
comma_ptr = comma_ptr-1; // Point right before comma
char* end_ptr = memchr(comma_ptr, '\0', len - ptrpos);
if (end_ptr == NULL) {
printBug("get_devtree_compatible_struct: Unable to find delimiter (2) (num_vendors=%d)", num_vendors);
return NULL;
}
int vendor_str_len = (comma_ptr-ptr)+1;
int model_str_len = (end_ptr-(comma_ptr+2))+1;
vendors[i] = emalloc(sizeof(struct devtree));
vendors[i]->vendor = ecalloc(vendor_str_len, sizeof(char));
vendors[i]->model = ecalloc(model_str_len, sizeof(char));
strncpy(vendors[i]->vendor, ptr, vendor_str_len);
strncpy(vendors[i]->model, comma_ptr+2, model_str_len);
ptr = memchr(ptr, '\0', len);
if (ptr == NULL) {
printBug("get_devtree_compatible_struct: Unable to find delimiter (3) (num_vendors=%d)", num_vendors);
return NULL;
}
ptr++; // Point right after delimiter
}
*num_vendors_ptr = num_vendors;
return vendors;
}

17
src/common/udev.h
View File

@@ -12,7 +12,6 @@
#include "cpu.h"
#define _PATH_CPUINFO "/proc/cpuinfo"
#define _PATH_SYS_SYSTEM "/sys/devices/system"
#define _PATH_SYS_CPU "/cpu"
#define _PATH_FREQUENCY "/cpufreq"
@@ -24,17 +23,10 @@
#define _PATH_CACHE_L3 "/cache/index3"
#define _PATH_CACHE_SIZE "/size"
#define _PATH_CACHE_SHARED_MAP "/shared_cpu_map"
#define _PATH_CPUS_PRESENT _PATH_SYS_SYSTEM _PATH_SYS_CPU "/present"
#define _PATH_TOPO_PACKAGE_CPUS "/topology/package_cpus"
#define _PATH_CPUS_PRESENT _PATH_SYS_SYSTEM _PATH_SYS_CPU "/present"
#define _PATH_FREQUENCY_MAX_LEN 100
#define _PATH_CACHE_MAX_LEN 200
#define _PATH_PACKAGE_MAX_LEN 200
struct devtree {
char* vendor;
char* model;
};
char* read_file(char* path, int* len);
long get_max_freq_from_file(uint32_t core);
@@ -44,11 +36,6 @@ long get_l1d_cache_size(uint32_t core);
long get_l2_cache_size(uint32_t core);
long get_l3_cache_size(uint32_t core);
int get_num_caches_by_level(struct cpuInfo* cpu, uint32_t level);
int get_num_sockets_package_cpus(struct topology* topo);
int get_ncores_from_cpuinfo(void);
char* get_field_from_cpuinfo(char* CPUINFO_FIELD);
bool is_devtree_compatible(char* str);
char* get_devtree_compatible(int *filelen);
struct devtree** get_devtree_compatible_struct(int *num_vendors);
int get_ncores_from_cpuinfo();
#endif

90
src/ppc/ppc.c
View File

@@ -11,20 +11,6 @@
#include "../common/udev.h"
#include "../common/global.h"
static char *hv_vendors_name[] = {
[HV_VENDOR_KVM] = "KVM",
[HV_VENDOR_QEMU] = "QEMU",
[HV_VENDOR_VBOX] = "VirtualBox",
[HV_VENDOR_HYPERV] = "Microsoft Hyper-V",
[HV_VENDOR_VMWARE] = "VMware",
[HV_VENDOR_XEN] = "Xen",
[HV_VENDOR_PARALLELS] = "Parallels",
[HV_VENDOR_PHYP] = "pHyp",
[HV_VENDOR_BHYVE] = "bhyve",
[HV_VENDOR_APPLEVZ] = "Apple VZ",
[HV_VENDOR_INVALID] = STRING_UNKNOWN
};
struct cache* get_cache_info(struct cpuInfo* cpu) {
struct cache* cach = emalloc(sizeof(struct cache));
init_cache_struct(cach);
@@ -77,34 +63,23 @@ struct topology* get_topology_info(struct cache* cach) {
printWarn("fill_core_ids_from_sys failed, output may be incomplete/invalid");
for(int i=0; i < topo->total_cores; i++) core_ids[i] = 0;
}
if(!fill_package_ids_from_sys(package_ids, topo->total_cores)) {
printWarn("fill_package_ids_from_sys failed, output may be incomplete/invalid");
for(int i=0; i < topo->total_cores; i++) package_ids[i] = 0;
// fill_package_ids_from_sys failed, use udev to try
// to find the number of sockets
topo->sockets = get_num_sockets_package_cpus(topo);
if (topo->sockets == UNKNOWN_DATA) {
printWarn("get_num_sockets_package_cpus failed: assuming 1 socket");
topo->sockets = 1;
}
}
else {
// fill_package_ids_from_sys succeeded, use the
// traditional socket detection algorithm
int *package_ids_count = emalloc(sizeof(int) * topo->total_cores);
for(int i=0; i < topo->total_cores; i++) {
package_ids_count[i] = 0;
// 2. Socket detection
int *package_ids_count = emalloc(sizeof(int) * topo->total_cores);
for(int i=0; i < topo->total_cores; i++) {
package_ids_count[i] = 0;
}
for(int i=0; i < topo->total_cores; i++) {
package_ids_count[package_ids[i]]++;
}
for(int i=0; i < topo->total_cores; i++) {
if(package_ids_count[i] != 0) {
topo->sockets++;
}
for(int i=0; i < topo->total_cores; i++) {
package_ids_count[package_ids[i]]++;
}
for(int i=0; i < topo->total_cores; i++) {
if(package_ids_count[i] != 0) {
topo->sockets++;
}
}
free(package_ids_count);
}
// 3. Physical cores detection
@@ -130,12 +105,13 @@ struct topology* get_topology_info(struct cache* cach) {
free(core_ids);
free(package_ids);
free(package_ids_count);
free(core_ids_unified);
return topo;
}
static inline uint32_t mfpvr(void) {
static inline uint32_t mfpvr() {
uint32_t pvr;
asm ("mfpvr %0"
@@ -147,19 +123,12 @@ struct uarch* get_cpu_uarch(struct cpuInfo* cpu) {
return get_uarch_from_pvr(cpu->pvr);
}
struct frequency* get_frequency_info(void) {
struct frequency* get_frequency_info() {
struct frequency* freq = emalloc(sizeof(struct frequency));
freq->measured = false;
freq->max = get_max_freq_from_file(0);
freq->base = get_min_freq_from_file(0);
if(freq->max == UNKNOWN_DATA) {
// If we are unable to find it in the
// standard path, try /proc/cpuinfo
freq->max = get_frequency_from_cpuinfo();
}
return freq;
}
@@ -189,29 +158,7 @@ int64_t get_peak_performance(struct cpuInfo* cpu, struct topology* topo, int64_t
return flops;
}
struct hypervisor* get_hp_info(void) {
struct hypervisor* hv = emalloc(sizeof(struct hypervisor));
hv->present = false;
// Weird heuristic found in lscpu:
// https://github.com/util-linux/util-linux/blob/master/sys-utils/lscpu-virt.c
if(access("/proc" _PATH_DT_IBM_PARTIT_NAME, F_OK) == 0 &&
access("/proc" _PATH_DT_HMC_MANAGED, F_OK) == 0 &&
access("/proc" _PATH_DT_QEMU_WIDTH, F_OK) != 0) {
hv->present = true;
hv->hv_vendor = HV_VENDOR_PHYP;
}
else if(is_devtree_compatible("qemu,pseries")) {
hv->present = true;
hv->hv_vendor = HV_VENDOR_QEMU;
}
hv->hv_name = hv_vendors_name[hv->hv_vendor];
return hv;
}
struct cpuInfo* get_cpu_info(void) {
struct cpuInfo* get_cpu_info() {
struct cpuInfo* cpu = emalloc(sizeof(struct cpuInfo));
struct features* feat = emalloc(sizeof(struct features));
cpu->feat = feat;
@@ -225,11 +172,8 @@ struct cpuInfo* get_cpu_info(void) {
char* path = emalloc(sizeof(char) * (strlen(_PATH_DT) + strlen(_PATH_DT_PART) + 1));
sprintf(path, "%s%s", _PATH_DT, _PATH_DT_PART);
if((cpu->cpu_name = read_file(path, &len)) == NULL) {
printWarn("Could not open '%s'", path);
}
cpu->cpu_name = read_file(path, &len);
cpu->pvr = mfpvr();
cpu->hv = get_hp_info();
cpu->arch = get_cpu_uarch(cpu);
cpu->freq = get_frequency_info();
cpu->topo = get_topology_info(cpu->cach);

2
src/ppc/ppc.h
View File

@@ -3,7 +3,7 @@
#include "../common/cpu.h"
struct cpuInfo* get_cpu_info(void);
struct cpuInfo* get_cpu_info();
char* get_str_altivec(struct cpuInfo* cpu);
char* get_str_topology(struct topology* topo, bool dual_socket);
void print_debug(struct cpuInfo* cpu);

25
src/ppc/uarch.c
View File

@@ -25,7 +25,6 @@ enum {
UARCH_PPC603,
UARCH_PPC440,
UARCH_PPC470,
UARCH_ESPRESSO, // Not exactly an uarch, but the codename of Wii U
UARCH_PPC970,
UARCH_PPC970FX,
UARCH_PPC970MP,
@@ -36,7 +35,6 @@ enum {
UARCH_POWER7,
UARCH_POWER7PLUS,
UARCH_POWER8,
UARCH_POWER8_DD21,
UARCH_POWER9,
UARCH_POWER9_DD20,
UARCH_POWER9_DD21,
@@ -76,7 +74,6 @@ void fill_uarch(struct uarch* arch, MICROARCH u) {
FILL_UARCH(arch->uarch, UARCH_PPC603, "PowerPC 603", UNK) // varies
FILL_UARCH(arch->uarch, UARCH_PPC440, "PowerPC 440", UNK)
FILL_UARCH(arch->uarch, UARCH_PPC470, "PowerPC 470", 45) // strange...
FILL_UARCH(arch->uarch, UARCH_ESPRESSO, "Espresso", 45) // https://en.wikipedia.org/wiki/PowerPC_7xx#Espresso, https://en.wikipedia.org/wiki/Espresso_(processor), https://github.com/Dr-Noob/cpufetch/issues/231
FILL_UARCH(arch->uarch, UARCH_PPC970, "PowerPC 970", 130)
FILL_UARCH(arch->uarch, UARCH_PPC970FX, "PowerPC 970FX", 90)
FILL_UARCH(arch->uarch, UARCH_PPC970MP, "PowerPC 970MP", 90)
@@ -87,7 +84,6 @@ void fill_uarch(struct uarch* arch, MICROARCH u) {
FILL_UARCH(arch->uarch, UARCH_POWER7, "POWER7", 45)
FILL_UARCH(arch->uarch, UARCH_POWER7PLUS, "POWER7+", 32)
FILL_UARCH(arch->uarch, UARCH_POWER8, "POWER8", 22)
FILL_UARCH(arch->uarch, UARCH_POWER8_DD21, "POWER8 (DD2.1)", 22)
FILL_UARCH(arch->uarch, UARCH_POWER9, "POWER9", 14)
FILL_UARCH(arch->uarch, UARCH_POWER9_DD20, "POWER9 (DD2.0)", 14)
FILL_UARCH(arch->uarch, UARCH_POWER9_DD21, "POWER9 (DD2.1)", 14)
@@ -104,19 +100,7 @@ void fill_uarch(struct uarch* arch, MICROARCH u) {
}
/*
* PVR masks/values from Linux kernel:
* - arch/powerpc/kernel/cputable.c (kernel <= 6.0)
* - arch/powerpc/kernel/cpu_specs_book3s_64.h (kernel >= 6.1)
*
* In the kernel, there is a POWER8E identifier. In
* https://wiki.raptorcs.com/wiki/POWER8E it says it is
* actually DD2.1, while other POWER8 should be DD2.0.
* The last assumption does not seem to be correct according
* to https://openbenchmarking.org/s/POWER8NVL, which shows a
* POWER8NVL where kernel says it is DD1.0. We implement this
* to show only the uarch, not the revision, since it seems a bit
* redundant?
*
* PVR masks/values from arch/powerpc/kernel/cputable.c (Linux kernel)
* This list may be incorrect, incomplete or overly simplified,
* specially in the case of 32 bit entries
*/
@@ -141,7 +125,7 @@ struct uarch* get_uarch_from_pvr(uint32_t pvr) {
CHECK_UARCH(arch, pvr, 0xffffffff, 0x0f000006, UARCH_POWER10)
CHECK_UARCH(arch, pvr, 0xffff0000, 0x003f0000, UARCH_POWER7)
CHECK_UARCH(arch, pvr, 0xffff0000, 0x004A0000, UARCH_POWER7PLUS)
CHECK_UARCH(arch, pvr, 0xffff0000, 0x004b0000, UARCH_POWER8_DD21)
CHECK_UARCH(arch, pvr, 0xffff0000, 0x004b0000, UARCH_POWER8)
CHECK_UARCH(arch, pvr, 0xffff0000, 0x004c0000, UARCH_POWER8)
CHECK_UARCH(arch, pvr, 0xffff0000, 0x004d0000, UARCH_POWER8)
CHECK_UARCH(arch, pvr, 0xffffefff, 0x004e0200, UARCH_POWER9_DD20)
@@ -236,7 +220,6 @@ struct uarch* get_uarch_from_pvr(uint32_t pvr) {
CHECK_UARCH(arch, pvr, 0xffff0000, 0x7ff50000, UARCH_PPC470)
CHECK_UARCH(arch, pvr, 0xffff0000, 0x00050000, UARCH_PPC470)
CHECK_UARCH(arch, pvr, 0xffff0000, 0x11a50000, UARCH_PPC470)
CHECK_UARCH(arch, pvr, 0xffffffff, 0x70010201, UARCH_ESPRESSO)
UARCH_END
return arch;
@@ -251,7 +234,6 @@ bool has_altivec(struct uarch* arch) {
case UARCH_POWER7:
case UARCH_POWER7PLUS:
case UARCH_POWER8:
case UARCH_POWER8_DD21:
case UARCH_POWER9:
case UARCH_POWER9_DD20:
case UARCH_POWER9_DD21:
@@ -283,6 +265,9 @@ char* get_str_process(struct cpuInfo* cpu) {
if(process == UNK) {
snprintf(str, strlen(STRING_UNKNOWN)+1, STRING_UNKNOWN);
}
else if(process > 100) {
sprintf(str, "%.2fum", (double)process/100);
}
else if(process > 0){
sprintf(str, "%dnm", process);
}

56
src/ppc/udev.c
View File

@@ -1,19 +1,16 @@
#include <errno.h>
#include "../common/udev.h"
#include "../common/global.h"
#include "udev.h"
#define _PATH_TOPO_CORE_ID "topology/core_id"
#define _PATH_TOPO_PACKAGE_ID "topology/physical_package_id"
#define CPUINFO_FREQUENCY_STR "clock\t\t: "
#define _PATH_TOPO_CORE_ID "topology/core_id"
#define _PATH_TOPO_PACKAGE_ID "topology/physical_package_id"
bool fill_array_from_sys(int *core_ids, int total_cores, char* SYS_PATH) {
int filelen;
char* buf;
char* end;
char path[128];
memset(name, 0, sizeof(char) * 128);
for(int i=0; i < total_cores; i++) {
sprintf(path, "%s%s/cpu%d/%s", _PATH_SYS_SYSTEM, _PATH_SYS_CPU, i, SYS_PATH);
@@ -39,52 +36,5 @@ bool fill_core_ids_from_sys(int *core_ids, int total_cores) {
}
bool fill_package_ids_from_sys(int* package_ids, int total_cores) {
bool status = fill_array_from_sys(package_ids, total_cores, _PATH_TOPO_PACKAGE_ID);
if(status) {
// fill_array_from_sys completed successfully, but we
// must to check the integrity of the package_ids array
for(int i=0; i < total_cores; i++) {
if(package_ids[i] == -1) {
printWarn("fill_package_ids_from_sys: package_ids[%d] = -1", i);
return false;
}
else if(package_ids[i] >= total_cores || package_ids[i] < 0) {
printBug("fill_package_ids_from_sys: package_ids[%d] = %d", i, package_ids[i]);
return false;
}
}
return true;
}
return false;
}
long get_frequency_from_cpuinfo(void) {
char* freq_str = get_field_from_cpuinfo(CPUINFO_FREQUENCY_STR);
if(freq_str == NULL) {
return UNKNOWN_DATA;
}
else {
// freq_str should be in the form XXXX.YYYYYYMHz
char* dot = strstr(freq_str, ".");
freq_str[dot-freq_str] = '\0';
char* end;
errno = 0;
long ret = strtol(freq_str, &end, 10);
if(errno != 0) {
printBug("strtol: %s", strerror(errno));
free(freq_str);
return UNKNOWN_DATA;
}
// We consider it an error if frequency is
// greater than 10 GHz or less than 100 MHz
if(ret > 10000 || ret < 100) {
printBug("Invalid data was read from file '%s': %ld\n", CPUINFO_FREQUENCY_STR, ret);
return UNKNOWN_DATA;
}
return ret;
}
return fill_array_from_sys(package_ids, total_cores, _PATH_TOPO_PACKAGE_ID);
}

9
src/ppc/udev.h
View File

@@ -2,15 +2,10 @@
#define __UDEV_PPC__
#include "../common/udev.h"
#define _PATH_DT "/proc/device-tree/vpd/root-node-vpd@a000/enclosure@1e00/backplane@800/processor@1000"
#define _PATH_DT_PART "/part-number"
#define _PATH_DT_IBM_PARTIT_NAME "/device-tree/ibm,partition-name"
#define _PATH_DT_HMC_MANAGED "/device-tree/hmc-managed?"
#define _PATH_DT_QEMU_WIDTH "/device-tree/chosen/qemu,graphic-width"
#define _PATH_DT "/proc/device-tree/vpd/root-node-vpd@a000/enclosure@1e00/backplane@800/processor@1000"
#define _PATH_DT_PART "/part-number"
bool fill_core_ids_from_sys(int *core_ids, int total_cores);
bool fill_package_ids_from_sys(int* package_ids, int total_cores);
int get_num_sockets_package_cpus(struct topology* topo);
long get_frequency_from_cpuinfo(void);
#endif

278
src/riscv/riscv.c
View File

@@ -1,278 +0,0 @@
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <ctype.h>
#include "../common/global.h"
#include "../common/udev.h"
#include "udev.h"
#include "uarch.h"
#include "soc.h"
#define SET_ISA_EXT_MAP(name, bit) \
if(strncmp(multi_letter_extension, name, \
multi_letter_extension_len) == 0) { \
ext->mask[bit] = true; \
maskset = true; \
} \
struct frequency* get_frequency_info(uint32_t core) {
struct frequency* freq = emalloc(sizeof(struct frequency));
freq->measured = false;
freq->base = UNKNOWN_DATA;
freq->max = get_max_freq_from_file(core);
return freq;
}
int64_t get_peak_performance(struct cpuInfo* cpu) {
//First check we have consistent data
if(get_freq(cpu->freq) == UNKNOWN_DATA) {
return -1;
}
int64_t flops = cpu->topo->total_cores * (get_freq(cpu->freq) * 1000000);
return flops;
}
// Returns the length of the multi-letter
// extension, or -1 if an error occurs
int parse_multi_letter_extension(struct extensions* ext, char* e) {
if(*e != '_') return -1;
char* multi_letter_extension_end = strstr(e+1, "_");
if(multi_letter_extension_end == NULL) {
// This is the last extension, find the end
// of the string
multi_letter_extension_end = e + strlen(e);
}
int multi_letter_extension_len = multi_letter_extension_end-(e+1);
bool maskset = false;
char* multi_letter_extension = emalloc(multi_letter_extension_len);
strncpy(multi_letter_extension, e+1, multi_letter_extension_len);
// This should be up-to-date with
// https://elixir.bootlin.com/linux/latest/source/arch/riscv/kernel/cpufeature.c
// which should represent the list of extensions available in real chips
SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF)
SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC)
SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL)
SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT)
SET_ISA_EXT_MAP("zbb", RISCV_ISA_EXT_ZBB)
SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM)
SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE)
SET_ISA_EXT_MAP("svnapot", RISCV_ISA_EXT_SVNAPOT)
SET_ISA_EXT_MAP("zicboz", RISCV_ISA_EXT_ZICBOZ)
SET_ISA_EXT_MAP("smaia", RISCV_ISA_EXT_SMAIA)
SET_ISA_EXT_MAP("ssaia", RISCV_ISA_EXT_SSAIA)
SET_ISA_EXT_MAP("zba", RISCV_ISA_EXT_ZBA)
SET_ISA_EXT_MAP("zbs", RISCV_ISA_EXT_ZBS)
SET_ISA_EXT_MAP("zicntr", RISCV_ISA_EXT_ZICNTR)
SET_ISA_EXT_MAP("zicsr", RISCV_ISA_EXT_ZICSR)
SET_ISA_EXT_MAP("zifencei", RISCV_ISA_EXT_ZIFENCEI)
SET_ISA_EXT_MAP("zihpm", RISCV_ISA_EXT_ZIHPM)
SET_ISA_EXT_MAP("smstateen", RISCV_ISA_EXT_SMSTATEEN)
SET_ISA_EXT_MAP("zicond", RISCV_ISA_EXT_ZICOND)
SET_ISA_EXT_MAP("zbc", RISCV_ISA_EXT_ZBC)
SET_ISA_EXT_MAP("zbkb", RISCV_ISA_EXT_ZBKB)
SET_ISA_EXT_MAP("zbkc", RISCV_ISA_EXT_ZBKC)
SET_ISA_EXT_MAP("zbkx", RISCV_ISA_EXT_ZBKX)
SET_ISA_EXT_MAP("zknd", RISCV_ISA_EXT_ZKND)
SET_ISA_EXT_MAP("zkne", RISCV_ISA_EXT_ZKNE)
SET_ISA_EXT_MAP("zknh", RISCV_ISA_EXT_ZKNH)
SET_ISA_EXT_MAP("zkr", RISCV_ISA_EXT_ZKR)
SET_ISA_EXT_MAP("zksed", RISCV_ISA_EXT_ZKSED)
SET_ISA_EXT_MAP("zksh", RISCV_ISA_EXT_ZKSH)
SET_ISA_EXT_MAP("zkt", RISCV_ISA_EXT_ZKT)
SET_ISA_EXT_MAP("zvbb", RISCV_ISA_EXT_ZVBB)
SET_ISA_EXT_MAP("zvbc", RISCV_ISA_EXT_ZVBC)
SET_ISA_EXT_MAP("zvkb", RISCV_ISA_EXT_ZVKB)
SET_ISA_EXT_MAP("zvkg", RISCV_ISA_EXT_ZVKG)
SET_ISA_EXT_MAP("zvkned", RISCV_ISA_EXT_ZVKNED)
SET_ISA_EXT_MAP("zvknha", RISCV_ISA_EXT_ZVKNHA)
SET_ISA_EXT_MAP("zvknhb", RISCV_ISA_EXT_ZVKNHB)
SET_ISA_EXT_MAP("zvksed", RISCV_ISA_EXT_ZVKSED)
SET_ISA_EXT_MAP("zvksh", RISCV_ISA_EXT_ZVKSH)
SET_ISA_EXT_MAP("zvkt", RISCV_ISA_EXT_ZVKT)
SET_ISA_EXT_MAP("zfh", RISCV_ISA_EXT_ZFH)
SET_ISA_EXT_MAP("zfhmin", RISCV_ISA_EXT_ZFHMIN)
SET_ISA_EXT_MAP("zihintntl", RISCV_ISA_EXT_ZIHINTNTL)
SET_ISA_EXT_MAP("zvfh", RISCV_ISA_EXT_ZVFH)
SET_ISA_EXT_MAP("zvfhmin", RISCV_ISA_EXT_ZVFHMIN)
SET_ISA_EXT_MAP("zfa", RISCV_ISA_EXT_ZFA)
SET_ISA_EXT_MAP("ztso", RISCV_ISA_EXT_ZTSO)
SET_ISA_EXT_MAP("zacas", RISCV_ISA_EXT_ZACAS)
SET_ISA_EXT_MAP("zve32x", RISCV_ISA_EXT_ZVE32X)
SET_ISA_EXT_MAP("zve32f", RISCV_ISA_EXT_ZVE32F)
SET_ISA_EXT_MAP("zve64x", RISCV_ISA_EXT_ZVE64X)
SET_ISA_EXT_MAP("zve64f", RISCV_ISA_EXT_ZVE64F)
SET_ISA_EXT_MAP("zve64d", RISCV_ISA_EXT_ZVE64D)
SET_ISA_EXT_MAP("zimop", RISCV_ISA_EXT_ZIMOP)
SET_ISA_EXT_MAP("zca", RISCV_ISA_EXT_ZCA)
SET_ISA_EXT_MAP("zcb", RISCV_ISA_EXT_ZCB)
SET_ISA_EXT_MAP("zcd", RISCV_ISA_EXT_ZCD)
SET_ISA_EXT_MAP("zcf", RISCV_ISA_EXT_ZCF)
SET_ISA_EXT_MAP("zcmop", RISCV_ISA_EXT_ZCMOP)
SET_ISA_EXT_MAP("zawrs", RISCV_ISA_EXT_ZAWRS)
SET_ISA_EXT_MAP("svvptc", RISCV_ISA_EXT_SVVPTC)
SET_ISA_EXT_MAP("smmpm", RISCV_ISA_EXT_SMMPM)
SET_ISA_EXT_MAP("smnpm", RISCV_ISA_EXT_SMNPM)
SET_ISA_EXT_MAP("ssnpm", RISCV_ISA_EXT_SSNPM)
SET_ISA_EXT_MAP("zabha", RISCV_ISA_EXT_ZABHA)
SET_ISA_EXT_MAP("ziccrse", RISCV_ISA_EXT_ZICCRSE)
SET_ISA_EXT_MAP("svade", RISCV_ISA_EXT_SVADE)
SET_ISA_EXT_MAP("svadu", RISCV_ISA_EXT_SVADU)
SET_ISA_EXT_MAP("zfbfmin", RISCV_ISA_EXT_ZFBFMIN)
SET_ISA_EXT_MAP("zvfbfmin", RISCV_ISA_EXT_ZVFBFMIN)
SET_ISA_EXT_MAP("zvfbfwma", RISCV_ISA_EXT_ZVFBFWMA)
SET_ISA_EXT_MAP("zaamo", RISCV_ISA_EXT_ZAAMO)
SET_ISA_EXT_MAP("zalrsc", RISCV_ISA_EXT_ZALRSC)
SET_ISA_EXT_MAP("zicbop", RISCV_ISA_EXT_ZICBOP)
SET_ISA_EXT_MAP("ime", RISCV_ISA_EXT_IME)
if(!maskset) {
printBug("parse_multi_letter_extension: Unknown multi-letter extension: %s", multi_letter_extension);
return -1;
}
return multi_letter_extension_len;
}
bool valid_extension(char ext) {
bool found = false;
uint64_t idx = 0;
while(idx < sizeof(extension_list)/sizeof(extension_list[0]) && !found) {
found = (extension_list[idx].id == (ext - 'a'));
if(!found) idx++;
}
return found;
}
struct extensions* get_extensions_from_str(char* str) {
struct extensions* ext = emalloc(sizeof(struct extensions));
ext->mask = ecalloc(RISCV_ISA_EXT_ID_MAX, sizeof(bool));
ext->str = NULL;
if(str == NULL) {
return ext;
}
int len = strlen(str)+1;
ext->str = emalloc(len * sizeof(char));
strncpy(ext->str, str, sizeof(char) * len);
// Code inspired in Linux kernel (riscv_fill_hwcap):
// https://elixir.bootlin.com/linux/v6.2.10/source/arch/riscv/kernel/cpufeature.c
// Now it seems to be here in riscv_parse_isa_string:
// https://elixir.bootlin.com/linux/v6.16/source/arch/riscv/kernel/cpufeature.c
char* isa = str;
if (!strncmp(isa, "rv32", 4))
isa += 4;
else if (!strncmp(isa, "rv64", 4))
isa += 4;
else {
printBug("get_extensions_from_str: ISA string must start with rv64 or rv32");
return ext;
}
for(char* e = isa; *e != '\0'; e++) {
if(*e == '_') {
// Multi-letter extension
int multi_letter_extension_len = parse_multi_letter_extension(ext, e);
if(multi_letter_extension_len == -1) {
return ext;
}
e += multi_letter_extension_len;
}
else {
// Single-letter extensions 's' and 'u' are invalid
// according to Linux kernel (arch/riscv/kernel/cpufeature.c:
// riscv_fill_hwcap). Optionally, we could opt for using
// hwcap instead of cpuinfo to avoid this
if (*e == 's' || *e == 'u') {
continue;
}
// Make sure that the extension is valid before
// adding it to the mask
if(valid_extension(*e)) {
int n = *e - 'a';
ext->mask[n] = true;
}
else {
printBug("get_extensions_from_str: Invalid extension: '%c'", *e);
}
}
}
return ext;
}
uint32_t get_num_extensions(bool* mask) {
uint32_t num = 0;
for (int i=0; i < RISCV_ISA_EXT_ID_MAX; i++) {
if (mask[i]) num++;
}
return num;
}
bool is_mask_empty(bool* mask) {
return get_num_extensions(mask) == 0;
}
struct cpuInfo* get_cpu_info(void) {
struct cpuInfo* cpu = malloc(sizeof(struct cpuInfo));
//init_cpu_info(cpu);
struct topology* topo = emalloc(sizeof(struct topology));
topo->total_cores = get_ncores_from_cpuinfo();
topo->cach = NULL;
cpu->topo = topo;
char* ext_str = get_extensions_from_cpuinfo();
cpu->hv = emalloc(sizeof(struct hypervisor));
cpu->hv->present = false;
cpu->ext = get_extensions_from_str(ext_str);
if(cpu->ext->str != NULL && is_mask_empty(cpu->ext->mask)) return NULL;
cpu->arch = get_uarch(cpu);
cpu->soc = get_soc(cpu);
cpu->freq = get_frequency_info(0);
cpu->peak_performance = get_peak_performance(cpu);
return cpu;
}
//TODO: Might be worth refactoring with other archs
char* get_str_topology(struct cpuInfo* cpu, struct topology* topo) {
uint32_t size = 3+7+1;
char* string = emalloc(sizeof(char)*size);
snprintf(string, size, "%d cores", topo->total_cores);
return string;
}
char* get_str_extensions(struct cpuInfo* cpu) {
if(cpu->ext != NULL) {
return cpu->ext->str;
}
return NULL;
}
void print_debug(struct cpuInfo* cpu) {
printf("- soc: ");
if(cpu->soc->raw_name == NULL) {
printf("NULL\n");
}
else {
printf("'%s'\n", cpu->soc->raw_name);
}
printf("- uarch: ");
char* arch_cpuinfo_str = get_arch_cpuinfo_str(cpu);
if(arch_cpuinfo_str == NULL) {
printf("NULL\n");
}
else {
printf("'%s'\n", arch_cpuinfo_str);
}
}

204
src/riscv/riscv.h
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@@ -1,204 +0,0 @@
#ifndef __RISCV__
#define __RISCV__
#include "../common/cpu.h"
struct extension {
int id;
char* str;
};
#define RISCV_ISA_EXT_NAME_LEN_MAX 32
#define RISCV_ISA_EXT_BASE 26
// https://elixir.bootlin.com/linux/latest/source/arch/riscv/include/asm/hwcap.h
// This enum represent the logical ID for multi-letter RISC-V ISA extensions.
// The logical ID should start from RISCV_ISA_EXT_BASE
enum riscv_isa_ext_id {
RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE,
RISCV_ISA_EXT_SSTC,
RISCV_ISA_EXT_SVINVAL,
RISCV_ISA_EXT_SVPBMT,
RISCV_ISA_EXT_ZBB,
RISCV_ISA_EXT_ZICBOM,
RISCV_ISA_EXT_ZIHINTPAUSE,
RISCV_ISA_EXT_SVNAPOT,
RISCV_ISA_EXT_ZICBOZ,
RISCV_ISA_EXT_SMAIA,
RISCV_ISA_EXT_SSAIA,
RISCV_ISA_EXT_ZBA,
RISCV_ISA_EXT_ZBS,
RISCV_ISA_EXT_ZICNTR,
RISCV_ISA_EXT_ZICSR,
RISCV_ISA_EXT_ZIFENCEI,
RISCV_ISA_EXT_ZIHPM,
RISCV_ISA_EXT_SMSTATEEN,
RISCV_ISA_EXT_ZICOND,
RISCV_ISA_EXT_ZBC,
RISCV_ISA_EXT_ZBKB,
RISCV_ISA_EXT_ZBKC,
RISCV_ISA_EXT_ZBKX,
RISCV_ISA_EXT_ZKND,
RISCV_ISA_EXT_ZKNE,
RISCV_ISA_EXT_ZKNH,
RISCV_ISA_EXT_ZKR,
RISCV_ISA_EXT_ZKSED,
RISCV_ISA_EXT_ZKSH,
RISCV_ISA_EXT_ZKT,
RISCV_ISA_EXT_ZVBB,
RISCV_ISA_EXT_ZVBC,
RISCV_ISA_EXT_ZVKB,
RISCV_ISA_EXT_ZVKG,
RISCV_ISA_EXT_ZVKNED,
RISCV_ISA_EXT_ZVKNHA,
RISCV_ISA_EXT_ZVKNHB,
RISCV_ISA_EXT_ZVKSED,
RISCV_ISA_EXT_ZVKSH,
RISCV_ISA_EXT_ZVKT,
RISCV_ISA_EXT_ZFH,
RISCV_ISA_EXT_ZFHMIN,
RISCV_ISA_EXT_ZIHINTNTL,
RISCV_ISA_EXT_ZVFH,
RISCV_ISA_EXT_ZVFHMIN,
RISCV_ISA_EXT_ZFA,
RISCV_ISA_EXT_ZTSO,
RISCV_ISA_EXT_ZACAS,
RISCV_ISA_EXT_ZVE32X,
RISCV_ISA_EXT_ZVE32F,
RISCV_ISA_EXT_ZVE64X,
RISCV_ISA_EXT_ZVE64F,
RISCV_ISA_EXT_ZVE64D,
RISCV_ISA_EXT_ZIMOP,
RISCV_ISA_EXT_ZCA,
RISCV_ISA_EXT_ZCB,
RISCV_ISA_EXT_ZCD,
RISCV_ISA_EXT_ZCF,
RISCV_ISA_EXT_ZCMOP,
RISCV_ISA_EXT_ZAWRS,
RISCV_ISA_EXT_SVVPTC,
RISCV_ISA_EXT_SMMPM,
RISCV_ISA_EXT_SMNPM,
RISCV_ISA_EXT_SSNPM,
RISCV_ISA_EXT_ZABHA,
RISCV_ISA_EXT_ZICCRSE,
RISCV_ISA_EXT_SVADE,
RISCV_ISA_EXT_SVADU,
RISCV_ISA_EXT_ZFBFMIN,
RISCV_ISA_EXT_ZVFBFMIN,
RISCV_ISA_EXT_ZVFBFWMA,
RISCV_ISA_EXT_ZAAMO,
RISCV_ISA_EXT_ZALRSC,
RISCV_ISA_EXT_ZICBOP,
RISCV_ISA_EXT_IME, // This is not in the kernel! but it was seen on a Muse Pi Pro board
RISCV_ISA_EXT_ID_MAX
};
// https://five-embeddev.com/riscv-isa-manual/latest/preface.html#preface
// https://en.wikichip.org/wiki/risc-v/standard_extensions
// (Zicbop) https://github.com/riscv/riscv-CMOs/blob/master/cmobase/Zicbop.adoc
// https://raw.githubusercontent.com/riscv/riscv-CMOs/master/specifications/cmobase-v1.0.1.pdf
// https://www.kernel.org/doc/Documentation/devicetree/bindings/riscv/extensions.yaml
// (Ime) https://github.com/riscv/integrated-matrix-extension (not confirmed, just a guess...)
// Included all except for G
static const struct extension extension_list[] = {
{ 'i' - 'a', "(I) Integer Instruction Set" },
{ 'm' - 'a', "(M) Integer Multiplication and Division" },
{ 'a' - 'a', "(A) Atomic Instructions" },
{ 'f' - 'a', "(F) Single-Precision Floating-Point" },
{ 'd' - 'a', "(D) Double-Precision Floating-Point" },
{ 'q' - 'a', "(Q) Quad-Precision Floating-Point" },
{ 'l' - 'a', "(L) Decimal Floating-Point" },
{ 'c' - 'a', "(C) Compressed Instructions" },
{ 'b' - 'a', "(B) Double-Precision Floating-Point" },
{ 'j' - 'a', "(J) Dynamically Translated Languages" },
{ 't' - 'a', "(T) Transactional Memory" },
{ 'p' - 'a', "(P) Packed-SIMD Instructions" },
{ 'v' - 'a', "(V) Vector Operations" },
{ 'n' - 'a', "(N) User-Level Interrupts" },
{ 'h' - 'a', "(H) Hypervisor" },
// multi-letter extensions
{ RISCV_ISA_EXT_SSCOFPMF, "(Sscofpmf) Count OverFlow and Privilege Mode Filtering" },
{ RISCV_ISA_EXT_SSTC, "(Sstc) S and VS level Time Compare" },
{ RISCV_ISA_EXT_SVINVAL, "(Svinval) Fast TLB Invalidation" },
{ RISCV_ISA_EXT_SVPBMT, "(Svpbmt) Page-based Memory Types" },
{ RISCV_ISA_EXT_ZBB, "(Zbb) Basic bit-manipulation" },
{ RISCV_ISA_EXT_ZICBOM, "(Zicbom) Cache Block Management Operations" },
{ RISCV_ISA_EXT_ZIHINTPAUSE, "(Zihintpause) Pause Hint" },
{ RISCV_ISA_EXT_SVNAPOT, "(Svnapot) Naturally Aligned Power of Two Pages" },
{ RISCV_ISA_EXT_ZICBOZ, "(Zicboz) Cache Block Zero Operations" },
{ RISCV_ISA_EXT_ZICBOP, "(Zicbop) Cache Block Prefetch Operations" },
{ RISCV_ISA_EXT_SMAIA, "(Smaia) Advanced Interrupt Architecture" },
{ RISCV_ISA_EXT_SSAIA, "(Ssaia) Advanced Interrupt Architecture" },
{ RISCV_ISA_EXT_ZBA, "(Zba) Address Generation" },
{ RISCV_ISA_EXT_ZBS, "(Zbs) Single-bit Instructions" },
{ RISCV_ISA_EXT_ZICNTR, "(Zicntr) Base Counters and Timers" },
{ RISCV_ISA_EXT_ZICSR, "(Zicsr) Control and Status Register" },
{ RISCV_ISA_EXT_ZIFENCEI, "(Zifencei) Instruction-Fetch Fence" },
{ RISCV_ISA_EXT_ZIHPM, "(Zihpm) Hardware Performance Counters" },
{ RISCV_ISA_EXT_SMSTATEEN, "(Smstateen) " },
{ RISCV_ISA_EXT_ZICOND, "(Zicond) Integer Conditional Operations" },
{ RISCV_ISA_EXT_ZBC, "(Zbc) Carry-Less Multiplication" },
{ RISCV_ISA_EXT_ZBKB, "(Zbkb) " },
{ RISCV_ISA_EXT_ZBKC, "(Zbkc) " },
{ RISCV_ISA_EXT_ZBKX, "(Zbkx) " },
{ RISCV_ISA_EXT_ZKND, "(Zknd) " },
{ RISCV_ISA_EXT_ZKNE, "(Zkne) " },
{ RISCV_ISA_EXT_ZKNH, "(Zknh) " },
{ RISCV_ISA_EXT_ZKR, "(Zkr) " },
{ RISCV_ISA_EXT_ZKSED, "(Zksed) " },
{ RISCV_ISA_EXT_ZKSH, "(Zksh) " },
{ RISCV_ISA_EXT_ZKT, "(Zkt) Data-Independent Execution Latency" },
{ RISCV_ISA_EXT_ZVBB, "(Zvbb) " },
{ RISCV_ISA_EXT_ZVBC, "(Zvbc) " },
{ RISCV_ISA_EXT_ZVKB, "(Zvkb) " },
{ RISCV_ISA_EXT_ZVKG, "(Zvkg) " },
{ RISCV_ISA_EXT_ZVKNED, "(Zvkned) " },
{ RISCV_ISA_EXT_ZVKNHA, "(Zvknha) " },
{ RISCV_ISA_EXT_ZVKNHB, "(Zvknhb) " },
{ RISCV_ISA_EXT_ZVKSED, "(Zvksed) " },
{ RISCV_ISA_EXT_ZVKSH, "(Zvksh) " },
{ RISCV_ISA_EXT_ZVKT, "(Zvkt) " },
{ RISCV_ISA_EXT_ZFH, "(Zfh) " },
{ RISCV_ISA_EXT_ZFHMIN, "(Zfhmin) " },
{ RISCV_ISA_EXT_ZIHINTNTL, "(Zihintntl) " },
{ RISCV_ISA_EXT_ZVFH, "(Zvfh) " },
{ RISCV_ISA_EXT_ZVFHMIN, "(Zvfhmin) " },
{ RISCV_ISA_EXT_ZFA, "(Zfa) " },
{ RISCV_ISA_EXT_ZTSO, "(Ztso) " },
{ RISCV_ISA_EXT_ZACAS, "(Zacas) " },
{ RISCV_ISA_EXT_ZVE32X, "(Zve32x) Vector Extensions (i32)" },
{ RISCV_ISA_EXT_ZVE32F, "(Zve32f) Vector Extensions (f32)" },
{ RISCV_ISA_EXT_ZVE64X, "(Zve64x) Vector Extensions (i64)" },
{ RISCV_ISA_EXT_ZVE64F, "(Zve64f) Vector Extensions (f64)" },
{ RISCV_ISA_EXT_ZVE64D, "(Zve64d) Vector Extensions (???)" },
{ RISCV_ISA_EXT_ZIMOP, "(Zimop) " },
{ RISCV_ISA_EXT_ZCA, "(Zca) " },
{ RISCV_ISA_EXT_ZCB, "(Zcb) " },
{ RISCV_ISA_EXT_ZCD, "(Zcd) " },
{ RISCV_ISA_EXT_ZCF, "(Zcf) " },
{ RISCV_ISA_EXT_ZCMOP, "(Zcmop) " },
{ RISCV_ISA_EXT_ZAWRS, "(Zawrs) " },
{ RISCV_ISA_EXT_SVVPTC, "(Svvptc) " },
{ RISCV_ISA_EXT_SMMPM, "(Smmpm) " },
{ RISCV_ISA_EXT_SMNPM, "(Smnpm) " },
{ RISCV_ISA_EXT_SSNPM, "(Ssnpm) " },
{ RISCV_ISA_EXT_ZABHA, "(Zabha) " },
{ RISCV_ISA_EXT_ZICCRSE, "(Ziccrse) " },
{ RISCV_ISA_EXT_SVADE, "(Svade) " },
{ RISCV_ISA_EXT_SVADU, "(Svadu) " },
{ RISCV_ISA_EXT_ZFBFMIN, "(Zfbfmin) " },
{ RISCV_ISA_EXT_ZVFBFMIN, "(Zvfbfmin) " },
{ RISCV_ISA_EXT_ZVFBFWMA, "(Zvfbfwma) " },
{ RISCV_ISA_EXT_ZAAMO, "(Zaamo) " },
{ RISCV_ISA_EXT_ZALRSC, "(Zalrsc) " },
{ RISCV_ISA_EXT_ZICBOP, "(Zicbop) " },
{ RISCV_ISA_EXT_IME, "(Ime) Integrated Matrix Extension" },
};
struct cpuInfo* get_cpu_info(void);
char* get_str_topology(struct cpuInfo* cpu, struct topology* topo);
char* get_str_extensions(struct cpuInfo* cpu);
uint32_t get_num_extensions(bool* mask);
void print_debug(struct cpuInfo* cpu);
#endif

102
src/riscv/soc.c
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@@ -1,102 +0,0 @@
#include "soc.h"
#include "socs.h"
#include "udev.h"
#include "../common/global.h"
#include <string.h>
bool match_sifive(char* soc_name, struct system_on_chip* soc) {
char* tmp = soc_name;
// Dont know if it makes sense in RISC-V
/*if((tmp = strstr(soc_name, "???")) == NULL)
return false;*/
//soc->vendor = ???
SOC_START
SOC_EQ(tmp, "fu740", "Freedom U740", SOC_SIFIVE_U740, soc, 40)
SOC_END
}
bool match_starfive(char* soc_name, struct system_on_chip* soc) {
SOC_START
SOC_EQ(soc_name, "jh7110#", "VisionFive 2", SOC_STARFIVE_VF2, soc, 28) // https://blog.bitsofnetworks.org/benchmarking-risc-v-visionfive-2-vs-the-world.html
SOC_EQ(soc_name, "jh7110", "VisionFive 2", SOC_STARFIVE_VF2, soc, 28)
SOC_END
}
bool match_allwinner(char* soc_name, struct system_on_chip* soc) {
SOC_START
SOC_EQ(soc_name, "sun20i-d1", "D1-H", SOC_ALLWINNER_D1H, soc, 22)
SOC_END
}
bool match_sipeed(char* soc_name, struct system_on_chip* soc) {
SOC_START
SOC_EQ(soc_name, "light", "Lichee Pi 4A", SOC_SIPEED_LICHEEPI4A, soc, 12) // https://github.com/Dr-Noob/cpufetch/issues/200, https://sipeed.com/licheepi4a
SOC_END
}
bool match_spacemit(char* soc_name, struct system_on_chip* soc) {
SOC_START
SOC_EQ(soc_name, "k1-x", "K1-X", SOC_SPACEMIT_K1X, soc, 22) // https://github.com/Dr-Noob/cpufetch/issues/286 https://www.spacemit.com/en/spacemit-x60-core/
SOC_END
}
struct system_on_chip* parse_soc_from_string(struct system_on_chip* soc) {
char* raw_name = soc->raw_name;
if(match_starfive(raw_name, soc))
return soc;
if(match_allwinner(raw_name, soc))
return soc;
if(match_sifive(raw_name, soc))
return soc;
if(match_spacemit(raw_name, soc))
return soc;
match_sipeed(raw_name, soc);
return soc;
}
struct system_on_chip* guess_soc_from_devtree(struct system_on_chip* soc) {
char* tmp = get_hardware_from_devtree();
if(tmp != NULL) {
soc->raw_name = tmp;
return parse_soc_from_string(soc);
}
return soc;
}
struct system_on_chip* get_soc(struct cpuInfo* cpu) {
struct system_on_chip* soc = emalloc(sizeof(struct system_on_chip));
soc->raw_name = NULL;
soc->vendor = SOC_VENDOR_UNKNOWN;
soc->model = SOC_MODEL_UNKNOWN;
soc->process = UNKNOWN;
soc = guess_soc_from_devtree(soc);
if(soc->vendor == SOC_VENDOR_UNKNOWN) {
if(soc->raw_name != NULL) {
printWarn("SoC detection failed using device tree: Found '%s' string", soc->raw_name);
}
else {
printWarn("SoC detection failed using device tree");
}
}
if(soc->model == SOC_MODEL_UNKNOWN) {
// raw_name might not be NULL, but if we were unable to find
// the exact SoC, just print "Unkwnown"
soc->raw_name = emalloc(sizeof(char) * (strlen(STRING_UNKNOWN)+1));
snprintf(soc->raw_name, strlen(STRING_UNKNOWN)+1, STRING_UNKNOWN);
}
return soc;
}

10
src/riscv/soc.h
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@@ -1,10 +0,0 @@
#ifndef __SOC_RISCV__
#define __SOC_RISCV__
#include "../common/soc.h"
#include "../common/cpu.h"
#include <stdint.h>
struct system_on_chip* get_soc(struct cpuInfo* cpu);
#endif

31
src/riscv/socs.h
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@@ -1,31 +0,0 @@
#ifndef __SOCS__
#define __SOCS__
#include "soc.h"
// List of supported SOCs
enum {
// SIFIVE
SOC_SIFIVE_U740,
// STARFIVE
SOC_STARFIVE_VF2,
// ALLWINNER
SOC_ALLWINNER_D1H,
// SIPEED
SOC_SIPEED_LICHEEPI4A,
// SPACEMIT
SOC_SPACEMIT_K1X,
// UNKNOWN
SOC_MODEL_UNKNOWN
};
inline static VENDOR get_soc_vendor_from_soc(SOC soc) {
if(soc >= SOC_SIFIVE_U740 && soc <= SOC_SIFIVE_U740) return SOC_VENDOR_SIFIVE;
if(soc >= SOC_STARFIVE_VF2 && soc <= SOC_STARFIVE_VF2) return SOC_VENDOR_STARFIVE;
if(soc >= SOC_ALLWINNER_D1H && soc <= SOC_ALLWINNER_D1H) return SOC_VENDOR_ALLWINNER;
if(soc >= SOC_SIPEED_LICHEEPI4A && soc <= SOC_SIPEED_LICHEEPI4A) return SOC_VENDOR_SIPEED;
if(soc >= SOC_SPACEMIT_K1X && soc <= SOC_SPACEMIT_K1X) return SOC_VENDOR_SPACEMIT;
return SOC_VENDOR_UNKNOWN;
}
#endif

122
src/riscv/uarch.c
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@@ -1,122 +0,0 @@
#include <stdbool.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "uarch.h"
#include "udev.h"
#include "../common/global.h"
typedef uint32_t MICROARCH;
struct uarch {
MICROARCH uarch;
char* uarch_str;
char* cpuinfo_str;
struct riscv_cpuinfo* ci;
};
enum {
UARCH_UNKNOWN,
// SIFIVE
UARCH_U54,
UARCH_U74,
// THEAD
UARCH_C906,
UARCH_C910,
// SPACEMIT
UARCH_X60
};
#define UARCH_START if (false) {}
#define CHECK_UARCH(arch, cpu, cpuinfo_str, uarch_str, str, uarch, vendor) \
else if (strcmp(cpuinfo_str, uarch_str) == 0) fill_uarch(arch, cpu, str, uarch, vendor);
#define UARCH_END else { printWarn("Unknown microarchitecture detected: uarch='%s'", cpuinfo_str); fill_uarch(arch, cpu, "Unknown", UARCH_UNKNOWN, CPU_VENDOR_UNKNOWN); }
#define ARCHID_START if (false) {}
#define CHECK_ARCHID(arch, marchid_val, str, uarch, vendor) \
else if (arch->ci->marchid == (unsigned long) marchid_val) fill_uarch(arch, cpu, str, uarch, vendor);
#define ARCHID_END else { printWarn("Unknown microarchitecture detected: marchid=0x%.8X", arch->ci->marchid); fill_uarch(arch, cpu, "Unknown", UARCH_UNKNOWN, CPU_VENDOR_UNKNOWN); }
void fill_uarch(struct uarch* arch, struct cpuInfo* cpu, char* str, MICROARCH u, VENDOR vendor) {
arch->uarch = u;
cpu->cpu_vendor = vendor;
arch->uarch_str = emalloc(sizeof(char) * (strlen(str)+1));
strcpy(arch->uarch_str, str);
}
// https://elixir.bootlin.com/linux/latest/source/Documentation/devicetree/bindings/riscv/cpus.yaml
// SiFive: https://www.sifive.com/risc-v-core-ip
// T-Head: https://www.t-head.cn/product/c906
struct uarch* get_uarch_from_cpuinfo_str(char* cpuinfo_str, struct cpuInfo* cpu, struct uarch* arch) {
arch->cpuinfo_str = cpuinfo_str;
// U74/U74-MC:
// SiFive says that U74-MC is "Multicore: four U74 cores and one S76 core" while
// U74 is "High performance Linux-capable processor". It's like U74-MC is somehow a small SoC containing
// the U74 and the S76? Then U74-MC is not a microarchitecture per se...
UARCH_START
CHECK_UARCH(arch, cpu, cpuinfo_str, "sifive,bullet0", "U74", UARCH_U74, CPU_VENDOR_SIFIVE) // bullet0 is present in U740, which has U74
// CHECK_UARCH(arch, cpu, cpuinfo_str, "sifive,e5", "XXXXXX", UARCH_U74, CPU_VENDOR_SIFIVE)
// CHECK_UARCH(arch, cpu, cpuinfo_str, "sifive,e7", "XXXXXX", UARCH_U74, CPU_VENDOR_SIFIVE)
// CHECK_UARCH(arch, cpu, cpuinfo_str, "sifive,e71", "XXXXXX", UARCH_U74, CPU_VENDOR_SIFIVE)
// CHECK_UARCH(arch, cpu, cpuinfo_str, "sifive,rocket0", "XXXXXX", UARCH_U74, CPU_VENDOR_SIFIVE)
// CHECK_UARCH(arch, cpu, cpuinfo_str, "sifive,u5", "XXXXXX", UARCH_U74, CPU_VENDOR_SIFIVE)
CHECK_UARCH(arch, cpu, cpuinfo_str, "sifive,u54", "U54", UARCH_U54, CPU_VENDOR_SIFIVE)
// CHECK_UARCH(arch, cpu, cpuinfo_str, "sifive,u7", "XXXXXX", UARCH_U74, CPU_VENDOR_SIFIVE)
CHECK_UARCH(arch, cpu, cpuinfo_str, "sifive,u74", "U74", UARCH_U74, CPU_VENDOR_SIFIVE)
CHECK_UARCH(arch, cpu, cpuinfo_str, "sifive,u74-mc", "U74", UARCH_U74, CPU_VENDOR_SIFIVE)
CHECK_UARCH(arch, cpu, cpuinfo_str, "thead,c906", "T-Head C906", UARCH_C906, CPU_VENDOR_THEAD)
CHECK_UARCH(arch, cpu, cpuinfo_str, "thead,c910", "T-Head C910", UARCH_C910, CPU_VENDOR_THEAD)
UARCH_END
return arch;
}
// Use marchid to get the microarchitecture
struct uarch* get_uarch_from_riscv_cpuinfo(struct cpuInfo* cpu, struct uarch* arch) {
ARCHID_START
CHECK_ARCHID(arch, 0x8000000058000001, "X60", UARCH_X60, CPU_VENDOR_SPACEMIT) // https://github.com/Dr-Noob/cpufetch/issues/286
ARCHID_END
return arch;
}
struct uarch* get_uarch(struct cpuInfo* cpu) {
char* cpuinfo_str = get_uarch_from_cpuinfo();
struct uarch* arch = emalloc(sizeof(struct uarch));
arch->uarch = UARCH_UNKNOWN;
arch->ci = NULL;
if (cpuinfo_str == NULL) {
printWarn("get_uarch_from_cpuinfo: Unable to detect microarchitecture using uarch: cpuinfo_str is NULL");
arch->ci = get_riscv_cpuinfo();
if (arch->ci == NULL || arch->ci->marchid == 0)
printWarn("get_riscv_cpuinfo: Unable to get marchid from udev");
else
arch = get_uarch_from_riscv_cpuinfo(cpu, arch);
}
else {
arch = get_uarch_from_cpuinfo_str(cpuinfo_str, cpu, arch);
}
if (arch->uarch == UARCH_UNKNOWN)
fill_uarch(arch, cpu, "Unknown", UARCH_UNKNOWN, CPU_VENDOR_UNKNOWN);
return arch;
}
char* get_str_uarch(struct cpuInfo* cpu) {
return cpu->arch->uarch_str;
}
char* get_arch_cpuinfo_str(struct cpuInfo* cpu) {
return cpu->arch->cpuinfo_str;
}
void free_uarch_struct(struct uarch* arch) {
free(arch->uarch_str);
free(arch);
}

14
src/riscv/uarch.h
View File

@@ -1,14 +0,0 @@
#ifndef __UARCH__
#define __UARCH__
#include <stdint.h>
#include "riscv.h"
struct uarch;
char* get_arch_cpuinfo_str(struct cpuInfo* cpu);
char* get_str_uarch(struct cpuInfo* cpu);
void free_uarch_struct(struct uarch* arch);
struct uarch* get_uarch(struct cpuInfo* cpu);
#endif

138
src/riscv/udev.c
View File

@@ -1,138 +0,0 @@
#include <errno.h>
#include <string.h>
#include "../common/global.h"
#include "udev.h"
#define _PATH_DEVTREE "/proc/device-tree/compatible"
#define CPUINFO_UARCH_STR "uarch\t\t: "
#define CPUINFO_EXTENSIONS_STR "isa\t\t: "
#define CPUINFO_RISCV_MVENDORID "mvendorid\t:"
#define CPUINFO_RISCV_MARCHID "marchid\t\t:"
#define CPUINFO_RISCV_MIMPID "mimpid\t\t:"
#define DEVTREE_HARDWARE_FIELD 0
char* get_field_from_devtree(int DEVTREE_FIELD) {
int filelen;
char* buf;
if((buf = read_file(_PATH_DEVTREE, &filelen)) == NULL) {
printWarn("read_file: %s: %s", _PATH_DEVTREE, strerror(errno));
return NULL;
}
// Here we would use strstr to find the comma.
// However, the device-tree file may contain NULL
// bytes in the middle of the string, which would
// cause strstr to return NULL even when there might
// be an occurence after the NULL byte
//
// We iterate the string backwards to find the field
// in position n-DEVTREE_HARDWARE_FIELD where n
// is the number of fields.
int i=0;
char* tmp1 = buf+filelen-1;
do {
tmp1--;
if(*tmp1 == ',') i++;
} while(tmp1 != buf && i <= DEVTREE_FIELD);
if(tmp1 == buf) {
printWarn("get_field_from_devtree: Unable to find field %d", DEVTREE_FIELD);
return NULL;
}
tmp1++;
int strlen = filelen-(tmp1-buf);
char* hardware = ecalloc(strlen, sizeof(char));
strncpy(hardware, tmp1, strlen-1);
return hardware;
}
char* parse_cpuinfo_field(char* field_str) {
int filelen;
char* buf;
if((buf = read_file(_PATH_CPUINFO, &filelen)) == NULL) {
printWarn("read_file: %s: %s", _PATH_CPUINFO, strerror(errno));
return NULL;
}
char* tmp = strstr(buf, field_str);
if(tmp == NULL) {
printWarn("parse_cpuinfo_field: Unable to find field %s", field_str);
return NULL;
}
tmp += strlen(field_str);
char* end = strstr(tmp, "\n");
if(end == NULL) {
printWarn("parse_cpuinfo_field: Unable to find newline after field %s", field_str);
return NULL;
}
int ret_strlen = (end-tmp);
char* ret = ecalloc(ret_strlen+1, sizeof(char));
strncpy(ret, tmp, sizeof(char) * ret_strlen);
return ret;
}
unsigned long parse_cpuinfo_field_uint64(char* field_str) {
int filelen;
char* buf;
if((buf = read_file(_PATH_CPUINFO, &filelen)) == NULL) {
printWarn("read_file: %s: %s", _PATH_CPUINFO, strerror(errno));
return 0;
}
char* tmp = strstr(buf, field_str);
if(tmp == NULL) return 0;
tmp += strlen(field_str);
char* end;
errno = 0;
unsigned long ret = strtoul(tmp, &end, 16);
if (errno != 0) {
printWarn("strtoul: %s: %s", strerror(errno), tmp);
return 0;
}
return ret;
}
// Creates and fills in the riscv_cpuinfo struct (which contains
// mvendorid, marchid and mimpid) using cpuinfo to fetch the values.
//
// Every RISC-V hart (hardware thread) [1] provides a
// marchid (Machine Architecture ID register) CSR that encodes its
// base microarchitecture [2]. For more information about
// marchid and the rest of values, see [3].
// [1] https://groups.google.com/a/groups.riscv.org/g/sw-dev/c/QKjUDjz_vKo
// [2] https://github.com/riscv/riscv-isa-manual/blob/main/marchid.md
// [3] https://five-embeddev.com/riscv-priv-isa-manual/Priv-v1.12/machine.html#machine-architecture-id-register-marchid
struct riscv_cpuinfo *get_riscv_cpuinfo(void) {
struct riscv_cpuinfo* ci = emalloc(sizeof(struct riscv_cpuinfo));
ci->mvendorid = parse_cpuinfo_field_uint64(CPUINFO_RISCV_MVENDORID);
ci->marchid = parse_cpuinfo_field_uint64(CPUINFO_RISCV_MARCHID);
ci->mimpid = parse_cpuinfo_field_uint64(CPUINFO_RISCV_MIMPID);
if (ci->mvendorid == 0 && ci->mvendorid == 0 && ci->mvendorid == 0)
return NULL;
return ci;
}
char* get_hardware_from_devtree(void) {
return get_field_from_devtree(DEVTREE_HARDWARE_FIELD);
}
char* get_uarch_from_cpuinfo(void) {
return parse_cpuinfo_field(CPUINFO_UARCH_STR);
}
char* get_extensions_from_cpuinfo(void) {
return parse_cpuinfo_field(CPUINFO_EXTENSIONS_STR);
}

20
src/riscv/udev.h
View File

@@ -1,20 +0,0 @@
#ifndef __UDEV_RISCV__
#define __UDEV_RISCV__
#include "../common/udev.h"
#define UNKNOWN -1
// https://elixir.bootlin.com/linux/v6.10.6/source/arch/riscv/include/asm/cpufeature.h#L21
struct riscv_cpuinfo {
unsigned long mvendorid;
unsigned long marchid;
unsigned long mimpid;
};
char* get_hardware_from_devtree(void);
char* get_uarch_from_cpuinfo(void);
char* get_extensions_from_cpuinfo(void);
struct riscv_cpuinfo *get_riscv_cpuinfo(void);
#endif

43
src/x86/apic.c
View File

@@ -72,6 +72,34 @@ uint32_t get_apic_id(bool x2apic_id) {
}
}
#ifndef __APPLE__
bool bind_to_cpu(int cpu_id) {
#ifdef _WIN32
HANDLE process = GetCurrentProcess();
DWORD_PTR processAffinityMask = 1 << cpu_id;
return SetProcessAffinityMask(process, processAffinityMask);
#elif defined __linux__
cpu_set_t currentCPU;
CPU_ZERO(&currentCPU);
CPU_SET(cpu_id, &currentCPU);
if (sched_setaffinity (0, sizeof(currentCPU), &currentCPU) == -1) {
printWarn("sched_setaffinity: %s", strerror(errno));
return false;
}
return true;
#elif defined __FreeBSD__
cpuset_t currentCPU;
CPU_ZERO(&currentCPU);
CPU_SET(cpu_id, &currentCPU);
if(cpuset_setaffinity(CPU_LEVEL_WHICH, CPU_WHICH_TID, -1, sizeof(cpuset_t), &currentCPU) == -1) {
printWarn("cpuset_setaffinity: %s", strerror(errno));
return false;
}
return true;
#endif
}
#endif
#ifdef __linux__
int get_total_cores_module(int total_cores, int module) {
int total_modules = 2;
@@ -234,11 +262,15 @@ uint32_t max_apic_id_size(uint32_t** cache_id_apic, struct topology* topo) {
bool build_topo_from_apic(uint32_t* apic_pkg, uint32_t* apic_smt, uint32_t** cache_id_apic, struct topology* topo) {
uint32_t size = max_apic_id_size(cache_id_apic, topo);
uint32_t* sockets = ecalloc(size, sizeof(uint32_t));
uint32_t* smt = ecalloc(size, sizeof(uint32_t));
uint32_t* apic_id = ecalloc(size, sizeof(uint32_t));
uint32_t* sockets = emalloc(sizeof(uint32_t) * size);
uint32_t* smt = emalloc(sizeof(uint32_t) * size);
uint32_t* apic_id = emalloc(sizeof(uint32_t) * size);
uint32_t num_caches = 0;
memset(sockets, 0, sizeof(uint32_t) * size);
memset(smt, 0, sizeof(uint32_t) * size);
memset(apic_id, 0, sizeof(uint32_t) * size);
// System topology
for(int i=0; i < topo->total_cores_module; i++) {
sockets[apic_pkg[i]] = 1;
@@ -365,11 +397,6 @@ bool fill_apic_ids(uint32_t* apic_ids, int first_core, int n, bool x2apic_id) {
}
bool get_topology_from_apic(struct cpuInfo* cpu, struct topology* topo) {
if (topo->cach == NULL) {
printWarn("get_topology_from_apic: cach is NULL");
return false;
}
uint32_t apic_id;
uint32_t* apic_ids = emalloc(sizeof(uint32_t) * topo->total_cores_module);
uint32_t* apic_pkg = emalloc(sizeof(uint32_t) * topo->total_cores_module);

4
src/x86/apic.h
View File

@@ -17,6 +17,10 @@ struct apic {
bool get_topology_from_apic(struct cpuInfo* cpu, struct topology* topo);
uint32_t is_smt_enabled_amd(struct topology* topo);
#ifndef __APPLE__
bool bind_to_cpu(int cpu_id);
#endif
#ifdef __linux__
int get_total_cores_module(int total_cores, int module);
#endif

371
src/x86/cpuid.c
View File

@@ -5,13 +5,6 @@
#include "../common/udev.h"
#include <unistd.h>
#endif
#if defined (__FreeBSD__) || defined (__APPLE__)
#include "../common/sysctl.h"
#endif
#ifdef __linux__
#include "../common/freq.h"
#endif
#include <stdio.h>
#include <stdlib.h>
@@ -29,35 +22,28 @@
#define CPU_VENDOR_INTEL_STRING "GenuineIntel"
#define CPU_VENDOR_AMD_STRING "AuthenticAMD"
#define CPU_VENDOR_HYGON_STRING "HygonGenuine"
static const char *hv_vendors_string[] = {
[HV_VENDOR_KVM] = "KVMKVMKVM",
[HV_VENDOR_QEMU] = "TCGTCGTCGTCG",
[HV_VENDOR_VBOX] = "VBoxVBoxVBox",
[HV_VENDOR_HYPERV] = "Microsoft Hv",
[HV_VENDOR_VMWARE] = "VMwareVMware",
[HV_VENDOR_XEN] = "XenVMMXenVMM",
[HV_VENDOR_PARALLELS] = "lrpepyh vr",
[HV_VENDOR_PHYP] = NULL,
[HV_VENDOR_BHYVE] = "bhyve bhyve ",
[HV_VENDOR_APPLEVZ] = "Apple VZ"
};
static char *hv_vendors_name[] = {
[HV_VENDOR_KVM] = "KVM",
[HV_VENDOR_QEMU] = "QEMU",
[HV_VENDOR_VBOX] = "VirtualBox",
[HV_VENDOR_HYPERV] = "Microsoft Hyper-V",
[HV_VENDOR_VMWARE] = "VMware",
[HV_VENDOR_XEN] = "Xen",
[HV_VENDOR_PARALLELS] = "Parallels",
[HV_VENDOR_PHYP] = "pHyp",
[HV_VENDOR_BHYVE] = "bhyve",
[HV_VENDOR_APPLEVZ] = "Apple VZ",
[HV_VENDOR_INVALID] = STRING_UNKNOWN
};
#define HYPERVISOR_NAME_MAX_LENGTH 17
#define MASK 0xFF
/*
@@ -84,14 +70,15 @@ void get_name_cpuid(char* name, uint32_t reg1, uint32_t reg2, uint32_t reg3) {
name[c++] = (reg3>>24) & MASK;
}
char* get_str_cpu_name_internal(void) {
char* get_str_cpu_name_internal() {
uint32_t eax = 0;
uint32_t ebx = 0;
uint32_t ecx = 0;
uint32_t edx = 0;
uint32_t c = 0;
char * name = ecalloc(CPU_NAME_MAX_LENGTH, sizeof(char));
char * name = emalloc(sizeof(char) * CPU_NAME_MAX_LENGTH);
memset(name, 0, CPU_NAME_MAX_LENGTH);
for(int i=0; i < 3; i++) {
eax = 0x80000002 + i;
@@ -210,18 +197,22 @@ int64_t get_peak_performance(struct cpuInfo* cpu, bool accurate_pp) {
for(int i=0; i < cpu->num_cpus; ptr = ptr->next_cpu, i++) {
struct topology* topo = ptr->topo;
int64_t freq = get_freq(ptr->freq);
int64_t max_freq = get_freq(ptr->freq);
int64_t freq;
#ifdef __linux__
if(accurate_pp)
freq = get_freq_pp(ptr->freq);
freq = measure_frequency(ptr);
else
freq = max_freq;
#else
// Silence compiler warning
(void)(accurate_pp);
freq = max_freq;
#endif
//First, check we have consistent data
if(freq == UNKNOWN_DATA || topo == NULL || topo->logical_cores == UNKNOWN_DATA) {
if(freq == UNKNOWN_DATA || topo->logical_cores == UNKNOWN_DATA) {
return -1;
}
@@ -232,10 +223,9 @@ int64_t get_peak_performance(struct cpuInfo* cpu, bool accurate_pp) {
if(feat->FMA3 || feat->FMA4)
flops = flops*2;
// NOTE:
// Some CPUs (Ice Lake, Zen 4) have AVX512, but they have only
// 1 VPU for AVX512, while they have 2 for AVX2. In such cases,
// we are computing the peak performance supposing AVX2, not AVX512
// Ice Lake has AVX512, but it has 1 VPU for AVX512, while
// it has 2 for AVX2. If this is a Ice Lake CPU, we are computing
// the peak performance supposing AVX2, not AVX512
if(feat->AVX512 && vpus_are_AVX512(ptr))
flops = flops*16;
else if(feat->AVX || feat->AVX2)
@@ -270,29 +260,23 @@ struct hypervisor* get_hp_info(bool hv_present) {
cpuid(&eax, &ebx, &ecx, &edx);
if(ebx == 0x0 && ecx == 0x0 && edx == 0x0) {
hv->hv_vendor = HV_VENDOR_INVALID;
printWarn("Hypervisor vendor is empty");
char name[13];
memset(name, 0, 13);
get_name_cpuid(name, ebx, ecx, edx);
bool found = false;
uint8_t len = sizeof(hv_vendors_string) / sizeof(hv_vendors_string[0]);
for(uint8_t v=0; v < len && !found; v++) {
if(strcmp(hv_vendors_string[v], name) == 0) {
hv->hv_vendor = v;
found = true;
}
}
else {
char name[13];
memset(name, 0, sizeof(char) * 13);
get_name_cpuid(name, ebx, ecx, edx);
bool found = false;
uint8_t len = sizeof(hv_vendors_string) / sizeof(hv_vendors_string[0]);
for(uint8_t v=0; v < len && !found; v++) {
if(hv_vendors_string[v] != NULL && strcmp(hv_vendors_string[v], name) == 0) {
hv->hv_vendor = v;
found = true;
}
}
if(!found) {
hv->hv_vendor = HV_VENDOR_INVALID;
printBug("Unknown hypervisor vendor: '%s'", name);
}
if(!found) {
hv->hv_vendor = HV_VENDOR_INVALID;
printWarn("Unknown hypervisor vendor: %s", name);
}
hv->hv_name = hv_vendors_name[hv->hv_vendor];
@@ -333,15 +317,6 @@ struct features* get_features_info(struct cpuInfo* cpu) {
bool hv_present = (ecx & (1U << 31)) != 0;
if((cpu->hv = get_hp_info(hv_present)) == NULL)
return NULL;
if(cpu->hv->present) {
// Hypervisor will likely mess up something and users will think that
// there is something wrong with cpufetch whereas actually cpufetch has
// nothing to do with it.
// https://github.com/Dr-Noob/cpufetch/issues/96
// https://github.com/Dr-Noob/cpufetch/issues/267
// https://github.com/Dr-Noob/cpufetch/issues/293
printWarn("You are running an hypervisor. Please note that it will likely tamper your results, so do not post an issue if you find anything incorrect");
}
}
else {
printWarn("Can't read features information from cpuid (needed level is 0x%.8X, max is 0x%.8X)", 0x00000001, cpu->maxLevels);
@@ -437,7 +412,7 @@ bool set_cpu_module(int m, int total_modules, int32_t* first_core) {
return true;
}
int32_t get_core_type(void) {
int32_t get_core_type() {
uint32_t eax = 0x0000001A;
uint32_t ebx = 0;
uint32_t ecx = 0;
@@ -455,24 +430,7 @@ int32_t get_core_type(void) {
}
}
#ifdef __linux__
// Gets the max frequency for estimating the peak performance,
// filling in the passed cpuInfo parameter with this information.
void fill_frequency_info_pp(struct cpuInfo* cpu) {
int32_t unused;
int32_t *max_freq_pp_vec = malloc(sizeof(int32_t) * cpu->num_cpus);
struct cpuInfo* ptr = cpu;
for (uint32_t i=0; i < cpu->num_cpus; i++) {
set_cpu_module(i, cpu->num_cpus, &unused);
ptr->freq->max_pp = measure_frequency(ptr, max_freq_pp_vec);
ptr = ptr->next_cpu;
}
}
#endif
struct cpuInfo* get_cpu_info(void) {
struct cpuInfo* get_cpu_info() {
struct cpuInfo* cpu = emalloc(sizeof(struct cpuInfo));
cpu->peak_performance = -1;
cpu->next_cpu = NULL;
@@ -480,7 +438,7 @@ struct cpuInfo* get_cpu_info(void) {
cpu->cach = NULL;
cpu->feat = NULL;
cpu->num_cpus = 1;
uint32_t modules = 1;
uint32_t eax = 0;
uint32_t ebx = 0;
uint32_t ecx = 0;
@@ -492,15 +450,13 @@ struct cpuInfo* get_cpu_info(void) {
//Fill vendor
char name[13];
memset(name, 0, sizeof(char) * 13);
memset(name,0,13);
get_name_cpuid(name, ebx, edx, ecx);
if(strcmp(CPU_VENDOR_INTEL_STRING,name) == 0)
cpu->cpu_vendor = CPU_VENDOR_INTEL;
else if (strcmp(CPU_VENDOR_AMD_STRING,name) == 0)
cpu->cpu_vendor = CPU_VENDOR_AMD;
else if (strcmp(CPU_VENDOR_HYGON_STRING,name) == 0)
cpu->cpu_vendor = CPU_VENDOR_HYGON;
else {
cpu->cpu_vendor = CPU_VENDOR_INVALID;
printErr("Unknown CPU vendor: %s", name);
@@ -519,8 +475,9 @@ struct cpuInfo* get_cpu_info(void) {
cpu->cpu_name = get_str_cpu_name_internal();
}
else {
cpu->cpu_name = NULL;
printWarn("Can't read CPU name from cpuid (needed extended level is 0x%.8X, max is 0x%.8X)", 0x80000004, cpu->maxExtendedLevels);
cpu->cpu_name = emalloc(sizeof(char) * (strlen(STRING_UNKNOWN) + 1));
strcpy(cpu->cpu_name, STRING_UNKNOWN);
printWarn("Can't read cpu name from cpuid (needed extended level is 0x%.8X, max is 0x%.8X)", 0x80000004, cpu->maxExtendedLevels);
}
cpu->topology_extensions = false;
@@ -538,12 +495,12 @@ struct cpuInfo* get_cpu_info(void) {
cpu->hybrid_flag = (edx >> 15) & 0x1;
}
if(cpu->hybrid_flag) cpu->num_cpus = 2;
if(cpu->hybrid_flag) modules = 2;
struct cpuInfo* ptr = cpu;
for(uint32_t i=0; i < cpu->num_cpus; i++) {
for(uint32_t i=0; i < modules; i++) {
int32_t first_core;
set_cpu_module(i, cpu->num_cpus, &first_core);
set_cpu_module(i, modules, &first_core);
if(i > 0) {
ptr->next_cpu = emalloc(sizeof(struct cpuInfo));
@@ -568,18 +525,16 @@ struct cpuInfo* get_cpu_info(void) {
ptr->core_type = get_core_type();
}
ptr->first_core_id = first_core;
ptr->module_id = i;
ptr->feat = get_features_info(ptr);
// If any field of the struct is NULL,
// return inmideately, as further functions
// require valid fields (cach, topo, etc)
ptr->arch = get_cpu_uarch(ptr);
ptr->freq = get_frequency_info(ptr);
if (cpu->cpu_name == NULL && ptr == cpu) {
// If we couldnt read CPU name from cpuid, infer it now
cpu->cpu_name = infer_cpu_name_from_uarch(cpu->arch);
}
ptr->cach = get_cache_info(ptr);
if(ptr->cach == NULL) return cpu;
if(cpu->hybrid_flag) {
ptr->topo = get_topology_info(ptr, ptr->cach, i);
@@ -587,30 +542,16 @@ struct cpuInfo* get_cpu_info(void) {
else {
ptr->topo = get_topology_info(ptr, ptr->cach, -1);
}
// If topo is NULL, return early, as get_peak_performance
// requries non-NULL topology.
if(ptr->topo == NULL) return cpu;
if(cpu->topo == NULL) return cpu;
}
#ifdef __linux__
// If accurate_pp is requested, we need to get the max frequency
// after fetching the topology for all CPU modules, since the topology
// is required by fill_frequency_info_pp
if (accurate_pp()) fill_frequency_info_pp(cpu);
#endif
cpu->num_cpus = modules;
cpu->peak_performance = get_peak_performance(cpu, accurate_pp());
return cpu;
}
bool get_cache_topology_amd(struct cpuInfo* cpu, struct topology* topo) {
if (topo->cach == NULL) {
printWarn("get_cache_topology_amd: cach is NULL");
return false;
}
if(cpu->maxExtendedLevels >= 0x8000001D && cpu->topology_extensions) {
uint32_t i, eax, ebx, ecx, edx, num_sharing_cache, cache_type, cache_level;
@@ -684,24 +625,15 @@ bool get_cache_topology_amd(struct cpuInfo* cpu, struct topology* topo) {
return true;
}
#ifdef __linux__
void get_topology_from_udev(struct topology* topo) {
topo->total_cores = get_ncores_from_cpuinfo();
// TODO: To be improved in the future
if (topo->total_cores == 1) {
// We can assume it's a single core CPU
topo->logical_cores = topo->total_cores;
topo->physical_cores = topo->total_cores;
}
else {
topo->logical_cores = UNKNOWN_DATA;
topo->physical_cores = UNKNOWN_DATA;
}
topo->total_cores = get_ncores_from_cpuinfo();
topo->logical_cores = topo->total_cores;
topo->physical_cores = topo->total_cores;
topo->smt_available = 1;
topo->smt_supported = 1;
topo->sockets = 1;
}
#endif
// Main reference: https://software.intel.com/content/www/us/en/develop/articles/intel-64-architecture-processor-topology-enumeration.html
// Very interesting resource: https://wiki.osdev.org/Detecting_CPU_Topology_(80x86)
@@ -741,31 +673,32 @@ struct topology* get_topology_info(struct cpuInfo* cpu, struct cache* cach, int
topo->total_cores_module = topo->total_cores;
}
bool toporet = false;
switch(cpu->cpu_vendor) {
case CPU_VENDOR_INTEL:
if (cpu->maxLevels >= 0x00000004) {
toporet = get_topology_from_apic(cpu, topo);
bool toporet = get_topology_from_apic(cpu, topo);
if(!toporet) {
#ifdef __linux__
printWarn("Failed to retrieve topology from APIC, using udev...\n");
get_topology_from_udev(topo);
#else
printErr("Failed to retrieve topology from APIC, assumming default values...\n");
topo->logical_cores = UNKNOWN_DATA;
topo->physical_cores = UNKNOWN_DATA;
topo->smt_available = 1;
topo->smt_supported = 1;
#endif
}
}
else {
printWarn("Can't read topology information from cpuid (needed level is 0x%.8X, max is 0x%.8X)", 0x00000004, cpu->maxLevels);
}
if(!toporet) {
#ifdef __linux__
printWarn("Failed to retrieve topology from APIC, using udev...");
get_topology_from_udev(topo);
#else
if (cpu->maxLevels >= 0x00000004)
printErr("Failed to retrieve topology from APIC, assumming default values...");
topo->logical_cores = UNKNOWN_DATA;
topo->physical_cores = UNKNOWN_DATA;
topo->smt_available = 1;
topo->smt_supported = 1;
#endif
printWarn("Can't read topology information from cpuid (needed level is 0x%.8X, max is 0x%.8X)", 0x00000001, cpu->maxLevels);
topo->physical_cores = 1;
topo->logical_cores = 1;
topo->smt_available = 1;
topo->smt_supported = 1;
}
break;
case CPU_VENDOR_AMD:
case CPU_VENDOR_HYGON:
if (cpu->maxExtendedLevels >= 0x80000008) {
eax = 0x80000008;
cpuid(&eax, &ebx, &ecx, &edx);
@@ -782,15 +715,10 @@ struct topology* get_topology_info(struct cpuInfo* cpu, struct cache* cach, int
}
}
else {
#ifdef __linux__
printWarn("Can't read topology information from cpuid (needed extended level is 0x%.8X, max is 0x%.8X), using udev...", 0x80000008, cpu->maxExtendedLevels);
get_topology_from_udev(topo);
#else
printWarn("Can't read topology information from cpuid (needed extended level is 0x%.8X, max is 0x%.8X)", 0x80000008, cpu->maxExtendedLevels);
topo->physical_cores = 1;
topo->logical_cores = 1;
topo->smt_supported = 1;
#endif
printWarn("Can't read topology information from cpuid (needed extended level is 0x%.8X, max is 0x%.8X)", 0x80000008, cpu->maxExtendedLevels);
topo->physical_cores = 1;
topo->logical_cores = 1;
topo->smt_supported = 1;
}
if (cpu->maxLevels >= 0x00000001) {
@@ -967,27 +895,16 @@ struct cache* get_cache_info(struct cpuInfo* cpu) {
struct frequency* get_frequency_info(struct cpuInfo* cpu) {
struct frequency* freq = emalloc(sizeof(struct frequency));
freq->measured = false;
if(cpu->maxLevels < 0x00000016) {
#if defined (_WIN32)
#if defined (_WIN32) || defined (__APPLE__)
printWarn("Can't read frequency information from cpuid (needed level is 0x%.8X, max is 0x%.8X)", 0x00000016, cpu->maxLevels);
freq->base = UNKNOWN_DATA;
freq->max = UNKNOWN_DATA;
#elif defined (__FreeBSD__) || defined (__APPLE__)
printWarn("Can't read frequency information from cpuid (needed level is 0x%.8X, max is 0x%.8X). Using sysctl", 0x00000016, cpu->maxLevels);
uint32_t freq_hz = get_sys_info_by_name(CPUFREQUENCY_SYSCTL);
if (freq_hz == 0) {
printWarn("Read max CPU frequency from sysctl and got 0 MHz");
freq->max = UNKNOWN_DATA;
}
freq->base = UNKNOWN_DATA;
freq->max = freq_hz;
#else
printWarn("Can't read frequency information from cpuid (needed level is 0x%.8X, max is 0x%.8X). Using udev", 0x00000016, cpu->maxLevels);
freq->base = UNKNOWN_DATA;
freq->max = get_max_freq_from_file(cpu->first_core_id);
freq->max = get_max_freq_from_file(0);
if(freq->max == 0) {
printWarn("Read max CPU frequency from udev and got 0 MHz");
@@ -1014,7 +931,7 @@ struct frequency* get_frequency_info(struct cpuInfo* cpu) {
printWarn("Read max CPU frequency from CPUID and got 0 MHz");
#ifdef __linux__
printWarn("Using udev to detect frequency");
freq->max = get_max_freq_from_file(cpu->first_core_id);
freq->max = get_max_freq_from_file(0);
if(freq->max == 0) {
printWarn("Read max CPU frequency from udev and got 0 MHz");
@@ -1026,16 +943,6 @@ struct frequency* get_frequency_info(struct cpuInfo* cpu) {
}
}
#ifdef __linux__
if (freq->max == UNKNOWN_DATA || measure_max_frequency_flag()) {
if (freq->max == UNKNOWN_DATA)
printWarn("All previous methods failed, measuring CPU frequency");
freq->max = measure_max_frequency(cpu->first_core_id);
freq->measured = true;
}
#endif
freq->max_pp = UNKNOWN_DATA;
return freq;
}
@@ -1057,34 +964,25 @@ char* get_str_topology(struct cpuInfo* cpu, struct topology* topo, bool dual_soc
string = emalloc(sizeof(char) * (strlen(STRING_UNKNOWN) + 1));
strcpy(string, STRING_UNKNOWN);
}
else {
char cores_str[6];
memset(cores_str, 0, sizeof(char) * 6);
if (topo->physical_cores * topo_sockets > 1)
strcpy(cores_str, "cores");
else
strcpy(cores_str, "core");
else if(topo->smt_supported > 1) {
// 4 for digits, 21 for ' cores (SMT disabled)' which is the longest possible output
uint32_t max_size = 4+21+1;
string = emalloc(sizeof(char) * max_size);
if(topo->smt_supported > 1) {
// 4 for digits, 21 for ' cores (SMT disabled)' which is the longest possible output
uint32_t max_size = 4+21+1;
string = emalloc(sizeof(char) * max_size);
if(topo->smt_available > 1)
snprintf(string, max_size, "%d %s (%d threads)", topo->physical_cores * topo_sockets, cores_str, topo->logical_cores * topo_sockets);
else {
if(cpu->cpu_vendor == CPU_VENDOR_AMD)
snprintf(string, max_size, "%d %s (SMT disabled)", topo->physical_cores * topo_sockets, cores_str);
else
snprintf(string, max_size, "%d %s (HT disabled)", topo->physical_cores * topo_sockets, cores_str);
}
}
if(topo->smt_available > 1)
snprintf(string, max_size, "%d cores (%d threads)", topo->physical_cores * topo_sockets, topo->logical_cores * topo_sockets);
else {
uint32_t max_size = 4+7+1;
string = emalloc(sizeof(char) * max_size);
snprintf(string, max_size, "%d %s",topo->physical_cores * topo_sockets, cores_str);
if(cpu->cpu_vendor == CPU_VENDOR_AMD)
snprintf(string, max_size, "%d cores (SMT disabled)", topo->physical_cores * topo_sockets);
else
snprintf(string, max_size, "%d cores (HT disabled)", topo->physical_cores * topo_sockets);
}
}
else {
uint32_t max_size = 4+7+1;
string = emalloc(sizeof(char) * max_size);
snprintf(string, max_size, "%d cores",topo->physical_cores * topo_sockets);
}
return string;
}
@@ -1144,14 +1042,8 @@ char* get_str_sse(struct cpuInfo* cpu) {
last+=SSE4_2_sl;
}
if (last == 0) {
snprintf(string, 2+1, "No");
}
else {
//Purge last comma
string[last-1] = '\0';
}
//Purge last comma
string[last-1] = '\0';
return string;
}
@@ -1192,29 +1084,12 @@ void print_debug(struct cpuInfo* cpu) {
free_cpuinfo_struct(cpu);
}
void print_raw_level(uint32_t reg) {
uint32_t eax = reg;
uint32_t ebx = 0;
uint32_t ecx = 0;
uint32_t edx = 0;
cpuid(&eax, &ebx, &ecx, &edx);
printf(" 0x%.8X 0x%.2X: 0x%.8X 0x%.8X 0x%.8X 0x%.8X\n", reg, 0x00, eax, ebx, ecx, edx);
}
void print_raw_sublevel(uint32_t reg, uint32_t reg2) {
uint32_t eax = reg;
uint32_t ebx = 0;
uint32_t ecx = reg2;
uint32_t edx = 0;
cpuid(&eax, &ebx, &ecx, &edx);
printf(" 0x%.8X 0x%.2X: 0x%.8X 0x%.8X 0x%.8X 0x%.8X\n", reg, reg2, eax, ebx, ecx, edx);
}
// TODO: Query HV and Xeon Phi levels
void print_raw(struct cpuInfo* cpu) {
uint32_t eax;
uint32_t ebx;
uint32_t ecx;
uint32_t edx;
printf("%s\n\n", cpu->cpu_name);
printf(" CPUID leaf sub EAX EBX ECX EDX \n");
printf("--------------------------------------------------------------\n");
@@ -1229,40 +1104,66 @@ void print_raw(struct cpuInfo* cpu) {
printf("CPU %d:\n", c);
// Standard levels
for(uint32_t reg=0x00000000; reg <= cpu->maxLevels; reg++) {
if(reg == 0x00000004) {
for(uint32_t reg2=0x00000000; reg2 < cpu->cach->max_cache_level; reg2++) {
print_raw_sublevel(reg, reg2);
eax = reg;
ebx = 0;
ecx = reg2;
edx = 0;
cpuid(&eax, &ebx, &ecx, &edx);
printf(" 0x%.8X 0x%.2X: 0x%.8X 0x%.8X 0x%.8X 0x%.8X\n", reg, reg2, eax, ebx, ecx, edx);
}
}
else if(reg == 0x0000000B) {
for(uint32_t reg2=0x00000000; reg2 < cpu->topo->smt_supported; reg2++) {
print_raw_sublevel(reg, reg2);
eax = reg;
ebx = 0;
ecx = reg2;
edx = 0;
cpuid(&eax, &ebx, &ecx, &edx);
printf(" 0x%.8X 0x%.2X: 0x%.8X 0x%.8X 0x%.8X 0x%.8X\n", reg, reg2, eax, ebx, ecx, edx);
}
}
else {
print_raw_level(reg);
eax = reg;
ebx = 0;
ecx = 0;
edx = 0;
cpuid(&eax, &ebx, &ecx, &edx);
printf(" 0x%.8X 0x%.2X: 0x%.8X 0x%.8X 0x%.8X 0x%.8X\n", reg, 0x00, eax, ebx, ecx, edx);
}
}
// Hypervisor levels
for(uint32_t reg=0x40000000; reg <= 0x40000006; reg++) {
print_raw_level(reg);
}
// Extended levels
for(uint32_t reg=0x80000000; reg <= cpu->maxExtendedLevels; reg++) {
if(reg == 0x8000001D) {
for(uint32_t reg2=0x00000000; reg2 < cpu->cach->max_cache_level; reg2++) {
print_raw_sublevel(reg, reg2);
eax = reg;
ebx = 0;
ecx = reg2;
edx = 0;
cpuid(&eax, &ebx, &ecx, &edx);
printf(" 0x%.8X 0x%.2X: 0x%.8X 0x%.8X 0x%.8X 0x%.8X\n", reg, reg2, eax, ebx, ecx, edx);
}
}
else {
print_raw_level(reg);
eax = reg;
ebx = 0;
ecx = 0;
edx = 0;
cpuid(&eax, &ebx, &ecx, &edx);
printf(" 0x%.8X 0x%.2X: 0x%.8X 0x%.8X 0x%.8X 0x%.8X\n", reg, 0x00, eax, ebx, ecx, edx);
}
}
}
}

2
src/x86/cpuid.h
View File

@@ -3,7 +3,7 @@
#include "../common/cpu.h"
struct cpuInfo* get_cpu_info(void);
struct cpuInfo* get_cpu_info();
struct cache* get_cache_info(struct cpuInfo* cpu);
struct frequency* get_frequency_info(struct cpuInfo* cpu);
struct topology* get_topology_info(struct cpuInfo* cpu, struct cache* cach, int module);

58
src/x86/freq/freq.c
View File

@@ -21,12 +21,9 @@
#define FREQ_VECTOR_SIZE 1<<16
struct freq_thread {
// Inputs
struct cpuInfo* cpu;
bool end;
bool measure;
// Output
int32_t *max_pp;
double freq;
};
double vector_average_harmonic(double* v, int len) {
@@ -51,7 +48,6 @@ void* measure_freq(void *freq_ptr) {
char* line = NULL;
size_t len = 0;
ssize_t read;
struct cpuInfo* cpu = freq->cpu;
int v = 0;
double* freq_vector = malloc(sizeof(double) * FREQ_VECTOR_SIZE);
@@ -80,43 +76,18 @@ void* measure_freq(void *freq_ptr) {
sleep_ms(500);
}
if (cpu->hybrid_flag) {
// We have an heterogeneous architecture. After measuring the
// frequency for all cores, we now need to compute the average
// independently for each CPU module.
struct cpuInfo* ptr = cpu;
double* freq_vector_ptr = freq_vector;
for (int i=0; i < cpu->num_cpus; ptr = ptr->next_cpu, i++) {
freq->max_pp[i] = vector_average_harmonic(freq_vector_ptr, ptr->topo->total_cores_module);
printWarn("AVX2 measured freq=%d (module %d)", freq->max_pp[i], i);
freq_vector_ptr = freq_vector_ptr + ptr->topo->total_cores_module;
}
}
else {
freq->max_pp[0] = vector_average_harmonic(freq_vector, v);
printWarn("AVX2 measured freq=%d\n", freq->max_pp[0]);
}
freq->freq = vector_average_harmonic(freq_vector, v);
printWarn("AVX2 measured freq=%f\n", freq->freq);
return NULL;
}
int32_t measure_frequency(struct cpuInfo* cpu, int32_t *max_freq_pp_vec) {
if (cpu->hybrid_flag && cpu->module_id > 0) {
// We have a hybrid architecture and we have already
// measured the frequency for this module in a previous
// call to this function, so now just return it.
return max_freq_pp_vec[cpu->module_id];
}
int64_t measure_frequency(struct cpuInfo* cpu) {
int ret;
int num_spaces;
struct freq_thread* freq_struct = malloc(sizeof(struct freq_thread));
freq_struct->end = false;
freq_struct->measure = false;
freq_struct->cpu = cpu;
freq_struct->max_pp = max_freq_pp_vec;
void* (*compute_function)(void*);
@@ -145,25 +116,8 @@ int32_t measure_frequency(struct cpuInfo* cpu, int32_t *max_freq_pp_vec) {
}
pthread_t* compute_th = malloc(sizeof(pthread_t) * cpu->topo->total_cores);
cpu_set_t cpus;
pthread_attr_t attr;
if ((ret = pthread_attr_init(&attr)) != 0) {
printErr("pthread_attr_init: %s", strerror(ret));
return -1;
}
for(int i=0; i < cpu->topo->total_cores; i++) {
// We might have called bind_to_cpu previously, binding the threads
// to a specific core, so now we must make sure we run the new thread
// on the correct core.
CPU_ZERO(&cpus);
CPU_SET(i, &cpus);
if ((ret = pthread_attr_setaffinity_np(&attr, sizeof(cpu_set_t), &cpus)) != 0) {
printErr("pthread_attr_setaffinity_np: %s", strerror(ret));
return -1;
}
ret = pthread_create(&compute_th[i], &attr, compute_function, NULL);
ret = pthread_create(&compute_th[i], NULL, compute_function, NULL);
if(ret != 0) {
fprintf(stderr, "Error creating thread\n");
@@ -188,5 +142,5 @@ int32_t measure_frequency(struct cpuInfo* cpu, int32_t *max_freq_pp_vec) {
}
printf("\r%*c", num_spaces, ' ');
return max_freq_pp_vec[0];
return freq_struct->freq;
}

3
src/x86/freq/freq.h
View File

@@ -3,11 +3,10 @@
#include <stdint.h>
#include "../../common/cpu.h"
#include "../../common/global.h"
#define MEASURE_TIME_SECONDS 5
#define LOOP_ITERS 100000000
int32_t measure_frequency(struct cpuInfo* cpu, int32_t *max_freq_pp_vec);
int64_t measure_frequency(struct cpuInfo* cpu);
#endif

3
src/x86/freq/freq_avx.c
View File

@@ -10,8 +10,7 @@
#include <stdint.h>
#include "freq.h"
void* compute_avx(void * pthread_arg) {
UNUSED(pthread_arg);
void* compute_avx() {
bool end = false;
struct timeval begin, now;

2
src/x86/freq/freq_avx.h
View File

@@ -1,6 +1,6 @@
#ifndef __FREQ_AVX__
#define __FREQ_AVX__
void* compute_avx(void * pthread_arg);
void* compute_avx();
#endif

3
src/x86/freq/freq_avx512.c
View File

@@ -10,8 +10,7 @@
#include <stdint.h>
#include "freq.h"
void* compute_avx512(void * pthread_arg) {
UNUSED(pthread_arg);
void* compute_avx512() {
bool end = false;
struct timeval begin, now;

2
src/x86/freq/freq_avx512.h
View File

@@ -1,6 +1,6 @@
#ifndef __FREQ_AVX512__
#define __FREQ_AVX512__
void* compute_avx512(void * pthread_arg);
void* compute_avx512();
#endif

3
src/x86/freq/freq_nov.c
View File

@@ -10,8 +10,7 @@
#include <stdint.h>
#include "freq.h"
void* compute_nov(void * pthread_arg) {
UNUSED(pthread_arg);
void* compute_nov() {
bool end = false;
struct timeval begin, now;

2
src/x86/freq/freq_nov.h
View File

@@ -1,6 +1,6 @@
#ifndef __FREQ_NO_VECTOR__
#define __FREQ_NO_VECTOR__
void* compute_nov(void * pthread_arg);
void* compute_nov();
#endif

464
src/x86/uarch.c
View File

@@ -47,12 +47,8 @@ typedef uint32_t MICROARCH;
enum {
UARCH_UNKNOWN,
// INTEL //
UARCH_I486,
UARCH_P5,
UARCH_P5_MMX,
UARCH_P6_PRO,
UARCH_P6_PENTIUM_II,
UARCH_P6_PENTIUM_III,
UARCH_P6,
UARCH_DOTHAN,
UARCH_YONAH,
UARCH_MEROM,
@@ -93,15 +89,12 @@ enum {
UARCH_CEDAR_MILL,
UARCH_ITANIUM2,
UARCH_ICE_LAKE,
UARCH_SAPPHIRE_RAPIDS,
UARCH_TIGER_LAKE,
UARCH_ALDER_LAKE,
UARCH_RAPTOR_LAKE,
// AMD //
UARCH_AM486,
UARCH_AM5X86,
UARCH_SSA5,
UARCH_K5,
UARCH_K6,
UARCH_K7,
UARCH_K8,
@@ -119,10 +112,7 @@ enum {
UARCH_ZEN2,
UARCH_ZEN3,
UARCH_ZEN3_PLUS,
UARCH_ZEN4,
UARCH_ZEN4C,
UARCH_ZEN5,
UARCH_ZEN5C,
UARCH_ZEN4
};
struct uarch {
@@ -134,8 +124,7 @@ struct uarch {
#define UARCH_START if (false) {}
#define CHECK_UARCH(arch, ef_, f_, em_, m_, s_, str, uarch, process) \
else if (ef_ == ef && f_ == f && (em_ == NA || em_ == em) && (m_ == NA || m_ == m) && (s_ == NA || s_ == s)) fill_uarch(arch, str, uarch, process);
#define UARCH_END else { printBugCheckRelease("Unknown microarchitecture detected: M=0x%X EM=0x%X F=0x%X EF=0x%X S=0x%X", m, em, f, ef, s); \
fill_uarch(arch, STRING_UNKNOWN, UARCH_UNKNOWN, UNK); }
#define UARCH_END else { printBug("Unknown microarchitecture detected: M=0x%.8X EM=0x%.8X F=0x%.8X EF=0x%.8X S=0x%.8X", m, em, f, ef, s); fill_uarch(arch, STRING_UNKNOWN, UARCH_UNKNOWN, 0); }
void fill_uarch(struct uarch* arch, char* str, MICROARCH u, uint32_t process) {
arch->uarch_str = emalloc(sizeof(char) * (strlen(str)+1));
@@ -148,144 +137,127 @@ void fill_uarch(struct uarch* arch, char* str, MICROARCH u, uint32_t process) {
struct uarch* get_uarch_from_cpuid_intel(uint32_t ef, uint32_t f, uint32_t em, uint32_t m, int s) {
struct uarch* arch = emalloc(sizeof(struct uarch));
// EF: Extended Family //
// F: Family //
// EM: Extended Model //
// M: Model //
// S: Stepping //
// ------------------------------------------------------------------------------- //
// EF F EM M S //
// EF: Extended Family //
// F: Family //
// EM: Extended Model //
// M: Model //
// S: Stepping //
// ----------------------------------------------------------------------------- //
// EF F EM M S //
UARCH_START
CHECK_UARCH(arch, 0, 4, 0, 0, NA, "i80486DX", UARCH_I486, UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
CHECK_UARCH(arch, 0, 4, 0, 1, NA, "i80486DX-50", UARCH_I486, UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
CHECK_UARCH(arch, 0, 4, 0, 2, NA, "i80486SX", UARCH_I486, UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
CHECK_UARCH(arch, 0, 4, 0, 3, NA, "i80486DX2", UARCH_I486, UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
CHECK_UARCH(arch, 0, 4, 0, 4, NA, "i80486SL", UARCH_I486, UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
CHECK_UARCH(arch, 0, 4, 0, 5, NA, "i80486SX2", UARCH_I486, UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
CHECK_UARCH(arch, 0, 4, 0, 7, NA, "i80486DX2WB", UARCH_I486, UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
CHECK_UARCH(arch, 0, 4, 0, 8, NA, "i80486DX4", UARCH_I486, UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
CHECK_UARCH(arch, 0, 4, 0, 9, NA, "i80486DX4WB", UARCH_I486, UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
CHECK_UARCH(arch, 0, 5, 0, 0, NA, "P5", UARCH_P5, 800)
CHECK_UARCH(arch, 0, 5, 0, 1, NA, "P5", UARCH_P5, 800)
CHECK_UARCH(arch, 0, 5, 0, 2, NA, "P54C", UARCH_P5, UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
CHECK_UARCH(arch, 0, 5, 0, 3, NA, "P24T (Overdrive)", UARCH_P5, 600) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
CHECK_UARCH(arch, 0, 5, 0, 4, NA, "P55C (MMX)", UARCH_P5_MMX, 350) // https://www.cpu-world.com/CPUs/Pentium/TYPE-Pentium%20MMX.html
CHECK_UARCH(arch, 0, 5, 0, 7, NA, "P54C", UARCH_P5, 350) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
CHECK_UARCH(arch, 0, 5, 0, 8, NA, "Tillamook", UARCH_P5_MMX, 250) // http://instlatx64.atw.hu./
CHECK_UARCH(arch, 0, 5, 0, 9, 0, "Lakemont", UARCH_LAKEMONT, 32)
CHECK_UARCH(arch, 0, 5, 0, 9, NA, "P5 (MMX)", UARCH_P5_MMX, UNK)
CHECK_UARCH(arch, 0, 5, 0, 10, 0, "Lakemont", UARCH_LAKEMONT, 32)
CHECK_UARCH(arch, 0, 6, 0, 1, 1, "P6", UARCH_P6_PRO, UNK)
CHECK_UARCH(arch, 0, 6, 0, 1, 2, "P6", UARCH_P6_PRO, UNK)
CHECK_UARCH(arch, 0, 6, 0, 1, 6, "P6", UARCH_P6_PRO, 350)
CHECK_UARCH(arch, 0, 6, 0, 1, 7, "P6", UARCH_P6_PRO, 350)
CHECK_UARCH(arch, 0, 6, 0, 1, 9, "P6", UARCH_P6_PRO, 350)
CHECK_UARCH(arch, 0, 6, 0, 0, NA, "P6 (Pentium II)", UARCH_P6_PENTIUM_II, UNK)
CHECK_UARCH(arch, 0, 6, 0, 1, NA, "P6 (Pentium II)", UARCH_P6_PENTIUM_II, UNK) // process depends on core
CHECK_UARCH(arch, 0, 6, 0, 2, NA, "P6 (Pentium II)", UARCH_P6_PENTIUM_II, UNK)
CHECK_UARCH(arch, 0, 6, 0, 3, NA, "P6 (Klamath)", UARCH_P6_PENTIUM_II, 350) // http://instlatx64.atw.hu.
CHECK_UARCH(arch, 0, 6, 0, 4, NA, "P6 (Pentium II)", UARCH_P6_PENTIUM_II, UNK)
CHECK_UARCH(arch, 0, 6, 0, 5, NA, "P6 (Deschutes)", UARCH_P6_PENTIUM_II, 250) // http://instlatx64.atw.hu.
CHECK_UARCH(arch, 0, 6, 0, 6, NA, "P6 (Dixon)", UARCH_P6_PENTIUM_II, UNK) // http://instlatx64.atw.hu.
CHECK_UARCH(arch, 0, 6, 0, 7, NA, "P6 (Katmai)", UARCH_P6_PENTIUM_III, 250) // Core names from: https://en.wikichip.org/wiki/intel/cpuid. NOTE: Xeon core names are different! https://www.techpowerup.com/cpu-specs/?generation=Intel+Pentium+III+Xeon
CHECK_UARCH(arch, 0, 6, 0, 8, NA, "P6 (Coppermine)", UARCH_P6_PENTIUM_III, 180) // Also: https://en.wikipedia.org/wiki/Pentium_III
CHECK_UARCH(arch, 0, 6, 0, 9, NA, "P6 (Pentium M)", UARCH_P6_PENTIUM_III, 130)
CHECK_UARCH(arch, 0, 6, 0, 10, NA, "P6 (Coppermine T)", UARCH_P6_PENTIUM_III, 180)
CHECK_UARCH(arch, 0, 6, 0, 11, NA, "P6 (Tualatin)", UARCH_P6_PENTIUM_III, 130)
CHECK_UARCH(arch, 0, 6, 0, 13, NA, "Dothan", UARCH_DOTHAN, UNK) // process depends on core
CHECK_UARCH(arch, 0, 6, 0, 14, NA, "Yonah", UARCH_YONAH, 65)
CHECK_UARCH(arch, 0, 6, 0, 15, NA, "Merom", UARCH_MEROM, 65)
CHECK_UARCH(arch, 0, 6, 1, 5, NA, "Dothan", UARCH_DOTHAN, 90)
CHECK_UARCH(arch, 0, 6, 1, 6, NA, "Merom", UARCH_MEROM, 65)
CHECK_UARCH(arch, 0, 6, 1, 7, NA, "Penryn", UARCH_PENYR, 45)
CHECK_UARCH(arch, 0, 6, 1, 10, NA, "Nehalem", UARCH_NEHALEM, 45)
CHECK_UARCH(arch, 0, 6, 1, 12, NA, "Bonnell", UARCH_BONNELL, 45)
CHECK_UARCH(arch, 0, 6, 1, 13, NA, "Penryn", UARCH_PENYR, 45)
CHECK_UARCH(arch, 0, 6, 1, 14, NA, "Nehalem", UARCH_NEHALEM, 45)
CHECK_UARCH(arch, 0, 6, 1, 15, NA, "Nehalem", UARCH_NEHALEM, 45)
CHECK_UARCH(arch, 0, 6, 2, 5, NA, "Westmere", UARCH_WESTMERE, 32)
CHECK_UARCH(arch, 0, 6, 2 , 6, NA, "Bonnell", UARCH_BONNELL, 45)
CHECK_UARCH(arch, 0, 6, 2, 7, NA, "Saltwell", UARCH_SALTWELL, 32)
CHECK_UARCH(arch, 0, 6, 2, 10, NA, "Sandy Bridge", UARCH_SANDY_BRIDGE, 32)
CHECK_UARCH(arch, 0, 6, 2, 12, NA, "Westmere", UARCH_WESTMERE, 32)
CHECK_UARCH(arch, 0, 6, 2, 13, NA, "Sandy Bridge", UARCH_SANDY_BRIDGE, 32)
CHECK_UARCH(arch, 0, 6, 2, 14, NA, "Nehalem", UARCH_NEHALEM, 45)
CHECK_UARCH(arch, 0, 6, 2, 15, NA, "Westmere", UARCH_WESTMERE, 32)
CHECK_UARCH(arch, 0, 6, 3, 5, NA, "Saltwell", UARCH_SALTWELL, 14)
CHECK_UARCH(arch, 0, 6, 3, 6, NA, "Saltwell", UARCH_SALTWELL, 32)
CHECK_UARCH(arch, 0, 6, 3, 7, NA, "Silvermont", UARCH_SILVERMONT, 22)
CHECK_UARCH(arch, 0, 6, 3, 10, NA, "Ivy Bridge", UARCH_IVY_BRIDGE, 22)
CHECK_UARCH(arch, 0, 6, 3, 12, NA, "Haswell", UARCH_HASWELL, 22)
CHECK_UARCH(arch, 0, 6, 3, 13, NA, "Broadwell", UARCH_BROADWELL, 14)
CHECK_UARCH(arch, 0, 6, 3, 14, NA, "Ivy Bridge", UARCH_IVY_BRIDGE, 22)
CHECK_UARCH(arch, 0, 6, 3, 15, NA, "Haswell", UARCH_HASWELL, 22)
CHECK_UARCH(arch, 0, 6, 4, 5, NA, "Haswell", UARCH_HASWELL, 22)
CHECK_UARCH(arch, 0, 6, 4, 6, NA, "Haswell", UARCH_HASWELL, 22)
CHECK_UARCH(arch, 0, 6, 4, 7, NA, "Broadwell", UARCH_BROADWELL, 14)
CHECK_UARCH(arch, 0, 6, 4, 10, NA, "Silvermont", UARCH_SILVERMONT, 22) // no docs, but /proc/cpuinfo seen in wild
CHECK_UARCH(arch, 0, 6, 4, 12, NA, "Airmont", UARCH_AIRMONT, 14)
CHECK_UARCH(arch, 0, 6, 4, 13, NA, "Silvermont", UARCH_SILVERMONT, 22)
CHECK_UARCH(arch, 0, 6, 4, 14, 8, "Kaby Lake", UARCH_KABY_LAKE, 14)
CHECK_UARCH(arch, 0, 6, 4, 14, NA, "Skylake", UARCH_SKYLAKE, 14)
CHECK_UARCH(arch, 0, 6, 4, 15, NA, "Broadwell", UARCH_BROADWELL, 14)
CHECK_UARCH(arch, 0, 6, 5, 5, 6, "Cascade Lake", UARCH_CASCADE_LAKE, 14) // no docs, but example from Greg Stewart
CHECK_UARCH(arch, 0, 6, 5, 5, 7, "Cascade Lake", UARCH_CASCADE_LAKE, 14)
CHECK_UARCH(arch, 0, 6, 5, 5, 10, "Cooper Lake", UARCH_COOPER_LAKE, 14)
CHECK_UARCH(arch, 0, 6, 5, 5, NA, "Skylake", UARCH_SKYLAKE, 14)
CHECK_UARCH(arch, 0, 6, 5, 6, NA, "Broadwell", UARCH_BROADWELL, 14)
CHECK_UARCH(arch, 0, 6, 5, 7, NA, "Knights Landing", UARCH_KNIGHTS_LANDING, 14)
CHECK_UARCH(arch, 0, 6, 5, 10, NA, "Silvermont", UARCH_SILVERMONT, 22) // no spec update; only MSR_CPUID_table* so far
CHECK_UARCH(arch, 0, 6, 5, 12, NA, "Goldmont", UARCH_GOLDMONT, 14)
CHECK_UARCH(arch, 0, 6, 5, 13, NA, "Silvermont", UARCH_SILVERMONT, 22) // no spec update; only MSR_CPUID_table* so far
CHECK_UARCH(arch, 0, 6, 5, 14, 8, "Kaby Lake", UARCH_KABY_LAKE, 14)
CHECK_UARCH(arch, 0, 6, 5, 14, NA, "Skylake", UARCH_SKYLAKE, 14)
CHECK_UARCH(arch, 0, 6, 5, 15, NA, "Goldmont", UARCH_GOLDMONT, 14)
CHECK_UARCH(arch, 0, 6, 6, 6, NA, "Palm Cove", UARCH_PALM_COVE, 10) // no spec update; only MSR_CPUID_table* so far
CHECK_UARCH(arch, 0, 6, 6, 10, NA, "Sunny Cove", UARCH_SUNNY_COVE, 10) // no spec update; only MSR_CPUID_table* so far
CHECK_UARCH(arch, 0, 6, 6, 12, NA, "Sunny Cove", UARCH_SUNNY_COVE, 10) // no spec update; only MSR_CPUID_table* so far
CHECK_UARCH(arch, 0, 6, 7, 5, NA, "Airmont", UARCH_AIRMONT, 14) // no spec update; whispers & rumors
CHECK_UARCH(arch, 0, 6, 7, 10, NA, "Goldmont Plus", UARCH_GOLDMONT_PLUS, 14)
CHECK_UARCH(arch, 0, 6, 7, 13, NA, "Sunny Cove", UARCH_SUNNY_COVE, 10) // no spec update; only MSR_CPUID_table* so far
CHECK_UARCH(arch, 0, 6, 7, 14, NA, "Ice Lake", UARCH_ICE_LAKE, 10)
CHECK_UARCH(arch, 0, 6, 8, 5, NA, "Knights Mill", UARCH_KNIGHTS_MILL, 14) // no spec update; only MSR_CPUID_table* so far
CHECK_UARCH(arch, 0, 6, 8, 6, NA, "Tremont", UARCH_TREMONT, 10) // LX*
CHECK_UARCH(arch, 0, 6, 8, 10, NA, "Tremont", UARCH_TREMONT, 10) // no spec update; only geekbench.com example
CHECK_UARCH(arch, 0, 6, 8, 12, NA, "Tiger Lake", UARCH_TIGER_LAKE, 10) // instlatx64
CHECK_UARCH(arch, 0, 6, 8, 13, NA, "Tiger Lake", UARCH_TIGER_LAKE, 10) // instlatx64
CHECK_UARCH(arch, 0, 5, 0, 0, NA, "P5", UARCH_P5, 800)
CHECK_UARCH(arch, 0, 5, 0, 1, NA, "P5", UARCH_P5, 800)
CHECK_UARCH(arch, 0, 5, 0, 2, NA, "P5", UARCH_P5, UNK)
CHECK_UARCH(arch, 0, 5, 0, 3, NA, "P5", UARCH_P5, 600)
CHECK_UARCH(arch, 0, 5, 0, 4, NA, "P5 MMX", UARCH_P5, UNK)
CHECK_UARCH(arch, 0, 5, 0, 7, NA, "P5 MMX", UARCH_P5, UNK)
CHECK_UARCH(arch, 0, 5, 0, 8, NA, "P5 MMX", UARCH_P5, 250)
CHECK_UARCH(arch, 0, 5, 0, 9, 0, "Lakemont", UARCH_LAKEMONT, 32)
CHECK_UARCH(arch, 0, 5, 0, 9, NA, "P5 MMX", UARCH_P5, UNK)
CHECK_UARCH(arch, 0, 5, 0, 10, 0, "Lakemont", UARCH_LAKEMONT, 32)
CHECK_UARCH(arch, 0, 6, 0, 0, NA, "P6 Pentium II", UARCH_P6, UNK)
CHECK_UARCH(arch, 0, 6, 0, 1, NA, "P6 Pentium II", UARCH_P6, UNK) // process depends on core
CHECK_UARCH(arch, 0, 6, 0, 2, NA, "P6 Pentium II", UARCH_P6, UNK)
CHECK_UARCH(arch, 0, 6, 0, 3, NA, "P6 Pentium II", UARCH_P6, 350)
CHECK_UARCH(arch, 0, 6, 0, 4, NA, "P6 Pentium II", UARCH_P6, UNK)
CHECK_UARCH(arch, 0, 6, 0, 5, NA, "P6 Pentium II", UARCH_P6, 250)
CHECK_UARCH(arch, 0, 6, 0, 6, NA, "P6 Pentium II", UARCH_P6, UNK)
CHECK_UARCH(arch, 0, 6, 0, 7, NA, "P6 Pentium III", UARCH_P6, 250)
CHECK_UARCH(arch, 0, 6, 0, 8, NA, "P6 Pentium III", UARCH_P6, 180)
CHECK_UARCH(arch, 0, 6, 0, 9, NA, "P6 Pentium M", UARCH_P6, 130)
CHECK_UARCH(arch, 0, 6, 0, 10, NA, "P6 Pentium III", UARCH_P6, 180)
CHECK_UARCH(arch, 0, 6, 0, 11, NA, "P6 Pentium III", UARCH_P6, 130)
CHECK_UARCH(arch, 0, 6, 0, 13, NA, "Dothan", UARCH_DOTHAN, UNK) // process depends on core
CHECK_UARCH(arch, 0, 6, 0, 14, NA, "Yonah", UARCH_YONAH, 65)
CHECK_UARCH(arch, 0, 6, 0, 15, NA, "Merom", UARCH_MEROM, 65)
CHECK_UARCH(arch, 0, 6, 1, 5, NA, "Dothan", UARCH_DOTHAN, 90)
CHECK_UARCH(arch, 0, 6, 1, 6, NA, "Merom", UARCH_MEROM, 65)
CHECK_UARCH(arch, 0, 6, 1, 7, NA, "Penryn", UARCH_PENYR, 45)
CHECK_UARCH(arch, 0, 6, 1, 10, NA, "Nehalem", UARCH_NEHALEM, 45)
CHECK_UARCH(arch, 0, 6, 1, 12, NA, "Bonnell", UARCH_BONNELL, 45)
CHECK_UARCH(arch, 0, 6, 1, 13, NA, "Penryn", UARCH_PENYR, 45)
CHECK_UARCH(arch, 0, 6, 1, 14, NA, "Nehalem", UARCH_NEHALEM, 45)
CHECK_UARCH(arch, 0, 6, 1, 15, NA, "Nehalem", UARCH_NEHALEM, 45)
CHECK_UARCH(arch, 0, 6, 2, 5, NA, "Westmere", UARCH_WESTMERE, 32)
CHECK_UARCH(arch, 0, 6, 2 , 6, NA, "Bonnell", UARCH_BONNELL, 45)
CHECK_UARCH(arch, 0, 6, 2, 7, NA, "Saltwell", UARCH_SALTWELL, 32)
CHECK_UARCH(arch, 0, 6, 2, 10, NA, "Sandy Bridge", UARCH_SANDY_BRIDGE, 32)
CHECK_UARCH(arch, 0, 6, 2, 12, NA, "Westmere", UARCH_WESTMERE, 32)
CHECK_UARCH(arch, 0, 6, 2, 13, NA, "Sandy Bridge", UARCH_SANDY_BRIDGE, 32)
CHECK_UARCH(arch, 0, 6, 2, 14, NA, "Nehalem", UARCH_NEHALEM, 45)
CHECK_UARCH(arch, 0, 6, 2, 15, NA, "Westmere", UARCH_WESTMERE, 32)
CHECK_UARCH(arch, 0, 6, 3, 5, NA, "Saltwell", UARCH_SALTWELL, 14)
CHECK_UARCH(arch, 0, 6, 3, 6, NA, "Saltwell", UARCH_SALTWELL, 32)
CHECK_UARCH(arch, 0, 6, 3, 7, NA, "Silvermont", UARCH_SILVERMONT, 22)
CHECK_UARCH(arch, 0, 6, 3, 10, NA, "Ivy Bridge", UARCH_IVY_BRIDGE, 22)
CHECK_UARCH(arch, 0, 6, 3, 12, NA, "Haswell", UARCH_HASWELL, 22)
CHECK_UARCH(arch, 0, 6, 3, 13, NA, "Broadwell", UARCH_BROADWELL, 14)
CHECK_UARCH(arch, 0, 6, 3, 14, NA, "Ivy Bridge", UARCH_IVY_BRIDGE, 22)
CHECK_UARCH(arch, 0, 6, 3, 15, NA, "Haswell", UARCH_HASWELL, 22)
CHECK_UARCH(arch, 0, 6, 4, 5, NA, "Haswell", UARCH_HASWELL, 22)
CHECK_UARCH(arch, 0, 6, 4, 6, NA, "Haswell", UARCH_HASWELL, 22)
CHECK_UARCH(arch, 0, 6, 4, 7, NA, "Broadwell", UARCH_BROADWELL, 14)
CHECK_UARCH(arch, 0, 6, 4, 10, NA, "Silvermont", UARCH_SILVERMONT, 22) // no docs, but /proc/cpuinfo seen in wild
CHECK_UARCH(arch, 0, 6, 4, 12, NA, "Airmont", UARCH_AIRMONT, 14)
CHECK_UARCH(arch, 0, 6, 4, 13, NA, "Silvermont", UARCH_SILVERMONT, 22)
CHECK_UARCH(arch, 0, 6, 4, 14, 8, "Kaby Lake", UARCH_KABY_LAKE, 14)
CHECK_UARCH(arch, 0, 6, 4, 14, NA, "Skylake", UARCH_SKYLAKE, 14)
CHECK_UARCH(arch, 0, 6, 4, 15, NA, "Broadwell", UARCH_BROADWELL, 14)
CHECK_UARCH(arch, 0, 6, 5, 5, 6, "Cascade Lake", UARCH_CASCADE_LAKE, 14) // no docs, but example from Greg Stewart
CHECK_UARCH(arch, 0, 6, 5, 5, 7, "Cascade Lake", UARCH_CASCADE_LAKE, 14)
CHECK_UARCH(arch, 0, 6, 5, 5, 10, "Cooper Lake", UARCH_COOPER_LAKE, 14)
CHECK_UARCH(arch, 0, 6, 5, 5, NA, "Skylake", UARCH_SKYLAKE, 14)
CHECK_UARCH(arch, 0, 6, 5, 6, NA, "Broadwell", UARCH_BROADWELL, 14)
CHECK_UARCH(arch, 0, 6, 5, 7, NA, "Knights Landing", UARCH_KNIGHTS_LANDING, 14)
CHECK_UARCH(arch, 0, 6, 5, 10, NA, "Silvermont", UARCH_SILVERMONT, 22) // no spec update; only MSR_CPUID_table* so far
CHECK_UARCH(arch, 0, 6, 5, 12, NA, "Goldmont", UARCH_GOLDMONT, 14)
CHECK_UARCH(arch, 0, 6, 5, 13, NA, "Silvermont", UARCH_SILVERMONT, 22) // no spec update; only MSR_CPUID_table* so far
CHECK_UARCH(arch, 0, 6, 5, 14, 8, "Kaby Lake", UARCH_KABY_LAKE, 14)
CHECK_UARCH(arch, 0, 6, 5, 14, NA, "Skylake", UARCH_SKYLAKE, 14)
CHECK_UARCH(arch, 0, 6, 5, 15, NA, "Goldmont", UARCH_GOLDMONT, 14)
CHECK_UARCH(arch, 0, 6, 6, 6, NA, "Palm Cove", UARCH_PALM_COVE, 10) // no spec update; only MSR_CPUID_table* so far
CHECK_UARCH(arch, 0, 6, 6, 10, NA, "Sunny Cove", UARCH_SUNNY_COVE, 10) // no spec update; only MSR_CPUID_table* so far
CHECK_UARCH(arch, 0, 6, 6, 12, NA, "Sunny Cove", UARCH_SUNNY_COVE, 10) // no spec update; only MSR_CPUID_table* so far
CHECK_UARCH(arch, 0, 6, 7, 5, NA, "Airmont", UARCH_AIRMONT, 14) // no spec update; whispers & rumors
CHECK_UARCH(arch, 0, 6, 7, 10, NA, "Goldmont Plus", UARCH_GOLDMONT_PLUS, 14)
CHECK_UARCH(arch, 0, 6, 7, 13, NA, "Sunny Cove", UARCH_SUNNY_COVE, 10) // no spec update; only MSR_CPUID_table* so far
CHECK_UARCH(arch, 0, 6, 7, 14, NA, "Ice Lake", UARCH_ICE_LAKE, 10)
CHECK_UARCH(arch, 0, 6, 8, 5, NA, "Knights Mill", UARCH_KNIGHTS_MILL, 14) // no spec update; only MSR_CPUID_table* so far
CHECK_UARCH(arch, 0, 6, 8, 6, NA, "Tremont", UARCH_TREMONT, 10) // LX*
CHECK_UARCH(arch, 0, 6, 8, 10, NA, "Tremont", UARCH_TREMONT, 10) // no spec update; only geekbench.com example
CHECK_UARCH(arch, 0, 6, 8, 12, NA, "Tiger Lake", UARCH_TIGER_LAKE, 10) // instlatx64
CHECK_UARCH(arch, 0, 6, 8, 13, NA, "Tiger Lake", UARCH_TIGER_LAKE, 10) // instlatx64
// CHECK_UARCH(arch, 0, 6, 8, 14, 9, ...) It is not possible to determine uarch only from CPUID dump (can be Kaby Lake or Amber Lake)
// CHECK_UARCH(arch, 0, 6, 8, 14, 10, ...) It is not possible to determine uarch only from CPUID dump (can be Kaby Lake R or Coffee Lake U)
CHECK_UARCH(arch, 0, 6, 8, 14, 11, "Whiskey Lake", UARCH_WHISKEY_LAKE, 14) // wikichip
// CHECK_UARCH(arch, 0, 6, 8, 14, 12, ...) It is not possible to determine uarch only from CPUID dump (can be Comet Lake U or Whiskey Lake U)
CHECK_UARCH(arch, 0, 6, 8, 15, 8, "Sapphire Rapids", UARCH_SAPPHIRE_RAPIDS, 7) // wikichip
CHECK_UARCH(arch, 0, 6, 9, 6, NA, "Tremont", UARCH_TREMONT, 10) // LX*
CHECK_UARCH(arch, 0, 6, 9, 7, NA, "Alder Lake", UARCH_ALDER_LAKE, 10) // instlatx64 (Alder Lake-S)
CHECK_UARCH(arch, 0, 6, 9, 10, NA, "Alder Lake", UARCH_ALDER_LAKE, 10) // instlatx64 (Alder Lake-P)
CHECK_UARCH(arch, 0, 6, 9, 12, NA, "Tremont", UARCH_TREMONT, 10) // LX*
CHECK_UARCH(arch, 0, 6, 9, 13, NA, "Sunny Cove", UARCH_SUNNY_COVE, 10) // LX*
CHECK_UARCH(arch, 0, 6, 9, 14, 9, "Kaby Lake", UARCH_KABY_LAKE, 14)
CHECK_UARCH(arch, 0, 6, 9, 14, 10, "Coffee Lake", UARCH_COFFEE_LAKE, 14)
CHECK_UARCH(arch, 0, 6, 9, 14, 11, "Coffee Lake", UARCH_COFFEE_LAKE, 14)
CHECK_UARCH(arch, 0, 6, 9, 14, 12, "Coffee Lake", UARCH_COFFEE_LAKE, 14)
CHECK_UARCH(arch, 0, 6, 9, 14, 13, "Coffee Lake", UARCH_COFFEE_LAKE, 14)
CHECK_UARCH(arch, 0, 6, 10, 5, NA, "Comet Lake", UARCH_COMET_LAKE, 14) // wikichip
CHECK_UARCH(arch, 0, 6, 10, 6, NA, "Comet Lake", UARCH_COMET_LAKE, 14) // instlatx64.atw.hu (i7-10710U)
CHECK_UARCH(arch, 0, 6, 10, 7, NA, "Rocket Lake", UARCH_ROCKET_LAKE, 14) // instlatx64.atw.hu (i7-11700K)
CHECK_UARCH(arch, 0, 6, 11, 7, NA, "Raptor Lake", UARCH_RAPTOR_LAKE, 10) // instlatx64.atw.hu (i5-13600K)
CHECK_UARCH(arch, 0, 6, 11, 10, NA, "Raptor Lake", UARCH_RAPTOR_LAKE, 10) // instlatx64.atw.hu (i7-1370P)
CHECK_UARCH(arch, 0, 6, 11, 14, NA, "Alder Lake", UARCH_ALDER_LAKE, 10) // instlatx64.atw.hu (Alder Lake-N)
CHECK_UARCH(arch, 0, 6, 11, 15, NA, "Raptor Lake", UARCH_RAPTOR_LAKE, 10) // instlatx64.atw.hu (i5-13500)
CHECK_UARCH(arch, 0, 11, 0, 0, NA, "Knights Ferry", UARCH_KNIGHTS_FERRY, 45) // found only on en.wikichip.org
CHECK_UARCH(arch, 0, 11, 0, 1, NA, "Knights Corner", UARCH_KNIGHTS_CORNER, 22)
CHECK_UARCH(arch, 0, 15, 0, 0, NA, "Willamette", UARCH_WILLAMETTE, 180)
CHECK_UARCH(arch, 0, 15, 0, 1, NA, "Willamette", UARCH_WILLAMETTE, 180)
CHECK_UARCH(arch, 0, 15, 0, 2, NA, "Northwood", UARCH_NORTHWOOD, 130)
CHECK_UARCH(arch, 0, 15, 0, 3, NA, "Prescott", UARCH_PRESCOTT, 90)
CHECK_UARCH(arch, 0, 15, 0, 4, NA, "Prescott", UARCH_PRESCOTT, 90)
CHECK_UARCH(arch, 0, 15, 0, 6, NA, "Cedar Mill", UARCH_CEDAR_MILL, 65)
CHECK_UARCH(arch, 1, 15, 0, 0, NA, "Itanium2", UARCH_ITANIUM2, 180)
CHECK_UARCH(arch, 1, 15, 0, 1, NA, "Itanium2", UARCH_ITANIUM2, 130)
CHECK_UARCH(arch, 1, 15, 0, 2, NA, "Itanium2", UARCH_ITANIUM2, 130)
CHECK_UARCH(arch, 0, 6, 8, 14, 10, "Coffee Lake", UARCH_COFFEE_LAKE, 14) // wikichip
CHECK_UARCH(arch, 0, 6, 8, 14, 11, "Whiskey Lake", UARCH_WHISKEY_LAKE, 14) // wikichip
CHECK_UARCH(arch, 0, 6, 8, 14, 12, "Comet Lake", UARCH_COMET_LAKE, 14) // wikichip
CHECK_UARCH(arch, 0, 6, 9, 6, NA, "Tremont", UARCH_TREMONT, 10) // LX*
CHECK_UARCH(arch, 0, 6, 9, 7, NA, "Alder Lake", UARCH_ALDER_LAKE, 10) // instlatx64 (Alder Lake-S)
CHECK_UARCH(arch, 0, 6, 9, 10, NA, "Alder Lake", UARCH_ALDER_LAKE, 10) // instlatx64 (Alder Lake-P)
CHECK_UARCH(arch, 0, 6, 9, 12, NA, "Tremont", UARCH_TREMONT, 10) // LX*
CHECK_UARCH(arch, 0, 6, 9, 13, NA, "Sunny Cove", UARCH_SUNNY_COVE, 10) // LX*
CHECK_UARCH(arch, 0, 6, 9, 14, 9, "Kaby Lake", UARCH_KABY_LAKE, 14)
CHECK_UARCH(arch, 0, 6, 9, 14, 10, "Coffee Lake", UARCH_COFFEE_LAKE, 14)
CHECK_UARCH(arch, 0, 6, 9, 14, 11, "Coffee Lake", UARCH_COFFEE_LAKE, 14)
CHECK_UARCH(arch, 0, 6, 9, 14, 12, "Coffee Lake", UARCH_COFFEE_LAKE, 14)
CHECK_UARCH(arch, 0, 6, 9, 14, 13, "Coffee Lake", UARCH_COFFEE_LAKE, 14)
CHECK_UARCH(arch, 0, 6, 10, 5, NA, "Comet Lake", UARCH_COMET_LAKE, 14) // wikichip
CHECK_UARCH(arch, 0, 6, 10, 6, NA, "Comet Lake", UARCH_COMET_LAKE, 14) // instlatx64.atw.hu (i7-10710U)
CHECK_UARCH(arch, 0, 6, 10, 7, NA, "Rocket Lake", UARCH_ROCKET_LAKE, 14) // instlatx64.atw.hu (i7-11700K)
CHECK_UARCH(arch, 0, 6, 11, 7, NA, "Raptor Lake", UARCH_RAPTOR_LAKE, 10) // instlatx64.atw.hu (i5-13600K)
CHECK_UARCH(arch, 0, 11, 0, 0, NA, "Knights Ferry", UARCH_KNIGHTS_FERRY, 45) // found only on en.wikichip.org
CHECK_UARCH(arch, 0, 11, 0, 1, NA, "Knights Corner", UARCH_KNIGHTS_CORNER, 22)
CHECK_UARCH(arch, 0, 15, 0, 0, NA, "Willamette", UARCH_WILLAMETTE, 180)
CHECK_UARCH(arch, 0, 15, 0, 1, NA, "Willamette", UARCH_WILLAMETTE, 180)
CHECK_UARCH(arch, 0, 15, 0, 2, NA, "Northwood", UARCH_NORTHWOOD, 130)
CHECK_UARCH(arch, 0, 15, 0, 3, NA, "Prescott", UARCH_PRESCOTT, 90)
CHECK_UARCH(arch, 0, 15, 0, 4, NA, "Prescott", UARCH_PRESCOTT, 90)
CHECK_UARCH(arch, 0, 15, 0, 6, NA, "Cedar Mill", UARCH_CEDAR_MILL, 65)
CHECK_UARCH(arch, 1, 15, 0, 0, NA, "Itanium2", UARCH_ITANIUM2, 180)
CHECK_UARCH(arch, 1, 15, 0, 1, NA, "Itanium2", UARCH_ITANIUM2, 130)
CHECK_UARCH(arch, 1, 15, 0, 2, NA, "Itanium2", UARCH_ITANIUM2, 130)
UARCH_END
return arch;
}
@@ -301,16 +273,11 @@ struct uarch* get_uarch_from_cpuid_amd(uint32_t ef, uint32_t f, uint32_t em, uin
// ----------------------------------------------------------------------------- //
// EF F EM M S //
UARCH_START
CHECK_UARCH(arch, 0, 4, 0, 3, NA, "Am486DX2", UARCH_AM486, UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
CHECK_UARCH(arch, 0, 4, 0, 7, NA, "Am486DX2WB", UARCH_AM486, UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
CHECK_UARCH(arch, 0, 4, 0, 8, NA, "Am486DX4", UARCH_AM486, UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
CHECK_UARCH(arch, 0, 4, 0, 9, NA, "Am486DX4WB", UARCH_AM486, UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
CHECK_UARCH(arch, 0, 4, 0, 14, NA, "Am5x86", UARCH_AM5X86, 350) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
CHECK_UARCH(arch, 0, 4, 0, 15, NA, "Am5x86WB", UARCH_AM5X86, 350) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
CHECK_UARCH(arch, 0, 5, 0, 0, NA, "SSA5 (K5)", UARCH_SSA5, 350) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
CHECK_UARCH(arch, 0, 5, 0, 1, NA, "K5", UARCH_K5, 350) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
CHECK_UARCH(arch, 0, 5, 0, 2, NA, "K5", UARCH_K5, 350) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
CHECK_UARCH(arch, 0, 5, 0, 3, NA, "K5", UARCH_K5, 350) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
CHECK_UARCH(arch, 0, 4, 0, 3, NA, "Am486", UARCH_AM486, UNK)
CHECK_UARCH(arch, 0, 4, 0, 7, NA, "Am486", UARCH_AM486, UNK)
CHECK_UARCH(arch, 0, 4, 0, 8, NA, "Am486", UARCH_AM486, UNK)
CHECK_UARCH(arch, 0, 4, 0, 9, NA, "Am486", UARCH_AM486, UNK)
CHECK_UARCH(arch, 0, 4, NA, NA, NA, "Am5x86", UARCH_AM5X86, UNK)
CHECK_UARCH(arch, 0, 5, 0, 6, NA, "K6", UARCH_K6, 300)
CHECK_UARCH(arch, 0, 5, 0, 7, NA, "K6", UARCH_K6, 250) // *p from sandpile.org
CHECK_UARCH(arch, 0, 5, 0, 10, NA, "K7", UARCH_K7, 130) // Geode NX
@@ -381,7 +348,6 @@ struct uarch* get_uarch_from_cpuid_amd(uint32_t ef, uint32_t f, uint32_t em, uin
CHECK_UARCH(arch, 6, 15, 6, 5, NA, "Excavator", UARCH_EXCAVATOR, 28) // undocumented, but sample from Alexandros Couloumbis
CHECK_UARCH(arch, 6, 15, 7, 0, NA, "Excavator", UARCH_EXCAVATOR, 28)
CHECK_UARCH(arch, 7, 15, 0, 0, NA, "Jaguar", UARCH_JAGUAR, 28)
CHECK_UARCH(arch, 7, 15, 1, NA, NA, "Jaguar", UARCH_JAGUAR, 14) // instlatx64 (PS4) Normal PS4 is 28nm, Slim and Pro are 16nm
CHECK_UARCH(arch, 7, 15, 2, 6, NA, "Jaguar", UARCH_JAGUAR, 28) // AMD Cato (Xbox One?)
CHECK_UARCH(arch, 7, 15, 3, 0, NA, "Puma 2014", UARCH_PUMA_2014, 28)
CHECK_UARCH(arch, 8, 15, 0, 0, NA, "Zen", UARCH_ZEN, 14) // instlatx64 engr sample
@@ -396,49 +362,12 @@ struct uarch* get_uarch_from_cpuid_amd(uint32_t ef, uint32_t f, uint32_t em, uin
CHECK_UARCH(arch, 8, 15, 6, 0, NA, "Zen 2", UARCH_ZEN2, 7) // undocumented, geekbench.com example
CHECK_UARCH(arch, 8, 15, 6, 8, NA, "Zen 2", UARCH_ZEN2, 7) // found on instlatx64
CHECK_UARCH(arch, 8, 15, 7, 1, NA, "Zen 2", UARCH_ZEN2, 7) // samples from Steven Noonan and instlatx64
CHECK_UARCH(arch, 8, 15, 8, 4, NA, "Zen 2", UARCH_ZEN2, 7) // instlatx64 (Xbox Series X?)
CHECK_UARCH(arch, 8, 15, 9, 0, 2, "Zen 2", UARCH_ZEN2, 7) // Steam Deck (instlatx64)
CHECK_UARCH(arch, 8, 15, 10, 0, NA, "Zen 2", UARCH_ZEN2, 6) // instlatx64
CHECK_UARCH(arch, 10, 15, 0, 1, NA, "Zen 3", UARCH_ZEN3, 7) // instlatx64
CHECK_UARCH(arch, 10, 15, 0, 8, NA, "Zen 3", UARCH_ZEN3, 7) // instlatx64
CHECK_UARCH(arch, 10, 15, 1, 1, NA, "Zen 4", UARCH_ZEN4, 5) // instlatx64
CHECK_UARCH(arch, 10, 15, 1, 8, NA, "Zen 4", UARCH_ZEN4, 5) // instlatx64
CHECK_UARCH(arch, 10, 15, 2, 1, NA, "Zen 3", UARCH_ZEN3, 7) // instlatx64
CHECK_UARCH(arch, 10, 15, 3, NA, NA, "Zen 3", UARCH_ZEN3, 7) // instlatx64
CHECK_UARCH(arch, 10, 15, 4, 4, NA, "Zen 3+", UARCH_ZEN3_PLUS, 6) // instlatx64 (they say it is Zen3...)
CHECK_UARCH(arch, 10, 15, 5, 0, NA, "Zen 3", UARCH_ZEN3, 7) // instlatx64
CHECK_UARCH(arch, 10, 15, 6, 1, 2, "Zen 4", UARCH_ZEN4, 5) // instlatx64
CHECK_UARCH(arch, 10, 15, 7, 4, 1, "Zen 4", UARCH_ZEN4, 4) // instlatx64
CHECK_UARCH(arch, 10, 15, 7, 5, 2, "Zen 4", UARCH_ZEN4, 4) // instlatx64
CHECK_UARCH(arch, 10, 15, 7, 8, 0, "Zen 4", UARCH_ZEN4, 4) // instlatx64
CHECK_UARCH(arch, 10, 15, 8, NA, NA, "Zen 4", UARCH_ZEN4, 5) // instlatx64 (AMD MI300C)
CHECK_UARCH(arch, 10, 15, 9, NA, NA, "Zen 4", UARCH_ZEN4, 5) // instlatx64 (AMD MI300A)
CHECK_UARCH(arch, 10, 15, 10, NA, NA, "Zen 4c", UARCH_ZEN4C, 5) // instlatx64
CHECK_UARCH(arch, 11, 15, 0, NA, NA, "Zen 5", UARCH_ZEN5, 4) // Turin/EPYC (instlatx64)
CHECK_UARCH(arch, 11, 15, 1, NA, NA, "Zen 5c", UARCH_ZEN5C, 3) // Zen5c EPYC (instlatx64, https://en.wikipedia.org/wiki/Zen_5#cite_note-10)
CHECK_UARCH(arch, 11, 15, 2, NA, NA, "Zen 5", UARCH_ZEN5, 4) // Strix Point (instlatx64)
CHECK_UARCH(arch, 11, 15, 4, NA, NA, "Zen 5", UARCH_ZEN5, 4) // Granite Ridge (instlatx64)
CHECK_UARCH(arch, 11, 15, 6, NA, NA, "Zen 5", UARCH_ZEN5, 4) // Krackan Point (instlatx64)
CHECK_UARCH(arch, 11, 15, 7, NA, NA, "Zen 5", UARCH_ZEN5, 4) // Strix Halo (instlatx64)
UARCH_END
return arch;
}
struct uarch* get_uarch_from_cpuid_hygon(uint32_t ef, uint32_t f, uint32_t em, uint32_t m, int s) {
struct uarch* arch = emalloc(sizeof(struct uarch));
// EF: Extended Family //
// F: Family //
// EM: Extended Model //
// M: Model //
// S: Stepping //
// ----------------------------------------------------------------------------- //
// EF F EM M S //
UARCH_START
// https://www.phoronix.com/news/Hygon-Dhyana-AMD-China-CPUs
CHECK_UARCH(arch, 9, 15, 0, 1, NA, "Zen", UARCH_ZEN, UNK) // https://github.com/Dr-Noob/cpufetch/issues/244
// CHECK_UARCH(arch, 9, 15, 0, 2, NA, "???", ?????????, UNK) // http://instlatx64.atw.hu/
UARCH_END
return arch;
@@ -446,17 +375,10 @@ struct uarch* get_uarch_from_cpuid_hygon(uint32_t ef, uint32_t f, uint32_t em, u
struct uarch* get_uarch_from_cpuid(struct cpuInfo* cpu, uint32_t dump, uint32_t ef, uint32_t f, uint32_t em, uint32_t m, int s) {
if(cpu->cpu_vendor == CPU_VENDOR_INTEL) {
struct uarch* arch = emalloc(sizeof(struct uarch));
// TODO: Refactor these 3 checks in a common function.
if(dump == 0x000806E9) {
if (cpu->cpu_name == NULL) {
printErr("Unable to find uarch without CPU name");
fill_uarch(arch, STRING_UNKNOWN, UARCH_UNKNOWN, UNK);
return arch;
}
// It is not possible to determine uarch only from CPUID dump (can be Kaby Lake or Amber Lake)
// See issue https://github.com/Dr-Noob/cpufetch/issues/122
struct uarch* arch = emalloc(sizeof(struct uarch));
if(strstr(cpu->cpu_name, "Y") != NULL) {
fill_uarch(arch, "Amber Lake", UARCH_AMBER_LAKE, 14);
}
@@ -466,133 +388,14 @@ struct uarch* get_uarch_from_cpuid(struct cpuInfo* cpu, uint32_t dump, uint32_t
return arch;
}
else if (dump == 0x000806EA) {
if (cpu->cpu_name == NULL) {
printErr("Unable to find uarch without CPU name");
fill_uarch(arch, STRING_UNKNOWN, UARCH_UNKNOWN, UNK);
return arch;
}
// It is not possible to determine uarch only from CPUID dump (can be Kaby Lake R or Coffee Lake U)
// See issue https://github.com/Dr-Noob/cpufetch/issues/149
if(strstr(cpu->cpu_name, "i5-8250U") != NULL ||
strstr(cpu->cpu_name, "i5-8350U") != NULL ||
strstr(cpu->cpu_name, "i7-8550U") != NULL ||
strstr(cpu->cpu_name, "i7-8650U") != NULL) {
fill_uarch(arch, "Kaby Lake", UARCH_KABY_LAKE, 14);
}
else {
fill_uarch(arch, "Coffee Lake", UARCH_COFFEE_LAKE, 14);
}
return arch;
}
else if (dump == 0x000806EC) {
if (cpu->cpu_name == NULL) {
printErr("Unable to find uarch without CPU name");
fill_uarch(arch, STRING_UNKNOWN, UARCH_UNKNOWN, UNK);
return arch;
}
// It is not possible to determine uarch only from CPUID dump (can be Comet Lake U or Whiskey Lake U)
// https://github.com/Dr-Noob/cpufetch/issues/298
if (strstr(cpu->cpu_name, "i3-8145U") != NULL ||
strstr(cpu->cpu_name, "i5-8265U") != NULL ||
strstr(cpu->cpu_name, "i5-8365U") != NULL ||
strstr(cpu->cpu_name, "i7-8565U") != NULL ||
strstr(cpu->cpu_name, "i7-8665U") != NULL ||
strstr(cpu->cpu_name, "5405U") != NULL ||
strstr(cpu->cpu_name, "4205U") != NULL) {
fill_uarch(arch, "Whiskey Lake", UARCH_WHISKEY_LAKE, 14);
}
else {
fill_uarch(arch, "Comet Lake", UARCH_COMET_LAKE, 14);
}
return arch;
}
return get_uarch_from_cpuid_intel(ef, f, em, m, s);
}
else if(cpu->cpu_vendor == CPU_VENDOR_AMD) {
else
return get_uarch_from_cpuid_amd(ef, f, em, m, s);
}
else if(cpu->cpu_vendor == CPU_VENDOR_HYGON) {
return get_uarch_from_cpuid_hygon(ef, f, em, m, s);
}
else {
printBug("Invalid CPU vendor: %d", cpu->cpu_vendor);
return NULL;
}
}
// If we cannot get the CPU name from CPUID, try to infer it from uarch
char* infer_cpu_name_from_uarch(struct uarch* arch) {
char* cpu_name = NULL;
if (arch == NULL) {
printErr("infer_cpu_name_from_uarch: Unable to find CPU name");
cpu_name = ecalloc(strlen(STRING_UNKNOWN) + 1, sizeof(char));
strcpy(cpu_name, STRING_UNKNOWN);
return cpu_name;
}
char *str = NULL;
switch (arch->uarch) {
// Intel
case UARCH_I486:
str = "Intel 486";
break;
case UARCH_P5:
str = "Intel Pentium";
break;
case UARCH_P5_MMX:
str = "Intel Pentium MMX";
break;
case UARCH_P6_PRO:
str = "Intel Pentium Pro";
break;
case UARCH_P6_PENTIUM_II:
str = "Intel Pentium II";
break;
case UARCH_P6_PENTIUM_III:
str = "Intel Pentium III";
break;
// AMD
case UARCH_AM486:
str = "AMD 486";
break;
case UARCH_AM5X86:
str = "AMD 5x86";
break;
case UARCH_SSA5:
str = "AMD 5k86";
break;
default:
printErr("Unable to find name from uarch: %d", arch->uarch);
break;
}
if (str == NULL) {
cpu_name = ecalloc(strlen(STRING_UNKNOWN) + 1, sizeof(char));
strcpy(cpu_name, STRING_UNKNOWN);
}
else {
cpu_name = ecalloc(strlen(str) + 1, sizeof(char));
strcpy(cpu_name, str);
}
return cpu_name;
}
bool vpus_are_AVX512(struct cpuInfo* cpu) {
// Zen5 actually has 2 x AVX512 units
// https://www.anandtech.com/show/21469/amd-details-ryzen-ai-300-series-for-mobile-strix-point-with-rdna-35-igpu-xdna-2-npu
return cpu->arch->uarch != UARCH_ICE_LAKE &&
cpu->arch->uarch != UARCH_TIGER_LAKE &&
cpu->arch->uarch != UARCH_ZEN4 &&
cpu->arch->uarch != UARCH_ZEN4C;
return cpu->arch->uarch != UARCH_ICE_LAKE && cpu->arch->uarch != UARCH_TIGER_LAKE;
}
bool is_knights_landing(struct cpuInfo* cpu) {
@@ -618,7 +421,6 @@ int get_number_of_vpus(struct cpuInfo* cpu) {
case UARCH_KNIGHTS_LANDING:
case UARCH_KNIGHTS_MILL:
case UARCH_SAPPHIRE_RAPIDS:
case UARCH_ICE_LAKE:
case UARCH_TIGER_LAKE:
case UARCH_ALDER_LAKE:
@@ -629,9 +431,6 @@ int get_number_of_vpus(struct cpuInfo* cpu) {
case UARCH_ZEN3:
case UARCH_ZEN3_PLUS:
case UARCH_ZEN4:
case UARCH_ZEN4C:
case UARCH_ZEN5:
case UARCH_ZEN5C:
return 2;
default:
return 1;
@@ -661,6 +460,9 @@ char* get_str_process(struct cpuInfo* cpu) {
if(process == UNK) {
snprintf(str, strlen(STRING_UNKNOWN)+1, STRING_UNKNOWN);
}
else if(process > 100) {
sprintf(str, "%.2fum", (double)process/100);
}
else if(process > 0){
sprintf(str, "%dnm", process);
}

1
src/x86/uarch.h
View File

@@ -8,7 +8,6 @@
struct uarch;
struct uarch* get_uarch_from_cpuid(struct cpuInfo* cpu, uint32_t dump, uint32_t ef, uint32_t f, uint32_t em, uint32_t m, int s);
char* infer_cpu_name_from_uarch(struct uarch* arch);
bool vpus_are_AVX512(struct cpuInfo* cpu);
bool is_knights_landing(struct cpuInfo* cpu);
int get_number_of_vpus(struct cpuInfo* cpu);