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2 Commits
i220 ... feat2

Author SHA1 Message Date
Dr-Noob
1fab1eefc1 [v1.01] Fix Google Tensor SoC matching name 2021-12-18 18:47:40 +01:00
Dr-Noob
27a0c42190 [v1.01] Add Google Tensor (reported by #134) 2021-12-17 22:38:07 +01:00
54 changed files with 873 additions and 3540 deletions
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352
LICENSE
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@@ -1,339 +1,21 @@
GNU GENERAL PUBLIC LICENSE
Version 2, June 1991
MIT License
Copyright (C) 1989, 1991 Free Software Foundation, Inc.,
51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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Copyright (c) 2018 Dr-Noob
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<one line to give the program's name and a brief idea of what it does.>
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This program is free software; you can redistribute it and/or modify
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Also add information on how to contact you by electronic and paper mail.
If the program is interactive, make it output a short notice like this
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mouse-clicks or menu items--whatever suits your program.
You should also get your employer (if you work as a programmer) or your
school, if any, to sign a "copyright disclaimer" for the program, if
necessary. Here is a sample; alter the names:
Yoyodyne, Inc., hereby disclaims all copyright interest in the program
`Gnomovision' (which makes passes at compilers) written by James Hacker.
<signature of Ty Coon>, 1 April 1989
Ty Coon, President of Vice
This General Public License does not permit incorporating your program into
proprietary programs. If your program is a subroutine library, you may
consider it more useful to permit linking proprietary applications with the
library. If this is what you want to do, use the GNU Lesser General
Public License instead of this License.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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25
Makefile
View File

@@ -1,7 +1,7 @@
CC ?= gcc
CFLAGS+=-Wall -Wextra -pedantic
SANITY_FLAGS=-Wfloat-equal -Wshadow -Wpointer-arith -Wstrict-prototypes
SANITY_FLAGS=-Wfloat-equal -Wshadow -Wpointer-arith
PREFIX ?= /usr
@@ -11,7 +11,6 @@ COMMON_SRC = $(SRC_COMMON)main.c $(SRC_COMMON)cpu.c $(SRC_COMMON)udev.c $(SRC_CO
COMMON_HDR = $(SRC_COMMON)ascii.h $(SRC_COMMON)cpu.h $(SRC_COMMON)udev.h $(SRC_COMMON)printer.h $(SRC_COMMON)args.h $(SRC_COMMON)global.h
ifneq ($(OS),Windows_NT)
GIT_VERSION := "$(shell git describe --abbrev=4 --dirty --always --tags)"
arch := $(shell uname -m)
ifeq ($(arch), $(filter $(arch), x86_64 amd64 i386 i486 i586 i686))
SRC_DIR=src/x86/
@@ -29,11 +28,11 @@ ifneq ($(OS),Windows_NT)
SRC_DIR=src/ppc/
SOURCE += $(COMMON_SRC) $(SRC_DIR)ppc.c $(SRC_DIR)uarch.c $(SRC_DIR)udev.c
HEADERS += $(COMMON_HDR) $(SRC_DIR)ppc.h $(SRC_DIR)uarch.h $(SRC_DIR)udev.c
CFLAGS += -DARCH_PPC -std=gnu99 -fstack-protector-all -Wno-language-extension-token
CFLAGS += -DARCH_PPC -std=gnu99 -fstack-protector-all
else ifeq ($(arch), $(filter $(arch), arm aarch64_be aarch64 arm64 armv8b armv8l armv7l armv6l))
SRC_DIR=src/arm/
SOURCE += $(COMMON_SRC) $(SRC_DIR)midr.c $(SRC_DIR)uarch.c $(SRC_COMMON)soc.c $(SRC_DIR)soc.c $(SRC_DIR)udev.c
HEADERS += $(COMMON_HDR) $(SRC_DIR)midr.h $(SRC_DIR)uarch.h $(SRC_COMMON)soc.h $(SRC_DIR)soc.h $(SRC_DIR)udev.c $(SRC_DIR)socs.h
SOURCE += $(COMMON_SRC) $(SRC_DIR)midr.c $(SRC_DIR)uarch.c $(SRC_DIR)soc.c $(SRC_DIR)udev.c
HEADERS += $(COMMON_HDR) $(SRC_DIR)midr.h $(SRC_DIR)uarch.h $(SRC_DIR)soc.h $(SRC_DIR)udev.c $(SRC_DIR)socs.h
CFLAGS += -DARCH_ARM -Wno-unused-parameter -std=c99 -fstack-protector-all
os := $(shell uname -s)
@@ -41,11 +40,6 @@ ifneq ($(OS),Windows_NT)
SOURCE += $(SRC_DIR)sysctl.c
HEADERS += $(SRC_DIR)sysctl.h
endif
else ifeq ($(arch), $(filter $(arch), riscv64 riscv32))
SRC_DIR=src/riscv/
SOURCE += $(COMMON_SRC) $(SRC_DIR)riscv.c $(SRC_DIR)uarch.c $(SRC_COMMON)soc.c $(SRC_DIR)soc.c $(SRC_DIR)udev.c
HEADERS += $(COMMON_HDR) $(SRC_DIR)riscv.h $(SRC_DIR)uarch.h $(SRC_COMMON)soc.h $(SRC_DIR)soc.h $(SRC_DIR)udev.h $(SRC_DIR)socs.h
CFLAGS += -DARCH_RISCV -Wno-unused-parameter -std=c99 -fstack-protector-all
else
# Error lines should not be tabulated because Makefile complains about it
$(warning Unsupported arch detected: $(arch). See https://github.com/Dr-Noob/cpufetch#1-support)
@@ -56,7 +50,6 @@ $(error Aborting compilation)
OUTPUT=cpufetch
else
# Assume x86_64
GIT_VERSION := ""
SRC_DIR=src/x86/
SOURCE += $(COMMON_SRC) $(SRC_DIR)cpuid.c $(SRC_DIR)apic.c $(SRC_DIR)cpuid_asm.c $(SRC_DIR)uarch.c
HEADERS += $(COMMON_HDR) $(SRC_DIR)cpuid.h $(SRC_DIR)apic.h $(SRC_DIR)cpuid_asm.h $(SRC_DIR)uarch.h
@@ -77,21 +70,17 @@ static: $(OUTPUT)
strict: CFLAGS += -O2 -Werror -fsanitize=undefined -D_FORTIFY_SOURCE=2
strict: $(OUTPUT)
freq_nov.o: Makefile $(SRC_DIR)freq/freq_nov.c $(SRC_DIR)freq/freq_nov.h $(SRC_DIR)freq/freq.h
freq_nov.o: Makefile $(SRC_DIR)freq/freq_nov.c $(SRC_DIR)freq/freq_nov.h
$(CC) $(CFLAGS) $(SANITY_FLAGS) -c -pthread $(SRC_DIR)freq/freq_nov.c -o $@
freq_avx.o: Makefile $(SRC_DIR)freq/freq_avx.c $(SRC_DIR)freq/freq_avx.h $(SRC_DIR)freq/freq.h
freq_avx.o: Makefile $(SRC_DIR)freq/freq_avx.c $(SRC_DIR)freq/freq_avx.h
$(CC) $(CFLAGS) $(SANITY_FLAGS) -c -mavx -pthread $(SRC_DIR)freq/freq_avx.c -o $@
freq_avx512.o: Makefile $(SRC_DIR)freq/freq_avx512.c $(SRC_DIR)freq/freq_avx512.h $(SRC_DIR)freq/freq.h
freq_avx512.o: Makefile $(SRC_DIR)freq/freq_avx512.c $(SRC_DIR)freq/freq_avx512.h
$(CC) $(CFLAGS) $(SANITY_FLAGS) -c -mavx512f -pthread $(SRC_DIR)freq/freq_avx512.c -o $@
$(OUTPUT): Makefile $(SOURCE) $(HEADERS)
ifeq ($(GIT_VERSION),"")
$(CC) $(CFLAGS) $(SANITY_FLAGS) $(SOURCE) -o $(OUTPUT)
else
$(CC) $(CFLAGS) $(SANITY_FLAGS) -DGIT_FULL_VERSION=\"$(GIT_VERSION)\" $(SOURCE) -o $(OUTPUT)
endif
run: $(OUTPUT)
./$(OUTPUT)

41
README.md
View File

@@ -50,8 +50,6 @@ cpufetch is a command-line tool written in C that displays the CPU information i
- [4.2 Specifying the colors in RGB format](#42-specifying-the-colors-in-rgb-format)
- [5. Implementation](#5-implementation)
- [6. Bugs or improvements](#6-bugs-or-improvements)
- [6.1 Unknown microarchitecture error](#61-unknown-microarchitecture-error)
- [6.2 Other situations](#62-other-situations)
- [7. Acknowledgements](#7-acknowledgements)
- [8. cpufetch for GPUs (gpufetch)](#8-cpufetch-for-gpus-gpufetch)
@@ -59,17 +57,17 @@ cpufetch is a command-line tool written in C that displays the CPU information i
## 1. Support
| OS | x86_64 / x86 | ARM | RISC-V | PowerPC |
|:-----------:|:------------------:|:------------------:|:------------------:|:------------------:|
| GNU / Linux | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
| Windows | :heavy_check_mark: | :x: | :x: | :x: |
| Android | :heavy_check_mark: | :heavy_check_mark: | :x: | :x: |
| macOS | :heavy_check_mark: | :heavy_check_mark: | :x: | :heavy_check_mark: |
| FreeBSD | :heavy_check_mark: | :x: | :x: | :x: |
| OS | x86_64 / x86 | ARM | PowerPC |
|:-----------:|:------------------:|:------------------:|:------------------:|
| GNU / Linux | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
| Windows | :heavy_check_mark: | :x: | :x: |
| Android | :heavy_check_mark: | :heavy_check_mark: | :x: |
| macOS | :heavy_check_mark: | :heavy_check_mark: | :x: |
| FreeBSD | :heavy_check_mark: | :x: | :x: |
**NOTES:**
- Colors will be used in Windows only if the terminal supports it.
- Support in macOS ARM is limited to Apple chips only
- Support in macOS ARM is limited to Apple M1 only
## 2. Installation
### 2.1 Installing from a package
@@ -149,31 +147,14 @@ By default, `cpufetch` will print the CPU logo with the system colorscheme. Howe
See [cpufetch programming documentation](https://github.com/Dr-Noob/cpufetch/tree/master/doc).
## 6. Bugs or improvements
### 6.1 Unknown microarchitecture error
If you get the `Unknown microarchitecture detected` error when running cpufetch, it might be caused by two possible reasons:
1. You are running an old release of cpufetch (most likely)
2. Your microarchitecture is not yet supported
Download and compile the latest version (see https://github.com/Dr-Noob/cpufetch#22-building-from-source for instructions)
and verify if the error persists.
* __If the error dissapears__: It means that this is the first situation. In this case, just use the
latest version of cpufetch which already has support for your hardware.
* __If the error does not dissapear__: It means that this is the
second situation. In this case, please create a new issue with the error message and the output of 'cpufetch --debug' on https://github.com/Dr-Noob/cpufetch/issues
### 6.2 Other situations
See [cpufetch contributing guidelines](https://github.com/Dr-Noob/cpufetch/blob/master/CONTRIBUTING.md).
## 7. Acknowledgements
Thanks to the fellow contributors and interested people in the project. Special thanks to:
- [Gonzalocl](https://github.com/Gonzalocl) and [OdnetninI](https://github.com/OdnetninI): Tested cpufetch in the earlier versions of the project in many different CPUs.
- [Gonzalocl](https://github.com/Gonzalocl), [OdnetninI](https://github.com/OdnetninI): Tested cpufetch in the earlier versions of the project in many different CPUs.
- [Kyngo](https://github.com/Kyngo): Tested cpufetch in the Apple M1 CPU.
- [avollmerhaus](https://github.com/avollmerhaus): Helped with PowerPC port giving ssh access to a PowerPC machine.
- [bbonev](https://github.com/bbonev) and [stephan-cr](https://github.com/stephan-cr): Reviewed the source code.
- [mdoksa76](https://github.com/mdoksa76) and [exkc](https://github.com/exkc): Excellent ideas and feedback for supporting Allwinner SoCs.
- [Sakura286](https://github.com/Sakura286), [exkc](https://github.com/exkc) and [Patola](https://github.com/Patola): Helped with RISC-V port with ssh access, ideas, testing, etc.
- [avollmerhaus](https://github.com/avollmerhaus): Gave me ssh acess to a PowerPC machine, allowing me to develop the PowerPC port.
- [bbonev](https://github.com/bbonev), [stephan-cr](https://github.com/stephan-cr): Reviewed the source code.
## 8. cpufetch for GPUs (gpufetch)
See [gpufetch](https://github.com/Dr-Noob/gpufetch) project!

152
src/arm/midr.c
View File

@@ -10,13 +10,19 @@
#include <asm/hwcap.h>
#elif defined __APPLE__ || __MACH__
#include "sysctl.h"
// From Linux kernel: arch/arm64/include/asm/cputype.h
#define MIDR_APPLE_M1_ICESTORM 0x610F0220
#define MIDR_APPLE_M1_FIRESTORM 0x610F0230
#ifndef CPUFAMILY_ARM_FIRESTORM_ICESTORM
#define CPUFAMILY_ARM_FIRESTORM_ICESTORM 0x1B588BB3
#endif
#endif
#include "../common/global.h"
#include "../common/soc.h"
#include "udev.h"
#include "midr.h"
#include "uarch.h"
#include "soc.h"
bool cores_are_equal(int c1pos, int c2pos, uint32_t* midr_array, int32_t* freq_array) {
return midr_array[c1pos] == midr_array[c2pos] && freq_array[c1pos] == freq_array[c2pos];
@@ -80,21 +86,15 @@ int64_t get_peak_performance(struct cpuInfo* cpu) {
}
}
int64_t total_flops = 0;
int64_t flops = 0;
ptr = cpu;
for(int i=0; i < cpu->num_cpus; ptr = ptr->next_cpu, i++) {
int vpus = get_number_of_vpus(ptr);
int vpus_width = get_vpus_width(ptr);
bool has_fma = has_fma_support(ptr);
int64_t flops = ptr->topo->total_cores * get_freq(ptr->freq) * 1000000 * vpus * (vpus_width/32);
if(has_fma) flops = flops * 2;
total_flops += flops;
flops += ptr->topo->total_cores * (get_freq(ptr->freq) * 1000000);
}
if(cpu->feat->NEON) flops = flops * 4;
return total_flops;
return flops;
}
uint32_t fill_ids_from_midr(uint32_t* midr_array, int32_t* freq_array, uint32_t* ids_array, int len) {
@@ -136,7 +136,7 @@ void init_cpu_info(struct cpuInfo* cpu) {
// true...
// ARM32 https://elixir.bootlin.com/linux/latest/source/arch/arm/include/uapi/asm/hwcap.h
// ARM64 https://elixir.bootlin.com/linux/latest/source/arch/arm64/include/uapi/asm/hwcap.h
struct features* get_features_info(void) {
struct features* get_features_info() {
struct features* feat = emalloc(sizeof(struct features));
bool *ptr = &(feat->AES);
for(uint32_t i = 0; i < sizeof(struct features)/sizeof(bool); i++, ptr++) {
@@ -244,7 +244,7 @@ struct cpuInfo* get_cpu_info_linux(struct cpuInfo* cpu) {
}
#elif defined __APPLE__ || __MACH__
void fill_cpu_info_firestorm_icestorm(struct cpuInfo* cpu, uint32_t pcores, uint32_t ecores) {
void fill_cpu_info_firestorm_icestorm(struct cpuInfo* cpu) {
// 1. Fill ICESTORM
struct cpuInfo* ice = cpu;
@@ -254,7 +254,7 @@ void fill_cpu_info_firestorm_icestorm(struct cpuInfo* cpu, uint32_t pcores, uint
ice->feat = get_features_info();
ice->topo = malloc(sizeof(struct topology));
ice->topo->cach = ice->cach;
ice->topo->total_cores = ecores;
ice->topo->total_cores = 4;
ice->freq = malloc(sizeof(struct frequency));
ice->freq->base = UNKNOWN_DATA;
ice->freq->max = 2064;
@@ -270,7 +270,7 @@ void fill_cpu_info_firestorm_icestorm(struct cpuInfo* cpu, uint32_t pcores, uint
fire->feat = get_features_info();
fire->topo = malloc(sizeof(struct topology));
fire->topo->cach = fire->cach;
fire->topo->total_cores = pcores;
fire->topo->total_cores = 4;
fire->freq = malloc(sizeof(struct frequency));
fire->freq->base = UNKNOWN_DATA;
fire->freq->max = 3200;
@@ -279,114 +279,15 @@ void fill_cpu_info_firestorm_icestorm(struct cpuInfo* cpu, uint32_t pcores, uint
fire->next_cpu = NULL;
}
void fill_cpu_info_avalanche_blizzard(struct cpuInfo* cpu, uint32_t pcores, uint32_t ecores) {
// 1. Fill BLIZZARD
struct cpuInfo* bli = cpu;
bli->midr = MIDR_APPLE_M2_BLIZZARD;
bli->arch = get_uarch_from_midr(bli->midr, bli);
bli->cach = get_cache_info(bli);
bli->feat = get_features_info();
bli->topo = malloc(sizeof(struct topology));
bli->topo->cach = bli->cach;
bli->topo->total_cores = ecores;
bli->freq = malloc(sizeof(struct frequency));
bli->freq->base = UNKNOWN_DATA;
bli->freq->max = 2800;
bli->hv = malloc(sizeof(struct hypervisor));
bli->hv->present = false;
bli->next_cpu = malloc(sizeof(struct cpuInfo));
// 2. Fill AVALANCHE
struct cpuInfo* ava = bli->next_cpu;
ava->midr = MIDR_APPLE_M2_AVALANCHE;
ava->arch = get_uarch_from_midr(ava->midr, ava);
ava->cach = get_cache_info(ava);
ava->feat = get_features_info();
ava->topo = malloc(sizeof(struct topology));
ava->topo->cach = ava->cach;
ava->topo->total_cores = pcores;
ava->freq = malloc(sizeof(struct frequency));
ava->freq->base = UNKNOWN_DATA;
ava->freq->max = 3500;
ava->hv = malloc(sizeof(struct hypervisor));
ava->hv->present = false;
ava->next_cpu = NULL;
}
void fill_cpu_info_everest_sawtooth(struct cpuInfo* cpu, uint32_t pcores, uint32_t ecores) {
// 1. Fill SAWTOOTH
struct cpuInfo* saw = cpu;
saw->midr = MIDR_APPLE_M3_SAWTOOTH;
saw->arch = get_uarch_from_midr(saw->midr, saw);
saw->cach = get_cache_info(saw);
saw->feat = get_features_info();
saw->topo = malloc(sizeof(struct topology));
saw->topo->cach = saw->cach;
saw->topo->total_cores = ecores;
saw->freq = malloc(sizeof(struct frequency));
saw->freq->base = UNKNOWN_DATA;
saw->freq->max = 2750;
saw->hv = malloc(sizeof(struct hypervisor));
saw->hv->present = false;
saw->next_cpu = malloc(sizeof(struct cpuInfo));
// 2. Fill EVEREST
struct cpuInfo* eve = saw->next_cpu;
eve->midr = MIDR_APPLE_M3_EVEREST;
eve->arch = get_uarch_from_midr(eve->midr, eve);
eve->cach = get_cache_info(eve);
eve->feat = get_features_info();
eve->topo = malloc(sizeof(struct topology));
eve->topo->cach = eve->cach;
eve->topo->total_cores = pcores;
eve->freq = malloc(sizeof(struct frequency));
eve->freq->base = UNKNOWN_DATA;
eve->freq->max = 4050;
eve->hv = malloc(sizeof(struct hypervisor));
eve->hv->present = false;
eve->next_cpu = NULL;
}
struct cpuInfo* get_cpu_info_mach(struct cpuInfo* cpu) {
// https://developer.apple.com/documentation/kernel/1387446-sysctlbyname/determining_system_capabilities
uint32_t nperflevels = get_sys_info_by_name("hw.nperflevels");
if((cpu->num_cpus = nperflevels) != 2) {
printBug("Expected to find SoC with 2 perf levels, found: %d", cpu->num_cpus);
return NULL;
}
uint32_t pcores = get_sys_info_by_name("hw.perflevel0.physicalcpu");
uint32_t ecores = get_sys_info_by_name("hw.perflevel1.physicalcpu");
if(ecores <= 0) {
printBug("Expected to find a numer of ecores > 0, found: %d", ecores);
return NULL;
}
if(pcores <= 0) {
printBug("Expected to find a numer of pcores > 0, found: %d", pcores);
return NULL;
}
uint32_t cpu_family = get_sys_info_by_name("hw.cpufamily");
// Manually fill the cpuInfo assuming that
// the CPU is an Apple SoC
// Manually fill the cpuInfo assuming that the CPU
// is a ARM_FIRESTORM_ICESTORM (Apple M1)
if(cpu_family == CPUFAMILY_ARM_FIRESTORM_ICESTORM) {
fill_cpu_info_firestorm_icestorm(cpu, pcores, ecores);
cpu->soc = get_soc();
cpu->peak_performance = get_peak_performance(cpu);
}
else if(cpu_family == CPUFAMILY_ARM_AVALANCHE_BLIZZARD) {
fill_cpu_info_avalanche_blizzard(cpu, pcores, ecores);
cpu->soc = get_soc();
cpu->peak_performance = get_peak_performance(cpu);
}
else if(cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH ||
cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH_PRO ||
cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH_MAX) {
fill_cpu_info_everest_sawtooth(cpu, pcores, ecores);
cpu->num_cpus = 2;
cpu->soc = get_soc();
fill_cpu_info_firestorm_icestorm(cpu);
cpu->peak_performance = get_peak_performance(cpu);
}
else {
@@ -398,7 +299,7 @@ struct cpuInfo* get_cpu_info_mach(struct cpuInfo* cpu) {
}
#endif
struct cpuInfo* get_cpu_info(void) {
struct cpuInfo* get_cpu_info() {
struct cpuInfo* cpu = malloc(sizeof(struct cpuInfo));
init_cpu_info(cpu);
@@ -475,15 +376,6 @@ void print_debug(struct cpuInfo* cpu) {
printf("%ld MHz\n", freq);
}
}
#if defined(__APPLE__) || defined(__MACH__)
printf("hw.cpufamily: 0x%.8X\n", get_sys_info_by_name("hw.cpufamily"));
printf("hw.cpusubfamily: 0x%.8X\n", get_sys_info_by_name("hw.cpusubfamily"));
printf("hw.nperflevels: %d\n", get_sys_info_by_name("hw.nperflevels"));
printf("hw.physicalcpu: %d\n", get_sys_info_by_name("hw.physicalcpu"));
printf("hw.perflevel0.physicalcpu: %d\n", get_sys_info_by_name("hw.perflevel0.physicalcpu"));
printf("hw.perflevel1.physicalcpu: %d\n", get_sys_info_by_name("hw.perflevel1.physicalcpu"));
#endif
}
void free_topo_struct(struct topology* topo) {

2
src/arm/midr.h
View File

@@ -3,7 +3,7 @@
#include "../common/cpu.h"
struct cpuInfo* get_cpu_info(void);
struct cpuInfo* get_cpu_info();
uint32_t get_nsockets(struct topology* topo);
char* get_str_topology(struct cpuInfo* cpu, struct topology* topo, bool dual_socket);

528
src/arm/soc.c
View File

@@ -8,22 +8,51 @@
#include "udev.h"
#include "../common/global.h"
#if defined(__APPLE__) || defined(__MACH__)
#include "sysctl.h"
#endif
#define NA -1
#define min(a,b) (((a)<(b))?(a):(b))
#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
static char* soc_trademark_string[] = {
[SOC_VENDOR_SNAPDRAGON] = "Snapdragon ",
[SOC_VENDOR_MEDIATEK] = "MediaTek ",
[SOC_VENDOR_EXYNOS] = "Exynos ",
[SOC_VENDOR_KIRIN] = "Kirin ",
[SOC_VENDOR_BROADCOM] = "Broadcom BCM",
[SOC_VENDOR_APPLE] = "Apple ",
[SOC_VENDOR_ALLWINNER] = "Allwinner ",
[SOC_VENDOR_GOOGLE] = "Google "
};
static char* soc_rpi_string[] = {
"BCM2835",
"BCM2836",
"BCM2837",
"BCM2711",
"BCM2712"
"BCM2711"
};
void fill_soc(struct system_on_chip* soc, char* soc_name, SOC soc_model, int32_t process) {
soc->soc_model = soc_model;
soc->soc_vendor = get_soc_vendor_from_soc(soc_model);
soc->process = process;
int len = strlen(soc_name) + strlen(soc_trademark_string[soc->soc_vendor]) + 1;
soc->soc_name = emalloc(sizeof(char) * len);
memset(soc->soc_name, 0, sizeof(char) * len);
sprintf(soc->soc_name, "%s%s", soc_trademark_string[soc->soc_vendor], soc_name);
}
bool match_soc(struct system_on_chip* soc, char* raw_name, char* expected_name, char* soc_name, SOC soc_model, int32_t process) {
int len1 = strlen(raw_name);
int len2 = strlen(expected_name);
int len = min(len1, len2);
if(strncmp(raw_name, expected_name, len) != 0) {
return false;
}
else {
fill_soc(soc, soc_name, soc_model, process);
return true;
}
}
char* toupperstr(char* str) {
int len = strlen(str) + 1;
char* ret = emalloc(sizeof(char) * len);
@@ -36,61 +65,11 @@ char* toupperstr(char* str) {
return ret;
}
uint32_t get_sid_from_nvmem(char* buf) {
uint32_t sid = 0;
sid += (unsigned char) buf[0] * 1<<0;
sid += (unsigned char) buf[1] * 1<<8;
sid += (unsigned char) buf[2] * 1<<16;
sid += (unsigned char) buf[3] * 1<<24;
return sid;
}
// Security ID (SID) is an identifier that can help with SoC detection
// in Allwinner SoCs (https://linux-sunxi.org/SID_Register_Guide#Security_ID)
// SIDs list:
// - https://linux-sunxi.org/SID_Register_Guide#Currently_known_SID.27s
// - https://github.com/Dr-Noob/cpufetch/issues/173
bool get_sunxisoc_from_sid(struct system_on_chip* soc, char* raw_name, uint32_t sid) {
typedef struct {
uint32_t sid;
struct system_on_chip soc;
} sidToSoC;
sidToSoC socFromSid[] = {
// --- sun8i Family ---
// H2+
{0x02c00042, {SOC_ALLWINNER_H2PLUS, SOC_VENDOR_ALLWINNER, 40, "H2+", raw_name} },
{0x02c00142, {SOC_ALLWINNER_H2PLUS, SOC_VENDOR_ALLWINNER, 40, "H2+", raw_name} },
// H3
{0x02c00181, {SOC_ALLWINNER_H3, SOC_VENDOR_ALLWINNER, 40, "H3", raw_name} },
{0x02c00081, {SOC_ALLWINNER_H3, SOC_VENDOR_ALLWINNER, 40, "H3", raw_name} },
// Others
{0x12c00017, {SOC_ALLWINNER_R40, SOC_VENDOR_ALLWINNER, 40, "R40", raw_name} },
{0x12c00000, {SOC_ALLWINNER_V3S, SOC_VENDOR_ALLWINNER, 40, "V3s", raw_name} }, // 40nm is only my guess, no source
// --- sun50i Family ---
{0x82800001, {SOC_ALLWINNER_H5, SOC_VENDOR_ALLWINNER, 40, "H5", raw_name} },
{0x82c00007, {SOC_ALLWINNER_H6, SOC_VENDOR_ALLWINNER, 28, "H6", raw_name} },
{0x92c000bb, {SOC_ALLWINNER_H64, SOC_VENDOR_ALLWINNER, 40, "H64", raw_name} }, // Same as A64
{0x32c05000, {SOC_ALLWINNER_H616, SOC_VENDOR_ALLWINNER, 28, "H616", raw_name} },
{0x92c000ba, {SOC_ALLWINNER_A64, SOC_VENDOR_ALLWINNER, 40, "A64", raw_name} },
// Unknown
{0x00000000, {UNKNOWN, SOC_VENDOR_UNKNOWN, -1, "", raw_name} }
};
int index = 0;
while(socFromSid[index].sid != 0x0) {
if(socFromSid[index].sid == sid) {
fill_soc(soc, socFromSid[index].soc.soc_name, socFromSid[index].soc.soc_model, socFromSid[index].soc.process);
return true;
}
index++;
}
printErr("SID was found but it does not match any known SIDs: %08x", sid);
return false;
}
// Exynos special define (not included in src/common/soc.h)
#define SOC_START if (false) {}
#define SOC_EQ(raw_name, expected_name, soc_name, soc_model, soc, process) \
else if (match_soc(soc, raw_name, expected_name, soc_name, soc_model, process)) return true;
#define SOC_END else { return false; }
// Exynos special define
#define SOC_EXY_EQ(raw_name, tmpsoc, soc_name, soc_model, soc, process) \
sprintf(tmpsoc, "exynos%s", soc_name); \
if (match_soc(soc, raw_name, tmpsoc, soc_name, soc_model, process)) return true; \
@@ -106,13 +85,12 @@ bool match_broadcom(char* soc_name, struct system_on_chip* soc) {
if((tmp = strstr(soc_name, "BCM")) == NULL)
return false;
soc->soc_vendor = SOC_VENDOR_BROADCOM;
SOC_START
SOC_EQ(tmp, "BCM2835", "2835", SOC_BCM_2835, soc, 65)
SOC_EQ(tmp, "BCM2836", "2836", SOC_BCM_2836, soc, 40)
SOC_EQ(tmp, "BCM2837", "2837", SOC_BCM_2837, soc, 40)
SOC_EQ(tmp, "BCM2837B0", "2837B0", SOC_BCM_2837B0, soc, 40)
SOC_EQ(tmp, "BCM2711", "2711", SOC_BCM_2711, soc, 28)
SOC_EQ(tmp, "BCM21553", "21553", SOC_BCM_21553, soc, 65)
SOC_EQ(tmp, "BCM21553-Thunderbird", "21553 Thunderbird", SOC_BCM_21553T, soc, 65)
SOC_EQ(tmp, "BCM21663", "21663", SOC_BCM_21663, soc, 40)
@@ -122,24 +100,6 @@ bool match_broadcom(char* soc_name, struct system_on_chip* soc) {
SOC_EQ(tmp, "BCM28145", "28145", SOC_BCM_28145, soc, 40)
SOC_EQ(tmp, "BCM2157", "2157", SOC_BCM_2157, soc, 65)
SOC_EQ(tmp, "BCM21654", "21654", SOC_BCM_21654, soc, 40)
SOC_EQ(tmp, "BCM2711", "2711", SOC_BCM_2711, soc, 28)
SOC_EQ(tmp, "BCM2712", "2712", SOC_BCM_2712, soc, 16)
SOC_END
}
// https://en.wikipedia.org/wiki/Google_Tensor
bool match_google(char* soc_name, struct system_on_chip* soc) {
char* tmp;
if((tmp = strstr(soc_name, "gs")) == NULL)
return false;
soc->soc_vendor = SOC_VENDOR_GOOGLE;
SOC_START
SOC_EQ(tmp, "gs101", "Tensor", SOC_GOOGLE_TENSOR, soc, 5)
SOC_EQ(tmp, "gs201", "Tensor G2", SOC_GOOGLE_TENSOR_G2, soc, 5)
SOC_EQ(tmp, "gs301", "Tensor G3", SOC_GOOGLE_TENSOR_G3, soc, 4)
SOC_END
}
@@ -148,13 +108,11 @@ bool match_google(char* soc_name, struct system_on_chip* soc) {
bool match_hisilicon(char* soc_name, struct system_on_chip* soc) {
char* tmp;
if((tmp = strstr(soc_name, "hi")) == NULL)
if((tmp = strstr(soc_name, "Hi")) == NULL)
return false;
soc->soc_vendor = SOC_VENDOR_KIRIN;
SOC_START
SOC_EQ(tmp, "hi3620GFC", "K3V2", SOC_HISILICON_3620, soc, 40)
SOC_EQ(tmp, "Hi3620GFC", "K3V2", SOC_HISILICON_3620, soc, 40)
//SOC_EQ(tmp, "?", "K3V2E", SOC_KIRIN, soc, ?)
//SOC_EQ(tmp, "?", "620", SOC_KIRIN, soc, 28)
//SOC_EQ(tmp, "?", "650", SOC_KIRIN, soc, 16)
@@ -170,18 +128,18 @@ bool match_hisilicon(char* soc_name, struct system_on_chip* soc) {
//SOC_EQ(tmp, "?", "9000E", SOC_KIRIN, soc, 5)
//SOC_EQ(tmp, "?", "910", SOC_KIRIN, soc, 28)
//SOC_EQ(tmp, "?", "910T", SOC_KIRIN, soc, 28)
SOC_EQ(tmp, "hi3630", "920", SOC_HISILICON_3630, soc, 28)
SOC_EQ(tmp, "Hi3630", "920", SOC_HISILICON_3630, soc, 28)
//SOC_EQ(tmp, "?", "925", SOC_KIRIN, soc, 28)
//SOC_EQ(tmp, "?", "930", SOC_KIRIN, soc, ?)
//SOC_EQ(tmp, "?", "935", SOC_KIRIN, soc, ?)
SOC_EQ(tmp, "hi3650", "950", SOC_HISILICON_3650, soc, 16)
SOC_EQ(tmp, "Hi3650", "950", SOC_HISILICON_3650, soc, 16)
//SOC_EQ(tmp, "?", "955", SOC_KIRIN, soc, ?)
SOC_EQ(tmp, "hi3660", "960", SOC_HISILICON_3660, soc, 16)
SOC_EQ(tmp, "Hi3660", "960", SOC_HISILICON_3660, soc, 16)
//SOC_EQ(tmp, "?", "960S", SOC_KIRIN, soc, 16)
SOC_EQ(tmp, "hi3670", "970", SOC_HISILICON_3670, soc, 10)
SOC_EQ(tmp, "hi3680", "980", SOC_HISILICON_3680, soc, 7)
SOC_EQ(tmp, "Hi3670", "970", SOC_HISILICON_3670, soc, 10)
SOC_EQ(tmp, "Hi3680", "980", SOC_HISILICON_3680, soc, 7)
//SOC_EQ(tmp, "?", "985", SOC_KIRIN, soc, 7)
SOC_EQ(tmp, "hi3690", "990", SOC_HISILICON_3690, soc, 7)
SOC_EQ(tmp, "Hi3690", "990", SOC_HISILICON_3690, soc, 7)
SOC_END
}
@@ -192,8 +150,6 @@ bool match_exynos(char* soc_name, struct system_on_chip* soc) {
else if((tmp = strstr(soc_name, "exynos")) != NULL);
else return false;
soc->soc_vendor = SOC_VENDOR_EXYNOS;
// Because exynos are recently using "exynosXXXX" instead
// of "universalXXXX" as codenames, SOC_EXY_EQ will check for
// both cases, since it seems that there are some SoCs that
@@ -241,10 +197,6 @@ bool match_exynos(char* soc_name, struct system_on_chip* soc) {
SOC_END
}
// https://www.phonemore.com/processors/mediatek/
// https://phonedb.net/
// https://en.wikipedia.org/wiki/List_of_MediaTek_systems_on_chips
// https://wikimovel.com/index.php/MediaTek
bool match_mediatek(char* soc_name, struct system_on_chip* soc) {
char* tmp;
char* soc_name_upper = toupperstr(soc_name);
@@ -252,42 +204,27 @@ bool match_mediatek(char* soc_name, struct system_on_chip* soc) {
if((tmp = strstr(soc_name_upper, "MT")) == NULL)
return false;
soc->soc_vendor = SOC_VENDOR_MEDIATEK;
SOC_START
// Dimensity //
SOC_EQ(tmp, "MT6893Z", "Dimensity 1300", SOC_MTK_MT6893Z, soc, 6)
SOC_EQ(tmp, "MT6893", "Dimensity 1200", SOC_MTK_MT6893, soc, 6)
SOC_EQ(tmp, "MT6891", "Dimensity 1100", SOC_MTK_MT6891, soc, 6)
//SOC_EQ(tmp, "MT6877V", "Dimensity 1080", SOC_MTK_MT6877V soc, 7) // There is a clash between this and another chip
SOC_EQ(tmp, "MT6879", "Dimensity 1050", SOC_MTK_MT6879, soc, 6)
SOC_EQ(tmp, "MT6889", "Dimensity 1000", SOC_MTK_MT6889, soc, 7)
SOC_EQ(tmp, "MT6885Z", "Dimensity 1000L", SOC_MTK_MT6885Z, soc, 7)
SOC_EQ(tmp, "MT6889Z", "Dimensity 1000+", SOC_MTK_MT6889Z, soc, 7)
SOC_EQ(tmp, "MT6883Z", "Dimensity 1000C", SOC_MTK_MT6883Z, soc, 7)
SOC_EQ(tmp, "MT6833", "Dimensity 700", SOC_MTK_MT6833, soc, 7)
//SOC_EQ(tmp, "?", "Dimensity 700", SOC_MTK_, soc, 7)
SOC_EQ(tmp, "MT6853", "Dimensity 720", SOC_MTK_MT6853, soc, 7)
SOC_EQ(tmp, "MT6873", "Dimensity 800", SOC_MTK_MT6873, soc, 7)
SOC_EQ(tmp, "MT6853V", "Dimensity 800U", SOC_MTK_MT6853V, soc, 7)
SOC_EQ(tmp, "MT6833", "Dimensity 810", SOC_MTK_MT6833, soc, 6)
SOC_EQ(tmp, "MT6875", "Dimensity 820", SOC_MTK_MT6875, soc, 7)
// Helio //
SOC_EQ(tmp, "MT6761D", "Helio A20", SOC_MTK_MT6761D, soc, 12)
SOC_EQ(tmp, "MT6761", "Helio A22", SOC_MTK_MT6761, soc, 12)
SOC_EQ(tmp, "MT6762D", "Helio A25", SOC_MTK_MT6762D, soc, 12)
SOC_EQ(tmp, "MT6762G", "Helio G25", SOC_MTK_MT6762G, soc, 12)
SOC_EQ(tmp, "MT6765G", "Helio G35", SOC_MTK_MT6765G, soc, 12)
//SOC_EQ(tmp, "???", "Helio G36", SOC_MTK_MT6765G, soc, ?)
SOC_EQ(tmp, "MT6765H", "Helio G37", SOC_MTK_MT6765H, soc, 12)
SOC_EQ(tmp, "MT6769V", "Helio G70", SOC_MTK_MT6769V, soc, 12)
SOC_EQ(tmp, "MT6769T", "Helio G80", SOC_MTK_MT6769T, soc, 12)
SOC_EQ(tmp, "MT6769Z", "Helio G85", SOC_MTK_MT6769Z, soc, 12)
SOC_EQ(tmp, "MT6769H", "Helio G88", SOC_MTK_MT6769H, soc, 12)
//SOC_EQ(tmp, "MT6785V/CD", "Helio G90", SOC_MTK_MT6785V_CD, soc, 12) // How to distingish between this and G95?
SOC_EQ(tmp, "MT6785V/CC", "Helio G90T", SOC_MTK_MT6785V_CC, soc, 12)
SOC_EQ(tmp, "MT6785V/CD", "Helio G95", SOC_MTK_MT6785V_CD, soc, 12)
SOC_EQ(tmp, "MT6789", "Helio G99", SOC_MTK_MT6789, soc, 6)
SOC_EQ(tmp, "MT8781V", "Helio G99", SOC_MTK_MT8781V, soc, 6) // Same as MT6789
//SOC_EQ(tmp, "?", "Helio G25", SOC_MTK_, soc, 12)
//SOC_EQ(tmp, "?", "Helio G35", SOC_MTK_, soc, 12)
//SOC_EQ(tmp, "?", "Helio G70", SOC_MTK_, soc, 12)
//SOC_EQ(tmp, "?", "Helio G80", SOC_MTK_, soc, 12)
//SOC_EQ(tmp, "?", "Helio G90", SOC_MTK_, soc, 12)
//SOC_EQ(tmp, "?", "Helio G90T", SOC_MTK_, soc, 12)
//SOC_EQ(tmp, "?", "Helio G95", SOC_MTK_, soc, 12)
SOC_EQ(tmp, "MT6755", "Helio P10", SOC_MTK_MT6755M, soc, 28)
SOC_EQ(tmp, "MT6755M", "Helio P10 M", SOC_MTK_MT6755M, soc, 28)
SOC_EQ(tmp, "MT6755T", "Helio P15", SOC_MTK_MT6755T, soc, 28)
@@ -302,8 +239,8 @@ bool match_mediatek(char* soc_name, struct system_on_chip* soc) {
SOC_EQ(tmp, "MT6768", "Helio P65", SOC_MTK_MT6768, soc, 12)
SOC_EQ(tmp, "MT6771T", "Helio P70", SOC_MTK_MT6771, soc, 12)
SOC_EQ(tmp, "MT6771V", "Helio P70", SOC_MTK_MT6771, soc, 12)
SOC_EQ(tmp, "MT6779V/CU", "Helio P90", SOC_MTK_MT6779V_CU, soc, 12)
SOC_EQ(tmp, "MT6779V/CV", "Helio P95", SOC_MTK_MT6779V_CV, soc, 12)
SOC_EQ(tmp, "MT6779", "Helio P90", SOC_MTK_MT6779, soc, 12)
//SOC_EQ(tmp, "?", "Helio P95", SOC_MTK_, soc, 12)
SOC_EQ(tmp, "MT6795", "Helio X10", SOC_MTK_MT6795, soc, 28)
SOC_EQ(tmp, "MT6795T", "Helio X10 T", SOC_MTK_MT6795, soc, 28)
SOC_EQ(tmp, "MT6797", "Helio X20", SOC_MTK_MT6797, soc, 20)
@@ -312,31 +249,7 @@ bool match_mediatek(char* soc_name, struct system_on_chip* soc) {
SOC_EQ(tmp, "MT6797T", "Helio X25", SOC_MTK_MT6797T, soc, 20)
SOC_EQ(tmp, "MT6797X", "Helio X27", SOC_MTK_MT6797X, soc, 20)
SOC_EQ(tmp, "MT6799", "Helio X30", SOC_MTK_MT6799, soc, 10)
// Pentonic
SOC_EQ(tmp, "MT9618", "Pentonic 700", SOC_MTK_MT9618, soc, 7)
SOC_EQ(tmp, "MT9653", "Pentonic 700", SOC_MTK_MT9653, soc, 7)
SOC_EQ(tmp, "MT9689", "Pentonic 700", SOC_MTK_MT9689, soc, 7) // !! Assumption only, needs confirmation
SOC_EQ(tmp, "MT9972", "Pentonic 1000", SOC_MTK_MT9972, soc, 7) // !! Assumption only, needs confirmation
SOC_EQ(tmp, "MT9902", "Pentonic 2000", SOC_MTK_MT9902, soc, 7)
SOC_EQ(tmp, "MT9982", "Pentonic 2000", SOC_MTK_MT9982, soc, 7)
// MT XXXX //
SOC_EQ(tmp, "MT5327", "MT5327", SOC_MTK_MT5327, soc, NA)
SOC_EQ(tmp, "MT5329", "MT5329", SOC_MTK_MT5329, soc, NA)
SOC_EQ(tmp, "MT5366", "MT5366", SOC_MTK_MT5366, soc, NA)
SOC_EQ(tmp, "MT5389", "MT5389", SOC_MTK_MT5389, soc, NA)
SOC_EQ(tmp, "MT5395", "MT5395", SOC_MTK_MT5395, soc, NA)
SOC_EQ(tmp, "MT5396", "MT5396", SOC_MTK_MT5396, soc, NA)
SOC_EQ(tmp, "MT5398", "MT5398", SOC_MTK_MT5398, soc, NA)
SOC_EQ(tmp, "MT5505", "MT5505", SOC_MTK_MT5505, soc, NA)
SOC_EQ(tmp, "MT5561", "MT5561", SOC_MTK_MT5561, soc, NA)
SOC_EQ(tmp, "MT5580", "MT5580", SOC_MTK_MT5580, soc, NA)
SOC_EQ(tmp, "MT5582", "MT5582", SOC_MTK_MT5582, soc, NA)
SOC_EQ(tmp, "MT5592", "MT5592", SOC_MTK_MT5592, soc, NA)
SOC_EQ(tmp, "MT5595", "MT5595", SOC_MTK_MT5595, soc, NA)
SOC_EQ(tmp, "MT5596", "MT5596", SOC_MTK_MT5596, soc, 28) // !! Assumption only, needs confirmation
SOC_EQ(tmp, "MT5597", "MT5597", SOC_MTK_MT5597, soc, 28) // !! Assumption only, needs confirmation
SOC_EQ(tmp, "MT5895", "MT5895", SOC_MTK_MT5895, soc, 28) // Same as MT9950*
SOC_EQ(tmp, "MT5889", "MT5889", SOC_MTK_MT5889, soc, 28) // Same as MT9615 (https://www.displayspecifications.com/en/model/97272c1f)
SOC_EQ(tmp, "MT6515", "MT6515", SOC_MTK_MT6515, soc, 40)
SOC_EQ(tmp, "MT6516", "MT6516", SOC_MTK_MT6516, soc, 65)
SOC_EQ(tmp, "MT6517", "MT6517", SOC_MTK_MT6517, soc, 40)
@@ -382,19 +295,6 @@ bool match_mediatek(char* soc_name, struct system_on_chip* soc) {
SOC_EQ(tmp, "MT8735", "MT8735", SOC_MTK_MT8735, soc, 28)
SOC_EQ(tmp, "MT8765B", "MT8765B", SOC_MTK_MT8765B, soc, 28)
SOC_EQ(tmp, "MT8783", "MT8783", SOC_MTK_MT8783, soc, 28)
SOC_EQ(tmp, "MT9602", "MT9602", SOC_MTK_MT9602, soc, 28) // Same as MT9675*
SOC_EQ(tmp, "MT9612", "MT9612", SOC_MTK_MT9612, soc, 28) // Same as MT9685*
SOC_EQ(tmp, "MT9613", "MT9613", SOC_MTK_MT9613, soc, 28) // !! Assumption only, needs confirmation
SOC_EQ(tmp, "MT9615", "MT9615", SOC_MTK_MT9615, soc, 28) // https://gadgetversus.com/processor/mediatek-mt9615-specs/
SOC_EQ(tmp, "MT9632", "MT9632", SOC_MTK_MT9632, soc, 28) // Same as MT9675*
SOC_EQ(tmp, "MT9638", "MT9638", SOC_MTK_MT9638, soc, 28) // !! Assumption only, needs confirmation
SOC_EQ(tmp, "MT9652", "MT9652", SOC_MTK_MT9652, soc, 28) // Same as MT9613*
SOC_EQ(tmp, "MT9675", "MT9675", SOC_MTK_MT9675, soc, 28) // !! Assumption only, needs confirmation
SOC_EQ(tmp, "MT9685", "MT9685", SOC_MTK_MT9685, soc, 28) // https://gadgetversus.com/processor/mediatek-mt9685-specs/
SOC_EQ(tmp, "MT9950", "MT9950", SOC_MTK_MT9950, soc, 28) // https://gadgetversus.com/processor/mediatek-mt9950-specs/
SOC_EQ(tmp, "MT9686", "MT9686", SOC_MTK_MT9686, soc, 28) // Same as MT9613*
// (*) Many SoCs are reported with different names but they are the same chip.
// Source: https://en.wikipedia.org/wiki/List_of_MediaTek_systems_on_chips#Digital_television_SoCs
SOC_END
}
@@ -432,8 +332,6 @@ bool match_qualcomm(char* soc_name, struct system_on_chip* soc) {
else if((tmp = strstr(soc_name_upper, "QSD")) != NULL);
else return false;
soc->soc_vendor = SOC_VENDOR_SNAPDRAGON;
SOC_START
// Snapdragon S1 //
SOC_EQ(tmp, "QSD8650", "S1", SOC_SNAPD_QSD8650, soc, 65)
@@ -529,7 +427,6 @@ bool match_qualcomm(char* soc_name, struct system_on_chip* soc) {
SOC_EQ(tmp, "SM7125", "720G", SOC_SNAPD_SM7125, soc, 8)
SOC_EQ(tmp, "SM7150-AA", "730", SOC_SNAPD_SM7150_AA, soc, 8)
SOC_EQ(tmp, "SM7150-AB", "730G", SOC_SNAPD_SM7150_AB, soc, 8)
SOC_EQ(tmp, "SDM730G", "730G", SOC_SNAPD_SM7150_AB, soc, 8) // Issue #174
SOC_EQ(tmp, "SM7150-AC", "732G", SOC_SNAPD_SM7150_AC, soc, 8)
SOC_EQ(tmp, "SM7225", "750G", SOC_SNAPD_SM7225, soc, 8)
SOC_EQ(tmp, "SM7250-AA", "765", SOC_SNAPD_SM7250_AA, soc, 7)
@@ -566,25 +463,40 @@ bool match_allwinner(char* soc_name, struct system_on_chip* soc) {
if((tmp = strstr(soc_name, "sun")) == NULL)
return false;
soc->soc_vendor = SOC_VENDOR_ALLWINNER;
SOC_START
// SoCs we can detect just with with the name
// A series 32 bits
SOC_EQ(tmp, "sun4i", "A10", SOC_ALLWINNER_A10, soc, 55)
SOC_EQ(tmp, "sun6i", "A31", SOC_ALLWINNER_A31, soc, 40)
SOC_EQ(tmp, "sun5i", "A13", SOC_ALLWINNER_A13, soc, 55)
SOC_EQ(tmp, "sun5i", "A10s", SOC_ALLWINNER_A10S, soc, 55)
SOC_EQ(tmp, "sun7i", "A20", SOC_ALLWINNER_A20, soc, 40)
else {
// sun5i/sun8i/sun9i/sun50i will fall here
// We need SID to actually distingish between the exact model
int filelen;
char* sid_nvmem = read_file(_PATH_SUNXI_NVMEM, &filelen);
if(sid_nvmem == NULL) {
printWarn("read_file: %s: %s", _PATH_SUNXI_NVMEM, strerror(errno));
return false;
}
uint32_t sid = get_sid_from_nvmem(sid_nvmem);
return get_sunxisoc_from_sid(soc, soc_name, sid);
}
SOC_EQ(tmp, "sun8i", "A23", SOC_ALLWINNER_A23, soc, 40)
SOC_EQ(tmp, "sun6i", "A31", SOC_ALLWINNER_A31, soc, 40)
SOC_EQ(tmp, "sun6i", "A31s", SOC_ALLWINNER_A31S, soc, 40)
SOC_EQ(tmp, "sun8i", "A33", SOC_ALLWINNER_A33, soc, 40)
SOC_EQ(tmp, "sun8i", "A40", SOC_ALLWINNER_A40, soc, 40)
SOC_EQ(tmp, "sun8i", "A50", SOC_ALLWINNER_A50, soc, 28)
SOC_EQ(tmp, "sun9i", "A80", SOC_ALLWINNER_A80, soc, 28)
SOC_EQ(tmp, "sun8i", "A83T", SOC_ALLWINNER_A83T, soc, 28)
// H series 32 bits
SOC_EQ(tmp, "sun8i", "H2+", SOC_ALLWINNER_HZP, soc, 40)
SOC_EQ(tmp, "sun8i", "H3", SOC_ALLWINNER_H3, soc, 40)
SOC_EQ(tmp, "sun8i", "H8", SOC_ALLWINNER_H8, soc, 28)
// H series 64 bits
SOC_EQ(tmp, "sun50i", "H5", SOC_ALLWINNER_H5, soc, 40)
SOC_EQ(tmp, "sun50i", "H6", SOC_ALLWINNER_H6, soc, 28)
SOC_EQ(tmp, "sun50i", "H616", SOC_ALLWINNER_H616, soc, 28)
// R series 32 bits
SOC_EQ(tmp, "sun5i", "R8", SOC_ALLWINNER_R8, soc, 55)
SOC_EQ(tmp, "sun8i", "R16", SOC_ALLWINNER_R16, soc, 40)
SOC_EQ(tmp, "sun8i", "R40", SOC_ALLWINNER_R40, soc, 40)
SOC_EQ(tmp, "sun8i", "R58", SOC_ALLWINNER_R58, soc, 28)
// R series 64 bits
SOC_EQ(tmp, "sun50i", "R329", SOC_ALLWINNER_R328, soc, 28)
SOC_END
}
bool match_special(char* soc_name, struct system_on_chip* soc) {
@@ -602,27 +514,12 @@ bool match_special(char* soc_name, struct system_on_chip* soc) {
return true;
}
// Snapdragon 8 Gen 1 reported as "taro"
if(strcmp(soc_name, "taro") == 0) {
fill_soc(soc, "8 Gen 1", SOC_SNAPD_SM8450, 4);
return true;
}
// Google Pixel 6
// https://github.com/Dr-Noob/cpufetch/issues/134
if(strcmp(soc_name, "oriole") == 0) {
// Google Pixel 6 (Proably stands for Google Silicon 101)'
if((tmp = strstr(soc_name, "gs101")) != NULL) {
fill_soc(soc, "Tensor", SOC_GOOGLE_TENSOR, 5);
return true;
}
// Google Pixel 8
// https://github.com/Dr-Noob/cpufetch/issues/198
if(strcmp(soc_name, "husky") == 0 ||
strcmp(soc_name, "zuma") == 0) {
fill_soc(soc, "Tensor G3", SOC_GOOGLE_TENSOR_G3, 4);
return true;
}
return false;
}
@@ -647,9 +544,6 @@ struct system_on_chip* parse_soc_from_string(struct system_on_chip* soc) {
if(match_allwinner(raw_name, soc))
return soc;
if(match_google(raw_name, soc))
return soc;
match_broadcom(raw_name, soc);
return soc;
}
@@ -709,78 +603,6 @@ struct system_on_chip* guess_soc_from_cpuinfo(struct system_on_chip* soc) {
return soc;
}
char* get_rk_efuse(void) {
int filelen;
char* rk_soc = read_file(_PATH_RK_EFUSE0, &filelen);
if(rk_soc == NULL) {
printWarn("read_file: %s: %s", _PATH_RK_EFUSE0, strerror(errno));
rk_soc = read_file(_PATH_RK_OTP0, &filelen);
if(rk_soc == NULL) {
printWarn("read_file: %s: %s", _PATH_RK_OTP0, strerror(errno));
}
}
return rk_soc;
}
bool get_rk_soc_from_efuse(struct system_on_chip* soc, char* efuse) {
typedef struct {
uint16_t rk_soc;
struct system_on_chip soc;
} rkToSoC;
uint16_t rk_soc = efuse[2]*256 + efuse[3];
// https://wikimovel.com/index.php/Rockchip
rkToSoC socFromRK[] = {
// TODO: Add RK2XXX
// RK3XXX
// Reverse order
{0x2388, {SOC_ROCKCHIP_3288, SOC_VENDOR_ROCKCHIP, 28, "RK3288", NULL} },
{0x2392, {SOC_ROCKCHIP_3229, SOC_VENDOR_ROCKCHIP, 28, "RK3229", NULL} }, // https://gadgetversus.com/processor/rockchip-rk3229-vs-rockchip-rk3128/
{0x3380, {SOC_ROCKCHIP_3308, SOC_VENDOR_ROCKCHIP, 28, "RK3308", NULL} }, // https://en.t-firefly.com/product/rocrk3308cc?theme=pc
{0x3381, {SOC_ROCKCHIP_3318, SOC_VENDOR_ROCKCHIP, 28, "RK3318", NULL} },
{0x3362, {SOC_ROCKCHIP_3326, SOC_VENDOR_ROCKCHIP, 28, "RK3326", NULL} },
{0x3382, {SOC_ROCKCHIP_3328, SOC_VENDOR_ROCKCHIP, 28, "RK3328", NULL} },
{0x3386, {SOC_ROCKCHIP_3368, SOC_VENDOR_ROCKCHIP, 28, "RK3368", NULL} },
{0x3399, {SOC_ROCKCHIP_3399, SOC_VENDOR_ROCKCHIP, 28, "RK3399", NULL} },
// Normal Order (https://github.com/Dr-Noob/cpufetch/issues/209)
{0x3528, {SOC_ROCKCHIP_3528, SOC_VENDOR_ROCKCHIP, 28, "RK3528", NULL} },
{0x3562, {SOC_ROCKCHIP_3562, SOC_VENDOR_ROCKCHIP, 22, "RK3562", NULL} },
{0x3566, {SOC_ROCKCHIP_3566, SOC_VENDOR_ROCKCHIP, 22, "RK3566", NULL} },
{0x3568, {SOC_ROCKCHIP_3568, SOC_VENDOR_ROCKCHIP, 22, "RK3568", NULL} },
{0x3588, {SOC_ROCKCHIP_3588, SOC_VENDOR_ROCKCHIP, 8, "RK3588", NULL} }, // No known way to distingish between S version: https://github.com/Dr-Noob/cpufetch/issues/188,209
// Unknown
{0x0000, {UNKNOWN, SOC_VENDOR_UNKNOWN, -1, "", NULL} }
};
int index = 0;
while(socFromRK[index].rk_soc != 0x0) {
if(socFromRK[index].rk_soc == rk_soc) {
fill_soc(soc, socFromRK[index].soc.soc_name, socFromRK[index].soc.soc_model, socFromRK[index].soc.process);
return true;
}
index++;
}
printErr("RK SoC was found but it does not match any known SoCs: 0x%04x", rk_soc);
return false;
}
struct system_on_chip* guess_soc_from_nvmem(struct system_on_chip* soc) {
// This method is only valid for Rockchip SoCs
char* rk_soc = get_rk_efuse();
if(rk_soc != NULL) {
if(rk_soc[0] == 0x52 && rk_soc[1] == 0x4b) {
get_rk_soc_from_efuse(soc, rk_soc);
return soc;
}
else {
printWarn("guess_soc_from_nvmem: efuse found, but contains unexpected header: 0x%x 0x%x", rk_soc[0], rk_soc[1]);
}
}
return soc;
}
int hex2int(char c) {
if (c >= '0' && c <= '9')
return c - '0';
@@ -792,13 +614,7 @@ int hex2int(char c) {
return -1;
}
/*
* https://www.raspberrypi.com/documentation/computers/raspberry-pi.html#raspberry-pi-revision-codes:
* NOTE: As of the 4.9 kernel, all Raspberry Pi computers report BCM2835, even those with BCM2836,
* BCM2837 and BCM2711 processors. You should not use this string to detect the processor. Decode the
* revision code using the information below.
* https://www.raspberrypi.com/documentation/computers/raspberry-pi.html#new-style-revision-codes-in-use
*/
// https://www.raspberrypi.org/documentation/hardware/raspberrypi/revision-codes/README.md
struct system_on_chip* guess_soc_raspbery_pi(struct system_on_chip* soc) {
char* revision = get_revision_from_cpuinfo();
@@ -814,112 +630,29 @@ struct system_on_chip* guess_soc_raspbery_pi(struct system_on_chip* soc) {
int arr_size = ARRAY_SIZE(soc_rpi_string);
int pppp = hex2int(revision[2]);
if(pppp < 0) {
printBug("[RPi] Found invalid RPi PPPP code: %s", pppp);
if(pppp == -1) {
printErr("[RPi] Found invalid RPi PPPP code: %s", revision[2]);
return soc;
}
if(pppp > arr_size-1) {
printBug("[RPi] Found invalid RPi PPPP code: %d (max is %d)", pppp, arr_size-1);
if(pppp > arr_size) {
printErr("[RPi] Found invalid RPi PPPP code: %d while max is %d", pppp, arr_size);
return soc;
}
char* soc_raw_name = soc_rpi_string[pppp];
/*int soc_len = strlen(soc_raw_name);
soc->raw_name = emalloc(sizeof(char) * (soc_len + 1));
strncpy(soc->raw_name, soc_raw_name, soc_len + 1);*/
match_broadcom(soc_raw_name, soc);
return soc;
}
#if defined(__APPLE__) || defined(__MACH__)
struct system_on_chip* guess_soc_apple(struct system_on_chip* soc) {
uint32_t cpu_family = get_sys_info_by_name("hw.cpufamily");
uint32_t cpu_subfamily = get_sys_info_by_name("hw.cpusubfamily");
if(cpu_family == CPUFAMILY_ARM_FIRESTORM_ICESTORM) {
// Check M1 version
if(cpu_subfamily == CPUSUBFAMILY_ARM_HG) {
fill_soc(soc, "M1", SOC_APPLE_M1, 5);
}
else if(cpu_subfamily == CPUSUBFAMILY_ARM_HS) {
fill_soc(soc, "M1 Pro", SOC_APPLE_M1_PRO, 5);
}
else if(cpu_subfamily == CPUSUBFAMILY_ARM_HC_HD) {
// Could be M1 Max or M1 Ultra (2x M1 Max)
uint32_t physicalcpu = get_sys_info_by_name("hw.physicalcpu");
if(physicalcpu == 20) {
fill_soc(soc, "M1 Ultra", SOC_APPLE_M1_ULTRA, 5);
}
else if(physicalcpu == 10) {
fill_soc(soc, "M1 Max", SOC_APPLE_M1_MAX, 5);
}
else {
printBug("Found invalid physical cpu number: %d", physicalcpu);
soc->soc_vendor = SOC_VENDOR_UNKNOWN;
}
}
else {
printBug("Found invalid cpu_subfamily: 0x%.8X", cpu_subfamily);
soc->soc_vendor = SOC_VENDOR_UNKNOWN;
}
}
else if(cpu_family == CPUFAMILY_ARM_AVALANCHE_BLIZZARD) {
// Check M2 version
if(cpu_subfamily == CPUSUBFAMILY_ARM_HG) {
fill_soc(soc, "M2", SOC_APPLE_M2, 5);
}
else if(cpu_subfamily == CPUSUBFAMILY_ARM_HS) {
fill_soc(soc, "M2 Pro", SOC_APPLE_M2_PRO, 5);
}
else if(cpu_subfamily == CPUSUBFAMILY_ARM_HC_HD) {
// Could be M2 Max or M2 Ultra (2x M1 Max)
uint32_t physicalcpu = get_sys_info_by_name("hw.physicalcpu");
if(physicalcpu == 24) {
fill_soc(soc, "M2 Ultra", SOC_APPLE_M2_ULTRA, 5);
}
else if(physicalcpu == 12) {
fill_soc(soc, "M2 Max", SOC_APPLE_M2_MAX, 5);
}
else {
printBug("Found invalid physical cpu number: %d", physicalcpu);
soc->soc_vendor = SOC_VENDOR_UNKNOWN;
}
}
else {
printBug("Found invalid cpu_subfamily: 0x%.8X", cpu_subfamily);
soc->soc_vendor = SOC_VENDOR_UNKNOWN;
}
}
else if(cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH ||
cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH_PRO ||
cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH_MAX) {
// Check M3 version
if(cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH) {
fill_soc(soc, "M3", SOC_APPLE_M3, 3);
}
else if(cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH_PRO) {
fill_soc(soc, "M3 Pro", SOC_APPLE_M3_PRO, 3);
}
else if(cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH_MAX) {
fill_soc(soc, "M3 Max", SOC_APPLE_M3_MAX, 3);
}
else {
printBug("Found invalid cpu_family: 0x%.8X", cpu_family);
soc->soc_vendor = SOC_VENDOR_UNKNOWN;
}
}
else {
printBug("Found invalid cpu_family: 0x%.8X", cpu_family);
soc->soc_vendor = SOC_VENDOR_UNKNOWN;
}
return soc;
}
#endif
struct system_on_chip* get_soc(void) {
struct system_on_chip* get_soc() {
struct system_on_chip* soc = emalloc(sizeof(struct system_on_chip));
soc->raw_name = NULL;
soc->soc_vendor = SOC_VENDOR_UNKNOWN;
soc->soc_model = SOC_MODEL_UNKNOWN;
soc->process = UNKNOWN;
#ifdef __linux__
@@ -927,7 +660,7 @@ struct system_on_chip* get_soc(void) {
if(isRPi) {
soc = guess_soc_raspbery_pi(soc);
if(soc->soc_vendor == SOC_VENDOR_UNKNOWN) {
printErr("[RPi] SoC detection failed using revision code, falling back to cpuinfo detection");
printWarn("SoC detection failed using revision code");
}
else {
return soc;
@@ -936,42 +669,51 @@ struct system_on_chip* get_soc(void) {
soc = guess_soc_from_cpuinfo(soc);
if(soc->soc_vendor == SOC_VENDOR_UNKNOWN) {
if(soc->raw_name != NULL) {
if(soc->raw_name != NULL)
printWarn("SoC detection failed using /proc/cpuinfo: Found '%s' string", soc->raw_name);
}
else {
else
printWarn("SoC detection failed using /proc/cpuinfo: No string found");
}
#ifdef __ANDROID__
soc = guess_soc_from_android(soc);
if(soc->raw_name == NULL) {
if(soc->raw_name == NULL)
printWarn("SoC detection failed using Android: No string found");
}
else if(soc->soc_vendor == SOC_VENDOR_UNKNOWN) {
else if(soc->soc_vendor == SOC_VENDOR_UNKNOWN)
printWarn("SoC detection failed using Android: Found '%s' string", soc->raw_name);
}
#endif // ifdef __ANDROID__
// If cpufinfo/Android (if available) detection fails, try with nvmem
if(soc->soc_vendor == SOC_VENDOR_UNKNOWN) {
soc = guess_soc_from_nvmem(soc);
}
}
#elif defined __APPLE__ || __MACH__
soc = guess_soc_apple(soc);
if(soc->soc_vendor == SOC_VENDOR_UNKNOWN) {
printWarn("SoC detection failed using cpu_subfamily");
}
else {
return soc;
}
fill_soc(soc, "M1", SOC_APPLE_M1, 5);
#endif // ifdef __linux__
if(soc->soc_model == SOC_MODEL_UNKNOWN) {
// raw_name might not be NULL, but if we were unable to find
// the exact SoC, just print "Unkwnown"
if(soc->raw_name == NULL) {
soc->raw_name = emalloc(sizeof(char) * (strlen(STRING_UNKNOWN)+1));
snprintf(soc->raw_name, strlen(STRING_UNKNOWN)+1, STRING_UNKNOWN);
}
return soc;
}
char* get_soc_name(struct system_on_chip* soc) {
if(soc->soc_vendor == SOC_VENDOR_UNKNOWN)
return soc->raw_name;
return soc->soc_name;
}
VENDOR get_soc_vendor(struct system_on_chip* soc) {
return soc->soc_vendor;
}
char* get_str_process(struct system_on_chip* soc) {
char* str;
if(soc->process == UNKNOWN) {
str = emalloc(sizeof(char) * (strlen(STRING_UNKNOWN)+1));
snprintf(str, strlen(STRING_UNKNOWN)+1, STRING_UNKNOWN);
}
else {
str = emalloc(sizeof(char) * 5);
memset(str, 0, sizeof(char) * 5);
snprintf(str, 5, "%dnm", soc->process);
}
return str;
}

32
src/arm/soc.h
View File

@@ -1,10 +1,34 @@
#ifndef __SOC_ARM__
#define __SOC_ARM__
#ifndef __SOC__
#define __SOC__
#include "../common/cpu.h"
#include "../common/soc.h"
#include <stdint.h>
struct system_on_chip* get_soc(void);
typedef int32_t SOC;
enum {
SOC_VENDOR_UNKNOWN,
SOC_VENDOR_SNAPDRAGON,
SOC_VENDOR_MEDIATEK,
SOC_VENDOR_EXYNOS,
SOC_VENDOR_KIRIN,
SOC_VENDOR_BROADCOM,
SOC_VENDOR_APPLE,
SOC_VENDOR_ALLWINNER,
SOC_VENDOR_GOOGLE
};
struct system_on_chip {
SOC soc_model;
VENDOR soc_vendor;
int32_t process;
char* soc_name;
char* raw_name;
};
struct system_on_chip* get_soc();
char* get_soc_name(struct system_on_chip* soc);
VENDOR get_soc_vendor(struct system_on_chip* soc);
char* get_str_process(struct system_on_chip* soc);
#endif

159
src/arm/socs.h
View File

@@ -10,6 +10,7 @@ enum {
SOC_BCM_2836,
SOC_BCM_2837,
SOC_BCM_2837B0,
SOC_BCM_2711,
SOC_BCM_21553,
SOC_BCM_21553T,
SOC_BCM_21663,
@@ -19,8 +20,6 @@ enum {
SOC_BCM_28145,
SOC_BCM_2157,
SOC_BCM_21654,
SOC_BCM_2711,
SOC_BCM_2712,
// Hisilicon //
SOC_HISILICON_3620,
SOC_HISILICON_3630,
@@ -64,23 +63,39 @@ enum {
SOC_EXYNOS_980,
SOC_EXYNOS_880,
// Mediatek //
SOC_MTK_MT5327,
SOC_MTK_MT5329,
SOC_MTK_MT5366,
SOC_MTK_MT5389,
SOC_MTK_MT5395,
SOC_MTK_MT5396,
SOC_MTK_MT5398,
SOC_MTK_MT5505,
SOC_MTK_MT5561,
SOC_MTK_MT5580,
SOC_MTK_MT5582,
SOC_MTK_MT5592,
SOC_MTK_MT5595,
SOC_MTK_MT5596,
SOC_MTK_MT5597,
SOC_MTK_MT5889,
SOC_MTK_MT5895,
SOC_MTK_MT6893,
SOC_MTK_MT6891,
SOC_MTK_MT6889,
SOC_MTK_MT6885Z,
SOC_MTK_MT6853,
SOC_MTK_MT6873,
SOC_MTK_MT6875,
SOC_MTK_MT6761D,
SOC_MTK_MT6761,
SOC_MTK_MT6762D,
SOC_MTK_MT6755,
SOC_MTK_MT6755M,
SOC_MTK_MT6755T,
SOC_MTK_MT6757,
SOC_MTK_MT6762,
SOC_MTK_MT6763V,
SOC_MTK_MT6763T,
SOC_MTK_MT6757CD,
SOC_MTK_MT6758,
SOC_MTK_MT6765,
SOC_MTK_MT6771,
SOC_MTK_MT6768,
SOC_MTK_MT6771T,
SOC_MTK_MT6771V,
SOC_MTK_MT6779,
SOC_MTK_MT6795,
SOC_MTK_MT6795T,
SOC_MTK_MT6797,
SOC_MTK_MT6797M,
SOC_MTK_MT6797D,
SOC_MTK_MT6797T,
SOC_MTK_MT6797X,
SOC_MTK_MT6799,
SOC_MTK_MT6515,
SOC_MTK_MT6516,
SOC_MTK_MT6517,
@@ -110,51 +125,7 @@ enum {
SOC_MTK_MT6750T,
SOC_MTK_MT6752,
SOC_MTK_MT6753,
SOC_MTK_MT6755M,
SOC_MTK_MT6755T,
SOC_MTK_MT6757,
SOC_MTK_MT6757CD,
SOC_MTK_MT6758,
SOC_MTK_MT6761,
SOC_MTK_MT6761D,
SOC_MTK_MT6762,
SOC_MTK_MT6762D,
SOC_MTK_MT6762G,
SOC_MTK_MT6763T,
SOC_MTK_MT6763V,
SOC_MTK_MT6765,
SOC_MTK_MT6765G,
SOC_MTK_MT6765H,
SOC_MTK_MT6768,
SOC_MTK_MT6769H,
SOC_MTK_MT6769T,
SOC_MTK_MT6769V,
SOC_MTK_MT6769Z,
SOC_MTK_MT6771,
SOC_MTK_MT6779V_CU,
SOC_MTK_MT6779V_CV,
SOC_MTK_MT6785V_CC,
SOC_MTK_MT6785V_CD,
SOC_MTK_MT6789,
SOC_MTK_MT6795,
SOC_MTK_MT6797,
SOC_MTK_MT6797T,
SOC_MTK_MT6797X,
SOC_MTK_MT6799,
SOC_MTK_MT6833,
SOC_MTK_MT6850,
SOC_MTK_MT6853,
SOC_MTK_MT6853V,
SOC_MTK_MT6873,
SOC_MTK_MT6875,
SOC_MTK_MT6879,
SOC_MTK_MT6883Z,
SOC_MTK_MT6885Z,
SOC_MTK_MT6889,
SOC_MTK_MT6889Z,
SOC_MTK_MT6891,
SOC_MTK_MT6893,
SOC_MTK_MT6893Z,
SOC_MTK_MT8121,
SOC_MTK_MT8125,
SOC_MTK_MT8127,
@@ -169,25 +140,7 @@ enum {
SOC_MTK_MT8581,
SOC_MTK_MT8735,
SOC_MTK_MT8765B,
SOC_MTK_MT8781V,
SOC_MTK_MT8783,
SOC_MTK_MT9602,
SOC_MTK_MT9612,
SOC_MTK_MT9613,
SOC_MTK_MT9615,
SOC_MTK_MT9618,
SOC_MTK_MT9632,
SOC_MTK_MT9638,
SOC_MTK_MT9652,
SOC_MTK_MT9653,
SOC_MTK_MT9675,
SOC_MTK_MT9685,
SOC_MTK_MT9686,
SOC_MTK_MT9689,
SOC_MTK_MT9902,
SOC_MTK_MT9950,
SOC_MTK_MT9972,
SOC_MTK_MT9982,
// Snapdragon //
SOC_SNAPD_QSD8650,
SOC_SNAPD_QSD8250,
@@ -299,19 +252,8 @@ enum {
SOC_SNAPD_SM8250,
SOC_SNAPD_SM8250_AB,
SOC_SNAPD_SM8350,
SOC_SNAPD_SM8450,
// APPLE
SOC_APPLE_M1,
SOC_APPLE_M1_PRO,
SOC_APPLE_M1_MAX,
SOC_APPLE_M1_ULTRA,
SOC_APPLE_M2,
SOC_APPLE_M2_PRO,
SOC_APPLE_M2_MAX,
SOC_APPLE_M2_ULTRA,
SOC_APPLE_M3,
SOC_APPLE_M3_PRO,
SOC_APPLE_M3_MAX,
// ALLWINNER
SOC_ALLWINNER_A10,
SOC_ALLWINNER_A13,
@@ -323,55 +265,32 @@ enum {
SOC_ALLWINNER_A33,
SOC_ALLWINNER_A40,
SOC_ALLWINNER_A50,
SOC_ALLWINNER_A64,
SOC_ALLWINNER_A80,
SOC_ALLWINNER_A83T,
SOC_ALLWINNER_V3S,
SOC_ALLWINNER_HZP,
SOC_ALLWINNER_H2PLUS,
SOC_ALLWINNER_H3,
SOC_ALLWINNER_H8,
SOC_ALLWINNER_H5,
SOC_ALLWINNER_H6,
SOC_ALLWINNER_H64,
SOC_ALLWINNER_H616,
SOC_ALLWINNER_R8,
SOC_ALLWINNER_R16,
SOC_ALLWINNER_R40,
SOC_ALLWINNER_R58,
SOC_ALLWINNER_R328,
// ROCKCHIP
SOC_ROCKCHIP_3288,
SOC_ROCKCHIP_3229,
SOC_ROCKCHIP_3308,
SOC_ROCKCHIP_3318,
SOC_ROCKCHIP_3326,
SOC_ROCKCHIP_3328,
SOC_ROCKCHIP_3368,
SOC_ROCKCHIP_3399,
SOC_ROCKCHIP_3528,
SOC_ROCKCHIP_3562,
SOC_ROCKCHIP_3566,
SOC_ROCKCHIP_3568,
SOC_ROCKCHIP_3588,
// GOOGLE
SOC_GOOGLE_TENSOR,
SOC_GOOGLE_TENSOR_G2,
SOC_GOOGLE_TENSOR_G3,
// UNKNOWN
SOC_MODEL_UNKNOWN
SOC_GOOGLE_TENSOR
};
inline static VENDOR get_soc_vendor_from_soc(SOC soc) {
if(soc >= SOC_BCM_2835 && soc <= SOC_BCM_2712) return SOC_VENDOR_BROADCOM;
if(soc >= SOC_BCM_2835 && soc <= SOC_BCM_21654) return SOC_VENDOR_BROADCOM;
else if(soc >= SOC_HISILICON_3620 && soc <= SOC_HISILICON_3690) return SOC_VENDOR_KIRIN;
else if(soc >= SOC_EXYNOS_3475 && soc <= SOC_EXYNOS_880) return SOC_VENDOR_EXYNOS;
else if(soc >= SOC_MTK_MT6893 && soc <= SOC_MTK_MT8783) return SOC_VENDOR_MEDIATEK;
else if(soc >= SOC_SNAPD_QSD8650 && soc <= SOC_SNAPD_SM8450) return SOC_VENDOR_SNAPDRAGON;
else if(soc >= SOC_APPLE_M1 && soc <= SOC_APPLE_M3_MAX) return SOC_VENDOR_APPLE;
else if(soc >= SOC_SNAPD_QSD8650 && soc <= SOC_SNAPD_SM8350) return SOC_VENDOR_SNAPDRAGON;
else if(soc >= SOC_APPLE_M1 && soc <= SOC_APPLE_M1) return SOC_VENDOR_APPLE;
else if(soc >= SOC_ALLWINNER_A10 && soc <= SOC_ALLWINNER_R328) return SOC_VENDOR_ALLWINNER;
else if(soc >= SOC_ROCKCHIP_3288 && soc <= SOC_ROCKCHIP_3588) return SOC_VENDOR_ROCKCHIP;
else if(soc >= SOC_GOOGLE_TENSOR && soc <= SOC_GOOGLE_TENSOR_G3) return SOC_VENDOR_GOOGLE;
else if(soc == SOC_GOOGLE_TENSOR) return SOC_VENDOR_GOOGLE;
return SOC_VENDOR_UNKNOWN;
}

39
src/arm/sysctl.h
View File

@@ -1,45 +1,6 @@
#ifndef __SYSCTL__
#define __SYSCTL__
// From Linux kernel: arch/arm64/include/asm/cputype.h
#define MIDR_APPLE_M1_ICESTORM 0x610F0220
#define MIDR_APPLE_M1_FIRESTORM 0x610F0230
// Kernel does not include those, so I just assume that
// APPLE_CPU_PART_M2_BLIZZARD=0x30,M2_AVALANCHE=0x31
#define MIDR_APPLE_M2_BLIZZARD 0x610F0300
#define MIDR_APPLE_M2_AVALANCHE 0x610F0310
// https://github.com/AsahiLinux/m1n1/blob/main/src/chickens.c
#define MIDR_APPLE_M3_SAWTOOTH 0x610F0480
#define MIDR_APPLE_M3_EVEREST 0x610F0490
// M1 / A14
#ifndef CPUFAMILY_ARM_FIRESTORM_ICESTORM
#define CPUFAMILY_ARM_FIRESTORM_ICESTORM 0x1B588BB3
#endif
// M2 / A15
#ifndef CPUFAMILY_ARM_AVALANCHE_BLIZZARD
#define CPUFAMILY_ARM_AVALANCHE_BLIZZARD 0xDA33D83D
#endif
// M3 / A16 / A17
// https://ratfactor.com/zig/stdlib-browseable2/c/darwin.zig.html
// https://github.com/Dr-Noob/cpufetch/issues/210
#define CPUFAMILY_ARM_EVEREST_SAWTOOTH 0x8765EDEA
#define CPUFAMILY_ARM_EVEREST_SAWTOOTH_PRO 0x5F4DEA93
#define CPUFAMILY_ARM_EVEREST_SAWTOOTH_MAX 0x72015832
// For detecting different M1 types
// NOTE: Could also be achieved detecting different
// MIDR values (e.g., APPLE_CPU_PART_M1_ICESTORM_PRO)
#ifndef CPUSUBFAMILY_ARM_HG
#define CPUSUBFAMILY_ARM_HG 2
#endif
#ifndef CPUSUBFAMILY_ARM_HS
#define CPUSUBFAMILY_ARM_HS 4
#endif
#ifndef CPUSUBFAMILY_ARM_HC_HD
#define CPUSUBFAMILY_ARM_HC_HD 5
#endif
uint32_t get_sys_info_by_name(char* name);
#endif

146
src/arm/uarch.c
View File

@@ -33,8 +33,6 @@ enum {
ISA_ARMv8_2_A,
ISA_ARMv8_3_A,
ISA_ARMv8_4_A,
ISA_ARMv8_5_A,
ISA_ARMv9_A
};
enum {
@@ -66,15 +64,9 @@ enum {
UARCH_CORTEX_A76,
UARCH_CORTEX_A77,
UARCH_CORTEX_A78,
UARCH_CORTEX_A510,
UARCH_CORTEX_A710,
UARCH_CORTEX_A715,
UARCH_CORTEX_X1,
UARCH_CORTEX_X2,
UARCH_CORTEX_X3,
UARCH_NEOVERSE_N1,
UARCH_NEOVERSE_E1,
UARCH_NEOVERSE_V1,
UARCH_SCORPION,
UARCH_KRAIT,
UARCH_KYRO,
@@ -103,10 +95,6 @@ enum {
UARCH_THUNDER, // Apple A13 processor (little cores).
UARCH_ICESTORM, // Apple M1 processor (little cores).
UARCH_FIRESTORM, // Apple M1 processor (big cores).
UARCH_BLIZZARD, // Apple M2 processor (little cores).
UARCH_AVALANCHE, // Apple M2 processor (big cores).
UARCH_SAWTOOTH, // Apple M3 processor (little cores).
UARCH_EVEREST, // Apple M3 processor (big cores).
// CAVIUM
UARCH_THUNDERX, // Cavium ThunderX
UARCH_THUNDERX2, // Cavium ThunderX2 (originally Broadcom Vulkan).
@@ -115,9 +103,7 @@ enum {
UARCH_BRAHMA_B15,
UARCH_BRAHMA_B53,
UARCH_XGENE, // Applied Micro X-Gene.
UARCH_TAISHAN_V110, // HiSilicon TaiShan v110 (Huawei Kunpeng 920 series processors).
// PHYTIUM
UARCH_XIAOMI, // Not to be confused with Xiaomi Inc
UARCH_TAISHAN_V110 // HiSilicon TaiShan v110 (Huawei Kunpeng 920 series processors).
};
static const ISA isas_uarch[] = {
@@ -145,15 +131,9 @@ static const ISA isas_uarch[] = {
[UARCH_CORTEX_A76] = ISA_ARMv8_2_A,
[UARCH_CORTEX_A77] = ISA_ARMv8_2_A,
[UARCH_CORTEX_A78] = ISA_ARMv8_2_A,
[UARCH_CORTEX_A510] = ISA_ARMv9_A,
[UARCH_CORTEX_A710] = ISA_ARMv9_A,
[UARCH_CORTEX_A715] = ISA_ARMv9_A,
[UARCH_CORTEX_X1] = ISA_ARMv8_2_A,
[UARCH_CORTEX_X2] = ISA_ARMv9_A,
[UARCH_CORTEX_X3] = ISA_ARMv9_A,
[UARCH_NEOVERSE_N1] = ISA_ARMv8_2_A,
[UARCH_NEOVERSE_E1] = ISA_ARMv8_2_A,
[UARCH_NEOVERSE_V1] = ISA_ARMv8_4_A,
[UARCH_BRAHMA_B15] = ISA_ARMv7_A, // Same as Cortex-A15
[UARCH_BRAHMA_B53] = ISA_ARMv8_A, // Same as Cortex-A53
[UARCH_THUNDERX] = ISA_ARMv8_A,
@@ -173,12 +153,9 @@ static const ISA isas_uarch[] = {
[UARCH_EXYNOS_M3] = ISA_ARMv8_A,
[UARCH_EXYNOS_M4] = ISA_ARMv8_2_A,
[UARCH_EXYNOS_M5] = ISA_ARMv8_2_A,
[UARCH_ICESTORM] = ISA_ARMv8_5_A, // https://github.com/llvm/llvm-project/blob/main/llvm/include/llvm/Support/AArch64TargetParser.def
[UARCH_FIRESTORM] = ISA_ARMv8_5_A,
[UARCH_BLIZZARD] = ISA_ARMv8_5_A, // Not confirmed
[UARCH_AVALANCHE] = ISA_ARMv8_5_A,
[UARCH_ICESTORM] = ISA_ARMv8_4_A,
[UARCH_FIRESTORM] = ISA_ARMv8_4_A,
[UARCH_PJ4] = ISA_ARMv7_A,
[UARCH_XIAOMI] = ISA_ARMv8_A,
};
static char* isas_string[] = {
@@ -192,17 +169,13 @@ static char* isas_string[] = {
[ISA_ARMv8_1_A] = "ARMv8.1",
[ISA_ARMv8_2_A] = "ARMv8.2",
[ISA_ARMv8_3_A] = "ARMv8.3",
[ISA_ARMv8_4_A] = "ARMv8.4",
[ISA_ARMv8_5_A] = "ARMv8.5",
[ISA_ARMv9_A] = "ARMv9"
[ISA_ARMv8_4_A] = "ARMv8.4"
};
#define UARCH_START if (false) {}
#define CHECK_UARCH(arch, cpu, im_, p_, v_, r_, str, uarch, vendor) \
else if (im_ == im && p_ == p && (v_ == NA || v_ == v) && (r_ == NA || r_ == r)) fill_uarch(arch, cpu, str, uarch, vendor);
#define UARCH_END else { printErr("Unknown microarchitecture detected: IM=0x%X P=0x%X V=0x%X R=0x%X", im, p, v, r); \
fprintf(stderr, "Please see https://github.com/Dr-Noob/cpufetch#61-unknown-microarchitecture-error to know how to report this error\n"); \
fill_uarch(arch, cpu, "Unknown", UARCH_UNKNOWN, CPU_VENDOR_UNKNOWN); }
#define UARCH_END else { printBug("Unknown microarchitecture detected: IM=0x%.8X P=0x%.8X V=0x%.8X R=0x%.8X", im, p, v, r); fill_uarch(arch, cpu, "Unknown", UARCH_UNKNOWN, CPU_VENDOR_UNKNOWN); }
void fill_uarch(struct uarch* arch, struct cpuInfo* cpu, char* str, MICROARCH u, VENDOR vendor) {
arch->uarch = u;
@@ -218,11 +191,10 @@ void fill_uarch(struct uarch* arch, struct cpuInfo* cpu, char* str, MICROARCH u,
/*
* Codes are based on pytorch/cpuinfo, more precisely:
* - https://github.com/pytorch/cpuinfo/blob/main/src/arm/uarch.c
* - https://github.com/pytorch/cpuinfo/blob/master/src/arm/uarch.c
* Other sources:
* - https://elixir.bootlin.com/linux/latest/source/arch/arm64/include/asm/cputype.h
* - https://elixir.bootlin.com/linux/latest/source/arch/arm/include/asm/cputype.h
* - https://github.com/AsahiLinux/m1n1/blob/main/src/chickens.c
*/
struct uarch* get_uarch_from_midr(uint32_t midr, struct cpuInfo* cpu) {
struct uarch* arch = emalloc(sizeof(struct uarch));
@@ -265,15 +237,9 @@ struct uarch* get_uarch_from_midr(uint32_t midr, struct cpuInfo* cpu) {
CHECK_UARCH(arch, cpu, 'A', 0xD0C, NA, NA, "Neoverse N1", UARCH_NEOVERSE_N1, CPU_VENDOR_ARM)
CHECK_UARCH(arch, cpu, 'A', 0xD0D, NA, NA, "Cortex-A77", UARCH_CORTEX_A77, CPU_VENDOR_ARM)
CHECK_UARCH(arch, cpu, 'A', 0xD0E, NA, NA, "Cortex-A76", UARCH_CORTEX_A76, CPU_VENDOR_ARM)
CHECK_UARCH(arch, cpu, 'A', 0xD40, NA, NA, "Neoverse V1", UARCH_NEOVERSE_V1, CPU_VENDOR_ARM)
CHECK_UARCH(arch, cpu, 'A', 0xD41, NA, NA, "Cortex-A78", UARCH_CORTEX_A78, CPU_VENDOR_ARM)
CHECK_UARCH(arch, cpu, 'A', 0xD44, NA, NA, "Cortex-X1", UARCH_CORTEX_X1, CPU_VENDOR_ARM)
CHECK_UARCH(arch, cpu, 'A', 0xD46, NA, NA, "Cortex‑A510", UARCH_CORTEX_A510, CPU_VENDOR_ARM)
CHECK_UARCH(arch, cpu, 'A', 0xD47, NA, NA, "Cortex‑A710", UARCH_CORTEX_A710, CPU_VENDOR_ARM)
CHECK_UARCH(arch, cpu, 'A', 0xD48, NA, NA, "Cortex-X2", UARCH_CORTEX_X2, CPU_VENDOR_ARM)
CHECK_UARCH(arch, cpu, 'A', 0xD4A, NA, NA, "Neoverse E1", UARCH_NEOVERSE_E1, CPU_VENDOR_ARM)
CHECK_UARCH(arch, cpu, 'A', 0xD4D, NA, NA, "Cortex-A715", UARCH_CORTEX_A715, CPU_VENDOR_ARM)
CHECK_UARCH(arch, cpu, 'A', 0xD4E, NA, NA, "Cortex-X3", UARCH_CORTEX_X3, CPU_VENDOR_ARM)
CHECK_UARCH(arch, cpu, 'B', 0x00F, NA, NA, "Brahma B15", UARCH_BRAHMA_B15, CPU_VENDOR_BROADCOM)
CHECK_UARCH(arch, cpu, 'B', 0x100, NA, NA, "Brahma B53", UARCH_BRAHMA_B53, CPU_VENDOR_BROADCOM)
@@ -323,15 +289,8 @@ struct uarch* get_uarch_from_midr(uint32_t midr, struct cpuInfo* cpu) {
CHECK_UARCH(arch, cpu, 'S', 0x003, 1, NA, "Exynos M4", UARCH_EXYNOS_M4, CPU_VENDOR_SAMSUNG) // Exynos 9820
CHECK_UARCH(arch, cpu, 'S', 0x004, 1, NA, "Exynos M5", UARCH_EXYNOS_M5, CPU_VENDOR_SAMSUNG) // Exynos 9820 (this one looks wrong at uarch.c ...)
CHECK_UARCH(arch, cpu, 'p', 0x663, 1, NA, "Xiaomi", UARCH_XIAOMI, CPU_VENDOR_PHYTIUM) // From a fellow contributor (https://github.com/Dr-Noob/cpufetch/issues/125)
// Also interesting: https://en.wikipedia.org/wiki/FeiTeng_(processor)
CHECK_UARCH(arch, cpu, 'a', 0x022, NA, NA, "Icestorm", UARCH_ICESTORM, CPU_VENDOR_APPLE)
CHECK_UARCH(arch, cpu, 'a', 0x023, NA, NA, "Firestorm", UARCH_FIRESTORM, CPU_VENDOR_APPLE)
CHECK_UARCH(arch, cpu, 'a', 0x030, NA, NA, "Blizzard", UARCH_BLIZZARD, CPU_VENDOR_APPLE)
CHECK_UARCH(arch, cpu, 'a', 0x031, NA, NA, "Avalanche", UARCH_AVALANCHE, CPU_VENDOR_APPLE)
CHECK_UARCH(arch, cpu, 'a', 0x048, NA, NA, "Sawtooth", UARCH_SAWTOOTH, CPU_VENDOR_APPLE)
CHECK_UARCH(arch, cpu, 'a', 0x049, NA, NA, "Everest", UARCH_EVEREST, CPU_VENDOR_APPLE)
CHECK_UARCH(arch, cpu, 'V', 0x581, NA, NA, "PJ4", UARCH_PJ4, CPU_VENDOR_MARVELL)
CHECK_UARCH(arch, cpu, 'V', 0x584, NA, NA, "PJ4B-MP", UARCH_PJ4, CPU_VENDOR_MARVELL)
@@ -341,99 +300,6 @@ struct uarch* get_uarch_from_midr(uint32_t midr, struct cpuInfo* cpu) {
return arch;
}
bool is_ARMv8_or_newer(struct cpuInfo* cpu) {
return cpu->arch->isa == ISA_ARMv8_A ||
cpu->arch->isa == ISA_ARMv8_A_AArch32 ||
cpu->arch->isa == ISA_ARMv8_1_A ||
cpu->arch->isa == ISA_ARMv8_2_A ||
cpu->arch->isa == ISA_ARMv8_3_A ||
cpu->arch->isa == ISA_ARMv8_4_A ||
cpu->arch->isa == ISA_ARMv8_5_A ||
cpu->arch->isa == ISA_ARMv9_A;
}
bool has_fma_support(struct cpuInfo* cpu) {
// Arm A64 Instruction Set Architecture
// https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions
return is_ARMv8_or_newer(cpu);
}
int get_vpus_width(struct cpuInfo* cpu) {
// If the CPU has NEON, width can be 64 or 128 [1].
// In >= ARMv8, NEON are 128 bits width [2]
// If the CPU has SVE/SVE2, width can be between 128-2048 [3],
// so we must check the exact width depending on
// the exact chip (Neoverse V1 uses 256b implementations.)
//
// [1] https://en.wikipedia.org/wiki/ARM_architecture_family#Advanced_SIMD_(Neon)
// [2] https://developer.arm.com/documentation/102474/0100/Fundamentals-of-Armv8-Neon-technology
// [3] https://www.anandtech.com/show/16640/arm-announces-neoverse-v1-n2-platforms-cpus-cmn700-mesh/5
MICROARCH ua = cpu->arch->uarch;
switch(ua) {
case UARCH_NEOVERSE_V1:
return 256;
default:
if(cpu->feat->NEON) {
if(is_ARMv8_or_newer(cpu)) {
return 128;
}
else {
return 64;
}
}
else {
return 32;
}
}
}
int get_number_of_vpus(struct cpuInfo* cpu) {
MICROARCH ua = cpu->arch->uarch;
switch(ua) {
case UARCH_EVEREST: // Just a guess, needs confirmation.
case UARCH_FIRESTORM: // [https://dougallj.github.io/applecpu/firestorm-simd.html]
case UARCH_AVALANCHE: // [https://en.wikipedia.org/wiki/Comparison_of_ARM_processors]
case UARCH_CORTEX_X1: // [https://www.anandtech.com/show/15813/arm-cortex-a78-cortex-x1-cpu-ip-diverging/3]
case UARCH_CORTEX_X2: // [https://www.anandtech.com/show/16693/arm-announces-mobile-armv9-cpu-microarchitectures-cortexx2-cortexa710-cortexa510/2]
case UARCH_CORTEX_X3: // [https://www.hwcooling.net/en/cortex-x3-the-new-fastest-arm-core-architecture-analysis: "The FPU and SIMD unit of the core still has four pipelines"]
case UARCH_NEOVERSE_V1: // [https://en.wikichip.org/wiki/arm_holdings/microarchitectures/neoverse_v1]
return 4;
case UARCH_SAWTOOTH: // Needs confirmation, rn this is the best we know: https://mastodon.social/@dougall/111118317031041336
case UARCH_EXYNOS_M3: // [https://www.anandtech.com/show/12361/samsung-exynos-m3-architecture]
case UARCH_EXYNOS_M4: // [https://en.wikichip.org/wiki/samsung/microarchitectures/m4#Block_Diagram]
case UARCH_EXYNOS_M5: // [https://en.wikichip.org/wiki/samsung/microarchitectures/m5]
return 3;
case UARCH_ICESTORM: // [https://dougallj.github.io/applecpu/icestorm-simd.html]
case UARCH_BLIZZARD: // [https://en.wikipedia.org/wiki/Comparison_of_ARM_processors]
case UARCH_CORTEX_A57: // [https://www.anandtech.com/show/8718/the-samsung-galaxy-note-4-exynos-review/5]
case UARCH_CORTEX_A72: // [https://www.anandtech.com/show/10347/arm-cortex-a73-artemis-unveiled/2]
case UARCH_CORTEX_A73: // [https://www.anandtech.com/show/10347/arm-cortex-a73-artemis-unveiled/2]
case UARCH_CORTEX_A75: // [https://www.anandtech.com/show/11441/dynamiq-and-arms-new-cpus-cortex-a75-a55/3]
case UARCH_CORTEX_A76: // [https://www.anandtech.com/show/12785/arm-cortex-a76-cpu-unveiled-7nm-powerhouse/3]
case UARCH_CORTEX_A77: // [https://fuse.wikichip.org/news/2339/arm-unveils-cortex-a77-emphasizes-single-thread-performance]
case UARCH_CORTEX_A78: // [https://fuse.wikichip.org/news/3536/arm-unveils-the-cortex-a78-when-less-is-more]
case UARCH_EXYNOS_M1: // [https://www.anandtech.com/show/12361/samsung-exynos-m3-architecture]
case UARCH_EXYNOS_M2: // [https://www.anandtech.com/show/12361/samsung-exynos-m3-architecture]
case UARCH_NEOVERSE_N1: // [https://en.wikichip.org/wiki/arm_holdings/microarchitectures/neoverse_n1#Individual_Core]
case UARCH_CORTEX_A710: // [https://chipsandcheese.com/2023/08/11/arms-cortex-a710-winning-by-default/]: Fig in Core Overview. Table in Instruction Scheduling and Execution
case UARCH_CORTEX_A715: // [https://www.hwcooling.net/en/arm-introduces-new-cortex-a715-core-architecture-analysis/]: "the numbers of ALU and FPU execution units themselves >
return 2;
case UARCH_NEOVERSE_E1: // [https://www.anandtech.com/show/13959/arm-announces-neoverse-n1-platform/5]
// A510 is integrated as part of a Complex. Normally, each complex would incorporate two Cortex-A510 cores.
// Each complex incorporates a single VPU with 2 ports, so for each A510 there is theoretically 1 port.
case UARCH_CORTEX_A510: // [https://en.wikichip.org/wiki/arm_holdings/microarchitectures/cortex-a510#Vector_Processing_Unit_.28VPU.29]
return 1;
default:
// ARMv6
// ARMv7
// Remaining UARCH_CORTEX_AXX
// Old Snapdragon (e.g., Scorpion, Krait, etc)
return 1;
}
}
char* get_str_uarch(struct cpuInfo* cpu) {
return cpu->arch->uarch_str;
}

3
src/arm/uarch.h
View File

@@ -6,9 +6,6 @@
#include "midr.h"
struct uarch* get_uarch_from_midr(uint32_t midr, struct cpuInfo* cpu);
int get_number_of_vpus(struct cpuInfo* cpu);
int get_vpus_width(struct cpuInfo* cpu);
bool has_fma_support(struct cpuInfo* cpu);
char* get_str_uarch(struct cpuInfo* cpu);
void free_uarch_struct(struct uarch* arch);

29
src/arm/udev.c
View File

@@ -3,6 +3,8 @@
#include "midr.h"
#define _PATH_DEVICETREE_MODEL "/sys/firmware/devicetree/base/model"
#define _PATH_CPUINFO "/proc/cpuinfo"
//#define _PATH_CPUINFO "cpuinfo_debug"
#define CPUINFO_CPU_IMPLEMENTER_STR "CPU implementer\t: "
#define CPUINFO_CPU_ARCHITECTURE_STR "CPU architecture: "
@@ -106,15 +108,36 @@ uint32_t get_midr_from_cpuinfo(uint32_t core, bool* success) {
return midr;
}
char* get_hardware_from_cpuinfo(void) {
char* get_field_from_cpuinfo(char* CPUINFO_FIELD) {
int filelen;
char* buf;
if((buf = read_file(_PATH_CPUINFO, &filelen)) == NULL) {
printWarn("read_file: %s: %s:\n", _PATH_CPUINFO, strerror(errno));
return NULL;
}
char* tmp1 = strstr(buf, CPUINFO_FIELD);
if(tmp1 == NULL) return NULL;
tmp1 = tmp1 + strlen(CPUINFO_FIELD);
char* tmp2 = strstr(tmp1, "\n");
int strlen = (1 + (tmp2-tmp1));
char* hardware = emalloc(sizeof(char) * strlen);
memset(hardware, 0, sizeof(char) * strlen);
strncpy(hardware, tmp1, tmp2-tmp1);
return hardware;
}
char* get_hardware_from_cpuinfo() {
return get_field_from_cpuinfo(CPUINFO_HARDWARE_STR);
}
char* get_revision_from_cpuinfo(void) {
char* get_revision_from_cpuinfo() {
return get_field_from_cpuinfo(CPUINFO_REVISION_STR);
}
bool is_raspberry_pi(void) {
bool is_raspberry_pi() {
int filelen;
char* buf;
if((buf = read_file(_PATH_DEVICETREE_MODEL, &filelen)) == NULL) {

12
src/arm/udev.h
View File

@@ -3,16 +3,12 @@
#include "../common/udev.h"
#define _PATH_SUNXI_NVMEM "/sys/bus/nvmem/devices/sunxi-sid0/nvmem"
#define _PATH_RK_EFUSE0 "/sys/bus/nvmem/devices/rockchip-efuse0/nvmem"
#define _PATH_RK_OTP0 "/sys/bus/nvmem/devices/rockchip-otp0/nvmem"
#define UNKNOWN -1
int get_ncores_from_cpuinfo(void);
int get_ncores_from_cpuinfo();
uint32_t get_midr_from_cpuinfo(uint32_t core, bool* success);
char* get_hardware_from_cpuinfo(void);
char* get_revision_from_cpuinfo(void);
bool is_raspberry_pi(void);
char* get_hardware_from_cpuinfo();
char* get_revision_from_cpuinfo();
bool is_raspberry_pi();
#endif

34
src/common/args.c
View File

@@ -12,8 +12,6 @@
#define COLOR_STR_AMD "amd"
#define COLOR_STR_IBM "ibm"
#define COLOR_STR_ARM "arm"
#define COLOR_STR_ROCKCHIP "rockchip"
#define COLOR_STR_SIFIVE "sifive"
static const char *SYTLES_STR_LIST[] = {
[STYLE_EMPTY] = NULL,
@@ -73,59 +71,59 @@ const char *args_str[] = {
static struct args_struct args;
STYLE get_style(void) {
STYLE get_style() {
return args.style;
}
struct color** get_colors(void) {
struct color** get_colors() {
return args.colors;
}
bool show_help(void) {
bool show_help() {
return args.help_flag;
}
bool show_version(void) {
bool show_version() {
return args.version_flag;
}
bool show_debug(void) {
bool show_debug() {
return args.debug_flag;
}
bool show_raw(void) {
bool show_raw() {
return args.raw_flag;
}
bool accurate_pp(void) {
bool accurate_pp() {
return args.accurate_pp;
}
bool show_full_cpu_name(void) {
bool show_full_cpu_name() {
return args.full_cpu_name_flag;
}
bool show_logo_long(void) {
bool show_logo_long() {
return args.logo_long;
}
bool show_logo_short(void) {
bool show_logo_short() {
return args.logo_short;
}
bool show_logo_intel_new(void) {
bool show_logo_intel_new() {
return args.logo_intel_new;
}
bool show_logo_intel_old(void) {
bool show_logo_intel_old() {
return args.logo_intel_old;
}
bool verbose_enabled(void) {
bool verbose_enabled() {
return args.verbose_flag;
}
int max_arg_str_length(void) {
int max_arg_str_length() {
int max_len = -1;
int len = sizeof(args_str) / sizeof(args_str[0]);
for(int i=0; i < len; i++) {
@@ -170,8 +168,6 @@ bool parse_color(char* optarg_str, struct color*** cs) {
else if(strcmp(optarg_str, COLOR_STR_AMD) == 0) color_to_copy = COLOR_DEFAULT_AMD;
else if(strcmp(optarg_str, COLOR_STR_IBM) == 0) color_to_copy = COLOR_DEFAULT_IBM;
else if(strcmp(optarg_str, COLOR_STR_ARM) == 0) color_to_copy = COLOR_DEFAULT_ARM;
else if(strcmp(optarg_str, COLOR_STR_ROCKCHIP) == 0) color_to_copy = COLOR_DEFAULT_ROCKCHIP;
else if(strcmp(optarg_str, COLOR_STR_SIFIVE) == 0) color_to_copy = COLOR_DEFAULT_SIFIVE;
else {
str_to_parse = optarg_str;
free_ptr = false;
@@ -215,7 +211,7 @@ bool parse_color(char* optarg_str, struct color*** cs) {
return true;
}
char* build_short_options(void) {
char* build_short_options() {
const char *c = args_chr;
int len = sizeof(args_chr) / sizeof(args_chr[0]);
char* str = (char *) emalloc(sizeof(char) * (len*2 + 1));

28
src/common/args.h
View File

@@ -39,21 +39,21 @@ extern const char *args_str[];
#include "printer.h"
int max_arg_str_length(void);
int max_arg_str_length();
bool parse_args(int argc, char* argv[]);
bool show_help(void);
bool accurate_pp(void);
bool show_full_cpu_name(void);
bool show_logo_long(void);
bool show_logo_short(void);
bool show_logo_intel_new(void);
bool show_logo_intel_old(void);
bool show_raw(void);
bool show_debug(void);
bool show_version(void);
bool verbose_enabled(void);
bool show_help();
bool accurate_pp();
bool show_full_cpu_name();
bool show_logo_long();
bool show_logo_short();
bool show_logo_intel_new();
bool show_logo_intel_old();
bool show_raw();
bool show_debug();
bool show_version();
bool verbose_enabled();
void free_colors_struct(struct color** cs);
struct color** get_colors(void);
STYLE get_style(void);
struct color** get_colors();
STYLE get_style();
#endif

178
src/common/ascii.h
View File

@@ -218,23 +218,6 @@ $C1 kMMMMMMMMMMMMMMMMMMMMMMd \
$C1 'KMMMMMMMWXXWMMMMMMMk. \
$C1 \"cooc\"* \"*coo'\" "
#define ASCII_GOOGLE \
"$C1 aaaaaaaa \
$C1 .MMMMMMMMMMMMMMMM. \
$C1 .MMMMMMMMMMMMMMMMMMMMM* \
$C1 .MMMMMMMM** *MM* \
$C2 MM$C1MMMMM. \
$C2 *MMM$C1MM. \
$C2*MMMMMM $C4lMMMMMMMMMMMMMMM* \
$C2MMMMMMM $C4lMMMMMMMMMMMMMMMM \
$C2*MMMMMM $C4lMMMMMMMMMMMMMMMd \
$C2 MMMM$C3MMM. $C4*MMMMM. \
$C2 MM$C3MMMMMM. $C4.MMMMMM. \
$C3 *MMMMMMMMM*.......MMM$C4MMMMMM* \
$C3 *MMMMMMMMMMMMMMMMMMMM$C4MM* \
$C3 *MMMMMMMMMMMMMM* \
$C3 ****** "
#define ASCII_ALLWINNER \
"$C1 \
$C1 ################# \
@@ -253,93 +236,21 @@ $C1 ##### ##. \
$C1 ###########. \
$C1 "
#define ASCII_ROCKCHIP \
#define ASCII_GOOGLE \
"$C1 \
$C1 $C2## \
$C1 ###### ## ## \
$C1 ##. ### ##### ##### ## .## ##### ######. ## ##### \
$C1 #######. ##. # #. ##### ##. ### ### # .## \
$C1##. ###. ####. #### ### .## #### ### ### #.##### \
$C1 ## \
$C1 "
#define ASCII_RISCV \
"$C1 \
$C1 ************ \
$C1 %%%%%%%%% *********** \
$C1 %%%%%%%%%% ********** \
$C1 %%%%%%%%% ********* \
$C1 % ******** \
$C1 %% .********* % \
$C1 %%%% ******* %%% \
$C1 %%%%%%. **** %%%%% \
$C1 %%%%%%%%. %%%%%%% \
$C1 \
$C1 \
$C1 ########### ## .######### ######### .## ## \
$C1 ## ## ## ## ## ### ### \
$C1 ########### ## ##########. ## #### .## ## \
$C1 ## ### ## ##. ## ### ### \
$C1 ## ### ## ##########. ########## ### \
$C1 "
#define ASCII_SIFIVE \
"$C1 ############################################## \
$C1 ###########@@@@@@@@@@@@@@@@@@@@@@@@########### \
$C1 #########@@@@@@@@@@@@@@@@@@@@@@@@@@@@######### \
$C1 ########@@@@######################@@@@######## \
$C1 #######@@@@########################@@@@####### \
$C1 ######@@@@##########################@@@@###### \
$C1 #####@@@@#######@@@@@@@@@@@@@@@@@@@@@@@@@##### \
$C1 ####@@@@#######@@@@@@@@@@@@@@@@@@@@@@@@@@@#### \
$C1 ###@@@@################################@@@@### \
$C1 ##@@@@##################################@@@@## \
$C1 #@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@#########@@@@# \
$C1 #@@@@@@@@@@@@@@@@@@@@@@@@@@@@@###########@@@@# \
$C1 ##@@@@@@############@@@@@@############@@@@@@## \
$C1 ######@@@@@###########@@###########@@@@@###### \
$C1 #########@@@@@@################@@@@@@######### \
$C1 #############@@@@@##########@@@@@############# \
$C1 ################@@@@@@##@@@@@@################ \
$C1 ####################@@@@@@#################### \
$C1 ############################################## "
#define ASCII_STARFIVE \
"$C1 # \
$C1 ########## \
$C1 ######## ######## \
$C1 ############ \
$C1 ####### #### \
$C1 #### ####### \
$C1 #### ##### ####### \
$C1 ####### ######## .## \
$C1 ######## ######## \
$C1 ### ########. ####### \
$C1 ####### ##### #### \
$C1 ######## #. #### \
$C1 # #### ####### \
$C1 ##### ####### \
$C1 ######## ######## \
$C1 ######### \
$C1 # "
#define ASCII_SIPEED \
"$C1 #################################### \
$C1######@@################################ \
$C1####@@##@@####@@@@@@@@@@@@@@@@########## \
$C1######@@####@@@@@@@@@@@@@@@@@@########## \
$C1#########@@@@########################### \
$C1#######@@@@@@########################### \
$C1#########@@@@########################### \
$C1###########@@@@@@@@@@@@@@@############## \
$C1##############@@@@@@@@@@@@@@@########### \
$C1###########################@@@@@######## \
$C1###########################@@@@@@####### \
$C1###########################@@@@@######## \
$C1##########@@@@@@@@@@@@@@@@@@@########### \
$C1##########@@@@@@@@@@@@@@@@############## \
$C1######################################## \
$C1 #################################### "
$C1 ################### \
$C1 ##################### \
$C1 ######## \
$C2 ###$C1#### \
$C2 #######$C3 ############## \
$C2 #######$C3 ############## \
$C2 #######$C3 ############## \
$C2 ###$C4####$C3 ####### \
$C4 ######## $C3######## \
$C4 #################$C3####### \
$C4 ###############$C3#### \
$C4 ########### "
// --------------------- LONG LOGOS ------------------------- //
#define ASCII_AMD_L \
@@ -425,59 +336,11 @@ $C1 ############ ################## ######### #### ######### \
$C1 \
$C1 ############ ################ ######### ## ######### "
#define ASCII_SIFIVE_L \
"$C1 ################################################### \
$C1 ###########@@@@@@@@@@@@@@@@@@@@@@@@@@@@############ \
$C1 ##########@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@########### \
$C1 #########@@@@@#######################@@@@########## \
$C1 ########@@@@@#########################@@@@######### \
$C1 #######@@@@@###########################@@@@######## \
$C1 ######@@@@@########@@@@@@@@@@@@@@@@@@@@@@@@@####### \
$C1 #####@@@@@########@@@@@@@@@@@@@@@@@@@@@@@@@@@###### \
$C1 ####@@@@@################################@@@@@##### \
$C1 ###@@@@@##################################@@@@@#### \
$C1 ##@@@@@####################################@@@@@### \
$C1 ##@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@#########@@@@### \
$C1 ##@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@############@@@@### \
$C1 ####@@@@@#############@@@@@@@############@@@@@##### \
$C1 #######@@@@@@############@############@@@@@@####### \
$C1 ##########@@@@@@###################@@@@@@########## \
$C1 ##############@@@@@@###########@@@@@@############## \
$C1 #################@@@@@@#####@@@@@@################# \
$C1 ####################@@@@@@@@@@@#################### \
$C1 ########################@@@######################## \
$C1 ################################################### "
#define ASCII_STARFIVE_L \
"$C1 ####### \
$C1 ################. \
$C1 ############ ########### \
$C1 ############ ##########. \
$C1 ############ # ###### \
$C1 ########### ##### ## \
$C1 #######. ########## \
$C1 ###### ### *########### \
$C1 ###### #######. ########## \
$C1 ######### ############ ###### \
$C1 ###########. ###########* # \
$C1 ############ ############ \
$C1 # ############. .########### \
$C1 ###### ########### ######### \
$C1 ########## .######, ##### \
$C1 ############ ##. #####. \
$C1 ######### ######## \
$C1 ## ##### ##########. \
$C1 ####### # ############ \
$C1 ########### ###########. \
$C1 ###########. ############ \
$C1 ################ \
$C1 ####### "
typedef struct ascii_logo asciiL;
// +-----------------------------------------------------------------------------------------------------------------+
// ------------------------------------------------------------------------------------------------------------------+
// | LOGO | W | H | REPLACE | COLORS LOGO (>0 && <10) | COLORS TEXT (=2) |
// +-----------------------------------------------------------------------------------------------------------------+
// ------------------------------------------------------------------------------------------------------------------+
asciiL logo_amd = { ASCII_AMD, 39, 15, false, {C_FG_WHITE, C_FG_GREEN}, {C_FG_WHITE, C_FG_GREEN} };
asciiL logo_intel = { ASCII_INTEL, 48, 14, false, {C_FG_CYAN}, {C_FG_CYAN, C_FG_WHITE} };
asciiL logo_intel_new = { ASCII_INTEL_NEW, 51, 9, false, {C_FG_CYAN}, {C_FG_CYAN, C_FG_WHITE} };
@@ -489,22 +352,15 @@ asciiL logo_broadcom = { ASCII_BROADCOM, 44, 19, false, {C_FG_WHITE, C_FG_
asciiL logo_arm = { ASCII_ARM, 42, 5, false, {C_FG_CYAN}, {C_FG_WHITE, C_FG_CYAN} };
asciiL logo_ibm = { ASCII_IBM, 42, 9, false, {C_FG_CYAN, C_FG_WHITE}, {C_FG_CYAN, C_FG_WHITE} };
asciiL logo_apple = { ASCII_APPLE, 32, 17, false, {C_FG_WHITE}, {C_FG_CYAN, C_FG_B_WHITE} };
asciiL logo_google = { ASCII_GOOGLE, 35, 15, false, {C_FG_RED, C_FG_YELLOW, C_FG_GREEN, C_FG_BLUE}, {C_FG_BLUE, C_FG_B_WHITE} };
asciiL logo_allwinner = { ASCII_ALLWINNER, 47, 16, false, {C_FG_CYAN}, {C_FG_B_BLACK, C_FG_B_CYAN } };
asciiL logo_rockchip = { ASCII_ROCKCHIP, 58, 8, false, {C_FG_CYAN, C_FG_YELLOW}, {C_FG_CYAN, C_FG_YELLOW} };
asciiL logo_riscv = { ASCII_RISCV, 63, 18, false, {C_FG_CYAN, C_FG_YELLOW}, {C_FG_CYAN, C_FG_YELLOW} };
asciiL logo_sifive = { ASCII_SIFIVE, 48, 19, true, {C_BG_WHITE, C_BG_BLACK}, {C_FG_WHITE, C_FG_BLUE} };
asciiL logo_starfive = { ASCII_STARFIVE, 33, 17, false, {C_FG_WHITE}, {C_FG_WHITE, C_FG_BLUE} };
asciiL logo_sipeed = { ASCII_SIPEED, 41, 16, true, {C_BG_RED, C_BG_WHITE}, {C_FG_RED, C_FG_WHITE} };
asciiL logo_google = { ASCII_GOOGLE, 34, 14, false, {C_FG_RED, C_FG_YELLOW, C_FG_BLUE, C_FG_GREEN}, {C_FG_BLUE} };
// Long variants | ----------------------------------------------------------------------------------------------------------------|
// Long variants | ---------------------------------------------------------------------------------------------------------------|
asciiL logo_amd_l = { ASCII_AMD_L, 62, 19, true, {C_BG_WHITE, C_BG_GREEN}, {C_FG_WHITE, C_FG_GREEN} };
asciiL logo_intel_l = { ASCII_INTEL_L, 62, 19, true, {C_BG_CYAN, C_BG_WHITE}, {C_FG_CYAN, C_FG_WHITE} };
asciiL logo_intel_l_new = { ASCII_INTEL_L_NEW, 57, 14, true, {C_BG_CYAN, C_BG_WHITE, C_BG_BLUE}, {C_FG_CYAN, C_FG_WHITE} };
asciiL logo_arm_l = { ASCII_ARM_L, 60, 8, true, {C_BG_CYAN}, {C_FG_WHITE, C_FG_CYAN} };
asciiL logo_ibm_l = { ASCII_IBM_L, 62, 13, true, {C_BG_CYAN, C_FG_WHITE}, {C_FG_CYAN, C_FG_WHITE} };
asciiL logo_starfive_l = { ASCII_STARFIVE_L, 50, 22, false, {C_FG_WHITE}, {C_FG_WHITE, C_FG_BLUE} };
asciiL logo_sifive_l = { ASCII_SIFIVE_L, 53, 21, true, {C_BG_WHITE, C_BG_BLACK}, {C_FG_WHITE, C_FG_CYAN} };
asciiL logo_unknown = { NULL, 0, 0, false, {COLOR_NONE}, {COLOR_NONE, COLOR_NONE} };
#endif

6
src/common/cpu.c
View File

@@ -14,10 +14,10 @@
#include "../ppc/uarch.h"
#elif ARCH_ARM
#include "../arm/uarch.h"
#elif ARCH_RISCV
#include "../riscv/uarch.h"
#endif
#define UNUSED(x) (void)(x)
#define STRING_YES "Yes"
#define STRING_NO "No"
#define STRING_NONE "None"
@@ -194,7 +194,7 @@ void init_topology_struct(struct topology* topo, struct cache* cach) {
topo->sockets = 0;
#ifdef ARCH_X86
topo->smt_available = 0;
topo->apic = ecalloc(1, sizeof(struct apic));
topo->apic = emalloc(sizeof(struct apic));
#endif
#endif
}

42
src/common/cpu.h
View File

@@ -19,11 +19,6 @@ enum {
CPU_VENDOR_HUAWUEI,
CPU_VENDOR_SAMSUNG,
CPU_VENDOR_MARVELL,
CPU_VENDOR_PHYTIUM,
// ARCH_RISCV
CPU_VENDOR_RISCV,
CPU_VENDOR_SIFIVE,
CPU_VENDOR_THEAD,
// OTHERS
CPU_VENDOR_UNKNOWN,
CPU_VENDOR_INVALID
@@ -36,18 +31,9 @@ enum {
HV_VENDOR_VMWARE,
HV_VENDOR_XEN,
HV_VENDOR_PARALLELS,
HV_VENDOR_PHYP,
HV_VENDOR_BHYVE,
HV_VENDOR_APPLEVZ,
HV_VENDOR_INVALID
};
enum {
CORE_TYPE_EFFICIENCY,
CORE_TYPE_PERFORMANCE,
CORE_TYPE_UNKNOWN
};
#define UNKNOWN_DATA -1
#define CPU_NAME_MAX_LENGTH 64
@@ -91,7 +77,6 @@ struct topology {
uint32_t smt_supported; // Number of SMT that CPU supports (equal to smt_available if SMT is enabled)
#ifdef ARCH_X86
uint32_t smt_available; // Number of SMT that is currently enabled
int32_t total_cores_module; // Total cores in the current module (only makes sense in hybrid archs, like ADL)
struct apic* apic;
#endif
#endif
@@ -123,11 +108,6 @@ struct features {
#endif
};
struct extensions {
char* str;
uint64_t mask;
};
struct cpuInfo {
VENDOR cpu_vendor;
struct uarch* arch;
@@ -135,15 +115,8 @@ struct cpuInfo {
struct frequency* freq;
struct cache* cach;
struct topology* topo;
int64_t peak_performance;
// Similar but not exactly equal
// to struct features
#ifdef ARCH_RISCV
struct extensions* ext;
#else
struct features* feat;
#endif
int64_t peak_performance;
#if defined(ARCH_X86) || defined(ARCH_PPC)
// CPU name from model
@@ -157,10 +130,6 @@ struct cpuInfo {
uint32_t maxExtendedLevels;
// Topology Extensions (AMD only)
bool topology_extensions;
// Hybrid Flag (Intel only)
bool hybrid_flag;
// Core Type (P/E)
uint32_t core_type;
#elif ARCH_PPC
uint32_t pvr;
#elif ARCH_ARM
@@ -168,20 +137,13 @@ struct cpuInfo {
uint32_t midr;
#endif
#if defined(ARCH_ARM) || defined(ARCH_RISCV)
#ifdef ARCH_ARM
struct system_on_chip* soc;
#endif
#if defined(ARCH_X86) || defined(ARCH_ARM)
// If SoC contains more than one CPU and they
// are different, the others will be stored in
// the next_cpu field
struct cpuInfo* next_cpu;
uint8_t num_cpus;
#ifdef ARCH_X86
// The index of the first core in the module
uint32_t first_core_id;
#endif
#endif
};

59
src/common/global.c
View File

@@ -20,40 +20,6 @@
#endif
#ifdef ARCH_X86
static const char* ARCH_STR = "x86 / x86_64 build";
#include "../x86/cpuid.h"
#elif ARCH_PPC
static const char* ARCH_STR = "PowerPC build";
#include "../ppc/ppc.h"
#elif ARCH_ARM
static const char* ARCH_STR = "ARM build";
#include "../arm/midr.h"
#elif ARCH_RISCV
static const char* ARCH_STR = "RISC-V build";
#include "../riscv/riscv.h"
#endif
#ifdef __linux__
#ifdef __ANDROID__
static const char* OS_STR = "Android";
#else
static const char* OS_STR = "Linux";
#endif
#elif __FreeBSD__
static const char* OS_STR = "FreeBSD";
#elif _WIN32
static const char* OS_STR = "Windows";
#elif defined __APPLE__ || __MACH__
static const char* OS_STR = "macOS";
#else
static const char* OS_STR = "Unknown OS";
#endif
#ifndef GIT_FULL_VERSION
static const char* VERSION = "1.04";
#endif
enum {
LOG_LEVEL_NORMAL,
LOG_LEVEL_VERBOSE
@@ -81,8 +47,6 @@ void printErr(const char *fmt, ...) {
vsnprintf(buffer,buffer_size, fmt, args);
va_end(args);
fprintf(stderr,RED "[ERROR]: "RESET "%s\n",buffer);
fprintf(stderr,"[VERSION]: ");
print_version(stderr);
}
void printBug(const char *fmt, ...) {
@@ -93,12 +57,10 @@ void printBug(const char *fmt, ...) {
vsnprintf(buffer,buffer_size, fmt, args);
va_end(args);
fprintf(stderr,RED "[ERROR]: "RESET "%s\n",buffer);
fprintf(stderr,"[VERSION]: ");
print_version(stderr);
#if defined(ARCH_X86) || defined(ARCH_PPC)
fprintf(stderr, "Please, create a new issue with this error message, the output of 'cpufetch' and 'cpufetch --debug' on https://github.com/Dr-Noob/cpufetch/issues\n");
#elif ARCH_ARM
fprintf(stderr, "Please, create a new issue with this error message, your smartphone/computer model, the output of 'cpufetch --verbose' and 'cpufetch --debug' on https://github.com/Dr-Noob/cpufetch/issues\n");
fprintf(stderr, "Please, create a new issue with this error message, your smartphone/computer model, the output of 'cpufetch' and 'cpufetch --debug' on https://github.com/Dr-Noob/cpufetch/issues\n");
#endif
}
@@ -149,22 +111,3 @@ void* ecalloc(size_t nmemb, size_t size) {
return ptr;
}
void* erealloc(void *ptr, size_t size) {
void* newptr = realloc(ptr, size);
if(newptr == NULL) {
printErr("realloc failed: %s", strerror(errno));
exit(1);
}
return newptr;
}
void print_version(FILE *restrict stream) {
#ifdef GIT_FULL_VERSION
fprintf(stream, "cpufetch %s (%s %s)\n", GIT_FULL_VERSION, OS_STR, ARCH_STR);
#else
fprintf(stream, "cpufetch v%s (%s %s)\n", VERSION, OS_STR, ARCH_STR);
#endif
}

4
src/common/global.h
View File

@@ -1,12 +1,10 @@
#ifndef __GLOBAL__
#define __GLOBAL__
#include <stdio.h>
#include <stdbool.h>
#include <stddef.h>
#define STRING_UNKNOWN "Unknown"
#define UNUSED(x) (void)(x)
void set_log_level(bool verbose);
void printWarn(const char *fmt, ...);
@@ -17,7 +15,5 @@ int max(int a, int b);
char *strremove(char *str, const char *sub);
void* emalloc(size_t size);
void* ecalloc(size_t nmemb, size_t size);
void* erealloc(void *ptr, size_t size);
void print_version(FILE *restrict stream);
#endif

62
src/common/main.c
View File

@@ -6,6 +6,35 @@
#include "printer.h"
#include "global.h"
#ifdef ARCH_X86
static const char* ARCH_STR = "x86_64 build";
#include "../x86/cpuid.h"
#elif ARCH_PPC
static const char* ARCH_STR = "PowerPC build";
#include "../ppc/ppc.h"
#elif ARCH_ARM
static const char* ARCH_STR = "ARM build";
#include "../arm/midr.h"
#endif
#ifdef __linux__
#ifdef __ANDROID__
static const char* OS_STR = "Android";
#else
static const char* OS_STR = "Linux";
#endif
#elif __FreeBSD__
static const char* OS_STR = "FreeBSD";
#elif _WIN32
static const char* OS_STR = "Windows";
#elif defined __APPLE__ || __MACH__
static const char* OS_STR = "macOS";
#else
static const char* OS_STR = "Unknown OS";
#endif
static const char* VERSION = "1.01";
void print_help(char *argv[]) {
const char **t = args_str;
const char *c = args_chr;
@@ -40,13 +69,10 @@ void print_help(char *argv[]) {
printf(" -%c, --%s %*s Print cpufetch version and exit\n", c[ARG_VERSION], t[ARG_VERSION], (int) (max_len-strlen(t[ARG_VERSION])), "");
printf("\nCOLORS: \n");
printf(" * \"intel\": Use Intel color scheme \n");
printf(" * \"intel-new\": Use Intel (new logo) color scheme \n");
printf(" * \"amd\": Use AMD color scheme \n");
printf(" * \"ibm\", Use IBM color scheme \n");
printf(" * \"arm\": Use ARM color scheme \n");
printf(" * \"rockchip\": Use ARM color scheme \n");
printf(" * \"sifive\": Use SiFive color scheme \n");
printf(" * \"intel\": Use Intel default color scheme \n");
printf(" * \"amd\": Use AMD default color scheme \n");
printf(" * \"ibm\", Use IBM default color scheme \n");
printf(" * \"arm\": Use ARM default color scheme \n");
printf(" * custom: If the argument of --color does not match any of the previous strings, a custom scheme can be specified.\n");
printf(" 5 colors must be given in RGB with the format: R,G,B:R,G,B:...\n");
printf(" The first 3 colors are the CPU art color and the next 2 colors are the text colors\n");
@@ -76,10 +102,12 @@ void print_help(char *argv[]) {
printf("\nNOTE: \n");
printf(" Peak performance information is NOT accurate. cpufetch computes peak performance using the max\n");
printf(" frequency of the CPU. However, to compute the peak performance, you need to know the frequency of the\n");
printf(" CPU running AVX code. By default, this value is not fetched by cpufetch, but you can use the\n");
printf(" --accurate-pp option, which will measure the AVX frequency and show a more precise estimation\n");
printf(" (this option is only available in x86 architectures).\n");
printf(" To precisely measure peak performance, see: https://github.com/Dr-Noob/peakperf\n");
printf(" CPU running AVX code. This value is not be fetched by cpufetch since it depends on each specific CPU.\n");
printf(" To correctly measure peak performance, see: https://github.com/Dr-Noob/peakperf\n");
}
void print_version() {
printf("cpufetch v%s (%s %s)\n",VERSION, OS_STR, ARCH_STR);
}
int main(int argc, char* argv[]) {
@@ -92,7 +120,7 @@ int main(int argc, char* argv[]) {
}
if(show_version()) {
print_version(stdout);
print_version();
return EXIT_SUCCESS;
}
@@ -103,7 +131,7 @@ int main(int argc, char* argv[]) {
return EXIT_FAILURE;
if(show_debug()) {
print_version(stdout);
print_version();
print_debug(cpu);
return EXIT_SUCCESS;
}
@@ -111,7 +139,7 @@ int main(int argc, char* argv[]) {
// TODO: This should be moved to the end of args.c
if(show_raw()) {
#ifdef ARCH_X86
print_version(stdout);
print_version();
print_raw(cpu);
return EXIT_SUCCESS;
#else
@@ -120,10 +148,8 @@ int main(int argc, char* argv[]) {
#endif
}
if(print_cpufetch(cpu, get_style(), get_colors(), show_full_cpu_name())) {
if(print_cpufetch(cpu, get_style(), get_colors(), show_full_cpu_name()))
return EXIT_SUCCESS;
}
else {
else
return EXIT_FAILURE;
}
}

292
src/common/printer.c
View File

@@ -16,15 +16,10 @@
#elif ARCH_PPC
#include "../ppc/uarch.h"
#include "../ppc/ppc.h"
#elif ARCH_ARM
#else
#include "../arm/uarch.h"
#include "../arm/midr.h"
#include "../arm/soc.h"
#include "../common/soc.h"
#elif ARCH_RISCV
#include "../riscv/riscv.h"
#include "../riscv/uarch.h"
#include "../riscv/soc.h"
#endif
#ifdef _WIN32
@@ -47,10 +42,8 @@
enum {
#if defined(ARCH_X86) || defined(ARCH_PPC)
ATTRIBUTE_NAME,
#elif defined(ARCH_ARM) || defined(ARCH_RISCV)
#elif ARCH_ARM
ATTRIBUTE_SOC,
#endif
#if defined(ARCH_X86) || defined(ARCH_ARM)
ATTRIBUTE_CPU_NUM,
#endif
ATTRIBUTE_HYPERVISOR,
@@ -67,8 +60,6 @@ enum {
ATTRIBUTE_ALTIVEC,
#elif ARCH_ARM
ATTRIBUTE_FEATURES,
#elif ARCH_RISCV
ATTRIBUTE_EXTENSIONS,
#endif
ATTRIBUTE_L1i,
ATTRIBUTE_L1d,
@@ -82,10 +73,8 @@ static const char* ATTRIBUTE_FIELDS [] = {
"Name:",
#elif ARCH_PPC
"Part Number:",
#elif defined(ARCH_ARM) || defined(ARCH_RISCV)
#elif ARCH_ARM
"SoC:",
#endif
#if defined(ARCH_X86) || defined(ARCH_ARM)
"",
#endif
"Hypervisor:",
@@ -102,8 +91,6 @@ static const char* ATTRIBUTE_FIELDS [] = {
"Altivec: ",
#elif defined(ARCH_ARM)
"Features: ",
#elif defined(ARCH_RISCV)
"Extensions: ",
#endif
"L1i Size:",
"L1d Size:",
@@ -119,8 +106,6 @@ static const char* ATTRIBUTE_FIELDS_SHORT [] = {
"P/N:",
#elif ARCH_ARM
"SoC:",
#endif
#if defined(ARCH_X86) || defined(ARCH_ARM)
"",
#endif
"Hypervisor:",
@@ -137,8 +122,6 @@ static const char* ATTRIBUTE_FIELDS_SHORT [] = {
"Altivec: ",
#elif defined(ARCH_ARM)
"Features: ",
#elif defined(ARCH_RISCV)
"Extensions: ",
#endif
"L1i Size:",
"L1d Size:",
@@ -314,6 +297,8 @@ bool ascii_fits_screen(int termw, struct ascii_logo logo, int lf) {
void replace_bgbyfg_color(struct ascii_logo* logo) {
// Replace background by foreground color
for(int i=0; i < 3; i++) {
if(logo->color_ascii[i] == NULL) break;
if(strcmp(logo->color_ascii[i], C_BG_BLACK) == 0) strcpy(logo->color_ascii[i], C_FG_BLACK);
else if(strcmp(logo->color_ascii[i], C_BG_RED) == 0) strcpy(logo->color_ascii[i], C_FG_RED);
else if(strcmp(logo->color_ascii[i], C_BG_GREEN) == 0) strcpy(logo->color_ascii[i], C_FG_GREEN);
@@ -368,26 +353,13 @@ void choose_ascii_art(struct ascii* art, struct color** cs, struct terminal* ter
art->art = &logo_broadcom;
else if(art->vendor == SOC_VENDOR_APPLE)
art->art = &logo_apple;
else if(art->vendor == SOC_VENDOR_GOOGLE)
art->art = &logo_google;
else if(art->vendor == SOC_VENDOR_ALLWINNER)
art->art = &logo_allwinner;
else if(art->vendor == SOC_VENDOR_ROCKCHIP)
art->art = &logo_rockchip;
else if(art->vendor == SOC_VENDOR_GOOGLE)
art->art = &logo_google;
else {
art->art = choose_ascii_art_aux(&logo_arm_l, &logo_arm, term, lf);
}
#elif ARCH_RISCV
if(art->vendor == SOC_VENDOR_SIFIVE)
art->art = choose_ascii_art_aux(&logo_sifive_l, &logo_sifive, term, lf);
else if(art->vendor == SOC_VENDOR_STARFIVE)
art->art = choose_ascii_art_aux(&logo_starfive_l, &logo_starfive, term, lf);
else if(art->vendor == SOC_VENDOR_ALLWINNER)
art->art = &logo_allwinner;
else if(art->vendor == SOC_VENDOR_SIPEED)
art->art = &logo_sipeed;
else
art->art = &logo_riscv;
#endif
// 2. Choose colors
@@ -454,12 +426,11 @@ uint32_t longest_field_length(struct ascii* art, int la) {
}
#if defined(ARCH_X86) || defined(ARCH_PPC)
void print_ascii_generic(struct ascii* art, uint32_t la, int32_t termw, const char** attribute_fields, bool hybrid_architecture) {
void print_ascii_generic(struct ascii* art, uint32_t la, int32_t termw, const char** attribute_fields) {
struct ascii_logo* logo = art->art;
int attr_to_print = 0;
int attr_type;
char* attr_value;
int32_t beg_space;
int32_t space_right;
int32_t space_up = ((int)logo->height - (int)art->n_attributes_set)/2;
int32_t space_down = (int)logo->height - (int)art->n_attributes_set - (int)space_up;
@@ -470,7 +441,6 @@ void print_ascii_generic(struct ascii* art, uint32_t la, int32_t termw, const ch
lbuf->buf = emalloc(sizeof(char) * LINE_BUFFER_SIZE);
lbuf->pos = 0;
lbuf->chars = 0;
bool add_space = false;
printf("\n");
for(int32_t n=0; n < iters; n++) {
@@ -505,28 +475,9 @@ void print_ascii_generic(struct ascii* art, uint32_t la, int32_t termw, const ch
attr_value = art->attributes[attr_to_print]->value;
attr_to_print++;
#ifdef ARCH_X86
if(attr_type == ATTRIBUTE_L3) {
add_space = false;
}
if(attr_type == ATTRIBUTE_CPU_NUM) {
printOut(lbuf, strlen(attr_value), "%s%s%s", logo->color_text[0], attr_value, art->reset);
add_space = true;
}
else {
#endif
beg_space = 0;
space_right = 2 + 1 + (la - strlen(attribute_fields[attr_type]));
if(hybrid_architecture && add_space) {
beg_space = 2;
space_right -= 2;
}
printOut(lbuf, beg_space + strlen(attribute_fields[attr_type]) + space_right + strlen(attr_value),
"%*s%s%s%s%*s%s%s%s", beg_space, "", logo->color_text[0], attribute_fields[attr_type], art->reset, space_right, "", logo->color_text[1], attr_value, art->reset);
#ifdef ARCH_X86
}
#endif
space_right = 1 + (la - strlen(attribute_fields[attr_type]));
printOut(lbuf, strlen(attribute_fields[attr_type]) + space_right + strlen(attr_value),
"%s%s%s%*s%s%s%s", logo->color_text[0], attribute_fields[attr_type], art->reset, space_right, "", logo->color_text[1], attr_value, art->reset);
}
printOutLine(lbuf, art, termw);
printf("\n");
@@ -552,56 +503,43 @@ bool print_cpufetch_x86(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
art->new_intel_logo = choose_new_intel_logo(cpu);
// Step 1. Retrieve attributes (if some structures are NULL, like topo
// or cache, do not try to retrieve them)
uint32_t socket_num = 1;
char* l1i, *l1d, *l2, *l3, *n_cores, *n_cores_dual, *sockets;
l1i = l1d = l2 = l3 = n_cores = n_cores_dual = sockets = NULL;
char* cpu_name = get_str_cpu_name(cpu, fcpuname);
char* uarch = get_str_uarch(cpu);
char* pp = get_str_peak_performance(cpu->peak_performance);
char* manufacturing_process = get_str_process(cpu);
bool hybrid_architecture = cpu->next_cpu != NULL;
char* max_frequency = get_str_freq(cpu->freq);
char* cpu_name = get_str_cpu_name(cpu, fcpuname);
char* avx = get_str_avx(cpu);
char* fma = get_str_fma(cpu);
char* pp = get_str_peak_performance(cpu->peak_performance);
if(cpu->topo != NULL) {
sockets = get_str_sockets(cpu->topo);
n_cores = get_str_topology(cpu, cpu->topo, false);
n_cores_dual = get_str_topology(cpu, cpu->topo, true);
}
if(cpu->cach != NULL) {
l1i = get_str_l1i(cpu->cach);
l1d = get_str_l1d(cpu->cach);
l2 = get_str_l2(cpu->cach);
l3 = get_str_l3(cpu->cach);
}
// Step 2. Set attributes
setAttribute(art, ATTRIBUTE_NAME, cpu_name);
if(cpu->hv->present) {
setAttribute(art, ATTRIBUTE_HYPERVISOR, cpu->hv->hv_name);
}
setAttribute(art, ATTRIBUTE_UARCH, uarch);
setAttribute(art, ATTRIBUTE_TECHNOLOGY, manufacturing_process);
struct cpuInfo* ptr = cpu;
for(int i = 0; i < cpu->num_cpus; ptr = ptr->next_cpu, i++) {
char* max_frequency = get_str_freq(ptr->freq);
char* avx = get_str_avx(ptr);
char* fma = get_str_fma(ptr);
char* cpu_num = emalloc(sizeof(char) * 9);
if(ptr->topo != NULL) {
sockets = get_str_sockets(ptr->topo);
n_cores = get_str_topology(ptr, ptr->topo, false);
n_cores_dual = get_str_topology(ptr, ptr->topo, true);
}
if(ptr->cach != NULL) {
l1i = get_str_l1i(ptr->cach);
l1d = get_str_l1d(ptr->cach);
l2 = get_str_l2(ptr->cach);
}
if(hybrid_architecture) {
if(ptr->core_type == CORE_TYPE_EFFICIENCY) sprintf(cpu_num, "E-cores:");
else if(ptr->core_type == CORE_TYPE_PERFORMANCE) sprintf(cpu_num, "P-cores:");
else printBug("Found invalid core type!\n");
setAttribute(art, ATTRIBUTE_CPU_NUM, cpu_num);
}
setAttribute(art, ATTRIBUTE_FREQUENCY, max_frequency);
if(ptr->topo != NULL) {
socket_num = get_nsockets(ptr->topo);
if(cpu->topo != NULL) {
socket_num = get_nsockets(cpu->topo);
if (socket_num > 1) {
setAttribute(art, ATTRIBUTE_SOCKETS, sockets);
setAttribute(art, ATTRIBUTE_NCORES, n_cores);
@@ -616,7 +554,6 @@ bool print_cpufetch_x86(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
if(l1i != NULL) setAttribute(art, ATTRIBUTE_L1i, l1i);
if(l1d != NULL) setAttribute(art, ATTRIBUTE_L1d, l1d);
if(l2 != NULL) setAttribute(art, ATTRIBUTE_L2, l2);
}
if(l3 != NULL) setAttribute(art, ATTRIBUTE_L3, l3);
setAttribute(art, ATTRIBUTE_PEAK, pp);
@@ -633,12 +570,15 @@ bool print_cpufetch_x86(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
longest_attribute = longest_attribute_length(art, attribute_fields);
}
print_ascii_generic(art, longest_attribute, term->w, attribute_fields, hybrid_architecture);
print_ascii_generic(art, longest_attribute, term->w, attribute_fields);
free(manufacturing_process);
free(max_frequency);
free(sockets);
free(n_cores);
free(n_cores_dual);
free(avx);
free(fma);
free(l1i);
free(l1d);
free(l2);
@@ -685,9 +625,6 @@ bool print_cpufetch_ppc(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
setAttribute(art,ATTRIBUTE_NAME,cpu_name);
}
setAttribute(art,ATTRIBUTE_UARCH,uarch);
if(cpu->hv->present) {
setAttribute(art, ATTRIBUTE_HYPERVISOR, cpu->hv->hv_name);
}
setAttribute(art,ATTRIBUTE_TECHNOLOGY,manufacturing_process);
setAttribute(art,ATTRIBUTE_FREQUENCY,max_frequency);
uint32_t socket_num = get_nsockets(cpu->topo);
@@ -721,7 +658,7 @@ bool print_cpufetch_ppc(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
longest_attribute = longest_attribute_length(art, attribute_fields);
}
print_ascii_generic(art, longest_attribute, term->w, attribute_fields, false);
print_ascii_generic(art, longest_attribute, term->w, attribute_fields);
return true;
}
@@ -854,6 +791,15 @@ bool print_cpufetch_arm(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
char* uarch = get_str_uarch(cpu);
char* max_frequency = get_str_freq(cpu->freq);
char* n_cores = get_str_topology(cpu, cpu->topo, false);
/*
* char* l1i = get_str_l1i(cpu->cach);
* char* l1d = get_str_l1d(cpu->cach);
* char* l2 = get_str_l2(cpu->cach);
* char* l3 = get_str_l3(cpu->cach);
* Do not setAttribute for caches.
* Cache functionality may be implemented
* in the future
*/
setAttribute(art,ATTRIBUTE_UARCH,uarch);
setAttribute(art,ATTRIBUTE_FREQUENCY,max_frequency);
@@ -868,8 +814,17 @@ bool print_cpufetch_arm(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
char* uarch = get_str_uarch(ptr);
char* max_frequency = get_str_freq(ptr->freq);
char* n_cores = get_str_topology(ptr, ptr->topo, false);
char* cpu_num = emalloc(sizeof(char) * 9);
/*
* char* l1i = get_str_l1i(cpu->cach);
* char* l1d = get_str_l1d(cpu->cach);
* char* l2 = get_str_l2(cpu->cach);
* char* l3 = get_str_l3(cpu->cach);
* Do not setAttribute for caches.
* Cache functionality may be implemented
* in the future
*/
char* cpu_num = emalloc(sizeof(char) * 9);
sprintf(cpu_num, "CPU %d:", i+1);
setAttribute(art, ATTRIBUTE_CPU_NUM, cpu_num);
setAttribute(art, ATTRIBUTE_UARCH, uarch);
@@ -920,142 +875,7 @@ bool print_cpufetch_arm(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
}
#endif
#ifdef ARCH_RISCV
// https://stackoverflow.com/a/2709523
uint64_t number_of_bits(uint64_t i) {
i = i - ((i >> 1) & 0x5555555555555555);
i = (i & 0x3333333333333333) + ((i >> 2) & 0x3333333333333333);
return (((i + (i >> 4)) & 0xF0F0F0F0F0F0F0F) * 0x101010101010101) >> 56;
}
void print_ascii_riscv(struct ascii* art, uint32_t la, int32_t termw, const char** attribute_fields, uint64_t extensions_mask) {
struct ascii_logo* logo = art->art;
int attr_to_print = 0;
int attr_type;
char* attr_value;
int32_t beg_space;
int32_t space_right;
int32_t ext_list_size = sizeof(extension_list)/sizeof(extension_list[0]);
int32_t ext_num = 0;
int32_t ext_to_print = 0;
int32_t num_extensions = number_of_bits(extensions_mask);
int32_t space_up = ((int)logo->height - (int)(art->n_attributes_set + num_extensions))/2;
int32_t space_down = (int)logo->height - (int)(art->n_attributes_set + num_extensions) - (int)space_up;
uint32_t logo_pos = 0;
int32_t iters = max(logo->height, art->n_attributes_set + num_extensions);
struct line_buffer* lbuf = emalloc(sizeof(struct line_buffer));
lbuf->buf = emalloc(sizeof(char) * LINE_BUFFER_SIZE);
lbuf->pos = 0;
lbuf->chars = 0;
printf("\n");
for(int32_t n=0; n < iters; n++) {
// 1. Print logo
if(space_up > 0 || (space_up + n >= 0 && space_up + n < (int)logo->height)) {
for(uint32_t i=0; i < logo->width; i++) {
if(logo->art[logo_pos] == '$') {
if(logo->replace_blocks) logo_pos += 3;
else parse_print_color(art, lbuf, &logo_pos);
}
if(logo->replace_blocks && logo->art[logo_pos] != ' ') {
if(logo->art[logo_pos] == '#') printOut(lbuf, 1, "%s%c%s", logo->color_ascii[0], ' ', art->reset);
else if(logo->art[logo_pos] == '@') printOut(lbuf, 1, "%s%c%s", logo->color_ascii[1], ' ', art->reset);
else if(logo->art[logo_pos] == '%') printOut(lbuf, 1, "%s%c%s", logo->color_ascii[2], ' ', art->reset);
else printOut(lbuf, 1, "%c", logo->art[logo_pos]);
}
else
printOut(lbuf, 1, "%c", logo->art[logo_pos]);
logo_pos++;
}
printOut(lbuf, 0, "%s", art->reset);
}
else {
// If logo should not be printed, fill with spaces
printOut(lbuf, logo->width, "%*c", logo->width, ' ');
}
// 2. Print text
if(space_up < 0 || (n > space_up-1 && n < (int)logo->height - space_down)) {
attr_type = art->attributes[attr_to_print]->type;
attr_value = art->attributes[attr_to_print]->value;
// Print extension
if(attr_to_print > 0 && art->attributes[attr_to_print-1]->type == ATTRIBUTE_EXTENSIONS && ext_num != num_extensions) {
// Search for the extension to print
while(ext_to_print < ext_list_size && !((extensions_mask >> extension_list[ext_to_print].id) & 1U)) ext_to_print++;
if(ext_to_print == ext_list_size) {
printBug("print_ascii_riscv: Unable to find the extension to print");
}
printOut(lbuf, 3 + strlen(extension_list[ext_to_print].str), "%s - %s%s", logo->color_text[0], extension_list[ext_to_print].str, art->reset);
ext_num++;
ext_to_print++;
}
else {
attr_to_print++;
beg_space = 0;
space_right = 2 + 1 + (la - strlen(attribute_fields[attr_type]));
printOut(lbuf, beg_space + strlen(attribute_fields[attr_type]) + space_right + strlen(attr_value),
"%*s%s%s%s%*s%s%s%s", beg_space, "", logo->color_text[0], attribute_fields[attr_type], art->reset, space_right, "", logo->color_text[1], attr_value, art->reset);
}
}
printOutLine(lbuf, art, termw);
printf("\n");
}
printf("\n");
free(lbuf->buf);
free(lbuf);
}
bool print_cpufetch_riscv(struct cpuInfo* cpu, STYLE s, struct color** cs, struct terminal* term) {
struct ascii* art = set_ascii(get_soc_vendor(cpu->soc), s);
if(art == NULL)
return false;
// Step 1. Retrieve attributes
char* uarch = get_str_uarch(cpu);
char* manufacturing_process = get_str_process(cpu->soc);
char* soc_name = get_soc_name(cpu->soc);
char* extensions = get_str_extensions(cpu);
char* max_frequency = get_str_freq(cpu->freq);
char* n_cores = get_str_topology(cpu, cpu->topo);
char* pp = get_str_peak_performance(cpu->peak_performance);
// Step 2. Set attributes
setAttribute(art, ATTRIBUTE_SOC, soc_name);
setAttribute(art, ATTRIBUTE_TECHNOLOGY, manufacturing_process);
setAttribute(art, ATTRIBUTE_UARCH, uarch);
setAttribute(art, ATTRIBUTE_NCORES, n_cores);
setAttribute(art, ATTRIBUTE_FREQUENCY, max_frequency);
if(extensions != NULL) {
setAttribute(art, ATTRIBUTE_EXTENSIONS, extensions);
}
setAttribute(art, ATTRIBUTE_PEAK, pp);
// Step 3. Print output
const char** attribute_fields = ATTRIBUTE_FIELDS;
uint32_t longest_attribute = longest_attribute_length(art, attribute_fields);
uint32_t longest_field = longest_field_length(art, longest_attribute);
choose_ascii_art(art, cs, term, longest_field);
if(!ascii_fits_screen(term->w, *art->art, longest_field)) {
// Despite of choosing the smallest logo, the output does not fit
// Choose the shorter field names and recalculate the longest attr
attribute_fields = ATTRIBUTE_FIELDS_SHORT;
longest_attribute = longest_attribute_length(art, attribute_fields);
}
print_ascii_riscv(art, longest_attribute, term->w, attribute_fields, cpu->ext->mask);
return true;
}
#endif
struct terminal* get_terminal_size(void) {
struct terminal* get_terminal_size() {
struct terminal* term = emalloc(sizeof(struct terminal));
#ifdef _WIN32
@@ -1092,7 +912,5 @@ bool print_cpufetch(struct cpuInfo* cpu, STYLE s, struct color** cs, bool show_f
return print_cpufetch_ppc(cpu, s, cs, term, show_full_cpu_name);
#elif ARCH_ARM
return print_cpufetch_arm(cpu, s, cs, term);
#elif ARCH_RISCV
return print_cpufetch_riscv(cpu, s, cs, term);
#endif
}

4
src/common/printer.h
View File

@@ -11,8 +11,6 @@ typedef int STYLE;
#include "../ppc/ppc.h"
#elif ARCH_ARM
#include "../arm/midr.h"
#elif ARCH_RISCV
#include "../riscv/riscv.h"
#endif
// +-----------------------------------+-----------------------+
@@ -23,8 +21,6 @@ typedef int STYLE;
#define COLOR_DEFAULT_AMD "250,250,250:000,154,102:000,000,000:250,250,250:000,154,102"
#define COLOR_DEFAULT_IBM "092,119,172:092,119,172:000,000,000:240,240,240:092,119,172"
#define COLOR_DEFAULT_ARM "000,145,189:000,145,189:000,000,000:240,240,240:000,145,189"
#define COLOR_DEFAULT_ROCKCHIP "114,159,207:229,195,000:000,000,000:240,240,240:114,159,207"
#define COLOR_DEFAULT_SIFIVE "255,255,255:000,000,000:000,000,000:255,255,255:000,000,000"
#ifdef ARCH_X86
void print_levels(struct cpuInfo* cpu);

90
src/common/soc.c
View File

@@ -1,90 +0,0 @@
#include "soc.h"
#ifdef ARCH_ARM
#include "../arm/socs.h"
#elif ARCH_RISCV
#include "../riscv/socs.h"
#endif
#include "udev.h"
#include "../common/global.h"
#include <string.h>
static char* soc_trademark_string[] = {
// ARM
[SOC_VENDOR_SNAPDRAGON] = "Snapdragon ",
[SOC_VENDOR_MEDIATEK] = "MediaTek ",
[SOC_VENDOR_EXYNOS] = "Exynos ",
[SOC_VENDOR_KIRIN] = "Kirin ",
[SOC_VENDOR_BROADCOM] = "Broadcom BCM",
[SOC_VENDOR_APPLE] = "Apple ",
[SOC_VENDOR_ROCKCHIP] = "Rockchip ",
[SOC_VENDOR_GOOGLE] = "Google ",
// RISC-V
[SOC_VENDOR_SIFIVE] = "SiFive ",
[SOC_VENDOR_STARFIVE] = "StarFive ",
[SOC_VENDOR_SIPEED] = "Sipeed ",
// ARM & RISC-V
[SOC_VENDOR_ALLWINNER] = "Allwinner "
};
VENDOR get_soc_vendor(struct system_on_chip* soc) {
return soc->soc_vendor;
}
char* get_str_process(struct system_on_chip* soc) {
char* str;
if(soc->process == UNKNOWN) {
str = emalloc(sizeof(char) * (strlen(STRING_UNKNOWN)+1));
snprintf(str, strlen(STRING_UNKNOWN)+1, STRING_UNKNOWN);
}
else {
str = emalloc(sizeof(char) * 5);
memset(str, 0, sizeof(char) * 5);
snprintf(str, 5, "%dnm", soc->process);
}
return str;
}
char* get_soc_name(struct system_on_chip* soc) {
if(soc->soc_model == SOC_MODEL_UNKNOWN)
return soc->raw_name;
return soc->soc_name;
}
void fill_soc(struct system_on_chip* soc, char* soc_name, SOC soc_model, int32_t process) {
soc->soc_model = soc_model;
soc->soc_vendor = get_soc_vendor_from_soc(soc_model);
soc->process = process;
if(soc->soc_vendor == SOC_VENDOR_UNKNOWN) {
printBug("fill_soc: soc->soc_vendor == SOC_VENDOR_UNKOWN");
// If we fall here there is a bug in socs.h
// Reset everything to avoid segfault
soc->soc_vendor = SOC_VENDOR_UNKNOWN;
soc->soc_model = SOC_MODEL_UNKNOWN;
soc->process = UNKNOWN;
soc->raw_name = emalloc(sizeof(char) * (strlen(STRING_UNKNOWN)+1));
snprintf(soc->raw_name, strlen(STRING_UNKNOWN)+1, STRING_UNKNOWN);
}
else {
soc->process = process;
int len = strlen(soc_name) + strlen(soc_trademark_string[soc->soc_vendor]) + 1;
soc->soc_name = emalloc(sizeof(char) * len);
memset(soc->soc_name, 0, sizeof(char) * len);
sprintf(soc->soc_name, "%s%s", soc_trademark_string[soc->soc_vendor], soc_name);
}
}
bool match_soc(struct system_on_chip* soc, char* raw_name, char* expected_name, char* soc_name, SOC soc_model, int32_t process) {
int len1 = strlen(raw_name);
int len2 = strlen(expected_name);
int len = min(len1, len2);
if(strncmp(raw_name, expected_name, len) != 0) {
return false;
}
else {
fill_soc(soc, soc_name, soc_model, process);
return true;
}
}

54
src/common/soc.h
View File

@@ -1,54 +0,0 @@
#ifndef __SOC__
#define __SOC__
// NOTE:
// soc.c/soc.h are used by
// ARM and RISC-V backends
#include "../common/cpu.h"
#include <stdint.h>
#define UNKNOWN -1
typedef int32_t SOC;
enum {
SOC_VENDOR_UNKNOWN,
// ARM
SOC_VENDOR_SNAPDRAGON,
SOC_VENDOR_MEDIATEK,
SOC_VENDOR_EXYNOS,
SOC_VENDOR_KIRIN,
SOC_VENDOR_BROADCOM,
SOC_VENDOR_APPLE,
SOC_VENDOR_ROCKCHIP,
SOC_VENDOR_GOOGLE,
// RISC-V
SOC_VENDOR_SIFIVE,
SOC_VENDOR_STARFIVE,
SOC_VENDOR_SIPEED,
// ARM & RISC-V
SOC_VENDOR_ALLWINNER
};
struct system_on_chip {
SOC soc_model;
VENDOR soc_vendor;
int32_t process;
char* soc_name;
char* raw_name;
};
struct system_on_chip* get_soc(void);
char* get_soc_name(struct system_on_chip* soc);
VENDOR get_soc_vendor(struct system_on_chip* soc);
bool match_soc(struct system_on_chip* soc, char* raw_name, char* expected_name, char* soc_name, SOC soc_model, int32_t process);
char* get_str_process(struct system_on_chip* soc);
void fill_soc(struct system_on_chip* soc, char* soc_name, SOC soc_model, int32_t process);
#define SOC_START if (false) {}
#define SOC_EQ(raw_name, expected_name, soc_name, soc_model, soc, process) \
else if (match_soc(soc, raw_name, expected_name, soc_name, soc_model, process)) return true;
#define SOC_END else { return false; }
#endif

161
src/common/udev.c
View File

@@ -3,7 +3,7 @@
#include "cpu.h"
// https://www.kernel.org/doc/html/latest/core-api/cpu_hotplug.html
int get_ncores_from_cpuinfo(void) {
int get_ncores_from_cpuinfo() {
// Examples:
// 0-271
// 0-7
@@ -54,18 +54,13 @@ char* read_file(char* path, int* len) {
//File exists, read it
int bytes_read = 0;
int offset = 0;
int block = 1024;
int buf_size = block * 4;
char* buf = emalloc(sizeof(char) * buf_size);
int block = 128;
char* buf = emalloc(sizeof(char)*DEFAULT_FILE_SIZE);
memset(buf, 0, sizeof(char)*DEFAULT_FILE_SIZE);
while ( (bytes_read = read(fd, buf+offset, block)) > 0 ) {
offset += bytes_read;
if(offset + block > buf_size) {
buf = erealloc(buf, sizeof(char) * (buf_size + block));
buf_size += block;
}
}
buf[offset] = '\0';
if (close(fd) == -1) {
return NULL;
@@ -129,27 +124,6 @@ long get_cache_size_from_file(char* path) {
return ret * 1024;
}
char* get_field_from_cpuinfo(char* CPUINFO_FIELD) {
int filelen;
char* buf;
if((buf = read_file(_PATH_CPUINFO, &filelen)) == NULL) {
printWarn("read_file: %s: %s:\n", _PATH_CPUINFO, strerror(errno));
return NULL;
}
char* tmp1 = strstr(buf, CPUINFO_FIELD);
if(tmp1 == NULL) return NULL;
tmp1 = tmp1 + strlen(CPUINFO_FIELD);
char* tmp2 = strstr(tmp1, "\n");
int strlen = (1 + (tmp2-tmp1));
char* hardware = emalloc(sizeof(char) * strlen);
memset(hardware, 0, sizeof(char) * strlen);
strncpy(hardware, tmp1, tmp2-tmp1);
return hardware;
}
long get_max_freq_from_file(uint32_t core) {
char path[_PATH_FREQUENCY_MAX_LEN];
sprintf(path, "%s%s/cpu%d%s%s", _PATH_SYS_SYSTEM, _PATH_SYS_CPU, core, _PATH_FREQUENCY, _PATH_FREQUENCY_MAX);
@@ -186,106 +160,54 @@ long get_l3_cache_size(uint32_t core) {
return get_cache_size_from_file(path);
}
void add_shared_map(uint32_t** src, int src_idx, uint32_t** dst, int dst_idx, int n) {
for(int j=0; j < n; j++) {
dst[dst_idx][j] = src[src_idx][j];
}
}
bool maps_equal(uint32_t* map1, uint32_t* map2, int n) {
for(int i=0; i < n; i++) {
if(map1[i] != map2[i]) return false;
}
return true;
}
// Generic function to count the number of distinct
// elements in the list of files passed in char** paths.
// An element can be potentially anything.
// We use this function to count:
// - The number of caches
// - The number of sockets
int get_num_elements_from_files(char** paths, int num_paths) {
int get_num_caches_from_files(char** paths, int num_paths) {
int SHARED_MAP_MAX_LEN = 8 + 1;
int filelen;
char* buf;
char* tmpbuf;
uint32_t* shared_maps = emalloc(sizeof(uint32_t *) * num_paths);
// 1. Count the number of bitmasks per file
if((buf = read_file(paths[0], &filelen)) == NULL) {
printWarn("Could not open '%s'", paths[0]);
return -1;
}
int num_bitmasks = 1;
for(int i=0; buf[i]; i++) {
num_bitmasks += (buf[i] == ',');
}
// 2. Read map from every core
uint32_t** maps = emalloc(sizeof(uint32_t *) * num_paths);
// 1. Read cpu_shared_map from every core
for(int i=0; i < num_paths; i++) {
maps[i] = emalloc(sizeof(uint32_t) * num_bitmasks);
if((buf = read_file(paths[i], &filelen)) == NULL) {
printWarn("Could not open '%s'", paths[i]);
return -1;
}
for(int j=0; j < num_bitmasks; j++) {
if(filelen > SHARED_MAP_MAX_LEN) {
printBug("Shared map length is %d while the max is be %d", filelen, SHARED_MAP_MAX_LEN);
return -1;
}
char* end;
tmpbuf = emalloc(sizeof(char) * (strlen(buf) + 1));
memset(tmpbuf, 0, sizeof(char) * (strlen(buf) + 1));
char* commaend = strstr(buf, ",");
if(commaend == NULL) {
strcpy(tmpbuf, buf);
}
else {
strncpy(tmpbuf, buf, commaend-buf);
}
errno = 0;
long ret = strtol(tmpbuf, &end, 16);
long ret = strtol(buf, &end, 16);
if(errno != 0) {
printf("strtol: %s", strerror(errno));
printBug("strtol: %s", strerror(errno));
free(buf);
return -1;
}
maps[i][j] = (uint32_t) ret;
buf = commaend + 1;
free(tmpbuf);
}
shared_maps[i] = (uint32_t) ret;
}
// 2. Count number of different masks; this is the number of elements
int num_elements = 0;
// 2. Count number of different masks; this is the number of caches
int num_caches = 0;
bool found = false;
uint32_t** unique_maps = emalloc(sizeof(uint32_t *) * num_paths);
for(int i=0; i < num_paths; i++) {
unique_maps[i] = emalloc(sizeof(uint32_t) * num_bitmasks);
for(int j=0; j < num_bitmasks; j++) {
unique_maps[i][j] = 0;
}
}
uint32_t* unique_shared_maps = emalloc(sizeof(uint32_t *) * num_paths);
for(int i=0; i < num_paths; i++) unique_shared_maps[i] = 0;
for(int i=0; i < num_paths; i++) {
for(int j=0; j < num_paths && !found; j++) {
if(maps_equal(maps[i], unique_maps[j], num_bitmasks)) found = true;
if(shared_maps[i] == unique_shared_maps[j]) found = true;
}
if(!found) {
add_shared_map(maps, i, unique_maps, num_elements, num_bitmasks);
num_elements++;
unique_shared_maps[num_caches] = shared_maps[i];
num_caches++;
}
found = false;
}
return num_elements;
}
int get_num_caches_from_files(char** paths, int num_paths) {
return get_num_elements_from_files(paths, num_paths);
}
int get_num_sockets_from_files(char** paths, int num_paths) {
return get_num_elements_from_files(paths, num_paths);
return num_caches;
}
int get_num_caches_by_level(struct cpuInfo* cpu, uint32_t level) {
@@ -314,38 +236,3 @@ int get_num_caches_by_level(struct cpuInfo* cpu, uint32_t level) {
return ret;
}
int get_num_sockets_package_cpus(struct topology* topo) {
// Get number of sockets using
// /sys/devices/system/cpu/cpu*/topology/package_cpus
char** paths = emalloc(sizeof(char *) * topo->total_cores);
for(int i=0; i < topo->total_cores; i++) {
paths[i] = emalloc(sizeof(char) * _PATH_PACKAGE_MAX_LEN);
sprintf(paths[i], "%s%s/cpu%d%s", _PATH_SYS_SYSTEM, _PATH_SYS_CPU, i, _PATH_TOPO_PACKAGE_CPUS);
}
int ret = get_num_sockets_from_files(paths, topo->total_cores);
for(int i=0; i < topo->total_cores; i++)
free(paths[i]);
free(paths);
return ret;
}
// Inspired in is_devtree_compatible from lscpu
bool is_devtree_compatible(char* str) {
int filelen;
char* buf;
if((buf = read_file("/proc/device-tree/compatible", &filelen)) == NULL) {
return false;
}
char* tmp;
if((tmp = strstr(buf, str)) == NULL) {
return false;
}
return true;
}

9
src/common/udev.h
View File

@@ -12,7 +12,6 @@
#include "cpu.h"
#define _PATH_CPUINFO "/proc/cpuinfo"
#define _PATH_SYS_SYSTEM "/sys/devices/system"
#define _PATH_SYS_CPU "/cpu"
#define _PATH_FREQUENCY "/cpufreq"
@@ -25,11 +24,10 @@
#define _PATH_CACHE_SIZE "/size"
#define _PATH_CACHE_SHARED_MAP "/shared_cpu_map"
#define _PATH_CPUS_PRESENT _PATH_SYS_SYSTEM _PATH_SYS_CPU "/present"
#define _PATH_TOPO_PACKAGE_CPUS "/topology/package_cpus"
#define _PATH_FREQUENCY_MAX_LEN 100
#define _PATH_CACHE_MAX_LEN 200
#define _PATH_PACKAGE_MAX_LEN 200
#define DEFAULT_FILE_SIZE 4096
char* read_file(char* path, int* len);
long get_max_freq_from_file(uint32_t core);
@@ -39,9 +37,6 @@ long get_l1d_cache_size(uint32_t core);
long get_l2_cache_size(uint32_t core);
long get_l3_cache_size(uint32_t core);
int get_num_caches_by_level(struct cpuInfo* cpu, uint32_t level);
int get_num_sockets_package_cpus(struct topology* topo);
int get_ncores_from_cpuinfo(void);
char* get_field_from_cpuinfo(char* CPUINFO_FIELD);
bool is_devtree_compatible(char* str);
int get_ncores_from_cpuinfo();
#endif

64
src/ppc/ppc.c
View File

@@ -11,19 +11,6 @@
#include "../common/udev.h"
#include "../common/global.h"
static char *hv_vendors_name[] = {
[HV_VENDOR_KVM] = "KVM",
[HV_VENDOR_QEMU] = "QEMU",
[HV_VENDOR_HYPERV] = "Microsoft Hyper-V",
[HV_VENDOR_VMWARE] = "VMware",
[HV_VENDOR_XEN] = "Xen",
[HV_VENDOR_PARALLELS] = "Parallels",
[HV_VENDOR_PHYP] = "pHyp",
[HV_VENDOR_BHYVE] = "bhyve",
[HV_VENDOR_APPLEVZ] = "Apple VZ",
[HV_VENDOR_INVALID] = STRING_UNKNOWN
};
struct cache* get_cache_info(struct cpuInfo* cpu) {
struct cache* cach = emalloc(sizeof(struct cache));
init_cache_struct(cach);
@@ -76,17 +63,12 @@ struct topology* get_topology_info(struct cache* cach) {
printWarn("fill_core_ids_from_sys failed, output may be incomplete/invalid");
for(int i=0; i < topo->total_cores; i++) core_ids[i] = 0;
}
if(!fill_package_ids_from_sys(package_ids, topo->total_cores)) {
printWarn("fill_package_ids_from_sys failed, output may be incomplete/invalid");
for(int i=0; i < topo->total_cores; i++) package_ids[i] = 0;
// fill_package_ids_from_sys failed, use a
// more sophisticated wat to find the number of sockets
topo->sockets = get_num_sockets_package_cpus(topo);
}
else {
// fill_package_ids_from_sys succeeded, use the
// traditional socket detection algorithm
// 2. Socket detection
int *package_ids_count = emalloc(sizeof(int) * topo->total_cores);
for(int i=0; i < topo->total_cores; i++) {
package_ids_count[i] = 0;
@@ -99,8 +81,6 @@ struct topology* get_topology_info(struct cache* cach) {
topo->sockets++;
}
}
free(package_ids_count);
}
// 3. Physical cores detection
int *core_ids_unified = emalloc(sizeof(int) * topo->total_cores);
@@ -125,12 +105,13 @@ struct topology* get_topology_info(struct cache* cach) {
free(core_ids);
free(package_ids);
free(package_ids_count);
free(core_ids_unified);
return topo;
}
static inline uint32_t mfpvr(void) {
static inline uint32_t mfpvr() {
uint32_t pvr;
asm ("mfpvr %0"
@@ -142,18 +123,12 @@ struct uarch* get_cpu_uarch(struct cpuInfo* cpu) {
return get_uarch_from_pvr(cpu->pvr);
}
struct frequency* get_frequency_info(void) {
struct frequency* get_frequency_info() {
struct frequency* freq = emalloc(sizeof(struct frequency));
freq->max = get_max_freq_from_file(0);
freq->base = get_min_freq_from_file(0);
if(freq->max == UNKNOWN_DATA) {
// If we are unable to find it in the
// standard path, try /proc/cpuinfo
freq->max = get_frequency_from_cpuinfo();
}
return freq;
}
@@ -183,29 +158,7 @@ int64_t get_peak_performance(struct cpuInfo* cpu, struct topology* topo, int64_t
return flops;
}
struct hypervisor* get_hp_info(void) {
struct hypervisor* hv = emalloc(sizeof(struct hypervisor));
hv->present = false;
// Weird heuristic found in lscpu:
// https://github.com/util-linux/util-linux/blob/master/sys-utils/lscpu-virt.c
if(access("/proc" _PATH_DT_IBM_PARTIT_NAME, F_OK) == 0 &&
access("/proc" _PATH_DT_HMC_MANAGED, F_OK) == 0 &&
access("/proc" _PATH_DT_QEMU_WIDTH, F_OK) != 0) {
hv->present = true;
hv->hv_vendor = HV_VENDOR_PHYP;
}
else if(is_devtree_compatible("qemu,pseries")) {
hv->present = true;
hv->hv_vendor = HV_VENDOR_QEMU;
}
hv->hv_name = hv_vendors_name[hv->hv_vendor];
return hv;
}
struct cpuInfo* get_cpu_info(void) {
struct cpuInfo* get_cpu_info() {
struct cpuInfo* cpu = emalloc(sizeof(struct cpuInfo));
struct features* feat = emalloc(sizeof(struct features));
cpu->feat = feat;
@@ -219,11 +172,8 @@ struct cpuInfo* get_cpu_info(void) {
char* path = emalloc(sizeof(char) * (strlen(_PATH_DT) + strlen(_PATH_DT_PART) + 1));
sprintf(path, "%s%s", _PATH_DT, _PATH_DT_PART);
if((cpu->cpu_name = read_file(path, &len)) == NULL) {
printWarn("Could not open '%s'", path);
}
cpu->cpu_name = read_file(path, &len);
cpu->pvr = mfpvr();
cpu->hv = get_hp_info();
cpu->arch = get_cpu_uarch(cpu);
cpu->freq = get_frequency_info();
cpu->topo = get_topology_info(cpu->cach);

6
src/ppc/ppc.h
View File

@@ -1,9 +1,9 @@
#ifndef __CPUFETCH_POWERPC__
#define __CPUFETCH_POWERPC__
#ifndef __POWERPC__
#define __POWERPC__
#include "../common/cpu.h"
struct cpuInfo* get_cpu_info(void);
struct cpuInfo* get_cpu_info();
char* get_str_altivec(struct cpuInfo* cpu);
char* get_str_topology(struct topology* topo, bool dual_socket);
void print_debug(struct cpuInfo* cpu);

23
src/ppc/uarch.c
View File

@@ -3,6 +3,7 @@
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sys/auxv.h>
#include <errno.h>
#include "uarch.h"
@@ -35,7 +36,6 @@ enum {
UARCH_POWER7,
UARCH_POWER7PLUS,
UARCH_POWER8,
UARCH_POWER8_DD21,
UARCH_POWER9,
UARCH_POWER9_DD20,
UARCH_POWER9_DD21,
@@ -85,7 +85,6 @@ void fill_uarch(struct uarch* arch, MICROARCH u) {
FILL_UARCH(arch->uarch, UARCH_POWER7, "POWER7", 45)
FILL_UARCH(arch->uarch, UARCH_POWER7PLUS, "POWER7+", 32)
FILL_UARCH(arch->uarch, UARCH_POWER8, "POWER8", 22)
FILL_UARCH(arch->uarch, UARCH_POWER8_DD21, "POWER8 (DD2.1)", 22)
FILL_UARCH(arch->uarch, UARCH_POWER9, "POWER9", 14)
FILL_UARCH(arch->uarch, UARCH_POWER9_DD20, "POWER9 (DD2.0)", 14)
FILL_UARCH(arch->uarch, UARCH_POWER9_DD21, "POWER9 (DD2.1)", 14)
@@ -102,19 +101,7 @@ void fill_uarch(struct uarch* arch, MICROARCH u) {
}
/*
* PVR masks/values from Linux kernel:
* - arch/powerpc/kernel/cputable.c (kernel <= 6.0)
* - arch/powerpc/kernel/cpu_specs_book3s_64.h (kernel >= 6.1)
*
* In the kernel, there is a POWER8E identifier. In
* https://wiki.raptorcs.com/wiki/POWER8E it says it is
* actually DD2.1, while other POWER8 should be DD2.0.
* The last assumption does not seem to be correct according
* to https://openbenchmarking.org/s/POWER8NVL, which shows a
* POWER8NVL where kernel says it is DD1.0. We implement this
* to show only the uarch, not the revision, since it seems a bit
* redundant?
*
* PVR masks/values from arch/powerpc/kernel/cputable.c (Linux kernel)
* This list may be incorrect, incomplete or overly simplified,
* specially in the case of 32 bit entries
*/
@@ -139,7 +126,7 @@ struct uarch* get_uarch_from_pvr(uint32_t pvr) {
CHECK_UARCH(arch, pvr, 0xffffffff, 0x0f000006, UARCH_POWER10)
CHECK_UARCH(arch, pvr, 0xffff0000, 0x003f0000, UARCH_POWER7)
CHECK_UARCH(arch, pvr, 0xffff0000, 0x004A0000, UARCH_POWER7PLUS)
CHECK_UARCH(arch, pvr, 0xffff0000, 0x004b0000, UARCH_POWER8_DD21)
CHECK_UARCH(arch, pvr, 0xffff0000, 0x004b0000, UARCH_POWER8)
CHECK_UARCH(arch, pvr, 0xffff0000, 0x004c0000, UARCH_POWER8)
CHECK_UARCH(arch, pvr, 0xffff0000, 0x004d0000, UARCH_POWER8)
CHECK_UARCH(arch, pvr, 0xffffefff, 0x004e0200, UARCH_POWER9_DD20)
@@ -248,7 +235,6 @@ bool has_altivec(struct uarch* arch) {
case UARCH_POWER7:
case UARCH_POWER7PLUS:
case UARCH_POWER8:
case UARCH_POWER8_DD21:
case UARCH_POWER9:
case UARCH_POWER9_DD20:
case UARCH_POWER9_DD21:
@@ -280,6 +266,9 @@ char* get_str_process(struct cpuInfo* cpu) {
if(process == UNK) {
snprintf(str, strlen(STRING_UNKNOWN)+1, STRING_UNKNOWN);
}
else if(process > 100) {
sprintf(str, "%.2fum", (double)process/100);
}
else if(process > 0){
sprintf(str, "%dnm", process);
}

52
src/ppc/udev.c
View File

@@ -1,19 +1,16 @@
#include <errno.h>
#include "../common/udev.h"
#include "../common/global.h"
#include "udev.h"
#define _PATH_TOPO_CORE_ID "topology/core_id"
#define _PATH_TOPO_PACKAGE_ID "topology/physical_package_id"
#define CPUINFO_FREQUENCY_STR "clock\t\t: "
bool fill_array_from_sys(int *core_ids, int total_cores, char* SYS_PATH) {
int filelen;
char* buf;
char* end;
char path[128];
memset(path, 0, 128);
for(int i=0; i < total_cores; i++) {
sprintf(path, "%s%s/cpu%d/%s", _PATH_SYS_SYSTEM, _PATH_SYS_CPU, i, SYS_PATH);
@@ -39,52 +36,5 @@ bool fill_core_ids_from_sys(int *core_ids, int total_cores) {
}
bool fill_package_ids_from_sys(int* package_ids, int total_cores) {
bool status = fill_array_from_sys(package_ids, total_cores, _PATH_TOPO_PACKAGE_ID);
if(status) {
// fill_array_from_sys completed successfully, but we
// must to check the integrity of the package_ids array
for(int i=0; i < total_cores; i++) {
if(package_ids[i] == -1) {
printWarn("fill_package_ids_from_sys: package_ids[%d] = -1", i);
return false;
}
else if(package_ids[i] >= total_cores || package_ids[i] < 0) {
printBug("fill_package_ids_from_sys: package_ids[%d] = %d", i, package_ids[i]);
return false;
}
}
return true;
}
return false;
}
long get_frequency_from_cpuinfo(void) {
char* freq_str = get_field_from_cpuinfo(CPUINFO_FREQUENCY_STR);
if(freq_str == NULL) {
return UNKNOWN_DATA;
}
else {
// freq_str should be in the form XXXX.YYYYYYMHz
char* dot = strstr(freq_str, ".");
freq_str[dot-freq_str] = '\0';
char* end;
errno = 0;
long ret = strtol(freq_str, &end, 10);
if(errno != 0) {
printBug("strtol: %s", strerror(errno));
free(freq_str);
return UNKNOWN_DATA;
}
// We consider it an error if frequency is
// greater than 10 GHz or less than 100 MHz
if(ret > 10000 || ret < 100) {
printBug("Invalid data was read from file '%s': %ld\n", CPUINFO_FREQUENCY_STR, ret);
return UNKNOWN_DATA;
}
return ret;
}
return fill_array_from_sys(package_ids, total_cores, _PATH_TOPO_PACKAGE_ID);
}

5
src/ppc/udev.h
View File

@@ -4,13 +4,8 @@
#include "../common/udev.h"
#define _PATH_DT "/proc/device-tree/vpd/root-node-vpd@a000/enclosure@1e00/backplane@800/processor@1000"
#define _PATH_DT_PART "/part-number"
#define _PATH_DT_IBM_PARTIT_NAME "/device-tree/ibm,partition-name"
#define _PATH_DT_HMC_MANAGED "/device-tree/hmc-managed?"
#define _PATH_DT_QEMU_WIDTH "/device-tree/chosen/qemu,graphic-width"
bool fill_core_ids_from_sys(int *core_ids, int total_cores);
bool fill_package_ids_from_sys(int* package_ids, int total_cores);
int get_num_sockets_package_cpus(struct topology* topo);
long get_frequency_from_cpuinfo(void);
#endif

206
src/riscv/riscv.c
View File

@@ -1,206 +0,0 @@
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <ctype.h>
#include "../common/global.h"
#include "../common/udev.h"
#include "udev.h"
#include "uarch.h"
#include "soc.h"
#define SET_ISA_EXT_MAP(name, bit) \
if(strncmp(multi_letter_extension, name, \
multi_letter_extension_len) == 0) { \
ext->mask |= 1UL << bit; \
maskset = true; \
} \
struct frequency* get_frequency_info(uint32_t core) {
struct frequency* freq = emalloc(sizeof(struct frequency));
freq->base = UNKNOWN_DATA;
freq->max = get_max_freq_from_file(core);
return freq;
}
int64_t get_peak_performance(struct cpuInfo* cpu) {
//First check we have consistent data
if(get_freq(cpu->freq) == UNKNOWN_DATA) {
return -1;
}
int64_t flops = cpu->topo->total_cores * (get_freq(cpu->freq) * 1000000);
return flops;
}
// Returns the length of the multi-letter
// extension, or -1 if an error occurs
int parse_multi_letter_extension(struct extensions* ext, char* e) {
if(*e != '_') return -1;
char* multi_letter_extension_end = strstr(e+1, "_");
if(multi_letter_extension_end == NULL) {
// This is the last extension, find the end
// of the string
multi_letter_extension_end = e + strlen(e);
}
int multi_letter_extension_len = multi_letter_extension_end-(e+1);
bool maskset = false;
char* multi_letter_extension = emalloc(multi_letter_extension_len);
strncpy(multi_letter_extension, e+1, multi_letter_extension_len);
// This should be up-to-date with
// https://elixir.bootlin.com/linux/latest/source/arch/riscv/kernel/cpufeature.c
// which should represent the list of extensions available in real chips
SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF)
SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC)
SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL)
SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT)
SET_ISA_EXT_MAP("zbb", RISCV_ISA_EXT_ZBB)
SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM)
SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE)
SET_ISA_EXT_MAP("svnapot", RISCV_ISA_EXT_SVNAPOT)
SET_ISA_EXT_MAP("zicboz", RISCV_ISA_EXT_ZICBOZ)
SET_ISA_EXT_MAP("smaia", RISCV_ISA_EXT_SMAIA)
SET_ISA_EXT_MAP("ssaia", RISCV_ISA_EXT_SSAIA)
SET_ISA_EXT_MAP("zba", RISCV_ISA_EXT_ZBA)
SET_ISA_EXT_MAP("zbs", RISCV_ISA_EXT_ZBS)
SET_ISA_EXT_MAP("zicntr", RISCV_ISA_EXT_ZICNTR)
SET_ISA_EXT_MAP("zicsr", RISCV_ISA_EXT_ZICSR)
SET_ISA_EXT_MAP("zifencei", RISCV_ISA_EXT_ZIFENCEI)
SET_ISA_EXT_MAP("zihpm", RISCV_ISA_EXT_ZIHPM)
if(!maskset) {
printBug("parse_multi_letter_extension: Unknown multi-letter extension: %s", multi_letter_extension);
return -1;
}
return multi_letter_extension_len;
}
bool valid_extension(char ext) {
bool found = false;
uint64_t idx = 0;
while(idx < sizeof(extension_list)/sizeof(extension_list[0]) && !found) {
found = (extension_list[idx].id == (ext - 'a'));
if(!found) idx++;
}
return found;
}
struct extensions* get_extensions_from_str(char* str) {
struct extensions* ext = emalloc(sizeof(struct extensions));
ext->mask = 0;
ext->str = NULL;
if(str == NULL) {
return ext;
}
int len = sizeof(char) * (strlen(str)+1);
ext->str = emalloc(sizeof(char) * len);
memset(ext->str, 0, len);
strncpy(ext->str, str, sizeof(char) * len);
// Code inspired in Linux kernel (riscv_fill_hwcap):
// https://elixir.bootlin.com/linux/v6.2.10/source/arch/riscv/kernel/cpufeature.c
char* isa = str;
if (!strncmp(isa, "rv32", 4))
isa += 4;
else if (!strncmp(isa, "rv64", 4))
isa += 4;
else {
printBug("get_extensions_from_str: ISA string must start with rv64 or rv32");
return ext;
}
for(char* e = isa; *e != '\0'; e++) {
if(*e == '_') {
// Multi-letter extension
int multi_letter_extension_len = parse_multi_letter_extension(ext, e);
if(multi_letter_extension_len == -1) {
return ext;
}
e += multi_letter_extension_len;
}
else {
// Single-letter extensions 's' and 'u' are invalid
// according to Linux kernel (arch/riscv/kernel/cpufeature.c:
// riscv_fill_hwcap). Optionally, we could opt for using
// hwcap instead of cpuinfo to avoid this
if (*e == 's' || *e == 'u') {
continue;
}
// Make sure that the extension is valid before
// adding it to the mask
if(valid_extension(*e)) {
int n = *e - 'a';
ext->mask |= 1UL << n;
}
else {
printBug("get_extensions_from_str: Invalid extension: '%c'", *e);
}
}
}
return ext;
}
struct cpuInfo* get_cpu_info(void) {
struct cpuInfo* cpu = malloc(sizeof(struct cpuInfo));
//init_cpu_info(cpu);
struct topology* topo = emalloc(sizeof(struct topology));
topo->total_cores = get_ncores_from_cpuinfo();
topo->cach = NULL;
cpu->topo = topo;
char* cpuinfo_str = get_uarch_from_cpuinfo();
char* ext_str = get_extensions_from_cpuinfo();
cpu->hv = emalloc(sizeof(struct hypervisor));
cpu->hv->present = false;
cpu->ext = get_extensions_from_str(ext_str);
if(cpu->ext->str != NULL && cpu->ext->mask == 0) return NULL;
cpu->arch = get_uarch_from_cpuinfo_str(cpuinfo_str, cpu);
cpu->soc = get_soc();
cpu->freq = get_frequency_info(0);
cpu->peak_performance = get_peak_performance(cpu);
return cpu;
}
//TODO: Might be worth refactoring with other archs
char* get_str_topology(struct cpuInfo* cpu, struct topology* topo) {
uint32_t size = 3+7+1;
char* string = emalloc(sizeof(char)*size);
snprintf(string, size, "%d cores", topo->total_cores);
return string;
}
char* get_str_extensions(struct cpuInfo* cpu) {
if(cpu->ext != NULL) {
return cpu->ext->str;
}
return NULL;
}
void print_debug(struct cpuInfo* cpu) {
printf("- soc: ");
if(cpu->soc->raw_name == NULL) {
printf("NULL\n");
}
else {
printf("'%s'\n", cpu->soc->raw_name);
}
printf("- uarch: ");
char* arch_cpuinfo_str = get_arch_cpuinfo_str(cpu);
if(arch_cpuinfo_str == NULL) {
printf("NULL\n");
}
else {
printf("'%s'\n", arch_cpuinfo_str);
}
}

82
src/riscv/riscv.h
View File

@@ -1,82 +0,0 @@
#ifndef __RISCV__
#define __RISCV__
#include "../common/cpu.h"
struct extension {
int id;
char* str;
};
#define RISCV_ISA_EXT_NAME_LEN_MAX 32
#define RISCV_ISA_EXT_BASE 26
// https://elixir.bootlin.com/linux/latest/source/arch/riscv/include/asm/hwcap.h
// This enum represent the logical ID for multi-letter RISC-V ISA extensions.
// The logical ID should start from RISCV_ISA_EXT_BASE
enum riscv_isa_ext_id {
RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE,
RISCV_ISA_EXT_SSTC,
RISCV_ISA_EXT_SVINVAL,
RISCV_ISA_EXT_SVPBMT,
RISCV_ISA_EXT_ZBB,
RISCV_ISA_EXT_ZICBOM,
RISCV_ISA_EXT_ZIHINTPAUSE,
RISCV_ISA_EXT_SVNAPOT,
RISCV_ISA_EXT_ZICBOZ,
RISCV_ISA_EXT_SMAIA,
RISCV_ISA_EXT_SSAIA,
RISCV_ISA_EXT_ZBA,
RISCV_ISA_EXT_ZBS,
RISCV_ISA_EXT_ZICNTR,
RISCV_ISA_EXT_ZICSR,
RISCV_ISA_EXT_ZIFENCEI,
RISCV_ISA_EXT_ZIHPM,
RISCV_ISA_EXT_ID_MAX
};
// https://five-embeddev.com/riscv-isa-manual/latest/preface.html#preface
// https://en.wikichip.org/wiki/risc-v/standard_extensions
// Included all except for G
static const struct extension extension_list[] = {
{ 'i' - 'a', "(I) Integer Instruction Set" },
{ 'm' - 'a', "(M) Integer Multiplication and Division" },
{ 'a' - 'a', "(A) Atomic Instructions" },
{ 'f' - 'a', "(F) Single-Precision Floating-Point" },
{ 'd' - 'a', "(D) Double-Precision Floating-Point" },
{ 'q' - 'a', "(Q) Quad-Precision Floating-Point" },
{ 'l' - 'a', "(L) Decimal Floating-Point" },
{ 'c' - 'a', "(C) Compressed Instructions" },
{ 'b' - 'a', "(B) Double-Precision Floating-Point" },
{ 'j' - 'a', "(J) Dynamically Translated Languages" },
{ 't' - 'a', "(T) Transactional Memory" },
{ 'p' - 'a', "(P) Packed-SIMD Instructions" },
{ 'v' - 'a', "(V) Vector Operations" },
{ 'n' - 'a', "(N) User-Level Interrupts" },
{ 'h' - 'a', "(H) Hypervisor" },
// multi-letter extensions
{ RISCV_ISA_EXT_SSCOFPMF, "(Sscofpmf) Count OverFlow and Privilege Mode Filtering" },
{ RISCV_ISA_EXT_SSTC, "(Sstc) S and VS level Time Compare" },
{ RISCV_ISA_EXT_SVINVAL, "(Svinval) Fast TLB Invalidation" },
{ RISCV_ISA_EXT_SVPBMT, "(Svpbmt) Page-based Memory Types" },
{ RISCV_ISA_EXT_ZBB, "(Zbb) Basic bit-manipulation" },
{ RISCV_ISA_EXT_ZICBOM, "(Zicbom) Cache Block Management Operations" },
{ RISCV_ISA_EXT_ZIHINTPAUSE, "(Zihintpause) Pause Hint" },
{ RISCV_ISA_EXT_SVNAPOT, "(Svnapot) Naturally Aligned Power of Two Pages" },
{ RISCV_ISA_EXT_ZICBOZ, "(Zicboz) Cache Block Zero Operations" },
{ RISCV_ISA_EXT_SMAIA, "(Smaia) Advanced Interrupt Architecture" },
{ RISCV_ISA_EXT_SSAIA, "(Ssaia) Advanced Interrupt Architecture" },
{ RISCV_ISA_EXT_ZBA, "(Zba) Address Generation" },
{ RISCV_ISA_EXT_ZBS, "(Zbs) Single-bit Instructions" },
{ RISCV_ISA_EXT_ZICNTR, "(Zicntr) Base Counters and Timers" },
{ RISCV_ISA_EXT_ZICSR, "(Zicsr) Control and Status Register" },
{ RISCV_ISA_EXT_ZIFENCEI, "(Zifencei) Instruction-Fetch Fence" },
{ RISCV_ISA_EXT_ZIHPM, "(Zihpm) Hardware Performance Counters" }
};
struct cpuInfo* get_cpu_info(void);
char* get_str_topology(struct cpuInfo* cpu, struct topology* topo);
char* get_str_extensions(struct cpuInfo* cpu);
void print_debug(struct cpuInfo* cpu);
#endif

93
src/riscv/soc.c
View File

@@ -1,93 +0,0 @@
#include "soc.h"
#include "socs.h"
#include "udev.h"
#include "../common/global.h"
#include <string.h>
bool match_sifive(char* soc_name, struct system_on_chip* soc) {
char* tmp = soc_name;
// Dont know if it makes sense in RISC-V
/*if((tmp = strstr(soc_name, "???")) == NULL)
return false;*/
//soc->soc_vendor = ???
SOC_START
SOC_EQ(tmp, "fu740", "Freedom U740", SOC_SIFIVE_U740, soc, 40)
SOC_END
}
bool match_starfive(char* soc_name, struct system_on_chip* soc) {
SOC_START
SOC_EQ(soc_name, "jh7110#", "VisionFive 2", SOC_STARFIVE_VF2, soc, 28) // https://blog.bitsofnetworks.org/benchmarking-risc-v-visionfive-2-vs-the-world.html
SOC_EQ(soc_name, "jh7110", "VisionFive 2", SOC_STARFIVE_VF2, soc, 28)
SOC_END
}
bool match_allwinner(char* soc_name, struct system_on_chip* soc) {
SOC_START
SOC_EQ(soc_name, "sun20i-d1", "D1-H", SOC_ALLWINNER_D1H, soc, 22)
SOC_END
}
bool match_sipeed(char* soc_name, struct system_on_chip* soc) {
SOC_START
SOC_EQ(soc_name, "light", "Lichee Pi 4A", SOC_SIPEED_LICHEEPI4A, soc, 12) // https://github.com/Dr-Noob/cpufetch/issues/200, https://sipeed.com/licheepi4a
SOC_END
}
struct system_on_chip* parse_soc_from_string(struct system_on_chip* soc) {
char* raw_name = soc->raw_name;
if(match_starfive(raw_name, soc))
return soc;
if(match_allwinner(raw_name, soc))
return soc;
if(match_sifive(raw_name, soc))
return soc;
match_sipeed(raw_name, soc);
return soc;
}
struct system_on_chip* guess_soc_from_devtree(struct system_on_chip* soc) {
char* tmp = get_hardware_from_devtree();
if(tmp != NULL) {
soc->raw_name = tmp;
return parse_soc_from_string(soc);
}
return soc;
}
struct system_on_chip* get_soc(void) {
struct system_on_chip* soc = emalloc(sizeof(struct system_on_chip));
soc->raw_name = NULL;
soc->soc_vendor = SOC_VENDOR_UNKNOWN;
soc->soc_model = SOC_MODEL_UNKNOWN;
soc->process = UNKNOWN;
soc = guess_soc_from_devtree(soc);
if(soc->soc_vendor == SOC_VENDOR_UNKNOWN) {
if(soc->raw_name != NULL) {
printWarn("SoC detection failed using device tree: Found '%s' string", soc->raw_name);
}
else {
printWarn("SoC detection failed using device tree");
}
}
if(soc->soc_model == SOC_MODEL_UNKNOWN) {
// raw_name might not be NULL, but if we were unable to find
// the exact SoC, just print "Unkwnown"
soc->raw_name = emalloc(sizeof(char) * (strlen(STRING_UNKNOWN)+1));
snprintf(soc->raw_name, strlen(STRING_UNKNOWN)+1, STRING_UNKNOWN);
}
return soc;
}

10
src/riscv/soc.h
View File

@@ -1,10 +0,0 @@
#ifndef __SOC_RISCV__
#define __SOC_RISCV__
#include "../common/soc.h"
#include "../common/cpu.h"
#include <stdint.h>
struct system_on_chip* get_soc(void);
#endif

28
src/riscv/socs.h
View File

@@ -1,28 +0,0 @@
#ifndef __SOCS__
#define __SOCS__
#include "soc.h"
// List of supported SOCs
enum {
// SIFIVE
SOC_SIFIVE_U740,
// STARFIVE
SOC_STARFIVE_VF2,
// ALLWINNER
SOC_ALLWINNER_D1H,
// SIPEED
SOC_SIPEED_LICHEEPI4A,
// UNKNOWN
SOC_MODEL_UNKNOWN
};
inline static VENDOR get_soc_vendor_from_soc(SOC soc) {
if(soc >= SOC_SIFIVE_U740 && soc <= SOC_SIFIVE_U740) return SOC_VENDOR_SIFIVE;
if(soc >= SOC_STARFIVE_VF2 && soc <= SOC_STARFIVE_VF2) return SOC_VENDOR_STARFIVE;
if(soc >= SOC_ALLWINNER_D1H && soc <= SOC_ALLWINNER_D1H) return SOC_VENDOR_ALLWINNER;
if(soc >= SOC_SIPEED_LICHEEPI4A && soc <= SOC_SIPEED_LICHEEPI4A) return SOC_VENDOR_SIPEED;
return SOC_VENDOR_UNKNOWN;
}
#endif

84
src/riscv/uarch.c
View File

@@ -1,84 +0,0 @@
#include <stdbool.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "uarch.h"
#include "../common/global.h"
typedef uint32_t MICROARCH;
struct uarch {
MICROARCH uarch;
char* uarch_str;
char* cpuinfo_str;
};
enum {
UARCH_UNKNOWN,
// SIFIVE
UARCH_U54,
UARCH_U74,
// THEAD
UARCH_C906,
UARCH_C910
};
#define UARCH_START if (false) {}
#define CHECK_UARCH(arch, cpu, cpuinfo_str, uarch_str, str, uarch, vendor) \
else if (strcmp(cpuinfo_str, uarch_str) == 0) fill_uarch(arch, cpu, str, uarch, vendor);
#define UARCH_END else { printBug("Unknown microarchitecture detected: uarch='%s'", cpuinfo_str); fill_uarch(arch, cpu, "Unknown", UARCH_UNKNOWN, CPU_VENDOR_UNKNOWN); }
void fill_uarch(struct uarch* arch, struct cpuInfo* cpu, char* str, MICROARCH u, VENDOR vendor) {
arch->uarch = u;
cpu->cpu_vendor = vendor;
arch->uarch_str = emalloc(sizeof(char) * (strlen(str)+1));
strcpy(arch->uarch_str, str);
}
// https://elixir.bootlin.com/linux/latest/source/Documentation/devicetree/bindings/riscv/cpus.yaml
// SiFive: https://www.sifive.com/risc-v-core-ip
// T-Head: https://www.t-head.cn/product/c906
struct uarch* get_uarch_from_cpuinfo_str(char* cpuinfo_str, struct cpuInfo* cpu) {
struct uarch* arch = emalloc(sizeof(struct uarch));
arch->cpuinfo_str = cpuinfo_str;
if(cpuinfo_str == NULL) {
printWarn("get_uarch_from_cpuinfo: Unable to detect microarchitecture, cpuinfo_str is NULL");
fill_uarch(arch, cpu, "Unknown", UARCH_UNKNOWN, CPU_VENDOR_UNKNOWN);
return arch;
}
// U74/U74-MC:
// SiFive says that U74-MC is "Multicore: four U74 cores and one S76 core" while
// U74 is "High performance Linux-capable processor". It's like U74-MC is somehow a small SoC containing
// the U74 and the S76? Then U74-MC is not a microarchitecture per se...
UARCH_START
CHECK_UARCH(arch, cpu, cpuinfo_str, "sifive,bullet0", "U74", UARCH_U74, CPU_VENDOR_SIFIVE) // bullet0 is present in U740, which has U74
// CHECK_UARCH(arch, cpu, cpuinfo_str, "sifive,e5", "XXXXXX", UARCH_U74, CPU_VENDOR_SIFIVE)
// CHECK_UARCH(arch, cpu, cpuinfo_str, "sifive,e7", "XXXXXX", UARCH_U74, CPU_VENDOR_SIFIVE)
// CHECK_UARCH(arch, cpu, cpuinfo_str, "sifive,e71", "XXXXXX", UARCH_U74, CPU_VENDOR_SIFIVE)
// CHECK_UARCH(arch, cpu, cpuinfo_str, "sifive,rocket0", "XXXXXX", UARCH_U74, CPU_VENDOR_SIFIVE)
// CHECK_UARCH(arch, cpu, cpuinfo_str, "sifive,u5", "XXXXXX", UARCH_U74, CPU_VENDOR_SIFIVE)
CHECK_UARCH(arch, cpu, cpuinfo_str, "sifive,u54", "U54", UARCH_U54, CPU_VENDOR_SIFIVE)
// CHECK_UARCH(arch, cpu, cpuinfo_str, "sifive,u7", "XXXXXX", UARCH_U74, CPU_VENDOR_SIFIVE)
CHECK_UARCH(arch, cpu, cpuinfo_str, "sifive,u74", "U74", UARCH_U74, CPU_VENDOR_SIFIVE)
CHECK_UARCH(arch, cpu, cpuinfo_str, "sifive,u74-mc", "U74", UARCH_U74, CPU_VENDOR_SIFIVE)
CHECK_UARCH(arch, cpu, cpuinfo_str, "thead,c906", "T-Head C906", UARCH_C906, CPU_VENDOR_THEAD)
CHECK_UARCH(arch, cpu, cpuinfo_str, "thead,c910", "T-Head C910", UARCH_C910, CPU_VENDOR_THEAD)
UARCH_END
return arch;
}
char* get_str_uarch(struct cpuInfo* cpu) {
return cpu->arch->uarch_str;
}
char* get_arch_cpuinfo_str(struct cpuInfo* cpu) {
return cpu->arch->cpuinfo_str;
}
void free_uarch_struct(struct uarch* arch) {
free(arch->uarch_str);
free(arch);
}

14
src/riscv/uarch.h
View File

@@ -1,14 +0,0 @@
#ifndef __UARCH__
#define __UARCH__
#include <stdint.h>
#include "riscv.h"
struct uarch;
char* get_arch_cpuinfo_str(struct cpuInfo* cpu);
char* get_str_uarch(struct cpuInfo* cpu);
void free_uarch_struct(struct uarch* arch);
struct uarch* get_uarch_from_cpuinfo_str(char* cpuinfo_str, struct cpuInfo* cpu);
#endif

91
src/riscv/udev.c
View File

@@ -1,91 +0,0 @@
#include <errno.h>
#include <string.h>
#include "../common/global.h"
#include "udev.h"
#define _PATH_DEVTREE "/proc/device-tree/compatible"
#define CPUINFO_UARCH_STR "uarch\t\t: "
#define CPUINFO_EXTENSIONS_STR "isa\t\t: "
#define DEVTREE_HARDWARE_FIELD 0
char* get_field_from_devtree(int DEVTREE_FIELD) {
int filelen;
char* buf;
if((buf = read_file(_PATH_DEVTREE, &filelen)) == NULL) {
printWarn("read_file: %s: %s", _PATH_DEVTREE, strerror(errno));
return NULL;
}
// Here we would use strstr to find the comma.
// However, the device-tree file may contain NULL
// bytes in the middle of the string, which would
// cause strstr to return NULL even when there might
// be an occurence after the NULL byte
//
// We iterate the string backwards to find the field
// in position n-DEVTREE_HARDWARE_FIELD where n
// is the number of fields.
int i=0;
char* tmp1 = buf+filelen-1;
do {
tmp1--;
if(*tmp1 == ',') i++;
} while(tmp1 != buf && i <= DEVTREE_FIELD);
if(tmp1 == buf) {
printWarn("get_field_from_devtree: Unable to find field %d", DEVTREE_FIELD);
return NULL;
}
tmp1++;
int strlen = filelen-(tmp1-buf);
char* hardware = emalloc(sizeof(char) * strlen);
memset(hardware, 0, sizeof(char) * strlen);
strncpy(hardware, tmp1, strlen-1);
return hardware;
}
char* parse_cpuinfo_field(char* field_str) {
int filelen;
char* buf;
if((buf = read_file(_PATH_CPUINFO, &filelen)) == NULL) {
printWarn("read_file: %s: %s", _PATH_CPUINFO, strerror(errno));
return NULL;
}
char* tmp = strstr(buf, field_str);
if(tmp == NULL) {
printWarn("parse_cpuinfo_field: Unable to find field %s", field_str);
return NULL;
}
tmp += strlen(field_str);
char* end = strstr(tmp, "\n");
if(end == NULL) {
printWarn("parse_cpuinfo_field: Unable to find newline after field %s", field_str);
return NULL;
}
int ret_strlen = (end-tmp);
char* ret = emalloc(sizeof(char) * (ret_strlen+1));
memset(ret, 0, sizeof(char) * (ret_strlen+1));
strncpy(ret, tmp, ret_strlen);
return ret;
}
char* get_hardware_from_devtree(void) {
return get_field_from_devtree(DEVTREE_HARDWARE_FIELD);
}
char* get_uarch_from_cpuinfo(void) {
return parse_cpuinfo_field(CPUINFO_UARCH_STR);
}
char* get_extensions_from_cpuinfo(void) {
return parse_cpuinfo_field(CPUINFO_EXTENSIONS_STR);
}

12
src/riscv/udev.h
View File

@@ -1,12 +0,0 @@
#ifndef __UDEV_RISCV__
#define __UDEV_RISCV__
#include "../common/udev.h"
#define UNKNOWN -1
char* get_hardware_from_devtree(void);
char* get_uarch_from_cpuinfo(void);
char* get_extensions_from_cpuinfo(void);
#endif

107
src/x86/apic.c
View File

@@ -7,6 +7,8 @@
#elif defined __FreeBSD__
#include <sys/param.h>
#include <sys/cpuset.h>
#elif defined __APPLE__
#define UNUSED(x) (void)(x)
#endif
#include <stdlib.h>
@@ -100,61 +102,6 @@ bool bind_to_cpu(int cpu_id) {
}
#endif
#ifdef __linux__
int get_total_cores_module(int total_cores, int module) {
int total_modules = 2;
int32_t current_module_idx = -1;
bool end = false;
int32_t* core_types = emalloc(sizeof(uint32_t) * total_modules);
for(int i=0; i < total_modules; i++) core_types[i] = -1;
int cores_in_module = 0;
int i = 0;
// Get the original mask to restore it later
cpu_set_t original_mask;
if(sched_getaffinity(0, sizeof(original_mask), &original_mask) == -1) {
printWarn("sched_getaffinity: %s", strerror(errno));
return false;
}
while(!end) {
if(!bind_to_cpu(i)) {
return -1;
}
uint32_t eax = 0x0000001A;
uint32_t ebx = 0;
uint32_t ecx = 0;
uint32_t edx = 0;
cpuid(&eax, &ebx, &ecx, &edx);
int32_t core_type = eax >> 24 & 0xFF;
bool found = false;
for(int j=0; j < total_modules && !found; j++) {
if(core_types[j] == core_type) found = true;
}
if(!found) {
current_module_idx++;
core_types[current_module_idx] = core_type;
}
if(current_module_idx == module) {
cores_in_module++;
if(i+1 == total_cores) end = true;
}
else if(cores_in_module > 0) end = true;
i++;
}
// Reset the original affinity
if (sched_setaffinity (0, sizeof(original_mask), &original_mask) == -1) {
printWarn("sched_setaffinity: %s", strerror(errno));
return false;
}
//printf("Module %d has %d cores\n", module, cores_in_module);
return cores_in_module;
}
#endif
bool fill_topo_masks_apic(struct topology* topo) {
uint32_t eax = 0x00000001;
uint32_t ebx = 0;
@@ -250,14 +197,14 @@ uint32_t max_apic_id_size(uint32_t** cache_id_apic, struct topology* topo) {
uint32_t max = 0;
for(int i=0; i < topo->cach->max_cache_level; i++) {
for(int j=0; j < topo->total_cores_module; j++) {
for(int j=0; j < topo->total_cores; j++) {
if(cache_id_apic[j][i] > max) max = cache_id_apic[j][i];
}
}
max++;
if(max > (uint32_t) topo->total_cores_module) return max;
return topo->total_cores_module;
if(max > (uint32_t) topo->total_cores) return max;
return topo->total_cores;
}
bool build_topo_from_apic(uint32_t* apic_pkg, uint32_t* apic_smt, uint32_t** cache_id_apic, struct topology* topo) {
@@ -272,18 +219,18 @@ bool build_topo_from_apic(uint32_t* apic_pkg, uint32_t* apic_smt, uint32_t** cac
memset(apic_id, 0, sizeof(uint32_t) * size);
// System topology
for(int i=0; i < topo->total_cores_module; i++) {
for(int i=0; i < topo->total_cores; i++) {
sockets[apic_pkg[i]] = 1;
smt[apic_smt[i]] = 1;
}
for(int i=0; i < topo->total_cores_module; i++) {
for(int i=0; i < topo->total_cores; i++) {
if(sockets[i] != 0)
topo->sockets++;
if(smt[i] != 0)
topo->smt_available++;
}
topo->logical_cores = topo->total_cores_module / topo->sockets;
topo->logical_cores = topo->total_cores / topo->sockets;
topo->physical_cores = topo->logical_cores / topo->smt_available;
// Cache topology
@@ -291,7 +238,7 @@ bool build_topo_from_apic(uint32_t* apic_pkg, uint32_t* apic_smt, uint32_t** cac
num_caches = 0;
memset(apic_id, 0, sizeof(uint32_t) * size);
for(int c=0; c < topo->total_cores_module; c++) {
for(int c=0; c < topo->total_cores; c++) {
apic_id[cache_id_apic[c][i]]++;
}
for(uint32_t c=0; c < size; c++) {
@@ -350,10 +297,9 @@ void add_apic_to_array(uint32_t apic, uint32_t* apic_ids, int n) {
}
}
bool fill_apic_ids(uint32_t* apic_ids, int first_core, int n, bool x2apic_id) {
bool fill_apic_ids(uint32_t* apic_ids, int n, bool x2apic_id) {
#ifdef __APPLE__
// macOS extremely dirty approach...
UNUSED(first_core);
printf("cpufetch is computing APIC IDs, please wait...\n");
bool end = false;
uint32_t apic;
@@ -376,12 +322,12 @@ bool fill_apic_ids(uint32_t* apic_ids, int first_core, int n, bool x2apic_id) {
}
#endif
for(int i=first_core; i < first_core+n; i++) {
for(int i=0; i < n; i++) {
if(!bind_to_cpu(i)) {
printErr("Failed binding the process to CPU %d", i);
return false;
}
apic_ids[i-first_core] = get_apic_id(x2apic_id);
apic_ids[i] = get_apic_id(x2apic_id);
}
#ifdef __linux__
@@ -398,12 +344,12 @@ bool fill_apic_ids(uint32_t* apic_ids, int first_core, int n, bool x2apic_id) {
bool get_topology_from_apic(struct cpuInfo* cpu, struct topology* topo) {
uint32_t apic_id;
uint32_t* apic_ids = emalloc(sizeof(uint32_t) * topo->total_cores_module);
uint32_t* apic_pkg = emalloc(sizeof(uint32_t) * topo->total_cores_module);
uint32_t* apic_core = emalloc(sizeof(uint32_t) * topo->total_cores_module);
uint32_t* apic_smt = emalloc(sizeof(uint32_t) * topo->total_cores_module);
uint32_t** cache_smt_id_apic = emalloc(sizeof(uint32_t*) * topo->total_cores_module);
uint32_t** cache_id_apic = emalloc(sizeof(uint32_t*) * topo->total_cores_module);
uint32_t* apic_ids = emalloc(sizeof(uint32_t) * topo->total_cores);
uint32_t* apic_pkg = emalloc(sizeof(uint32_t) * topo->total_cores);
uint32_t* apic_core = emalloc(sizeof(uint32_t) * topo->total_cores);
uint32_t* apic_smt = emalloc(sizeof(uint32_t) * topo->total_cores);
uint32_t** cache_smt_id_apic = emalloc(sizeof(uint32_t*) * topo->total_cores);
uint32_t** cache_id_apic = emalloc(sizeof(uint32_t*) * topo->total_cores);
bool x2apic_id;
if(cpu->maxLevels >= 0x0000000B) {
@@ -421,7 +367,7 @@ bool get_topology_from_apic(struct cpuInfo* cpu, struct topology* topo) {
x2apic_id = false;
}
for(int i=0; i < topo->total_cores_module; i++) {
for(int i=0; i < topo->total_cores; i++) {
cache_smt_id_apic[i] = emalloc(sizeof(uint32_t) * (topo->cach->max_cache_level));
cache_id_apic[i] = emalloc(sizeof(uint32_t) * (topo->cach->max_cache_level));
}
@@ -439,10 +385,10 @@ bool get_topology_from_apic(struct cpuInfo* cpu, struct topology* topo) {
get_cache_topology_from_apic(topo);
if(!fill_apic_ids(apic_ids, cpu->first_core_id, topo->total_cores_module, x2apic_id))
if(!fill_apic_ids(apic_ids, topo->total_cores, x2apic_id))
return false;
for(int i=0; i < topo->total_cores_module; i++) {
for(int i=0; i < topo->total_cores; i++) {
apic_id = apic_ids[i];
apic_pkg[i] = (apic_id & topo->apic->pkg_mask) >> topo->apic->pkg_mask_shift;
@@ -458,19 +404,20 @@ bool get_topology_from_apic(struct cpuInfo* cpu, struct topology* topo) {
/* DEBUG
for(int i=0; i < topo->cach->max_cache_level; i++) {
printf("[CACH %1d]", i);
for(int j=0; j < topo->total_cores_module; j++)
for(int j=0; j < topo->total_cores; j++)
printf("[%03d]", cache_id_apic[j][i]);
printf("\n");
}
for(int i=0; i < topo->total_cores_module; i++)
for(int i=0; i < topo->total_cores; i++)
printf("[%2d] 0x%.8X\n", i, apic_pkg[i]);
printf("\n");
for(int i=0; i < topo->total_cores_module; i++)
for(int i=0; i < topo->total_cores; i++)
printf("[%2d] 0x%.8X\n", i, apic_core[i]);
printf("\n");
for(int i=0; i < topo->total_cores_module; i++)
for(int i=0; i < topo->total_cores; i++)
printf("[%2d] 0x%.8X\n", i, apic_smt[i]);*/
bool ret = build_topo_from_apic(apic_pkg, apic_smt, cache_id_apic, topo);
// Assumption: If we cant get smt_available, we assume it is equal to smt_supported...
@@ -482,7 +429,7 @@ bool get_topology_from_apic(struct cpuInfo* cpu, struct topology* topo) {
free(apic_pkg);
free(apic_core);
free(apic_smt);
for(int i=0; i < topo->total_cores_module; i++) {
for(int i=0; i < topo->total_cores; i++) {
free(cache_smt_id_apic[i]);
free(cache_id_apic[i]);
}

4
src/x86/apic.h
View File

@@ -21,8 +21,4 @@ uint32_t is_smt_enabled_amd(struct topology* topo);
bool bind_to_cpu(int cpu_id);
#endif
#ifdef __linux__
int get_total_cores_module(int total_cores, int module);
#endif
#endif

392
src/x86/cpuid.c
View File

@@ -30,9 +30,6 @@ static const char *hv_vendors_string[] = {
[HV_VENDOR_VMWARE] = "VMwareVMware",
[HV_VENDOR_XEN] = "XenVMMXenVMM",
[HV_VENDOR_PARALLELS] = "lrpepyh vr",
[HV_VENDOR_PHYP] = NULL,
[HV_VENDOR_BHYVE] = "bhyve bhyve ",
[HV_VENDOR_APPLEVZ] = "Apple VZ"
};
static char *hv_vendors_name[] = {
@@ -42,12 +39,11 @@ static char *hv_vendors_name[] = {
[HV_VENDOR_VMWARE] = "VMware",
[HV_VENDOR_XEN] = "Xen",
[HV_VENDOR_PARALLELS] = "Parallels",
[HV_VENDOR_PHYP] = "pHyp",
[HV_VENDOR_BHYVE] = "bhyve",
[HV_VENDOR_APPLEVZ] = "Apple VZ",
[HV_VENDOR_INVALID] = STRING_UNKNOWN
};
#define HYPERVISOR_NAME_MAX_LENGTH 17
#define MASK 0xFF
/*
@@ -74,7 +70,7 @@ void get_name_cpuid(char* name, uint32_t reg1, uint32_t reg2, uint32_t reg3) {
name[c++] = (reg3>>24) & MASK;
}
char* get_str_cpu_name_internal(void) {
char* get_str_cpu_name_internal() {
uint32_t eax = 0;
uint32_t ebx = 0;
uint32_t ecx = 0;
@@ -183,7 +179,7 @@ struct uarch* get_cpu_uarch(struct cpuInfo* cpu) {
return get_uarch_from_cpuid(cpu, eax, efamily, family, emodel, model, (int)stepping);
}
int64_t get_peak_performance(struct cpuInfo* cpu, bool accurate_pp) {
int64_t get_peak_performance(struct cpuInfo* cpu, struct topology* topo, int64_t max_freq, bool accurate_pp) {
/*
* PP = PeakPerformance
* SP = SinglePrecision
@@ -196,17 +192,10 @@ int64_t get_peak_performance(struct cpuInfo* cpu, bool accurate_pp) {
* 16(If AVX512), 8(If AVX), 4(If SSE) *
*/
struct cpuInfo* ptr = cpu;
int64_t total_flops = 0;
for(int i=0; i < cpu->num_cpus; ptr = ptr->next_cpu, i++) {
struct topology* topo = ptr->topo;
int64_t max_freq = get_freq(ptr->freq);
int64_t freq;
#ifdef __linux__
if(accurate_pp)
freq = measure_frequency(ptr);
freq = measure_frequency(cpu);
else
freq = max_freq;
#else
@@ -220,18 +209,17 @@ int64_t get_peak_performance(struct cpuInfo* cpu, bool accurate_pp) {
return -1;
}
struct features* feat = ptr->feat;
int vpus = get_number_of_vpus(ptr);
struct features* feat = cpu->feat;
int vpus = get_number_of_vpus(cpu);
int64_t flops = topo->physical_cores * topo->sockets * (freq*1000000) * vpus;
if(feat->FMA3 || feat->FMA4)
flops = flops*2;
// NOTE:
// Some CPUs (Ice Lake, Zen 4) have AVX512, but they have only
// 1 VPU for AVX512, while they have 2 for AVX2. In such cases,
// we are computing the peak performance supposing AVX2, not AVX512
if(feat->AVX512 && vpus_are_AVX512(ptr))
// Ice Lake has AVX512, but it has 1 VPU for AVX512, while
// it has 2 for AVX2. If this is a Ice Lake CPU, we are computing
// the peak performance supposing AVX2, not AVX512
if(feat->AVX512 && vpus_are_AVX512(cpu))
flops = flops*16;
else if(feat->AVX || feat->AVX2)
flops = flops*8;
@@ -240,13 +228,10 @@ int64_t get_peak_performance(struct cpuInfo* cpu, bool accurate_pp) {
// See https://sites.utexas.edu/jdm4372/2018/01/22/a-peculiar-
// throughput-limitation-on-intels-xeon-phi-x200-knights-landing/
if(is_knights_landing(ptr))
if(is_knights_landing(cpu))
flops = flops * 6 / 7;
total_flops += flops;
}
return total_flops;
return flops;
}
struct hypervisor* get_hp_info(bool hv_present) {
@@ -265,11 +250,6 @@ struct hypervisor* get_hp_info(bool hv_present) {
cpuid(&eax, &ebx, &ecx, &edx);
if(ebx == 0x0 && ecx == 0x0 && edx == 0x0) {
hv->hv_vendor = HV_VENDOR_INVALID;
printWarn("Hypervisor vendor is empty");
}
else {
char name[13];
memset(name, 0, 13);
get_name_cpuid(name, ebx, ecx, edx);
@@ -278,7 +258,7 @@ struct hypervisor* get_hp_info(bool hv_present) {
uint8_t len = sizeof(hv_vendors_string) / sizeof(hv_vendors_string[0]);
for(uint8_t v=0; v < len && !found; v++) {
if(hv_vendors_string[v] != NULL && strcmp(hv_vendors_string[v], name) == 0) {
if(strcmp(hv_vendors_string[v], name) == 0) {
hv->hv_vendor = v;
found = true;
}
@@ -286,8 +266,7 @@ struct hypervisor* get_hp_info(bool hv_present) {
if(!found) {
hv->hv_vendor = HV_VENDOR_INVALID;
printBug("Unknown hypervisor vendor: '%s'", name);
}
printWarn("Unknown hypervisor vendor: %s", name);
}
hv->hv_name = hv_vendors_name[hv->hv_vendor];
@@ -295,19 +274,51 @@ struct hypervisor* get_hp_info(bool hv_present) {
return hv;
}
struct features* get_features_info(struct cpuInfo* cpu) {
uint32_t eax = 0;
uint32_t ebx = 0;
uint32_t ecx = 0;
uint32_t edx = 0;
struct cpuInfo* get_cpu_info() {
struct cpuInfo* cpu = emalloc(sizeof(struct cpuInfo));
struct features* feat = emalloc(sizeof(struct features));
cpu->feat = feat;
cpu->peak_performance = -1;
cpu->topo = NULL;
cpu->cach = NULL;
bool *ptr = &(feat->AES);
for(uint32_t i = 0; i < sizeof(struct features)/sizeof(bool); i++, ptr++) {
*ptr = false;
}
uint32_t eax = 0;
uint32_t ebx = 0;
uint32_t ecx = 0;
uint32_t edx = 0;
//Get max cpuid level
cpuid(&eax, &ebx, &ecx, &edx);
cpu->maxLevels = eax;
//Fill vendor
char name[13];
memset(name,0,13);
get_name_cpuid(name, ebx, edx, ecx);
if(strcmp(CPU_VENDOR_INTEL_STRING,name) == 0)
cpu->cpu_vendor = CPU_VENDOR_INTEL;
else if (strcmp(CPU_VENDOR_AMD_STRING,name) == 0)
cpu->cpu_vendor = CPU_VENDOR_AMD;
else {
cpu->cpu_vendor = CPU_VENDOR_INVALID;
printErr("Unknown CPU vendor: %s", name);
return NULL;
}
//Get max extended level
eax = 0x80000000;
ebx = 0;
ecx = 0;
edx = 0;
cpuid(&eax, &ebx, &ecx, &edx);
cpu->maxExtendedLevels = eax;
//Fill instructions support
if (cpu->maxLevels >= 0x00000001){
eax = 0x00000001;
@@ -362,132 +373,13 @@ struct features* get_features_info(struct cpuInfo* cpu) {
printWarn("Can't read features information from cpuid (needed extended level is 0x%.8X, max is 0x%.8X)", 0x80000001, cpu->maxExtendedLevels);
}
return feat;
}
bool set_cpu_module(int m, int total_modules, int32_t* first_core) {
if(total_modules > 1) {
#ifdef __APPLE__
UNUSED(m);
printBug("Hybrid architectures are not supported under macOS");
return false;
#else
// We have a hybrid architecture.
// 1. Find the first core from module m
int32_t core_id = -1;
int32_t currrent_module_idx = -1;
int32_t* core_types = emalloc(sizeof(uint32_t) * total_modules);
for(int i=0; i < total_modules; i++) core_types[i] = -1;
int i = 0;
while(core_id == -1) {
if(!bind_to_cpu(i)) {
return false;
}
uint32_t eax = 0x0000001A;
uint32_t ebx = 0;
uint32_t ecx = 0;
uint32_t edx = 0;
cpuid(&eax, &ebx, &ecx, &edx);
int32_t core_type = eax >> 24 & 0xFF;
bool found = false;
for(int j=0; j < total_modules && !found; j++) {
if(core_types[j] == core_type) found = true;
}
if(!found) {
currrent_module_idx++;
core_types[currrent_module_idx] = core_type;
if(currrent_module_idx == m) {
core_id = i;
}
}
i++;
}
*first_core = core_id;
//printf("Module %d: Core %d\n", m, core_id);
// 2. Now bind to that core
if(!bind_to_cpu(core_id)) {
return false;
}
#endif
}
else {
// This is a normal architecture
*first_core = 0;
}
return true;
}
int32_t get_core_type(void) {
uint32_t eax = 0x0000001A;
uint32_t ebx = 0;
uint32_t ecx = 0;
uint32_t edx = 0;
eax = 0x0000001A;
cpuid(&eax, &ebx, &ecx, &edx);
int32_t type = eax >> 24 & 0xFF;
if(type == 0x20) return CORE_TYPE_EFFICIENCY;
else if(type == 0x40) return CORE_TYPE_PERFORMANCE;
else {
printErr("Found invalid core type: 0x%.8X\n", type);
return CORE_TYPE_UNKNOWN;
}
}
struct cpuInfo* get_cpu_info(void) {
struct cpuInfo* cpu = emalloc(sizeof(struct cpuInfo));
cpu->peak_performance = -1;
cpu->next_cpu = NULL;
cpu->topo = NULL;
cpu->cach = NULL;
cpu->feat = NULL;
uint32_t modules = 1;
uint32_t eax = 0;
uint32_t ebx = 0;
uint32_t ecx = 0;
uint32_t edx = 0;
//Get max cpuid level
cpuid(&eax, &ebx, &ecx, &edx);
cpu->maxLevels = eax;
//Fill vendor
char name[13];
memset(name,0,13);
get_name_cpuid(name, ebx, edx, ecx);
if(strcmp(CPU_VENDOR_INTEL_STRING,name) == 0)
cpu->cpu_vendor = CPU_VENDOR_INTEL;
else if (strcmp(CPU_VENDOR_AMD_STRING,name) == 0)
cpu->cpu_vendor = CPU_VENDOR_AMD;
else {
cpu->cpu_vendor = CPU_VENDOR_INVALID;
printErr("Unknown CPU vendor: %s", name);
return NULL;
}
//Get max extended level
eax = 0x80000000;
ebx = 0;
ecx = 0;
edx = 0;
cpuid(&eax, &ebx, &ecx, &edx);
cpu->maxExtendedLevels = eax;
if (cpu->maxExtendedLevels >= 0x80000004){
cpu->cpu_name = get_str_cpu_name_internal();
}
else {
cpu->cpu_name = NULL;
printWarn("Can't read CPU name from cpuid (needed extended level is 0x%.8X, max is 0x%.8X)", 0x80000004, cpu->maxExtendedLevels);
cpu->cpu_name = emalloc(sizeof(char) * (strlen(STRING_UNKNOWN) + 1));
strcpy(cpu->cpu_name, STRING_UNKNOWN);
printWarn("Can't read cpu name from cpuid (needed extended level is 0x%.8X, max is 0x%.8X)", 0x80000004, cpu->maxExtendedLevels);
}
cpu->topology_extensions = false;
@@ -497,71 +389,19 @@ struct cpuInfo* get_cpu_info(void) {
cpu->topology_extensions = (ecx >> 22) & 1;
}
cpu->hybrid_flag = false;
if(cpu->cpu_vendor == CPU_VENDOR_INTEL && cpu->maxLevels >= 0x00000007) {
eax = 0x00000007;
ecx = 0x00000000;
cpuid(&eax, &ebx, &ecx, &edx);
cpu->hybrid_flag = (edx >> 15) & 0x1;
}
if(cpu->hybrid_flag) modules = 2;
struct cpuInfo* ptr = cpu;
for(uint32_t i=0; i < modules; i++) {
int32_t first_core;
set_cpu_module(i, modules, &first_core);
if(i > 0) {
ptr->next_cpu = emalloc(sizeof(struct cpuInfo));
ptr = ptr->next_cpu;
ptr->next_cpu = NULL;
ptr->peak_performance = -1;
ptr->topo = NULL;
ptr->cach = NULL;
ptr->feat = NULL;
// We assume that this cores have the
// same cpuid capabilities
ptr->cpu_vendor = cpu->cpu_vendor;
ptr->maxLevels = cpu->maxLevels;
ptr->maxExtendedLevels = cpu->maxExtendedLevels;
ptr->hybrid_flag = cpu->hybrid_flag;
}
if(cpu->hybrid_flag) {
// Detect core type
eax = 0x0000001A;
cpuid(&eax, &ebx, &ecx, &edx);
ptr->core_type = get_core_type();
}
ptr->first_core_id = first_core;
ptr->feat = get_features_info(ptr);
ptr->arch = get_cpu_uarch(ptr);
ptr->freq = get_frequency_info(ptr);
if (cpu->cpu_name == NULL && ptr == cpu) {
// If we couldnt read CPU name from cpuid, infer it now
cpu->cpu_name = infer_cpu_name_from_uarch(cpu->arch);
}
// If any field of the struct is NULL,
// return early, as next functions
// require non NULL fields in cach and topo
ptr->cach = get_cache_info(ptr);
if(ptr->cach == NULL) return cpu;
// return inmideately, as further functions
// require valid fields (cach, topo, etc)
cpu->arch = get_cpu_uarch(cpu);
cpu->freq = get_frequency_info(cpu);
if(cpu->hybrid_flag) {
ptr->topo = get_topology_info(ptr, ptr->cach, i);
}
else {
ptr->topo = get_topology_info(ptr, ptr->cach, -1);
}
cpu->cach = get_cache_info(cpu);
if(cpu->cach == NULL) return cpu;
cpu->topo = get_topology_info(cpu, cpu->cach);
if(cpu->topo == NULL) return cpu;
}
cpu->num_cpus = modules;
cpu->peak_performance = get_peak_performance(cpu, accurate_pp());
cpu->peak_performance = get_peak_performance(cpu, cpu->topo, get_freq(cpu->freq), accurate_pp());
return cpu;
}
@@ -640,7 +480,6 @@ bool get_cache_topology_amd(struct cpuInfo* cpu, struct topology* topo) {
return true;
}
#ifdef __linux__
void get_topology_from_udev(struct topology* topo) {
// TODO: To be improved in the future
topo->total_cores = get_ncores_from_cpuinfo();
@@ -650,11 +489,10 @@ void get_topology_from_udev(struct topology* topo) {
topo->smt_supported = 1;
topo->sockets = 1;
}
#endif
// Main reference: https://software.intel.com/content/www/us/en/develop/articles/intel-64-architecture-processor-topology-enumeration.html
// Very interesting resource: https://wiki.osdev.org/Detecting_CPU_Topology_(80x86)
struct topology* get_topology_info(struct cpuInfo* cpu, struct cache* cach, int module) {
struct topology* get_topology_info(struct cpuInfo* cpu, struct cache* cach) {
struct topology* topo = emalloc(sizeof(struct topology));
init_topology_struct(topo, cach);
@@ -678,18 +516,6 @@ struct topology* get_topology_info(struct cpuInfo* cpu, struct cache* cach, int
}
#endif
if(cpu->hybrid_flag) {
#ifdef __linux__
topo->total_cores_module = get_total_cores_module(topo->total_cores, module);
#else
UNUSED(module);
topo->total_cores_module = topo->total_cores;
#endif
}
else {
topo->total_cores_module = topo->total_cores;
}
switch(cpu->cpu_vendor) {
case CPU_VENDOR_INTEL:
if (cpu->maxLevels >= 0x00000004) {
@@ -1093,37 +919,17 @@ void print_debug(struct cpuInfo* cpu) {
if(cpu->cpu_vendor == CPU_VENDOR_AMD) {
printf("- AMD topology extensions: %d\n", cpu->topology_extensions);
}
if(cpu->cpu_vendor == CPU_VENDOR_INTEL) {
printf("- Hybrid Flag: %d\n", cpu->hybrid_flag);
}
printf("- CPUID dump: 0x%.8X\n", eax);
free_cpuinfo_struct(cpu);
}
void print_raw_level(uint32_t reg) {
uint32_t eax = reg;
uint32_t ebx = 0;
uint32_t ecx = 0;
uint32_t edx = 0;
cpuid(&eax, &ebx, &ecx, &edx);
printf(" 0x%.8X 0x%.2X: 0x%.8X 0x%.8X 0x%.8X 0x%.8X\n", reg, 0x00, eax, ebx, ecx, edx);
}
void print_raw_sublevel(uint32_t reg, uint32_t reg2) {
uint32_t eax = reg;
uint32_t ebx = 0;
uint32_t ecx = reg2;
uint32_t edx = 0;
cpuid(&eax, &ebx, &ecx, &edx);
printf(" 0x%.8X 0x%.2X: 0x%.8X 0x%.8X 0x%.8X 0x%.8X\n", reg, reg2, eax, ebx, ecx, edx);
}
// TODO: Query HV and Xeon Phi levels
void print_raw(struct cpuInfo* cpu) {
uint32_t eax;
uint32_t ebx;
uint32_t ecx;
uint32_t edx;
printf("%s\n\n", cpu->cpu_name);
printf(" CPUID leaf sub EAX EBX ECX EDX \n");
printf("--------------------------------------------------------------\n");
@@ -1138,40 +944,66 @@ void print_raw(struct cpuInfo* cpu) {
printf("CPU %d:\n", c);
// Standard levels
for(uint32_t reg=0x00000000; reg <= cpu->maxLevels; reg++) {
if(reg == 0x00000004) {
for(uint32_t reg2=0x00000000; reg2 < cpu->cach->max_cache_level; reg2++) {
print_raw_sublevel(reg, reg2);
eax = reg;
ebx = 0;
ecx = reg2;
edx = 0;
cpuid(&eax, &ebx, &ecx, &edx);
printf(" 0x%.8X 0x%.2X: 0x%.8X 0x%.8X 0x%.8X 0x%.8X\n", reg, reg2, eax, ebx, ecx, edx);
}
}
else if(reg == 0x0000000B) {
for(uint32_t reg2=0x00000000; reg2 < cpu->topo->smt_supported; reg2++) {
print_raw_sublevel(reg, reg2);
eax = reg;
ebx = 0;
ecx = reg2;
edx = 0;
cpuid(&eax, &ebx, &ecx, &edx);
printf(" 0x%.8X 0x%.2X: 0x%.8X 0x%.8X 0x%.8X 0x%.8X\n", reg, reg2, eax, ebx, ecx, edx);
}
}
else {
print_raw_level(reg);
}
}
eax = reg;
ebx = 0;
ecx = 0;
edx = 0;
// Hypervisor levels
for(uint32_t reg=0x40000000; reg <= 0x40000006; reg++) {
print_raw_level(reg);
}
cpuid(&eax, &ebx, &ecx, &edx);
// Extended levels
printf(" 0x%.8X 0x%.2X: 0x%.8X 0x%.8X 0x%.8X 0x%.8X\n", reg, 0x00, eax, ebx, ecx, edx);
}
}
for(uint32_t reg=0x80000000; reg <= cpu->maxExtendedLevels; reg++) {
if(reg == 0x8000001D) {
for(uint32_t reg2=0x00000000; reg2 < cpu->cach->max_cache_level; reg2++) {
print_raw_sublevel(reg, reg2);
eax = reg;
ebx = 0;
ecx = reg2;
edx = 0;
cpuid(&eax, &ebx, &ecx, &edx);
printf(" 0x%.8X 0x%.2X: 0x%.8X 0x%.8X 0x%.8X 0x%.8X\n", reg, reg2, eax, ebx, ecx, edx);
}
}
else {
print_raw_level(reg);
}
}
eax = reg;
ebx = 0;
ecx = 0;
edx = 0;
cpuid(&eax, &ebx, &ecx, &edx);
printf(" 0x%.8X 0x%.2X: 0x%.8X 0x%.8X 0x%.8X 0x%.8X\n", reg, 0x00, eax, ebx, ecx, edx);
}
}
}
}

4
src/x86/cpuid.h
View File

@@ -3,10 +3,10 @@
#include "../common/cpu.h"
struct cpuInfo* get_cpu_info(void);
struct cpuInfo* get_cpu_info();
struct cache* get_cache_info(struct cpuInfo* cpu);
struct frequency* get_frequency_info(struct cpuInfo* cpu);
struct topology* get_topology_info(struct cpuInfo* cpu, struct cache* cach, int module);
struct topology* get_topology_info(struct cpuInfo* cpu, struct cache* cach);
char* get_str_avx(struct cpuInfo* cpu);
char* get_str_sse(struct cpuInfo* cpu);

3
src/x86/freq/freq.h
View File

@@ -3,10 +3,9 @@
#include <stdint.h>
#include "../../common/cpu.h"
#include "../../common/global.h"
#define MEASURE_TIME_SECONDS 5
#define LOOP_ITERS 100000000
#define LOOP_ITERS 1000000000
int64_t measure_frequency(struct cpuInfo* cpu);

24
src/x86/freq/freq_avx.c
View File

@@ -10,31 +10,18 @@
#include <stdint.h>
#include "freq.h"
void* compute_avx(void * pthread_arg) {
UNUSED(pthread_arg);
void* compute_avx() {
bool end = false;
struct timeval begin, now;
__m256 a[8];
__m256 b[8];
for(int i=0; i < 8; i++) {
a[i] = _mm256_set1_ps(1.5);
b[i] = _mm256_set1_ps(1.2);
}
__m256 a = _mm256_set1_ps(1.5);
__m256 b = _mm256_set1_ps(1.2);
gettimeofday(&begin, NULL);
while(!end) {
for(uint64_t i=0; i < LOOP_ITERS; i++) {
a[0] = _mm256_add_ps(a[0], b[0]);
a[1] = _mm256_add_ps(a[1], b[1]);
a[2] = _mm256_add_ps(a[2], b[2]);
a[3] = _mm256_add_ps(a[3], b[3]);
a[4] = _mm256_add_ps(a[4], b[4]);
a[5] = _mm256_add_ps(a[5], b[5]);
a[6] = _mm256_add_ps(a[6], b[6]);
a[7] = _mm256_add_ps(a[7], b[7]);
a = _mm256_add_ps(a, b);
}
gettimeofday(&now, NULL);
@@ -47,8 +34,7 @@ void* compute_avx(void * pthread_arg) {
printf("fopen: %s", strerror(errno));
}
else {
for(int i=0; i < 8; i++)
fprintf(fp, "%f", a[i][0]);
fprintf(fp, "%f", a[0]);
fclose(fp);
}

2
src/x86/freq/freq_avx.h
View File

@@ -1,6 +1,6 @@
#ifndef __FREQ_AVX__
#define __FREQ_AVX__
void* compute_avx(void * pthread_arg);
void* compute_avx();
#endif

9
src/x86/freq/freq_avx512.c
View File

@@ -10,8 +10,13 @@
#include <stdint.h>
#include "freq.h"
void* compute_avx512(void * pthread_arg) {
UNUSED(pthread_arg);
/*
* For AVX512, it seems that multiple independent
* instructions are needed to force the CPU to
* use AVX512 frequency, since with only one instruction
* (as the AVX implementaion) it still uses AVX frequency
*/
void* compute_avx512() {
bool end = false;
struct timeval begin, now;

2
src/x86/freq/freq_avx512.h
View File

@@ -1,6 +1,6 @@
#ifndef __FREQ_AVX512__
#define __FREQ_AVX512__
void* compute_avx512(void * pthread_arg);
void* compute_avx512();
#endif

3
src/x86/freq/freq_nov.c
View File

@@ -10,8 +10,7 @@
#include <stdint.h>
#include "freq.h"
void* compute_nov(void * pthread_arg) {
UNUSED(pthread_arg);
void* compute_nov() {
bool end = false;
struct timeval begin, now;

2
src/x86/freq/freq_nov.h
View File

@@ -1,6 +1,6 @@
#ifndef __FREQ_NO_VECTOR__
#define __FREQ_NO_VECTOR__
void* compute_nov(void * pthread_arg);
void* compute_nov();
#endif

169
src/x86/uarch.c
View File

@@ -48,9 +48,7 @@ enum {
UARCH_UNKNOWN,
// INTEL //
UARCH_P5,
UARCH_P5_MMX,
UARCH_P6_PENTIUM_II,
UARCH_P6_PENTIUM_III,
UARCH_P6,
UARCH_DOTHAN,
UARCH_YONAH,
UARCH_MEROM,
@@ -81,7 +79,7 @@ enum {
UARCH_GOLDMONT_PLUS,
UARCH_TREMONT,
UARCH_LAKEMONT,
UARCH_COFFEE_LAKE,
UARCH_COFFE_LAKE,
UARCH_ITANIUM,
UARCH_KNIGHTS_FERRY,
UARCH_KNIGHTS_CORNER,
@@ -92,8 +90,6 @@ enum {
UARCH_ITANIUM2,
UARCH_ICE_LAKE,
UARCH_TIGER_LAKE,
UARCH_ALDER_LAKE,
UARCH_RAPTOR_LAKE,
// AMD //
UARCH_AM486,
UARCH_AM5X86,
@@ -112,10 +108,7 @@ enum {
UARCH_ZEN,
UARCH_ZEN_PLUS,
UARCH_ZEN2,
UARCH_ZEN3,
UARCH_ZEN3_PLUS,
UARCH_ZEN4,
UARCH_ZEN4C
UARCH_ZEN3
};
struct uarch {
@@ -127,9 +120,7 @@ struct uarch {
#define UARCH_START if (false) {}
#define CHECK_UARCH(arch, ef_, f_, em_, m_, s_, str, uarch, process) \
else if (ef_ == ef && f_ == f && (em_ == NA || em_ == em) && (m_ == NA || m_ == m) && (s_ == NA || s_ == s)) fill_uarch(arch, str, uarch, process);
#define UARCH_END else { printErr("Unknown microarchitecture detected: M=0x%X EM=0x%X F=0x%X EF=0x%X S=0x%X", m, em, f, ef, s); \
fprintf(stderr, "Please see https://github.com/Dr-Noob/cpufetch#61-unknown-microarchitecture-error to know how to report this error\n"); \
fill_uarch(arch, STRING_UNKNOWN, UARCH_UNKNOWN, UNK); }
#define UARCH_END else { printBug("Unknown microarchitecture detected: M=0x%.8X EM=0x%.8X F=0x%.8X EF=0x%.8X S=0x%.8X", m, em, f, ef, s); fill_uarch(arch, STRING_UNKNOWN, UARCH_UNKNOWN, 0); }
void fill_uarch(struct uarch* arch, char* str, MICROARCH u, uint32_t process) {
arch->uarch_str = emalloc(sizeof(char) * (strlen(str)+1));
@@ -147,31 +138,31 @@ struct uarch* get_uarch_from_cpuid_intel(uint32_t ef, uint32_t f, uint32_t em, u
// EM: Extended Model //
// M: Model //
// S: Stepping //
// ------------------------------------------------------------------------------- //
// ----------------------------------------------------------------------------- //
// EF F EM M S //
UARCH_START
CHECK_UARCH(arch, 0, 5, 0, 0, NA, "P5", UARCH_P5, 800)
CHECK_UARCH(arch, 0, 5, 0, 1, NA, "P5", UARCH_P5, 800)
CHECK_UARCH(arch, 0, 5, 0, 2, NA, "P5", UARCH_P5, UNK)
CHECK_UARCH(arch, 0, 5, 0, 3, NA, "P5", UARCH_P5, 600)
CHECK_UARCH(arch, 0, 5, 0, 4, NA, "P5 (MMX)", UARCH_P5_MMX, UNK)
CHECK_UARCH(arch, 0, 5, 0, 7, NA, "P5 (MMX)", UARCH_P5_MMX, UNK)
CHECK_UARCH(arch, 0, 5, 0, 8, NA, "P5 (MMX)", UARCH_P5_MMX, 250)
CHECK_UARCH(arch, 0, 5, 0, 4, NA, "P5 MMX", UARCH_P5, UNK)
CHECK_UARCH(arch, 0, 5, 0, 7, NA, "P5 MMX", UARCH_P5, UNK)
CHECK_UARCH(arch, 0, 5, 0, 8, NA, "P5 MMX", UARCH_P5, 250)
CHECK_UARCH(arch, 0, 5, 0, 9, 0, "Lakemont", UARCH_LAKEMONT, 32)
CHECK_UARCH(arch, 0, 5, 0, 9, NA, "P5 (MMX)", UARCH_P5_MMX, UNK)
CHECK_UARCH(arch, 0, 5, 0, 9, NA, "P5 MMX", UARCH_P5, UNK)
CHECK_UARCH(arch, 0, 5, 0, 10, 0, "Lakemont", UARCH_LAKEMONT, 32)
CHECK_UARCH(arch, 0, 6, 0, 0, NA, "P6 (Pentium II)", UARCH_P6_PENTIUM_II, UNK)
CHECK_UARCH(arch, 0, 6, 0, 1, NA, "P6 (Pentium II)", UARCH_P6_PENTIUM_II, UNK) // process depends on core
CHECK_UARCH(arch, 0, 6, 0, 2, NA, "P6 (Pentium II)", UARCH_P6_PENTIUM_II, UNK)
CHECK_UARCH(arch, 0, 6, 0, 3, NA, "P6 (Klamath)", UARCH_P6_PENTIUM_II, 350) // http://instlatx64.atw.hu.
CHECK_UARCH(arch, 0, 6, 0, 4, NA, "P6 (Pentium II)", UARCH_P6_PENTIUM_II, UNK)
CHECK_UARCH(arch, 0, 6, 0, 5, NA, "P6 (Deschutes)", UARCH_P6_PENTIUM_II, 250) // http://instlatx64.atw.hu.
CHECK_UARCH(arch, 0, 6, 0, 6, NA, "P6 (Dixon)", UARCH_P6_PENTIUM_II, UNK) // http://instlatx64.atw.hu.
CHECK_UARCH(arch, 0, 6, 0, 7, NA, "P6 (Katmai)", UARCH_P6_PENTIUM_III, 250) // Core names from: https://en.wikichip.org/wiki/intel/cpuid. NOTE: Xeon core names are different! https://www.techpowerup.com/cpu-specs/?generation=Intel+Pentium+III+Xeon
CHECK_UARCH(arch, 0, 6, 0, 8, NA, "P6 (Coppermine)", UARCH_P6_PENTIUM_III, 180) // Also: https://en.wikipedia.org/wiki/Pentium_III
CHECK_UARCH(arch, 0, 6, 0, 9, NA, "P6 (Pentium M)", UARCH_P6_PENTIUM_III, 130)
CHECK_UARCH(arch, 0, 6, 0, 10, NA, "P6 (Coppermine T)", UARCH_P6_PENTIUM_III, 180)
CHECK_UARCH(arch, 0, 6, 0, 11, NA, "P6 (Tualatin)", UARCH_P6_PENTIUM_III, 130)
CHECK_UARCH(arch, 0, 6, 0, 0, NA, "P6 Pentium II", UARCH_P6, UNK)
CHECK_UARCH(arch, 0, 6, 0, 1, NA, "P6 Pentium II", UARCH_P6, UNK) // process depends on core
CHECK_UARCH(arch, 0, 6, 0, 2, NA, "P6 Pentium II", UARCH_P6, UNK)
CHECK_UARCH(arch, 0, 6, 0, 3, NA, "P6 Pentium II", UARCH_P6, 350)
CHECK_UARCH(arch, 0, 6, 0, 4, NA, "P6 Pentium II", UARCH_P6, UNK)
CHECK_UARCH(arch, 0, 6, 0, 5, NA, "P6 Pentium II", UARCH_P6, 250)
CHECK_UARCH(arch, 0, 6, 0, 6, NA, "P6 Pentium II", UARCH_P6, UNK)
CHECK_UARCH(arch, 0, 6, 0, 7, NA, "P6 Pentium III", UARCH_P6, 250)
CHECK_UARCH(arch, 0, 6, 0, 8, NA, "P6 Pentium III", UARCH_P6, 180)
CHECK_UARCH(arch, 0, 6, 0, 9, NA, "P6 Pentium M", UARCH_P6, 130)
CHECK_UARCH(arch, 0, 6, 0, 10, NA, "P6 Pentium III", UARCH_P6, 180)
CHECK_UARCH(arch, 0, 6, 0, 11, NA, "P6 Pentium III", UARCH_P6, 130)
CHECK_UARCH(arch, 0, 6, 0, 13, NA, "Dothan", UARCH_DOTHAN, UNK) // process depends on core
CHECK_UARCH(arch, 0, 6, 0, 14, NA, "Yonah", UARCH_YONAH, 65)
CHECK_UARCH(arch, 0, 6, 0, 15, NA, "Merom", UARCH_MEROM, 65)
@@ -233,26 +224,21 @@ struct uarch* get_uarch_from_cpuid_intel(uint32_t ef, uint32_t f, uint32_t em, u
CHECK_UARCH(arch, 0, 6, 8, 12, NA, "Tiger Lake", UARCH_TIGER_LAKE, 10) // instlatx64
CHECK_UARCH(arch, 0, 6, 8, 13, NA, "Tiger Lake", UARCH_TIGER_LAKE, 10) // instlatx64
// CHECK_UARCH(arch, 0, 6, 8, 14, 9, ...) It is not possible to determine uarch only from CPUID dump (can be Kaby Lake or Amber Lake)
// CHECK_UARCH(arch, 0, 6, 8, 14, 10, ...) It is not possible to determine uarch only from CPUID dump (can be Kaby Lake R or Coffee Lake U)
CHECK_UARCH(arch, 0, 6, 8, 14, 10, "Kaby Lake", UARCH_KABY_LAKE, 14) // wikichip
CHECK_UARCH(arch, 0, 6, 8, 14, 11, "Whiskey Lake", UARCH_WHISKEY_LAKE, 14) // wikichip
CHECK_UARCH(arch, 0, 6, 8, 14, 12, "Comet Lake", UARCH_COMET_LAKE, 14) // wikichip
CHECK_UARCH(arch, 0, 6, 9, 6, NA, "Tremont", UARCH_TREMONT, 10) // LX*
CHECK_UARCH(arch, 0, 6, 9, 7, NA, "Alder Lake", UARCH_ALDER_LAKE, 10) // instlatx64 (Alder Lake-S)
CHECK_UARCH(arch, 0, 6, 9, 10, NA, "Alder Lake", UARCH_ALDER_LAKE, 10) // instlatx64 (Alder Lake-P)
CHECK_UARCH(arch, 0, 6, 9, 10, NA, "Tremont", UARCH_TREMONT, 10) // instlatx64
CHECK_UARCH(arch, 0, 6, 9, 12, NA, "Tremont", UARCH_TREMONT, 10) // LX*
CHECK_UARCH(arch, 0, 6, 9, 13, NA, "Sunny Cove", UARCH_SUNNY_COVE, 10) // LX*
CHECK_UARCH(arch, 0, 6, 9, 14, 9, "Kaby Lake", UARCH_KABY_LAKE, 14)
CHECK_UARCH(arch, 0, 6, 9, 14, 10, "Coffee Lake", UARCH_COFFEE_LAKE, 14)
CHECK_UARCH(arch, 0, 6, 9, 14, 11, "Coffee Lake", UARCH_COFFEE_LAKE, 14)
CHECK_UARCH(arch, 0, 6, 9, 14, 12, "Coffee Lake", UARCH_COFFEE_LAKE, 14)
CHECK_UARCH(arch, 0, 6, 9, 14, 13, "Coffee Lake", UARCH_COFFEE_LAKE, 14)
CHECK_UARCH(arch, 0, 6, 9, 14, 10, "Coffee Lake", UARCH_COFFE_LAKE, 14)
CHECK_UARCH(arch, 0, 6, 9, 14, 11, "Coffee Lake", UARCH_COFFE_LAKE, 14)
CHECK_UARCH(arch, 0, 6, 9, 14, 12, "Coffee Lake", UARCH_COFFE_LAKE, 14)
CHECK_UARCH(arch, 0, 6, 9, 14, 13, "Coffee Lake", UARCH_COFFE_LAKE, 14)
CHECK_UARCH(arch, 0, 6, 10, 5, NA, "Comet Lake", UARCH_COMET_LAKE, 14) // wikichip
CHECK_UARCH(arch, 0, 6, 10, 6, NA, "Comet Lake", UARCH_COMET_LAKE, 14) // instlatx64.atw.hu (i7-10710U)
CHECK_UARCH(arch, 0, 6, 10, 7, NA, "Rocket Lake", UARCH_ROCKET_LAKE, 14) // instlatx64.atw.hu (i7-11700K)
CHECK_UARCH(arch, 0, 6, 11, 7, NA, "Raptor Lake", UARCH_RAPTOR_LAKE, 10) // instlatx64.atw.hu (i5-13600K)
CHECK_UARCH(arch, 0, 6, 11, 10, NA, "Raptor Lake", UARCH_RAPTOR_LAKE, 10) // instlatx64.atw.hu (i7-1370P)
CHECK_UARCH(arch, 0, 6, 11, 14, NA, "Alder Lake", UARCH_ALDER_LAKE, 10) // instlatx64.atw.hu (Alder Lake-N)
CHECK_UARCH(arch, 0, 6, 11, 15, NA, "Raptor Lake", UARCH_RAPTOR_LAKE, 10) // instlatx64.atw.hu (i5-13500)
CHECK_UARCH(arch, 0, 11, 0, 0, NA, "Knights Ferry", UARCH_KNIGHTS_FERRY, 45) // found only on en.wikichip.org
CHECK_UARCH(arch, 0, 11, 0, 1, NA, "Knights Corner", UARCH_KNIGHTS_CORNER, 22)
CHECK_UARCH(arch, 0, 15, 0, 0, NA, "Willamette", UARCH_WILLAMETTE, 180)
@@ -265,10 +251,11 @@ struct uarch* get_uarch_from_cpuid_intel(uint32_t ef, uint32_t f, uint32_t em, u
CHECK_UARCH(arch, 1, 15, 0, 1, NA, "Itanium2", UARCH_ITANIUM2, 130)
CHECK_UARCH(arch, 1, 15, 0, 2, NA, "Itanium2", UARCH_ITANIUM2, 130)
UARCH_END
return arch;
}
// Inspired in Todd Allen's decode_uarch_amd
// iNApired in Todd Allen's decode_uarch_amd
struct uarch* get_uarch_from_cpuid_amd(uint32_t ef, uint32_t f, uint32_t em, uint32_t m, int s) {
struct uarch* arch = emalloc(sizeof(struct uarch));
@@ -355,7 +342,6 @@ struct uarch* get_uarch_from_cpuid_amd(uint32_t ef, uint32_t f, uint32_t em, uin
CHECK_UARCH(arch, 6, 15, 6, 5, NA, "Excavator", UARCH_EXCAVATOR, 28) // undocumented, but sample from Alexandros Couloumbis
CHECK_UARCH(arch, 6, 15, 7, 0, NA, "Excavator", UARCH_EXCAVATOR, 28)
CHECK_UARCH(arch, 7, 15, 0, 0, NA, "Jaguar", UARCH_JAGUAR, 28)
CHECK_UARCH(arch, 7, 15, 1, NA, NA, "Jaguar", UARCH_JAGUAR, 14) // instlatx64 (PS4) Normal PS4 is 28nm, Slim and Pro are 16nm
CHECK_UARCH(arch, 7, 15, 2, 6, NA, "Jaguar", UARCH_JAGUAR, 28) // AMD Cato (Xbox One?)
CHECK_UARCH(arch, 7, 15, 3, 0, NA, "Puma 2014", UARCH_PUMA_2014, 28)
CHECK_UARCH(arch, 8, 15, 0, 0, NA, "Zen", UARCH_ZEN, 14) // instlatx64 engr sample
@@ -370,23 +356,9 @@ struct uarch* get_uarch_from_cpuid_amd(uint32_t ef, uint32_t f, uint32_t em, uin
CHECK_UARCH(arch, 8, 15, 6, 0, NA, "Zen 2", UARCH_ZEN2, 7) // undocumented, geekbench.com example
CHECK_UARCH(arch, 8, 15, 6, 8, NA, "Zen 2", UARCH_ZEN2, 7) // found on instlatx64
CHECK_UARCH(arch, 8, 15, 7, 1, NA, "Zen 2", UARCH_ZEN2, 7) // samples from Steven Noonan and instlatx64
CHECK_UARCH(arch, 8, 15, 8, 4, NA, "Zen 2", UARCH_ZEN2, 7) // instlatx64 (Xbox Series X?)
CHECK_UARCH(arch, 8, 15, 9, 0, 2, "Zen 2", UARCH_ZEN2, 7) // Steam Deck (instlatx64)
CHECK_UARCH(arch, 8, 15, 10, 0, NA, "Zen 2", UARCH_ZEN2, 6) // instlatx64
CHECK_UARCH(arch, 10, 15, 0, 1, NA, "Zen 3", UARCH_ZEN3, 7) // instlatx64
CHECK_UARCH(arch, 10, 15, 0, 8, NA, "Zen 3", UARCH_ZEN3, 7) // instlatx64
CHECK_UARCH(arch, 10, 15, 1, 1, NA, "Zen 4", UARCH_ZEN4, 5) // instlatx64
CHECK_UARCH(arch, 10, 15, 1, 8, NA, "Zen 4", UARCH_ZEN4, 5) // instlatx64
CHECK_UARCH(arch, 10, 15, 2, 1, NA, "Zen 3", UARCH_ZEN3, 7) // instlatx64
CHECK_UARCH(arch, 10, 15, 3, NA, NA, "Zen 3", UARCH_ZEN3, 7) // instlatx64
CHECK_UARCH(arch, 10, 15, 4, 4, NA, "Zen 3+", UARCH_ZEN3_PLUS, 6) // instlatx64 (they say it is Zen3...)
CHECK_UARCH(arch, 10, 15, 5, 0, NA, "Zen 3", UARCH_ZEN3, 7) // instlatx64
CHECK_UARCH(arch, 10, 15, 6, 1, 2, "Zen 4", UARCH_ZEN4, 5) // instlatx64
CHECK_UARCH(arch, 10, 15, 7, 4, 1, "Zen 4", UARCH_ZEN4, 4) // instlatx64
CHECK_UARCH(arch, 10, 15, 7, 8, 0, "Zen 4", UARCH_ZEN4, 4) // instlatx64
CHECK_UARCH(arch, 10, 15, 8, NA, NA, "Zen 4", UARCH_ZEN4, 5) // instlatx64 (AMD MI300C)
CHECK_UARCH(arch, 10, 15, 9, NA, NA, "Zen 4", UARCH_ZEN4, 5) // instlatx64 (AMD MI300A)
CHECK_UARCH(arch, 10, 15, 10, NA, NA, "Zen 4c", UARCH_ZEN4C, 5) // instlatx64
UARCH_END
return arch;
@@ -394,16 +366,10 @@ struct uarch* get_uarch_from_cpuid_amd(uint32_t ef, uint32_t f, uint32_t em, uin
struct uarch* get_uarch_from_cpuid(struct cpuInfo* cpu, uint32_t dump, uint32_t ef, uint32_t f, uint32_t em, uint32_t m, int s) {
if(cpu->cpu_vendor == CPU_VENDOR_INTEL) {
struct uarch* arch = emalloc(sizeof(struct uarch));
if(dump == 0x000806E9) {
if (cpu->cpu_name == NULL) {
printErr("Unable to find uarch without CPU name");
fill_uarch(arch, STRING_UNKNOWN, UARCH_UNKNOWN, UNK);
return arch;
}
// It is not possible to determine uarch only from CPUID dump (can be Kaby Lake or Amber Lake)
// See issue https://github.com/Dr-Noob/cpufetch/issues/122
struct uarch* arch = emalloc(sizeof(struct uarch));
if(strstr(cpu->cpu_name, "Y") != NULL) {
fill_uarch(arch, "Amber Lake", UARCH_AMBER_LAKE, 14);
}
@@ -413,73 +379,14 @@ struct uarch* get_uarch_from_cpuid(struct cpuInfo* cpu, uint32_t dump, uint32_t
return arch;
}
else if (dump == 0x000806EA) {
if (cpu->cpu_name == NULL) {
printErr("Unable to find uarch without CPU name");
fill_uarch(arch, STRING_UNKNOWN, UARCH_UNKNOWN, UNK);
return arch;
}
// It is not possible to determine uarch only from CPUID dump (can be Kaby Lake R or Coffee Lake U)
// See issue https://github.com/Dr-Noob/cpufetch/issues/149
if(strstr(cpu->cpu_name, "i5-8250U") != NULL ||
strstr(cpu->cpu_name, "i5-8350U") != NULL ||
strstr(cpu->cpu_name, "i7-8550U") != NULL ||
strstr(cpu->cpu_name, "i7-8650U") != NULL) {
fill_uarch(arch, "Kaby Lake", UARCH_KABY_LAKE, 14);
}
else {
fill_uarch(arch, "Coffee Lake", UARCH_COFFEE_LAKE, 14);
}
return arch;
}
return get_uarch_from_cpuid_intel(ef, f, em, m, s);
}
else
return get_uarch_from_cpuid_amd(ef, f, em, m, s);
}
// If we cannot get the CPU name from CPUID, try to infer it from uarch
char* infer_cpu_name_from_uarch(struct uarch* arch) {
char* cpu_name = NULL;
if (arch == NULL) {
printErr("infer_cpu_name_from_uarch: Unable to find CPU name");
cpu_name = ecalloc(strlen(STRING_UNKNOWN) + 1, sizeof(char));
strcpy(cpu_name, STRING_UNKNOWN);
return cpu_name;
}
char *str = NULL;
if (arch->uarch == UARCH_P5)
str = "Intel Pentium";
else if (arch->uarch == UARCH_P5_MMX)
str = "Intel Pentium MMX";
else if (arch->uarch == UARCH_P6_PENTIUM_II)
str = "Intel Pentium II";
else if (arch->uarch == UARCH_P6_PENTIUM_III)
str = "Intel Pentium III";
else
printErr("Unable to find name from uarch: %d", arch->uarch);
if (str == NULL) {
cpu_name = ecalloc(strlen(STRING_UNKNOWN) + 1, sizeof(char));
strcpy(cpu_name, STRING_UNKNOWN);
}
else {
cpu_name = ecalloc(strlen(str) + 1, sizeof(char));
strcpy(cpu_name, str);
}
return cpu_name;
}
bool vpus_are_AVX512(struct cpuInfo* cpu) {
return cpu->arch->uarch != UARCH_ICE_LAKE &&
cpu->arch->uarch != UARCH_TIGER_LAKE &&
cpu->arch->uarch != UARCH_ZEN4 &&
cpu->arch->uarch != UARCH_ZEN4C;
return cpu->arch->uarch != UARCH_ICE_LAKE && cpu->arch->uarch != UARCH_TIGER_LAKE;
}
bool is_knights_landing(struct cpuInfo* cpu) {
@@ -499,7 +406,7 @@ int get_number_of_vpus(struct cpuInfo* cpu) {
case UARCH_ROCKET_LAKE:
case UARCH_AMBER_LAKE:
case UARCH_WHISKEY_LAKE:
case UARCH_COFFEE_LAKE:
case UARCH_COFFE_LAKE:
case UARCH_PALM_COVE:
case UARCH_KNIGHTS_LANDING:
@@ -507,15 +414,10 @@ int get_number_of_vpus(struct cpuInfo* cpu) {
case UARCH_ICE_LAKE:
case UARCH_TIGER_LAKE:
case UARCH_ALDER_LAKE:
case UARCH_RAPTOR_LAKE:
// AMD
case UARCH_ZEN2:
case UARCH_ZEN3:
case UARCH_ZEN3_PLUS:
case UARCH_ZEN4:
case UARCH_ZEN4C:
return 2;
default:
return 1;
@@ -524,10 +426,8 @@ int get_number_of_vpus(struct cpuInfo* cpu) {
bool choose_new_intel_logo_uarch(struct cpuInfo* cpu) {
switch(cpu->arch->uarch) {
case UARCH_ALDER_LAKE:
case UARCH_ROCKET_LAKE:
case UARCH_TIGER_LAKE:
case UARCH_RAPTOR_LAKE:
return true;
default:
return false;
@@ -545,6 +445,9 @@ char* get_str_process(struct cpuInfo* cpu) {
if(process == UNK) {
snprintf(str, strlen(STRING_UNKNOWN)+1, STRING_UNKNOWN);
}
else if(process > 100) {
sprintf(str, "%.2fum", (double)process/100);
}
else if(process > 0){
sprintf(str, "%dnm", process);
}

1
src/x86/uarch.h
View File

@@ -8,7 +8,6 @@
struct uarch;
struct uarch* get_uarch_from_cpuid(struct cpuInfo* cpu, uint32_t dump, uint32_t ef, uint32_t f, uint32_t em, uint32_t m, int s);
char* infer_cpu_name_from_uarch(struct uarch* arch);
bool vpus_are_AVX512(struct cpuInfo* cpu);
bool is_knights_landing(struct cpuInfo* cpu);
int get_number_of_vpus(struct cpuInfo* cpu);