Completing extension strings...

This follows the same approach of gpufetch (in
6589de971750b7f4e52c0c35c031fe6204cefdba) where, instead of having a
separate struct for long and short names, both gets merged in a single
struct (ATTRIBUTE_INFO)

This indirectly fixes a bug in RISC-V printer where, if the output
was too large and the short name was selected, it could try to print
an out-of-bound value when accessing the ATTRIBUTE_PEAK. The reason is
that the long and short structures didnt have the same length (because
one attribute name was missing in the short struct). This is now fixed
since we have combined both long and short attribute names.

commit 6e8cccde32
Author: Dr-Noob <peibolms@gmail.com>
Date:   Wed Oct 29 21:54:38 2025 +0100

    Reorganize attributes in printer

Makefile

@@ -70,12 +70,27 @@ $(error Aborting compilation)
 
 	OUTPUT=cpufetch
 else
-	# Assume x86_64
+	arch := $(shell cc -dumpmachine)
-	GIT_VERSION := ""
+	arch := $(firstword $(subst -, ,$(arch)))
+
+	ifeq ($(arch), $(filter $(arch), x86_64 amd64 i386 i486 i586 i686))
 		SRC_DIR=src/x86/
 		SOURCE += $(COMMON_SRC) $(SRC_DIR)cpuid.c $(SRC_DIR)apic.c $(SRC_DIR)cpuid_asm.c $(SRC_DIR)uarch.c
 		HEADERS += $(COMMON_HDR) $(SRC_DIR)cpuid.h $(SRC_DIR)apic.h $(SRC_DIR)cpuid_asm.h $(SRC_DIR)uarch.h
 		CFLAGS += -DARCH_X86 -std=c99
+	else ifeq ($(arch), $(filter $(arch), arm aarch64_be aarch64 arm64 armv8b armv8l armv7l armv6l))
+		SRC_DIR=src/arm/
+		SOURCE += $(COMMON_SRC) $(SRC_DIR)midr.c $(SRC_DIR)uarch.c $(SRC_COMMON)soc.c $(SRC_DIR)soc.c $(SRC_COMMON)pci.c $(SRC_DIR)udev.c sve.o
+		HEADERS += $(COMMON_HDR) $(SRC_DIR)midr.h $(SRC_DIR)uarch.h  $(SRC_COMMON)soc.h $(SRC_DIR)soc.h $(SRC_COMMON)pci.h $(SRC_DIR)udev.c $(SRC_DIR)socs.h
+		CFLAGS += -DARCH_ARM -std=c99
+	else
+		# Error lines should not be tabulated because Makefile complains about it
+$(warning Unsupported arch detected: $(arch). See https://github.com/Dr-Noob/cpufetch#1-support)
+$(warning If your architecture is supported but the compilation fails, please open an issue in https://github.com/Dr-Noob/cpufetch/issues)
+$(error Aborting compilation)
+	endif
+
+	GIT_VERSION := ""
 	SANITY_FLAGS += -Wno-pedantic-ms-format
 	OUTPUT=cpufetch.exe
 endif

README.md

@@ -63,7 +63,7 @@ cpufetch is a command-line tool written in C that displays the CPU information i
 | OS          | x86_64 / x86       | ARM                | RISC-V             | PowerPC            |
 |:-----------:|:------------------:|:------------------:|:------------------:|:------------------:|
 | GNU / Linux | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| Windows     | :heavy_check_mark: | :x:                | :x:                | :x:                |
+| Windows     | :heavy_check_mark: | :heavy_check_mark: | :x:                | :x:                |
 | Android     | :heavy_check_mark: | :heavy_check_mark: | :x:                | :x:                |
 | macOS       | :heavy_check_mark: | :heavy_check_mark: | :x:                | :heavy_check_mark: |
 | FreeBSD     | :heavy_check_mark: | :x:                | :x:                | :x:                |

src/arm/midr.c

@@ -11,6 +11,10 @@
   #include "../common/freq.h"
 #elif defined __APPLE__ || __MACH__
   #include "../common/sysctl.h"
+#elif defined _WIN32
+  #define WIN32_LEAN_AND_MEAN
+  #define NOMINMAX
+  #include <windows.h>
 #endif
 
 #include "../common/global.h"
@@ -21,6 +25,60 @@
 #include "uarch.h"
 #include "sve.h"
 
+
+#if defined _WIN32
+// Windows stores processor information in registery at:
+// "HKEY_LOCAL_MACHINE\HARDWARE\DESCRIPTION\System\CentralProcessor"
+// Within this directory, each core will get its own folder with
+// registery entries named `CP ####` that map to ARM system registers.
+// Ex. the MIDR register for core 0 is the `REG_QWORD` at:
+// "HKEY_LOCAL_MACHINE\HARDWARE\DESCRIPTION\System\CentralProcessor\0\CP 4000"
+// The name of these `CP ####`-registers follow their register ID encoding in hexadecimal
+// (op0&1):op1:crn:crm:op2.
+// More registers can be found here:
+// https://developer.arm.com/documentation/ddi0601/2024-06/AArch64-Registers
+// Some important ones:
+// CP 4000: MIDR_EL1
+// CP 4020: ID_AA64PFR0_EL1
+// CP 4021: ID_AA64PFR1_EL1
+// CP 4028: ID_AA64DFR0_EL1
+// CP 4029: ID_AA64DFR1_EL1
+// CP 402C: ID_AA64AFR0_EL1
+// CP 402D: ID_AA64AFR1_EL1
+// CP 4030: ID_AA64ISAR0_EL1
+// CP 4031: ID_AA64ISAR1_EL1
+// CP 4038: ID_AA64MMFR0_EL1
+// CP 4039: ID_AA64MMFR1_EL1
+// CP 403A: ID_AA64MMFR2_EL1
+
+bool read_registry_hklm_int(char* path, char* name, void* value, bool is64) {  
+  DWORD value_len;
+  int reg_type;
+  if (is64) {
+    value_len = sizeof(int64_t);
+    reg_type = RRF_RT_REG_QWORD;
+  }
+  else {
+    value_len = sizeof(int32_t);
+    reg_type = RRF_RT_REG_DWORD;
+  }
+
+  if(RegGetValueA(HKEY_LOCAL_MACHINE, path, name, reg_type, NULL, value, &value_len) != ERROR_SUCCESS) {
+    printBug("Error reading registry entry \"%s\\%s\"", path, name);
+    return false;
+  }
+  return true;
+}
+
+bool get_win32_core_info_int(uint32_t core_index, char* name, void* value, bool is64) {
+  // path + digits
+  uint32_t max_path_size = 45+3+1;
+  char* path = ecalloc(sizeof(char) * max_path_size, sizeof(char));
+  snprintf(path, max_path_size, "HARDWARE\\DESCRIPTION\\System\\CentralProcessor\\%u", core_index);
+  return read_registry_hklm_int(path, name, value, is64);
+}
+#endif
+
 bool cores_are_equal(int c1pos, int c2pos, uint32_t* midr_array, int32_t* freq_array) {
   return midr_array[c1pos] == midr_array[c2pos] && freq_array[c1pos] == freq_array[c2pos];
 }
@@ -208,6 +266,46 @@ struct features* get_features_info(void) {
   feat->NEON = true;
   feat->SVE = false;
   feat->SVE2 = false;
+#elif defined _WIN32
+
+  // CP 4020 maps to the ID_AA64PFR0_EL1 register on Windows
+  // https://developer.arm.com/documentation/ddi0601/2024-06/AArch64-Registers/ID-AA64PFR0-EL1--AArch64-Processor-Feature-Register-0
+  int64_t pfr0 = 0;
+  if(!get_win32_core_info_int(0, "CP 4020", &pfr0, true)) {
+    printWarn("Unable to retrieve PFR0 via registry");
+  }
+  else {
+    // AdvSimd[23:20]
+    // -1: Not available
+    //  0: AdvSimd support
+    //  1: AdvSimd support + FP16
+    int8_t adv_simd = ((int64_t)(pfr0 << (60 - 20)) >> 60);
+    feat->NEON = (adv_simd >= 0);
+
+    // SVE[35:32]
+    feat->SVE = (pfr0 >> 32) & 0xF ? true : false;
+  }
+
+  // Windoes does not expose a registry entry for the ID_AA64ZFR0_EL1 register
+  // this would have mapped to "CP 4024".
+  feat->SVE2 = false;
+
+  // CP 4030 maps to the ID_AA64ISAR0_EL1 register on Windows
+  // https://developer.arm.com/documentation/ddi0601/2024-06/AArch64-Registers/ID-AA64ISAR0-EL1--AArch64-Instruction-Set-Attribute-Register-0
+  int64_t isar0 = 0;
+  if(!get_win32_core_info_int(0, "CP 4030", &isar0, true)) {
+    printWarn("Unable to retrieve ISAR0 via registry");
+  }
+  else {
+    // AES[7:4]
+    feat->AES = (isar0 >> 4) & 0xF ? true : false;
+    // SHA1[11:8]
+    feat->SHA1 = (isar0 >> 8) & 0xF ? true : false;
+    // SHA2[15:12]
+    feat->SHA2 = (isar0 >> 12) & 0xF ? true : false;
+    // CRC32[19:16]
+    feat->CRC32 = (isar0 >> 16) & 0xF ? true : false;
+  }
 #endif  // ifdef __linux__
 
   if (feat->SVE || feat->SVE2) {
@@ -428,6 +526,68 @@ struct cpuInfo* get_cpu_info_mach(struct cpuInfo* cpu) {
 
   return cpu;
 }
+#elif defined _WIN32
+struct cpuInfo* get_cpu_info_windows(struct cpuInfo* cpu) {
+  init_cpu_info(cpu);
+
+  SYSTEM_INFO sys_info;
+  GetSystemInfo(&sys_info);
+  int ncores = sys_info.dwNumberOfProcessors;
+
+  uint32_t* midr_array = emalloc(sizeof(uint32_t) * ncores);
+  int32_t* freq_array = emalloc(sizeof(uint32_t) * ncores);
+  uint32_t* ids_array = emalloc(sizeof(uint32_t) * ncores);
+  for(int i=0; i < ncores; i++) {
+    // Cast from 64 to 32 bit to be able to re-use the pre-existing
+    // functions such as fill_ids_from_midr and cores_are_equal
+    int64_t midr_64;
+    if(!get_win32_core_info_int(i, "CP 4000", &midr_64, true)) {
+      return NULL;
+    }
+    midr_array[i] = midr_64;
+    if(!get_win32_core_info_int(i, "~MHz", &freq_array[i], false)) {
+      return NULL;
+    }
+  }
+
+  uint32_t sockets = fill_ids_from_midr(midr_array, freq_array, ids_array, ncores);
+
+  struct cpuInfo* ptr = cpu;
+  int midr_idx = 0;
+  int tmp_midr_idx = 0;
+  for(uint32_t i=0; i < sockets; i++) {
+    if(i > 0) {
+      ptr->next_cpu = emalloc(sizeof(struct cpuInfo));
+      ptr = ptr->next_cpu;
+      init_cpu_info(ptr);
+
+      tmp_midr_idx = midr_idx;
+      while(cores_are_equal(midr_idx, tmp_midr_idx, midr_array, freq_array)) tmp_midr_idx++;
+      midr_idx = tmp_midr_idx;
+    }
+
+    ptr->midr = midr_array[midr_idx];
+    ptr->arch = get_uarch_from_midr(ptr->midr, ptr);
+
+    ptr->feat = get_features_info();
+    
+    ptr->freq = emalloc(sizeof(struct frequency));
+    ptr->freq->measured = false;
+    ptr->freq->base = freq_array[midr_idx];
+    ptr->freq->max = UNKNOWN_DATA;
+
+    ptr->cach = get_cache_info(ptr);
+    ptr->topo = get_topology_info(ptr, ptr->cach, midr_array, freq_array, i, ncores);
+  }
+
+  cpu->num_cpus = sockets;
+  cpu->hv = emalloc(sizeof(struct hypervisor));
+  cpu->hv->present = false;
+  cpu->soc = get_soc(cpu);
+  cpu->peak_performance = get_peak_performance(cpu);
+
+  return cpu;
+}
 #endif
 
 struct cpuInfo* get_cpu_info(void) {
@@ -438,6 +598,8 @@ struct cpuInfo* get_cpu_info(void) {
     return get_cpu_info_linux(cpu);
   #elif defined __APPLE__ || __MACH__
     return get_cpu_info_mach(cpu);
+  #elif defined _WIN32
+    return get_cpu_info_windows(cpu);
   #endif
 }
 

src/arm/soc.c

@@ -14,6 +14,28 @@
   #include "../common/sysctl.h"
 #endif
 
+#if defined(_WIN32)
+  #define WIN32_LEAN_AND_MEAN
+  #define NOMINMAX
+  #include <windows.h>
+
+// Gets a RRF_RT_REG_SZ-entry from the Windows registry, returning a newly allocated
+// string and its length
+bool read_registry_hklm_sz(char* path, char* value, char** string, LPDWORD length) {
+	// First call to RegGetValueA gets the length of the string and determines how much
+  // memory should be allocated for the new string
+  if(RegGetValueA(HKEY_LOCAL_MACHINE, path, value, RRF_RT_REG_SZ, NULL, NULL, length) != ERROR_SUCCESS) {
+    return false;
+  }
+  *string = ecalloc(*length, sizeof(char));
+  // Second call actually writes the string data
+  if(RegGetValueA(HKEY_LOCAL_MACHINE, path, value, RRF_RT_REG_SZ, NULL, *string, length) != ERROR_SUCCESS) {
+    return false;
+  }
+  return true;
+}
+#endif
+
 #define NA -1
 #define min(a,b) (((a)<(b))?(a):(b))
 #define ARRAY_SIZE(arr)     (sizeof(arr) / sizeof((arr)[0]))
@@ -284,7 +306,21 @@ bool match_mediatek(char* soc_name, struct system_on_chip* soc) {
   soc->vendor = SOC_VENDOR_MEDIATEK;
 
   SOC_START
-  // Dimensity //
+  // TODO
+  // Dimensity 6000 Series //
+  // Dimensity 7000 Series //
+  // Dimensity 8000 Series //
+  // END TODO
+  // Dimensity 9000 Series //
+  SOC_EQ(tmp, "MT6983Z",  "Dimensity 9000",  SOC_MTK_MT6983Z,  soc, 4)
+  SOC_EQ(tmp, "MT8798Z/C","Dimensity 9000",  SOC_MTK_MT8798ZC, soc, 4)
+  SOC_EQ(tmp, "MT6983W",  "Dimensity 9000+", SOC_MTK_MT6983W,  soc, 4)
+  SOC_EQ(tmp, "MT8798Z/T","Dimensity 9000+", SOC_MTK_MT8798ZT, soc, 4)
+  SOC_EQ(tmp, "MT6985W",  "Dimensity 9200+", SOC_MTK_MT6985W,  soc, 4)
+  SOC_EQ(tmp, "MT6985",   "Dimensity 9200",  SOC_MTK_MT6985,   soc, 4)
+  SOC_EQ(tmp, "MT6989",   "Dimensity 9300",  SOC_MTK_MT6989,   soc, 4)
+  SOC_EQ(tmp, "MT8796",   "Dimensity 9300",  SOC_MTK_MT8796,   soc, 4)
+  // Dimensity 1000 //
   SOC_EQ(tmp, "MT6893Z",  "Dimensity 1300",  SOC_MTK_MT6893Z,  soc, 6)
   SOC_EQ(tmp, "MT6893",   "Dimensity 1200",  SOC_MTK_MT6893,   soc, 6)
   SOC_EQ(tmp, "MT6891",   "Dimensity 1100",  SOC_MTK_MT6891,   soc, 6)
@@ -294,12 +330,21 @@ bool match_mediatek(char* soc_name, struct system_on_chip* soc) {
   SOC_EQ(tmp, "MT6885Z",  "Dimensity 1000L", SOC_MTK_MT6885Z,  soc, 7)
   SOC_EQ(tmp, "MT6889Z",  "Dimensity 1000+", SOC_MTK_MT6889Z,  soc, 7)
   SOC_EQ(tmp, "MT6883Z",  "Dimensity 1000C", SOC_MTK_MT6883Z,  soc, 7)
-  SOC_EQ(tmp, "MT6833",   "Dimensity 700",   SOC_MTK_MT6833,   soc, 7)
+  // Dimensity 900
-  SOC_EQ(tmp, "MT6853",   "Dimensity 720",   SOC_MTK_MT6853,   soc, 7)
+  SOC_EQ(tmp, "MT6877V/Z","Dimensity 900",   SOC_MTK_MT6877VZ, soc, 6)
+  SOC_EQ(tmp, "MT6877T"  ,"Dimensity 920",   SOC_MTK_MT6877T,  soc, 6)
+  SOC_EQ(tmp, "MT6855"   ,"Dimensity 930",   SOC_MTK_MT6855,   soc, 6)
+  // Dimensity 800
   SOC_EQ(tmp, "MT6873",   "Dimensity 800",   SOC_MTK_MT6873,   soc, 7)
-  SOC_EQ(tmp, "MT6853V",  "Dimensity 800U",  SOC_MTK_MT6853V,  soc, 7)
+  SOC_EQ(tmp, "MT6853V/T","Dimensity 800U",  SOC_MTK_MT6853VT, soc, 7)
-  SOC_EQ(tmp, "MT6833",   "Dimensity 810",   SOC_MTK_MT6833,   soc, 6)
+  SOC_EQ(tmp, "MT6853T",  "Dimensity 800U",  SOC_MTK_MT6853T,  soc, 7)
+  SOC_EQ(tmp, "MT6833P",  "Dimensity 810",   SOC_MTK_MT6833P,  soc, 6)
+  SOC_EQ(tmp, "MT6833GP", "Dimensity 810",   SOC_MTK_MT6833GP, soc, 6)
+  SOC_EQ(tmp, "MT6833V",  "Dimensity 810",   SOC_MTK_MT6833V,  soc, 6)
   SOC_EQ(tmp, "MT6875",   "Dimensity 820",   SOC_MTK_MT6875,   soc, 7)
+  // Dimensity 700
+  SOC_EQ(tmp, "MT6833",   "Dimensity 700",   SOC_MTK_MT6833,   soc, 7)
+  SOC_EQ(tmp, "MT6853V",  "Dimensity 720",   SOC_MTK_MT6853,   soc, 7)
   // Helio //
   SOC_EQ(tmp, "MT6761D",  "Helio A20",       SOC_MTK_MT6761D,  soc, 12)
   SOC_EQ(tmp, "MT6761",   "Helio A22",       SOC_MTK_MT6761,   soc, 12)
@@ -947,6 +992,7 @@ bool match_dt(struct system_on_chip* soc, char* dt, int filelen, char* expected_
 // substring.
 // TODO: Implement this by going trough NULL-separated fields rather than
 // using strstr.
+// https://trac.gateworks.com/wiki/linux/devicetree
 struct system_on_chip* guess_soc_from_devtree(struct system_on_chip* soc) {
   int len;
   char* dt = get_devtree_compatible(&len);
@@ -970,12 +1016,115 @@ struct system_on_chip* guess_soc_from_devtree(struct system_on_chip* soc) {
   DT_EQ(dt, len, soc, "apple,t6030", "M3 Pro",   SOC_APPLE_M3_PRO,   3)
   DT_EQ(dt, len, soc, "apple,t6031", "M3 Max",   SOC_APPLE_M3_MAX,   3)
   DT_EQ(dt, len, soc, "apple,t6034", "M3 Max",   SOC_APPLE_M3_MAX,   3)
-  // https://github.com/Dr-Noob/cpufetch/issues/261
+  // NVIDIA
-  // https://www.nxp.com/docs/en/fact-sheet/IMX8MPLUSFS.pdf
+  // https://elixir.bootlin.com/linux/v6.10.6/source/arch/arm64/boot/dts/nvidia
-  DT_EQ(dt, len, soc, "imx8mp-nitrogen8mp", "i.MX 8M Plus", SOC_NXP_IMX8MP, 14)
+  // https://elixir.bootlin.com/linux/v6.10.6/source/arch/arm/boot/dts/nvidia
+  DT_EQ(dt, len, soc, "nvidia,tegra20",  "Tegra 2",      SOC_TEGRA_2,      40) // https://en.wikipedia.org/wiki/Tegra#Tegra_2
+  DT_EQ(dt, len, soc, "nvidia,tegra30",  "Tegra 3",      SOC_TEGRA_3,      40) // https://en.wikipedia.org/wiki/Tegra#Tegra_3
+  DT_EQ(dt, len, soc, "nvidia,tegra114", "Tegra 4",      SOC_TEGRA_4,      28) // https://en.wikipedia.org/wiki/Tegra#Tegra_4
+  DT_EQ(dt, len, soc, "nvidia,tegra124", "Tegra K1",     SOC_TEGRA_K1,     28) // https://en.wikipedia.org/wiki/Tegra#Tegra_K1
+  DT_EQ(dt, len, soc, "nvidia,tegra132", "Tegra K1",     SOC_TEGRA_K1,     28) // https://en.wikipedia.org/wiki/Tegra#Tegra_K1
+  DT_EQ(dt, len, soc, "nvidia,tegra210", "Tegra X1",     SOC_TEGRA_X1,     20) // https://en.wikipedia.org/wiki/Tegra#Tegra_X1
+  DT_EQ(dt, len, soc, "nvidia,tegra186", "Tegra X2",     SOC_TEGRA_X2,     16) // https://en.wikipedia.org/wiki/Tegra#Tegra_X2
+  DT_EQ(dt, len, soc, "nvidia,tegra194", "Tegra Xavier", SOC_TEGRA_XAVIER, 12) // https://en.wikipedia.org/wiki/Tegra#Xavier
+  DT_EQ(dt, len, soc, "nvidia,tegra234", "Tegra Orin",   SOC_TEGRA_ORIN,    8) // https://www.phoronix.com/news/NVIDIA-Orin-Tegra234-Audio, https://github.com/Dr-Noob/cpufetch/issues/275, https://en.wikipedia.org/wiki/Tegra#Orin
+  // Qualcomm now also in devtree...
+  // TODO: Integrate this with SOC_EQ
+  DT_EQ(dt, len, soc, "qcom,sc8280", "8cx Gen 3", SOC_SNAPD_SC8280XP, 5)
+  // grep -oR -h --color -E '"fsl,.*' *.dtsi | sort | uniq | cut -d ',' -f1-2 | grep -v '-'
+  // https://elixir.bootlin.com/linux/v6.10.6/source/arch/arm64/boot/dts/freescale    
+  DT_EQ(dt, len, soc, "fsl,imx8qm",  "i.MX 8QuadMax",   SOC_NXP_IMX8QM,  28) // https://www.nxp.com/docs/en/fact-sheet/IMX8FAMFS.pdf  
+  DT_EQ(dt, len, soc, "fsl,imx8qp",  "i.MX 8QuadPlus",  SOC_NXP_IMX8QP,  28) // Actually not in dtsi, compatible string is just a guess
+  DT_EQ(dt, len, soc, "fsl,imx8mp",  "i.MX 8M Plus",    SOC_NXP_IMX8MP,  14) // https://www.nxp.com/docs/en/fact-sheet/IMX8MPLUSFS.pdf https://github.com/Dr-Noob/cpufetch/issues/261
+  DT_EQ(dt, len, soc, "fsl,imx8mn",  "i.MX 8M Nano",    SOC_NXP_IMX8MN,  NA)
+  DT_EQ(dt, len, soc, "fsl,imx8mm",  "i.MX 8M Mini",    SOC_NXP_IMX8MM,  NA) // https://www.nxp.com/docs/en/fact-sheet/IMX8MMINIFS.pdf
+  DT_EQ(dt, len, soc, "fsl,imx8dxp", "i.MX 8DualXPlus", SOC_NXP_IMX8DXP, NA)
+  DT_EQ(dt, len, soc, "fsl,imx8qxp", "i.MX 8QuadXPlus", SOC_NXP_IMX8QXP, NA)
+  DT_EQ(dt, len, soc, "fsl,imx93",   "i.MX 93",         SOC_NXP_IMX93,   NA)  
+  // [1] https://elixir.bootlin.com/linux/v6.10.6/source/arch/arm64/boot/dts/amlogic
+  // [2] https://github.com/Dr-Noob/cpufetch/issues/268
+  // [3] https://www.amlogic.com/#Products/393/index.html
+  // [4] https://wikimovel.com
+  // [5] https://wiki.postmarketos.org/wiki/Amlogic_S905W/S905D/S905X/S905L/S805X/S805Y/S905Z
+  DT_EQ(dt, len, soc, "amlogic,a311d",  "A311D",  SOC_AMLOGIC_A311D,  12) // [1,2,3,4]
+  DT_EQ(dt, len, soc, "amlogic,a311d2", "A311D2", SOC_AMLOGIC_A311D2, 12) // [1,4]
+  DT_EQ(dt, len, soc, "amlogic,s905w",  "S905W",  SOC_AMLOGIC_S905W,  28) // [1,5]
+  DT_EQ(dt, len, soc, "amlogic,s905d",  "S905D",  SOC_AMLOGIC_S905D,  28) // [1,5]
+  DT_EQ(dt, len, soc, "amlogic,s905x",  "S905X",  SOC_AMLOGIC_S905X,  28) // [1,4,5]
+  DT_EQ(dt, len, soc, "amlogic,s805x",  "S805X",  SOC_AMLOGIC_S805X,  28) // [1,5]
+  // Marvell
+  // https://elixir.bootlin.com/linux/v6.10.6/source/arch/arm64/boot/dts/marvell
+  DT_EQ(dt, len, soc, "marvell,armada3700", "Armada 3700", SOC_MARVELL_A3700,  28) // http://wiki.espressobin.net/tiki-index.php?page=Armada+3700 (pdf), https://github.com/Dr-Noob/cpufetch/issues/279
+  DT_EQ(dt, len, soc, "marvell,armada3710", "Armada 3710", SOC_MARVELL_A3710,  28) // https://gzhls.at/blob/ldb/2/7/4/2/6eacf9661c5a2d20c4d7cd3328ffba47bfd6.pdf
+  DT_EQ(dt, len, soc, "marvell,armada3720", "Armada 3720", SOC_MARVELL_A3720,  28) // https://gzhls.at/blob/ldb/2/7/4/2/6eacf9661c5a2d20c4d7cd3328ffba47bfd6.pdf
+  DT_EQ(dt, len, soc, "marvell,armada7200", "Armada 7200", SOC_MARVELL_A7200,  28) // Assuming same manufacturing process as 7400
+  DT_EQ(dt, len, soc, "marvell,armada7400", "Armada 7400", SOC_MARVELL_A7400,  28) // https://www.marvell.com/content/dam/marvell/en/public-collateral/embedded-processors/marvell-embedded-processors-armada-7040-product-brief-2017-12.pdf
+  DT_EQ(dt, len, soc, "marvell,armada8020", "Armada 8020", SOC_MARVELL_A8020,  28) // https://datasheet.datasheetarchive.com/originals/crawler/marvell.com/da7b6a997e49e9e93fa4b1f4cfbed71b.pdf
+  DT_EQ(dt, len, soc, "marvell,armada8040", "Armada 8040", SOC_MARVELL_A8040,  28) // https://www.verical.com/datasheet/marvell-technology-group-application-processors-and-soc-88f8040-a2-bvp4i160-6331367.pdf
+  DT_EQ(dt, len, soc, "marvell,cn9130",     "CN9130",      SOC_MARVELL_CN9130, NA) // https://www.marvell.com/content/dam/marvell/en/public-collateral/embedded-processors/marvell-infrastructure-processors-octeon-tx2-cn913x-product-brief.pdf
+  DT_EQ(dt, len, soc, "marvell,cn9131",     "CN9131",      SOC_MARVELL_CN9131, NA) // https://www.marvell.com/content/dam/marvell/en/public-collateral/embedded-processors/marvell-infrastructure-processors-octeon-tx2-cn913x-product-brief.pdf
+  DT_EQ(dt, len, soc, "marvell,cn9132",     "CN9132",      SOC_MARVELL_CN9132, NA) // https://www.marvell.com/content/dam/marvell/en/public-collateral/embedded-processors/marvell-infrastructure-processors-octeon-tx2-cn913x-product-brief.pdf
   DT_END(dt, len)
 }
 
+// This function is different from the rest guess_soc_from_xxx, which try infering
+// the exact SoC model by matching some string against a list of known values.
+// On the other hand, this function will just try to infer the SoC vendor first by
+// matching the device tree vendor name (i.e., the first value, before the comma).
+// If that is successfull, then it also fills in the SoC name using the string from
+// the device tree.
+// The critical difference is that this function does not need a LUT to fill in the
+// SoC, it just needs to find a known vendor. On the other hand, the detection is
+// less powerful since we cannot get the manufacturing process, and the SoC name will
+// come directly from the device tree, meaning that it will likely be less precise.
+struct system_on_chip* guess_raw_soc_from_devtree(struct system_on_chip* soc) {
+  int num_vendors;
+  struct devtree** dt_vendors = get_devtree_compatible_struct(&num_vendors);
+  if (dt_vendors == NULL) {
+    return soc;
+  }
+
+  typedef struct {
+    char* compatible;
+    VENDOR soc_vendor;
+  } devtreeToVendor;
+
+  // https://elixir.bootlin.com/linux/v6.10.6/source/arch/arm64/boot/dts
+  // grep -oR --color -E 'compatible = ".*"' <soc_vendor> | cut -d '=' -f2 | cut -d ',' -f1 | tr -d '"' | sort | uniq -c | sort
+  // - The following vendors are not included because they dont seem to be present in dts:
+  // SOC_VENDOR_(KIRIN, KUNPENG, GOOGLE, AMPERE).
+  // - The commented vendors are not included intentionally, because I prefer updating its LUT manually.
+  devtreeToVendor socFromDevtree[] = {
+    // {"qcom",       SOC_VENDOR_SNAPDRAGON},
+    // {"samsung",    SOC_VENDOR_EXYNOS},
+    // {"brcm",       SOC_VENDOR_BROADCOM},
+    // {"apple",      SOC_VENDOR_APPLE},
+    // {"rockchip",   SOC_VENDOR_ROCKCHIP},
+    // {"nvidia",     SOC_VENDOR_NVIDIA},
+    {"mediatek",   SOC_VENDOR_MEDIATEK},
+    {"fsl",        SOC_VENDOR_NXP     },
+    {"nxp",        SOC_VENDOR_NXP     },
+    {"amlogic",    SOC_VENDOR_AMLOGIC },
+    {"marvell",    SOC_VENDOR_MARVELL },
+    {NULL,         SOC_VENDOR_UNKNOWN }
+  };
+
+  int index = 0;
+  while (socFromDevtree[index].compatible != 0x0) {
+    for (int i=0; i < num_vendors; i++) {
+      if (strcmp(socFromDevtree[index].compatible, dt_vendors[i]->vendor) == 0) {
+        fill_soc_raw(soc, dt_vendors[i]->model, socFromDevtree[index].soc_vendor);
+        printWarn("Your SoC is unsupported by cpufetch but could still be detected successfully. If you want to help improve the project, please paste the output of 'cpufetch --verbose' on https://github.com/Dr-Noob/cpufetch/issues");
+        return soc;
+      }
+    }
+    index++;
+  }
+
+  printWarn("guess_raw_soc_from_devtree: No device matched the list");
+  return soc;
+}
+
 struct system_on_chip* guess_soc_from_pci(struct system_on_chip* soc, struct cpuInfo* cpu) {
   struct pci_devices * pci = get_pci_devices();
   if (pci == NULL) {
@@ -1202,6 +1351,11 @@ struct system_on_chip* get_soc(struct cpuInfo* cpu) {
     if(soc->vendor == SOC_VENDOR_UNKNOWN) {
       soc = guess_soc_from_pci(soc, cpu);
     }
+    if (soc->vendor == SOC_VENDOR_UNKNOWN) {
+      // If we fall here it means all previous functions failed to detect the SoC.
+      // In such case, try with our last resort. If it also fails, we will just give up
+      soc = guess_raw_soc_from_devtree(soc);
+    }
   }
 #elif defined __APPLE__ || __MACH__
   soc = guess_soc_apple(soc);
@@ -1211,14 +1365,30 @@ struct system_on_chip* get_soc(struct cpuInfo* cpu) {
   else {
     return soc;
   }
-#endif // ifdef __linux__
+#endif
 
-  if(soc->model == SOC_MODEL_UNKNOWN) {
+#if defined _WIN32
-    // raw_name might not be NULL, but if we were unable to find
+  // Use the first core to determine the SoC
-    // the exact SoC, just print "Unkwnown"
+  char* processor_name_string = NULL;
+  unsigned long processor_name_string_len = 0;
+  if(!read_registry_hklm_sz("HARDWARE\\DESCRIPTION\\System\\CentralProcessor\\0", "ProcessorNameString", &processor_name_string, &processor_name_string_len)) {
+    printWarn("Failed to aquire SoC name from registery");
+    return soc;
+  }
+
+  soc->name = processor_name_string;
+  soc->raw_name = processor_name_string;
+  soc->vendor = try_match_soc_vendor_name(processor_name_string);
+  soc->model = SOC_MODEL_UNKNOWN;
+  soc->process = UNKNOWN;
+#else
+  if(soc->raw_name == NULL) {
+    // We were unable to find the SoC, so just initialize raw_name
+    // with the unknown string
     soc->raw_name = emalloc(sizeof(char) * (strlen(STRING_UNKNOWN)+1));
     snprintf(soc->raw_name, strlen(STRING_UNKNOWN)+1, STRING_UNKNOWN);
   }
+#endif 
 
   return soc;
 }

src/arm/socs.h

@@ -192,6 +192,22 @@ enum {
   SOC_MTK_MT9950,
   SOC_MTK_MT9972,
   SOC_MTK_MT9982,
+  SOC_MTK_MT6983Z,
+  SOC_MTK_MT8798ZC,
+  SOC_MTK_MT6983W,
+  SOC_MTK_MT8798ZT,
+  SOC_MTK_MT6985W,
+  SOC_MTK_MT6985,
+  SOC_MTK_MT6989,
+  SOC_MTK_MT8796,
+  SOC_MTK_MT6877VZ,
+  SOC_MTK_MT6877T,
+  SOC_MTK_MT6855,
+  SOC_MTK_MT6853VT,
+  SOC_MTK_MT6853T,
+  SOC_MTK_MT6833P,
+  SOC_MTK_MT6833GP,
+  SOC_MTK_MT6833V,
   // Snapdragon //
   SOC_SNAPD_QSD8650,
   SOC_SNAPD_QSD8250,
@@ -318,6 +334,7 @@ enum {
   SOC_SNAPD_SM8550_AB,
   SOC_SNAPD_SM8635,
   SOC_SNAPD_SM8650_AB,
+  SOC_SNAPD_SC8280XP,
   // APPLE
   SOC_APPLE_M1,
   SOC_APPLE_M1_PRO,
@@ -379,11 +396,44 @@ enum {
   SOC_GOOGLE_TENSOR_G2,
   SOC_GOOGLE_TENSOR_G3,
   // NVIDIA,
+  SOC_TEGRA_2,
+  SOC_TEGRA_3,
+  SOC_TEGRA_4,
+  SOC_TEGRA_K1,
+  SOC_TEGRA_K2,
   SOC_TEGRA_X1,
+  SOC_TEGRA_X2,
+  SOC_TEGRA_XAVIER,
+  SOC_TEGRA_ORIN,
   // ALTRA
   SOC_AMPERE_ALTRA,
   // NXP
+  SOC_NXP_IMX8QM,
+  SOC_NXP_IMX8QP,
   SOC_NXP_IMX8MP,
+  SOC_NXP_IMX8MN,
+  SOC_NXP_IMX8MM,
+  SOC_NXP_IMX8DXP,
+  SOC_NXP_IMX8QXP,
+  SOC_NXP_IMX93,
+  // AMLOGIC
+  SOC_AMLOGIC_A311D,
+  SOC_AMLOGIC_A311D2,
+  SOC_AMLOGIC_S905W,
+  SOC_AMLOGIC_S905D,
+  SOC_AMLOGIC_S905X,
+  SOC_AMLOGIC_S805X,
+  // MARVELL
+  SOC_MARVELL_A3700,
+  SOC_MARVELL_A3710,
+  SOC_MARVELL_A3720,
+  SOC_MARVELL_A7200,
+  SOC_MARVELL_A7400,
+  SOC_MARVELL_A8020,
+  SOC_MARVELL_A8040,
+  SOC_MARVELL_CN9130,
+  SOC_MARVELL_CN9131,
+  SOC_MARVELL_CN9132,
   // UNKNOWN
   SOC_MODEL_UNKNOWN
 };
@@ -393,15 +443,17 @@ inline static VENDOR get_soc_vendor_from_soc(SOC soc) {
   else if(soc >= SOC_HISILICON_3620 && soc <= SOC_HISILICON_9000S) return SOC_VENDOR_KIRIN;
   else if(soc >= SOC_KUNPENG_920 && soc <= SOC_KUNPENG_930) return SOC_VENDOR_KUNPENG;
   else if(soc >= SOC_EXYNOS_3475 && soc <= SOC_EXYNOS_880) return SOC_VENDOR_EXYNOS;
-  else if(soc >= SOC_MTK_MT6893 && soc <= SOC_MTK_MT8783) return SOC_VENDOR_MEDIATEK;
+  else if(soc >= SOC_MTK_MT5327 && soc <= SOC_MTK_MT6833V) return SOC_VENDOR_MEDIATEK;
-  else if(soc >= SOC_SNAPD_QSD8650 && soc <= SOC_SNAPD_SM8650_AB) return SOC_VENDOR_SNAPDRAGON;
+  else if(soc >= SOC_SNAPD_QSD8650 && soc <= SOC_SNAPD_SC8280XP) return SOC_VENDOR_SNAPDRAGON;
   else if(soc >= SOC_APPLE_M1 && soc <= SOC_APPLE_M3_MAX) return SOC_VENDOR_APPLE;
   else if(soc >= SOC_ALLWINNER_A10 && soc <= SOC_ALLWINNER_R328) return SOC_VENDOR_ALLWINNER;
   else if(soc >= SOC_ROCKCHIP_3288 && soc <= SOC_ROCKCHIP_3588) return SOC_VENDOR_ROCKCHIP;
   else if(soc >= SOC_GOOGLE_TENSOR && soc <= SOC_GOOGLE_TENSOR_G3) return SOC_VENDOR_GOOGLE;
-  else if(soc >= SOC_TEGRA_X1 && soc <= SOC_TEGRA_X1) return SOC_VENDOR_NVIDIA;
+  else if(soc >= SOC_TEGRA_2 && soc <= SOC_TEGRA_ORIN) return SOC_VENDOR_NVIDIA;
   else if(soc >= SOC_AMPERE_ALTRA && soc <= SOC_AMPERE_ALTRA) return SOC_VENDOR_AMPERE;
-  else if(soc >= SOC_NXP_IMX8MP && soc <= SOC_NXP_IMX8MP) return SOC_VENDOR_NXP;
+  else if(soc >= SOC_NXP_IMX8QM && soc <= SOC_NXP_IMX93) return SOC_VENDOR_NXP;
+  else if(soc >= SOC_AMLOGIC_A311D && soc <= SOC_AMLOGIC_S805X) return SOC_VENDOR_AMLOGIC;
+  else if(soc >= SOC_MARVELL_A3700 && soc <= SOC_MARVELL_CN9132) return SOC_VENDOR_MARVELL;
   return SOC_VENDOR_UNKNOWN;
 }
 

src/arm/uarch.c

@@ -34,7 +34,8 @@ enum {
   ISA_ARMv8_4_A,
   ISA_ARMv8_5_A,
   ISA_ARMv8_6_A,
-  ISA_ARMv9_A
+  ISA_ARMv9_A,
+  ISA_ARMv9_2_A
 };
 
 static const ISA isas_uarch[] = {
@@ -62,15 +63,26 @@ static const ISA isas_uarch[] = {
   [UARCH_CORTEX_A76]   = ISA_ARMv8_2_A,
   [UARCH_CORTEX_A77]   = ISA_ARMv8_2_A,
   [UARCH_CORTEX_A78]   = ISA_ARMv8_2_A,
+  [UARCH_CORTEX_A78C]  = ISA_ARMv8_2_A,
+  [UARCH_CORTEX_A78AE] = ISA_ARMv8_2_A,
   [UARCH_CORTEX_A510]   = ISA_ARMv9_A,
+  [UARCH_CORTEX_A520]  = ISA_ARMv9_2_A,
   [UARCH_CORTEX_A710]   = ISA_ARMv9_A,
   [UARCH_CORTEX_A715]  = ISA_ARMv9_A,
+  [UARCH_CORTEX_A720]  = ISA_ARMv9_2_A,
+  [UARCH_CORTEX_A725]  = ISA_ARMv9_2_A,
   [UARCH_CORTEX_X1]    = ISA_ARMv8_2_A,
+  [UARCH_CORTEX_X1C]   = ISA_ARMv8_2_A, // Assuming same as X1
   [UARCH_CORTEX_X2]    = ISA_ARMv9_A,
   [UARCH_CORTEX_X3]    = ISA_ARMv9_A,
+  [UARCH_CORTEX_X4]    = ISA_ARMv9_2_A,
+  [UARCH_CORTEX_X925]  = ISA_ARMv9_2_A,
   [UARCH_NEOVERSE_N1]  = ISA_ARMv8_2_A,
+  [UARCH_NEOVERSE_N2]  = ISA_ARMv9_A,
   [UARCH_NEOVERSE_E1]  = ISA_ARMv8_2_A,
   [UARCH_NEOVERSE_V1]  = ISA_ARMv8_4_A,
+  [UARCH_NEOVERSE_V2]  = ISA_ARMv9_A,
+  [UARCH_NEOVERSE_V3]  = ISA_ARMv9_2_A,
   [UARCH_BRAHMA_B15]   = ISA_ARMv7_A,   // Same as Cortex-A15
   [UARCH_BRAHMA_B53]   = ISA_ARMv8_A,   // Same as Cortex-A53
   [UARCH_THUNDERX]     = ISA_ARMv8_A,
@@ -116,7 +128,8 @@ static char* isas_string[] = {
   [ISA_ARMv8_4_A] = "ARMv8.4",
   [ISA_ARMv8_5_A] = "ARMv8.5",
   [ISA_ARMv8_6_A] = "ARMv8.6",
-  [ISA_ARMv9_A] = "ARMv9"
+  [ISA_ARMv9_A] = "ARMv9",
+  [ISA_ARMv9_2_A] = "ARMv9.2",
 };
 
 #define UARCH_START if (false) {}
@@ -188,13 +201,24 @@ struct uarch* get_uarch_from_midr(uint32_t midr, struct cpuInfo* cpu) {
   CHECK_UARCH(arch, cpu, 'A', 0xD0E, NA, NA, "Cortex-A76",            UARCH_CORTEX_A76,   CPU_VENDOR_ARM)
   CHECK_UARCH(arch, cpu, 'A', 0xD40, NA, NA, "Neoverse V1",           UARCH_NEOVERSE_V1,  CPU_VENDOR_ARM)
   CHECK_UARCH(arch, cpu, 'A', 0xD41, NA, NA, "Cortex-A78",            UARCH_CORTEX_A78,   CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xD42, NA, NA, "Cortex-A78AE",          UARCH_CORTEX_A78AE, CPU_VENDOR_ARM)
   CHECK_UARCH(arch, cpu, 'A', 0xD44, NA, NA, "Cortex-X1",             UARCH_CORTEX_X1,    CPU_VENDOR_ARM)
   CHECK_UARCH(arch, cpu, 'A', 0xD46, NA, NA, "Cortex‑A510",           UARCH_CORTEX_A510,  CPU_VENDOR_ARM)
   CHECK_UARCH(arch, cpu, 'A', 0xD47, NA, NA, "Cortex‑A710",           UARCH_CORTEX_A710,  CPU_VENDOR_ARM)
   CHECK_UARCH(arch, cpu, 'A', 0xD48, NA, NA, "Cortex-X2",             UARCH_CORTEX_X2,    CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xD49, NA, NA, "Neoverse N2",           UARCH_NEOVERSE_N2,  CPU_VENDOR_ARM)
   CHECK_UARCH(arch, cpu, 'A', 0xD4A, NA, NA, "Neoverse E1",           UARCH_NEOVERSE_E1,  CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xD4B, NA, NA, "Cortex-A78C",           UARCH_CORTEX_A78C,  CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xD4C, NA, NA, "Cortex-X1C",            UARCH_CORTEX_X1C,   CPU_VENDOR_ARM)
   CHECK_UARCH(arch, cpu, 'A', 0xD4D, NA, NA, "Cortex-A715",           UARCH_CORTEX_A715,  CPU_VENDOR_ARM)
   CHECK_UARCH(arch, cpu, 'A', 0xD4E, NA, NA, "Cortex-X3",             UARCH_CORTEX_X3,    CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xD4F, NA, NA, "Neoverse V2",           UARCH_NEOVERSE_V2,  CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xD80, NA, NA, "Cortex-A520",           UARCH_CORTEX_A520,  CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xD81, NA, NA, "Cortex-A720",           UARCH_CORTEX_A720,  CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xD82, NA, NA, "Cortex-X4",             UARCH_CORTEX_X4,    CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xD84, NA, NA, "Neoverse V3",           UARCH_NEOVERSE_V3,  CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xD85, NA, NA, "Cortex-X925",           UARCH_CORTEX_X925,  CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xD87, NA, NA, "Cortex-A725",           UARCH_CORTEX_A725,  CPU_VENDOR_ARM)
 
   CHECK_UARCH(arch, cpu, 'B', 0x00F, NA, NA, "Brahma B15",            UARCH_BRAHMA_B15,   CPU_VENDOR_BROADCOM)
   CHECK_UARCH(arch, cpu, 'B', 0x100, NA, NA, "Brahma B53",            UARCH_BRAHMA_B53,   CPU_VENDOR_BROADCOM)
@@ -268,15 +292,7 @@ struct uarch* get_uarch_from_midr(uint32_t midr, struct cpuInfo* cpu) {
 }
 
 bool is_ARMv8_or_newer(struct cpuInfo* cpu) {
-  return cpu->arch->isa == ISA_ARMv8_A         ||
+  return cpu->arch->isa >= ISA_ARMv8_A;
-         cpu->arch->isa == ISA_ARMv8_A_AArch32 ||
-         cpu->arch->isa == ISA_ARMv8_1_A       ||
-         cpu->arch->isa == ISA_ARMv8_2_A       ||
-         cpu->arch->isa == ISA_ARMv8_3_A       ||
-         cpu->arch->isa == ISA_ARMv8_4_A       ||
-         cpu->arch->isa == ISA_ARMv8_5_A       ||
-         cpu->arch->isa == ISA_ARMv8_6_A       ||
-         cpu->arch->isa == ISA_ARMv9_A;
 }
 
 bool has_fma_support(struct cpuInfo* cpu) {
@@ -289,18 +305,13 @@ int get_vpus_width(struct cpuInfo* cpu) {
   // If the CPU has NEON, width can be 64 or 128 [1].
   // In >= ARMv8, NEON are 128 bits width [2]
   // If the CPU has SVE/SVE2, width can be between 128-2048 [3],
-  // so we must check the exact width depending on
+  // so we get the exact value from cntb [4]
-  // the exact chip (Neoverse V1 uses 256b implementations.)
   //
   // [1] https://en.wikipedia.org/wiki/ARM_architecture_family#Advanced_SIMD_(Neon)
   // [2] https://developer.arm.com/documentation/102474/0100/Fundamentals-of-Armv8-Neon-technology
   // [3] https://www.anandtech.com/show/16640/arm-announces-neoverse-v1-n2-platforms-cpus-cmn700-mesh/5
+  // [4] https://developer.arm.com/documentation/ddi0596/2020-12/SVE-Instructions/CNTB--CNTD--CNTH--CNTW--Set-scalar-to-multiple-of-predicate-constraint-element-count-
 
-  MICROARCH ua = cpu->arch->uarch;
-  switch(ua) {
-    case UARCH_NEOVERSE_V1:
-      return 256;
-    default:
   if (cpu->feat->SVE && cpu->feat->cntb > 0) {
     return cpu->feat->cntb * 8;
   }
@@ -316,19 +327,24 @@ int get_vpus_width(struct cpuInfo* cpu) {
     return 32;
   }
 }
-}
 
 int get_number_of_vpus(struct cpuInfo* cpu) {
   MICROARCH ua = cpu->arch->uarch;
 
   switch(ua) {
+    case UARCH_CORTEX_X925: // [https://www.anandtech.com/show/21399/arm-unveils-2024-cpu-core-designs-cortex-x925-a725-and-a520-arm-v9-2-redefined-for-3nm-/2]
+      return 6;
     case UARCH_EVEREST:     // Just a guess, needs confirmation.
     case UARCH_FIRESTORM:   // [https://dougallj.github.io/applecpu/firestorm-simd.html]
     case UARCH_AVALANCHE:   // [https://en.wikipedia.org/wiki/Comparison_of_ARM_processors]
     case UARCH_CORTEX_X1:   // [https://www.anandtech.com/show/15813/arm-cortex-a78-cortex-x1-cpu-ip-diverging/3]
+    case UARCH_CORTEX_X1C:  // Assuming same as X1
     case UARCH_CORTEX_X2:   // [https://www.anandtech.com/show/16693/arm-announces-mobile-armv9-cpu-microarchitectures-cortexx2-cortexa710-cortexa510/2]
     case UARCH_CORTEX_X3:   // [https://www.hwcooling.net/en/cortex-x3-the-new-fastest-arm-core-architecture-analysis: "The FPU and SIMD unit of the core still has four pipelines"]
+    case UARCH_CORTEX_X4:   // [https://www.anandtech.com/show/18871/arm-unveils-armv92-mobile-architecture-cortex-x4-a720-and-a520-64bit-exclusive/2]: "Cortex-X4: Out-of-Order Core"
     case UARCH_NEOVERSE_V1: // [https://en.wikichip.org/wiki/arm_holdings/microarchitectures/neoverse_v1]
+    case UARCH_NEOVERSE_V2: // [https://chipsandcheese.com/2023/09/11/hot-chips-2023-arms-neoverse-v2/]
+    case UARCH_NEOVERSE_V3: // Assuming same as V2
       return 4;
     case UARCH_SAWTOOTH:    // Needs confirmation, rn this is the best we know: https://mastodon.social/@dougall/111118317031041336
     case UARCH_EXYNOS_M3:   // [https://www.anandtech.com/show/12361/samsung-exynos-m3-architecture]
@@ -347,16 +363,22 @@ int get_number_of_vpus(struct cpuInfo* cpu) {
     case UARCH_CORTEX_A76:  // [https://www.anandtech.com/show/12785/arm-cortex-a76-cpu-unveiled-7nm-powerhouse/3]
     case UARCH_CORTEX_A77:  // [https://fuse.wikichip.org/news/2339/arm-unveils-cortex-a77-emphasizes-single-thread-performance]
     case UARCH_CORTEX_A78:  // [https://fuse.wikichip.org/news/3536/arm-unveils-the-cortex-a78-when-less-is-more]
+    case UARCH_CORTEX_A78C: // Assuming same as A78
+    case UARCH_CORTEX_A78AE:// Assuming same as A78
     case UARCH_EXYNOS_M1:   // [https://www.anandtech.com/show/12361/samsung-exynos-m3-architecture]
     case UARCH_EXYNOS_M2:   // [https://www.anandtech.com/show/12361/samsung-exynos-m3-architecture]
     case UARCH_NEOVERSE_N1: // [https://en.wikichip.org/wiki/arm_holdings/microarchitectures/neoverse_n1#Individual_Core]
+    case UARCH_NEOVERSE_N2: // [https://chipsandcheese.com/2023/08/18/arms-neoverse-n2-cortex-a710-for-servers/]
     case UARCH_CORTEX_A710: // [https://chipsandcheese.com/2023/08/11/arms-cortex-a710-winning-by-default/]: Fig in Core Overview. Table in Instruction Scheduling and Execution
     case UARCH_CORTEX_A715: // [https://www.hwcooling.net/en/arm-introduces-new-cortex-a715-core-architecture-analysis/]: "the numbers of ALU and FPU execution units themselves >
+    case UARCH_CORTEX_A720: // Assuming same as A715: https://www.anandtech.com/show/18871/arm-unveils-armv92-mobile-architecture-cortex-x4-a720-and-a520-64bit-exclusive/3
+    case UARCH_CORTEX_A725: // Assuming same as A720
       return 2;
     case UARCH_NEOVERSE_E1: // [https://www.anandtech.com/show/13959/arm-announces-neoverse-n1-platform/5]
     // A510 is integrated as part of a Complex. Normally, each complex would incorporate two Cortex-A510 cores.
     // Each complex incorporates a single VPU with 2 ports, so for each A510 there is theoretically 1 port.
     case UARCH_CORTEX_A510: // [https://en.wikichip.org/wiki/arm_holdings/microarchitectures/cortex-a510#Vector_Processing_Unit_.28VPU.29]
+    case UARCH_CORTEX_A520: // Assuming same as A50: https://www.anandtech.com/show/18871/arm-unveils-armv92-mobile-architecture-cortex-x4-a720-and-a520-64bit-exclusive/4
       return 1;
     default:
       // ARMv6

src/arm/uarch.h

@@ -34,15 +34,26 @@ enum {
   UARCH_CORTEX_A76,
   UARCH_CORTEX_A77,
   UARCH_CORTEX_A78,
+  UARCH_CORTEX_A78AE,
+  UARCH_CORTEX_A78C,
   UARCH_CORTEX_A510,
+  UARCH_CORTEX_A520,
   UARCH_CORTEX_A710,
   UARCH_CORTEX_A715,
+  UARCH_CORTEX_A720,
+  UARCH_CORTEX_A725,
   UARCH_CORTEX_X1,
+  UARCH_CORTEX_X1C,
   UARCH_CORTEX_X2,
   UARCH_CORTEX_X3,
+  UARCH_CORTEX_X4,
+  UARCH_CORTEX_X925,
   UARCH_NEOVERSE_N1,
+  UARCH_NEOVERSE_N2,
   UARCH_NEOVERSE_E1,
   UARCH_NEOVERSE_V1,
+  UARCH_NEOVERSE_V2,
+  UARCH_NEOVERSE_V3,
   UARCH_SCORPION,
   UARCH_KRAIT,
   UARCH_KYRO,

src/common/ascii.h

@@ -423,6 +423,48 @@ $C1#####     ######### $C2############## $C3###############     \
 $C1#####       ###### $C2######    ###### $C3####               \
 $C1#####         ## $C2######        ###### $C3##               "
 
+#define ASCII_AMLOGIC \
+"$C1      .#####.             ###                  ###        \
+$C1     ########             ###                             \
+$C1    ####..###  ########## ###   ###     #####  ###   ###  \
+$C1  .## #.  ###  ##  ##  ## ### ##   ## ##   ##  ### ##     \
+$C1 #### #.# ###  ##  ##  ## ### ##   ## ##   ##  ### ##     \
+$C1#########.###  ##  ##  ##  ##   ###    ######   ##   ###  \
+$C1                                          ###             \
+$C1                                       ###                "
+
+#define ASCII_MARVELL \
+"$C1                       ...........          ........... \
+$C1                   .###          .       .##          . \
+$C1                 .#####          .      ####          . \
+$C1                #######          .   #######          . \
+$C1             .#########__________. #########__________. \
+$C1          .###########|__________|#########|__________| \
+$C1        ############   ______############   __________  \
+$C1     .#########       |__________|######   |__________| \
+$C1   ###########         ___###########       __________  \
+$C1.##########           |__________|         |__________| "
+
+#define ASCII_SPACEMIT \
+"$C1                      :#:  \
+$C1                   :####:  \
+$C1                :#######:  \
+$C1              :#########:  \
+$C1              :#########:  \
+$C1              :#######:    \
+$C1              :####:       \
+$C1              :#:          \
+$C1:##:             :#:       \
+$C1:####:         :###:       \
+$C1:#######:     :####:       \
+$C1:##########:  :###:        \
+$C1:###########: :#:          \
+$C1:###########:              \
+$C1 :##########:              \
+$C1    :#######:              \
+$C1       :####:              \
+$C1         :##:              "
+
 // --------------------- LONG LOGOS ------------------------- //
 #define ASCII_AMD_L \
 "$C1                                                              \
@@ -600,6 +642,9 @@ asciiL logo_sipeed      = { ASCII_SIPEED,      41, 16, true,  {C_BG_RED, C_BG_WH
 asciiL logo_nvidia      = { ASCII_NVIDIA,      45, 19, false, {C_FG_GREEN, C_FG_WHITE},                       {C_FG_WHITE,   C_FG_GREEN}   };
 asciiL logo_ampere      = { ASCII_AMPERE,      50, 17, false, {C_FG_RED},                                     {C_FG_WHITE,   C_FG_RED}     };
 asciiL logo_nxp         = { ASCII_NXP,         55,  8, false, {C_FG_YELLOW, C_FG_CYAN, C_FG_GREEN},           {C_FG_CYAN,    C_FG_WHITE}   };
+asciiL logo_amlogic     = { ASCII_AMLOGIC,     58,  8, false, {C_FG_BLUE},                                    {C_FG_BLUE,    C_FG_B_WHITE} };
+asciiL logo_marvell     = { ASCII_MARVELL,     56, 10, false, {C_FG_B_BLACK},                                 {C_FG_B_BLACK, C_FG_B_WHITE} };
+asciiL logo_spacemit    = { ASCII_SPACEMIT,    27, 18, false, {C_FG_B_GREEN},                                 {C_FG_B_GREEN, C_FG_B_WHITE} };
 
 // Long variants          | ----------------------------------------------------------------------------------------------------------------|
 asciiL logo_amd_l       = { ASCII_AMD_L,       62, 19, true,  {C_BG_WHITE, C_BG_GREEN},                       {C_FG_WHITE, C_FG_GREEN}     };

src/common/cpu.c

@@ -34,6 +34,12 @@ int64_t get_freq(struct frequency* freq) {
   return freq->max;
 }
 
+#ifdef ARCH_X86
+int64_t get_freq_pp(struct frequency* freq) {
+  return freq->max_pp;
+}
+#endif
+
 #if defined(ARCH_X86) || defined(ARCH_PPC)
 char* get_str_cpu_name(struct cpuInfo* cpu, bool fcpuname) {
   #ifdef ARCH_X86

src/common/cpu.h

@@ -25,6 +25,7 @@ enum {
   CPU_VENDOR_RISCV,
   CPU_VENDOR_SIFIVE,
   CPU_VENDOR_THEAD,
+  CPU_VENDOR_SPACEMIT,
 // OTHERS
   CPU_VENDOR_UNKNOWN,
   CPU_VENDOR_INVALID
@@ -60,6 +61,11 @@ struct frequency {
   int32_t max;
   // Indicates if max frequency was measured
   bool measured;
+#ifdef ARCH_X86
+  // Max frequency when running vectorized code.
+  // Used only for peak performance computation.
+  int32_t max_pp;
+#endif
 };
 
 struct hypervisor {
@@ -132,7 +138,7 @@ struct features {
 
 struct extensions {
   char* str;
-  uint64_t mask;
+  bool* mask; // allocated at runtime with size RISCV_ISA_EXT_ID_MAX-1
 };
 
 struct cpuInfo {
@@ -188,6 +194,8 @@ struct cpuInfo {
 #ifdef ARCH_X86
   // The index of the first core in the module
   uint32_t first_core_id;
+  // The index of this module
+  uint32_t module_id;
 #endif
 #endif
 };
@@ -200,6 +208,9 @@ uint32_t get_nsockets(struct topology* topo);
 
 VENDOR get_cpu_vendor(struct cpuInfo* cpu);
 int64_t get_freq(struct frequency* freq);
+#ifdef ARCH_X86
+int64_t get_freq_pp(struct frequency* freq);
+#endif
 
 char* get_str_aes(struct cpuInfo* cpu);
 char* get_str_sha(struct cpuInfo* cpu);

src/common/printer.c

@@ -20,6 +20,7 @@
   #include "../arm/uarch.h"
   #include "../arm/midr.h"
   #include "../arm/soc.h"
+  #include "../arm/socs.h"
   #include "../common/soc.h"
 #elif ARCH_RISCV
   #include "../riscv/riscv.h"
@@ -44,9 +45,17 @@
 #define MAX_ATTRIBUTES      100
 #define MAX_TERM_SIZE       1024
 
+typedef struct {
+  int id;
+  const char *name;
+  const char *shortname;
+} AttributeField;
+
 enum {
-#if defined(ARCH_X86) || defined(ARCH_PPC)
+#if defined(ARCH_X86)
   ATTRIBUTE_NAME,
+#elif defined(ARCH_PPC)
+  ATTRIBUTE_PART_NUMBER,
 #elif defined(ARCH_ARM) || defined(ARCH_RISCV)
   ATTRIBUTE_SOC,
 #endif
@@ -78,76 +87,40 @@ enum {
   ATTRIBUTE_PEAK
 };
 
-static const char* ATTRIBUTE_FIELDS [] = {
+static const AttributeField ATTRIBUTE_INFO[] = {
-#ifdef ARCH_X86
-  "Name:",
-#elif ARCH_PPC
-  "Part Number:",
-#elif defined(ARCH_ARM) || defined(ARCH_RISCV)
-  "SoC:",
-#endif
-#if defined(ARCH_X86) || defined(ARCH_ARM)
-  "",
-#endif
-  "Hypervisor:",
-  "Microarchitecture:",
-  "Technology:",
-  "Max Frequency:",
-  "Sockets:",
-  "Cores:",
-  "Cores (Total):",
-#ifdef ARCH_X86
-  "SSE:",
-  "AVX:",
-  "FMA:",
-#elif ARCH_PPC
-  "Altivec: ",
-#elif defined(ARCH_ARM)
-  "Features: ",
-#elif defined(ARCH_RISCV)
-  "Extensions: ",
-#endif
-  "L1i Size:",
-  "L1d Size:",
-  "L2 Size:",
-  "L3 Size:",
-  "Peak Performance:",
-};
-
-static const char* ATTRIBUTE_FIELDS_SHORT [] = {
 #if defined(ARCH_X86)
-  "Name:",
+  { ATTRIBUTE_NAME,        "Name:",              "Name:"          },
-#elif ARCH_PPC
+#elif defined(ARCH_PPC)
-  "P/N:",
+  { ATTRIBUTE_PART_NUMBER, "Part Number:",       "P/N:"           },
-#elif ARCH_ARM
+#elif defined(ARCH_ARM) || defined(ARCH_RISCV)
-  "SoC:",
+  { ATTRIBUTE_SOC,         "SoC:",               "SoC:"           },
 #endif
 #if defined(ARCH_X86) || defined(ARCH_ARM)
-  "",
+  { ATTRIBUTE_CPU_NUM,     "",                   ""               },     
 #endif
-  "Hypervisor:",
+  { ATTRIBUTE_HYPERVISOR,  "Hypervisor:",        "Hypervisor:"    },
-  "uArch:",
+  { ATTRIBUTE_UARCH,       "Microarchitecture:", "uArch:"         },
-  "Technology:",
+  { ATTRIBUTE_TECHNOLOGY,  "Technology:",        "Technology:"    },
-  "Max Freq:",
+  { ATTRIBUTE_FREQUENCY,   "Max Frequency:",     "Max Freq:"      },
-  "Sockets:",
+  { ATTRIBUTE_SOCKETS,     "Sockets:",           "Sockets:"       },
-  "Cores:",
+  { ATTRIBUTE_NCORES,      "Cores:",             "Cores:"         },
-  "Cores (Total):",
+  { ATTRIBUTE_NCORES_DUAL, "Cores (Total):",     "Cores (Total):" },
 #ifdef ARCH_X86
-  "SSE:",
+  { ATTRIBUTE_SSE,         "SSE:",               "SSE:"           },
-  "AVX:",
+  { ATTRIBUTE_AVX,         "AVX:",               "AVX:"           },
-  "FMA:",
+  { ATTRIBUTE_FMA,         "FMA:",               "FMA:"           },
 #elif ARCH_PPC
-  "Altivec: ",
+  { ATTRIBUTE_ALTIVEC,     "Altivec: ",          "Altivec: "      },
-#elif defined(ARCH_ARM)
+#elif ARCH_ARM
-  "Features: ",
+  { ATTRIBUTE_FEATURES,    "Features: ",         "Features: "     },
-#elif defined(ARCH_RISCV)
+#elif ARCH_RISCV
-  "Extensions: ",
+  { ATTRIBUTE_EXTENSIONS,  "Extensions: ",       "Extensions: "   },
 #endif
-  "L1i Size:",
+  { ATTRIBUTE_L1i,         "L1i Size:",          "L1i Size:"      },
-  "L1d Size:",
+  { ATTRIBUTE_L1d,         "L1d Size:",          "L1d Size:"      },
-  "L2 Size:",
+  { ATTRIBUTE_L2,          "L2 Size:",           "L2 Size:"       },
-  "L3 Size:",
+  { ATTRIBUTE_L3,          "L3 Size:",           "L3 Size:"       },
-  "Peak Perf.:",
+  { ATTRIBUTE_PEAK,        "Peak Performance:",  "Peak Perf.:"    },
 };
 
 struct terminal {
@@ -393,6 +366,10 @@ void choose_ascii_art(struct ascii* art, struct color** cs, struct terminal* ter
     art->art = &logo_ampere;
   else if(art->vendor == SOC_VENDOR_NXP)
     art->art = &logo_nxp;
+  else if(art->vendor == SOC_VENDOR_AMLOGIC)
+    art->art = &logo_amlogic;
+  else if(art->vendor == SOC_VENDOR_MARVELL)
+    art->art = &logo_marvell;
   else if(art->vendor == SOC_VENDOR_NVIDIA)
     art->art = choose_ascii_art_aux(&logo_nvidia_l, &logo_nvidia, term, lf);
   else {
@@ -407,6 +384,8 @@ void choose_ascii_art(struct ascii* art, struct color** cs, struct terminal* ter
     art->art = &logo_allwinner;
   else if(art->vendor == SOC_VENDOR_SIPEED)
     art->art = &logo_sipeed;
+  else if(art->vendor == SOC_VENDOR_SPACEMIT)
+    art->art = &logo_spacemit;
   else
     art->art = &logo_riscv;
 #endif
@@ -447,13 +426,14 @@ void choose_ascii_art(struct ascii* art, struct color** cs, struct terminal* ter
   }
 }
 
-uint32_t longest_attribute_length(struct ascii* art, const char** attribute_fields) {
+uint32_t longest_attribute_length(struct ascii* art, bool use_short) {
   uint32_t max = 0;
   uint64_t len = 0;
 
   for(uint32_t i=0; i < art->n_attributes_set; i++) {
     if(art->attributes[i]->value != NULL) {
-      len = strlen(attribute_fields[art->attributes[i]->type]);
+      const char* str = use_short ? ATTRIBUTE_INFO[art->attributes[i]->type].shortname : ATTRIBUTE_INFO[art->attributes[i]->type].name;
+      len = strlen(str);
       if(len > max) max = len;
     }
   }
@@ -478,7 +458,7 @@ uint32_t longest_field_length(struct ascii* art, int la) {
 }
 
 #if defined(ARCH_X86) || defined(ARCH_PPC)
-void print_ascii_generic(struct ascii* art, uint32_t la, int32_t termw, const char** attribute_fields, bool hybrid_architecture) {
+void print_ascii_generic(struct ascii* art, uint32_t la, int32_t termw, bool use_short, bool hybrid_architecture) {
   struct ascii_logo* logo = art->art;
   int attr_to_print = 0;
   int attr_type;
@@ -540,14 +520,15 @@ void print_ascii_generic(struct ascii* art, uint32_t la, int32_t termw, const ch
       else {
 #endif
         beg_space = 0;
-        space_right = 2 + 1 + (la - strlen(attribute_fields[attr_type]));
+        const char* attr_str = use_short ? ATTRIBUTE_INFO[attr_type].shortname : ATTRIBUTE_INFO[attr_type].name;
+        space_right = 2 + 1 + (la - strlen(attr_str));
         if(hybrid_architecture && add_space) {
           beg_space = 2;
           space_right -= 2;
         }
 
-        printOut(lbuf, beg_space + strlen(attribute_fields[attr_type]) + space_right + strlen(attr_value),
+        printOut(lbuf, beg_space + strlen(attr_str) + space_right + strlen(attr_value),
-                 "%*s%s%s%s%*s%s%s%s", beg_space, "", logo->color_text[0], attribute_fields[attr_type], art->reset, space_right, "", logo->color_text[1], attr_value, art->reset);
+                 "%*s%s%s%s%*s%s%s%s", beg_space, "", logo->color_text[0], attr_str, art->reset, space_right, "", logo->color_text[1], attr_value, art->reset);
 #ifdef ARCH_X86
       }
 #endif
@@ -656,19 +637,19 @@ bool print_cpufetch_x86(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
   setAttribute(art, ATTRIBUTE_PEAK, pp);
 
   // Step 3. Print output
-  const char** attribute_fields = ATTRIBUTE_FIELDS;
+  bool use_short = false;
-  uint32_t longest_attribute = longest_attribute_length(art, attribute_fields);
+  uint32_t longest_attribute = longest_attribute_length(art, use_short);
   uint32_t longest_field = longest_field_length(art, longest_attribute);
   choose_ascii_art(art, cs, term, longest_field);
 
   if(!ascii_fits_screen(term->w, *art->art, longest_field)) {
     // Despite of choosing the smallest logo, the output does not fit
     // Choose the shorter field names and recalculate the longest attr
-    attribute_fields = ATTRIBUTE_FIELDS_SHORT;
+    use_short = true;
-    longest_attribute = longest_attribute_length(art, attribute_fields);
+    longest_attribute = longest_attribute_length(art, use_short);
   }
 
-  print_ascii_generic(art, longest_attribute, term->w, attribute_fields, hybrid_architecture);
+  print_ascii_generic(art, longest_attribute, term->w, use_short, hybrid_architecture);
 
   free(manufacturing_process);
   free(sockets);
@@ -717,7 +698,7 @@ bool print_cpufetch_ppc(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
 
   // Step 2. Set attributes
   if(cpu_name != NULL) {
-    setAttribute(art, ATTRIBUTE_NAME, cpu_name);
+    setAttribute(art, ATTRIBUTE_PART_NUMBER, cpu_name);
   }
   setAttribute(art, ATTRIBUTE_UARCH, uarch);
   if(cpu->hv->present) {
@@ -744,19 +725,19 @@ bool print_cpufetch_ppc(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
   setAttribute(art, ATTRIBUTE_PEAK, pp);
 
   // Step 3. Print output
-  const char** attribute_fields = ATTRIBUTE_FIELDS;
+  bool use_short = false;
-  uint32_t longest_attribute = longest_attribute_length(art, attribute_fields);
+  uint32_t longest_attribute = longest_attribute_length(art, use_short);
   uint32_t longest_field = longest_field_length(art, longest_attribute);
   choose_ascii_art(art, cs, term, longest_field);
 
   if(!ascii_fits_screen(term->w, *art->art, longest_field)) {
     // Despite of choosing the smallest logo, the output does not fit
     // Choose the shorter field names and recalculate the longest attr
-    attribute_fields = ATTRIBUTE_FIELDS_SHORT;
+    use_short = true;
-    longest_attribute = longest_attribute_length(art, attribute_fields);
+    longest_attribute = longest_attribute_length(art, use_short);
   }
 
-  print_ascii_generic(art, longest_attribute, term->w, attribute_fields, false);
+  print_ascii_generic(art, longest_attribute, term->w, use_short, false);
 
   return true;
 }
@@ -784,7 +765,7 @@ uint32_t longest_field_length_arm(struct ascii* art, int la) {
   return max;
 }
 
-void print_ascii_arm(struct ascii* art, uint32_t la, int32_t termw, const char** attribute_fields) {
+void print_ascii_arm(struct ascii* art, uint32_t la, int32_t termw, bool use_short) {
   struct ascii_logo* logo = art->art;
   int attr_to_print = 0;
   int attr_type;
@@ -855,14 +836,15 @@ void print_ascii_arm(struct ascii* art, uint32_t la, int32_t termw, const char**
       }
       else {
         beg_space = 0;
-        space_right = 2 + 1 + (la - strlen(attribute_fields[attr_type]));
+        const char* attr_str = use_short ? ATTRIBUTE_INFO[attr_type].shortname : ATTRIBUTE_INFO[attr_type].name;
+        space_right = 2 + 1 + (la - strlen(attr_str));
         if(add_space) {
           beg_space = 2;
           space_right -= 2;
         }
 
-        printOut(lbuf, beg_space + strlen(attribute_fields[attr_type]) + space_right + strlen(attr_value),
+        printOut(lbuf, beg_space + strlen(attr_str) + space_right + strlen(attr_value),
-               "%*s%s%s%s%*s%s%s%s", beg_space, "", logo->color_text[0], attribute_fields[attr_type], art->reset, space_right, "", logo->color_text[1], attr_value, art->reset);
+               "%*s%s%s%s%*s%s%s%s", beg_space, "", logo->color_text[0], attr_str, art->reset, space_right, "", logo->color_text[1], attr_value, art->reset);
       }
     }
     printOutLine(lbuf, art, termw);
@@ -883,7 +865,18 @@ bool print_cpufetch_arm(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
   char* soc_name = get_soc_name(cpu->soc);
   char* features = get_str_features(cpu);
   setAttribute(art, ATTRIBUTE_SOC, soc_name);
+
+  // Currently no reliable way to identify the specific SoC on Windows
+  // https://github.com/Dr-Noob/cpufetch/pull/273
+  // Hide manufacturing process
+#if !defined(_WIN32)
+  // In the case that the model is unknown but the vendor isn't (this is, when
+  // guess_raw_soc_from_devtree succeeded), do not show the manufacturing process
+  // (as it will be unknown)
+  if (cpu->soc->model != SOC_MODEL_UNKNOWN ||
+    (cpu->soc->model == SOC_MODEL_UNKNOWN && cpu->soc->vendor == SOC_VENDOR_UNKNOWN))
   setAttribute(art, ATTRIBUTE_TECHNOLOGY, manufacturing_process);
+#endif
 
   if(cpu->num_cpus == 1) {
     char* uarch = get_str_uarch(cpu);
@@ -921,8 +914,8 @@ bool print_cpufetch_arm(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
     setAttribute(art, ATTRIBUTE_HYPERVISOR, cpu->hv->hv_name);
   }
 
-  const char** attribute_fields = ATTRIBUTE_FIELDS;
+  bool use_short = false;
-  uint32_t longest_attribute = longest_attribute_length(art, attribute_fields);
+  uint32_t longest_attribute = longest_attribute_length(art, use_short);
   uint32_t longest_field = longest_field_length_arm(art, longest_attribute);
   choose_ascii_art(art, cs, term, longest_field);
 
@@ -934,11 +927,11 @@ bool print_cpufetch_arm(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
   if(!ascii_fits_screen(term->w, *art->art, longest_field)) {
     // Despite of choosing the smallest logo, the output does not fit
     // Choose the shorter field names and recalculate the longest attr
-    attribute_fields = ATTRIBUTE_FIELDS_SHORT;
+    use_short = true;
-    longest_attribute = longest_attribute_length(art, attribute_fields);
+    longest_attribute = longest_attribute_length(art, use_short);
   }
 
-  print_ascii_arm(art, longest_attribute, term->w, attribute_fields);
+  print_ascii_arm(art, longest_attribute, term->w, use_short);
 
   free(manufacturing_process);
   free(pp);
@@ -956,14 +949,7 @@ bool print_cpufetch_arm(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
 #endif
 
 #ifdef ARCH_RISCV
-// https://stackoverflow.com/a/2709523
+void print_ascii_riscv(struct ascii* art, uint32_t la, int32_t termw, bool use_short, bool* extensions_mask) {
-uint64_t number_of_bits(uint64_t i) {
-  i = i - ((i >> 1) & 0x5555555555555555);
-  i = (i & 0x3333333333333333) + ((i >> 2) & 0x3333333333333333);
-  return (((i + (i >> 4)) & 0xF0F0F0F0F0F0F0F) * 0x101010101010101) >> 56;
-}
-
-void print_ascii_riscv(struct ascii* art, uint32_t la, int32_t termw, const char** attribute_fields, uint64_t extensions_mask) {
   struct ascii_logo* logo = art->art;
   int attr_to_print = 0;
   int attr_type;
@@ -973,7 +959,7 @@ void print_ascii_riscv(struct ascii* art, uint32_t la, int32_t termw, const char
   int32_t ext_list_size = sizeof(extension_list)/sizeof(extension_list[0]);
   int32_t ext_num = 0;
   int32_t ext_to_print = 0;
-  int32_t num_extensions = number_of_bits(extensions_mask);
+  int32_t num_extensions = get_num_extensions(extensions_mask);
   int32_t space_up = ((int)logo->height - (int)(art->n_attributes_set + num_extensions))/2;
   int32_t space_down = (int)logo->height - (int)(art->n_attributes_set + num_extensions) - (int)space_up;
   uint32_t logo_pos = 0;
@@ -1019,7 +1005,9 @@ void print_ascii_riscv(struct ascii* art, uint32_t la, int32_t termw, const char
       // Print extension
       if(attr_to_print > 0 && art->attributes[attr_to_print-1]->type == ATTRIBUTE_EXTENSIONS && ext_num != num_extensions) {
         // Search for the extension to print
-        while(ext_to_print < ext_list_size && !((extensions_mask >> extension_list[ext_to_print].id) & 1U)) ext_to_print++;
+        while (ext_to_print < ext_list_size && !((extensions_mask[extension_list[ext_to_print].id])))
+          ext_to_print++;
+
         if(ext_to_print == ext_list_size) {
           printBug("print_ascii_riscv: Unable to find the extension to print");
         }
@@ -1031,10 +1019,11 @@ void print_ascii_riscv(struct ascii* art, uint32_t la, int32_t termw, const char
       else {
         attr_to_print++;
         beg_space = 0;
-        space_right = 2 + 1 + (la - strlen(attribute_fields[attr_type]));
+        const char* attr_str = use_short ? ATTRIBUTE_INFO[attr_type].shortname : ATTRIBUTE_INFO[attr_type].name;
+        space_right = 2 + 1 + (la - strlen(attr_str));
 
-        printOut(lbuf, beg_space + strlen(attribute_fields[attr_type]) + space_right + strlen(attr_value),
+        printOut(lbuf, beg_space + strlen(attr_str) + space_right + strlen(attr_value),
-                 "%*s%s%s%s%*s%s%s%s", beg_space, "", logo->color_text[0], attribute_fields[attr_type], art->reset, space_right, "", logo->color_text[1], attr_value, art->reset);
+                 "%*s%s%s%s%*s%s%s%s", beg_space, "", logo->color_text[0], attr_str, art->reset, space_right, "", logo->color_text[1], attr_value, art->reset);
       }
     }
     printOutLine(lbuf, art, termw);
@@ -1072,19 +1061,19 @@ bool print_cpufetch_riscv(struct cpuInfo* cpu, STYLE s, struct color** cs, struc
   setAttribute(art, ATTRIBUTE_PEAK, pp);
 
   // Step 3. Print output
-  const char** attribute_fields = ATTRIBUTE_FIELDS;
+  bool use_short = false;
-  uint32_t longest_attribute = longest_attribute_length(art, attribute_fields);
+  uint32_t longest_attribute = longest_attribute_length(art, use_short);
   uint32_t longest_field = longest_field_length(art, longest_attribute);
   choose_ascii_art(art, cs, term, longest_field);
 
   if(!ascii_fits_screen(term->w, *art->art, longest_field)) {
     // Despite of choosing the smallest logo, the output does not fit
     // Choose the shorter field names and recalculate the longest attr
-    attribute_fields = ATTRIBUTE_FIELDS_SHORT;
+    use_short = true;
-    longest_attribute = longest_attribute_length(art, attribute_fields);
+    longest_attribute = longest_attribute_length(art, use_short);
   }
 
-  print_ascii_riscv(art, longest_attribute, term->w, attribute_fields, cpu->ext->mask);
+  print_ascii_riscv(art, longest_attribute, term->w, use_short, cpu->ext->mask);
 
   return true;
 }

src/common/soc.c

@@ -23,10 +23,13 @@ static char* soc_trademark_string[] = {
   [SOC_VENDOR_NVIDIA]     = "NVIDIA ",
   [SOC_VENDOR_AMPERE]     = "Ampere ",
   [SOC_VENDOR_NXP]        = "NXP ",
+  [SOC_VENDOR_AMLOGIC]    = "Amlogic ",
+  [SOC_VENDOR_MARVELL]    = "Marvell",
   // RISC-V
   [SOC_VENDOR_SIFIVE]     = "SiFive ",
   [SOC_VENDOR_STARFIVE]   = "StarFive ",
   [SOC_VENDOR_SIPEED]     = "Sipeed ",
+  [SOC_VENDOR_SPACEMIT]   = "SpacemiT ",
   // ARM & RISC-V
   [SOC_VENDOR_ALLWINNER]  = "Allwinner "
 };
@@ -77,6 +80,28 @@ void fill_soc(struct system_on_chip* soc, char* soc_name, SOC soc_model, int32_t
   }
 }
 
+void fill_soc_raw(struct system_on_chip* soc, char* soc_name, VENDOR vendor) {
+  soc->model = SOC_MODEL_UNKNOWN;
+  soc->vendor = vendor;
+  soc->process = UNKNOWN;
+
+  int len = strlen(soc_name) + strlen(soc_trademark_string[soc->vendor]) + 1;
+  soc->raw_name = emalloc(sizeof(char) * len);
+  sprintf(soc->raw_name, "%s%s", soc_trademark_string[soc->vendor], soc_name);
+}
+
+#ifdef _WIN32
+VENDOR try_match_soc_vendor_name(char* vendor_name)
+{
+  for(size_t i=1; i < sizeof(soc_trademark_string)/sizeof(soc_trademark_string[0]); i++) {
+    if(strstr(vendor_name, soc_trademark_string[i]) != NULL) {
+      return i;
+    }
+  }
+  return SOC_VENDOR_UNKNOWN;
+}
+#endif
+
 bool match_soc(struct system_on_chip* soc, char* raw_name, char* expected_name, char* soc_name, SOC soc_model, int32_t process) {
   int len1 = strlen(raw_name);
   int len2 = strlen(expected_name);

src/common/soc.h

@@ -27,10 +27,13 @@ enum {
   SOC_VENDOR_NVIDIA,
   SOC_VENDOR_AMPERE,
   SOC_VENDOR_NXP,
+  SOC_VENDOR_AMLOGIC,
+  SOC_VENDOR_MARVELL,
   // RISC-V
   SOC_VENDOR_SIFIVE,
   SOC_VENDOR_STARFIVE,
   SOC_VENDOR_SIPEED,
+  SOC_VENDOR_SPACEMIT,
   // ARM & RISC-V
   SOC_VENDOR_ALLWINNER
 };
@@ -49,6 +52,10 @@ VENDOR get_soc_vendor(struct system_on_chip* soc);
 bool match_soc(struct system_on_chip* soc, char* raw_name, char* expected_name, char* soc_name, SOC soc_model, int32_t process);
 char* get_str_process(struct system_on_chip* soc);
 void fill_soc(struct system_on_chip* soc, char* soc_name, SOC soc_model, int32_t process);
+void fill_soc_raw(struct system_on_chip* soc, char* soc_name, VENDOR vendor);
+#ifdef _WIN32
+VENDOR try_match_soc_vendor_name(char* vendor_name);
+#endif
 
 #define SOC_START if (false) {}
 #define SOC_EQ(raw_name, expected_name, soc_name, soc_model, soc, process) \

src/common/udev.c

@@ -361,3 +361,69 @@ char* get_devtree_compatible(int *filelen) {
 
   return buf;
 }
+
+// Returns a list of structs devtree, each containing both the vendor and the
+// model, coming from the compatible file from the device tree. In this
+// context, vendor refers to the first string of every entry and the model to
+// the second. For instance, given a compatible file with:
+// "str1,foo1.str2,foo2" (where . denotes the NULL byte, i.e., the separator),
+// then this function will return a list with two structs, the first one
+// containing str1 and foo1 and the other containing str2 and foo2.
+struct devtree** get_devtree_compatible_struct(int *num_vendors_ptr) {
+  int len;
+  char* dt = get_devtree_compatible(&len);
+  if (dt == NULL) {
+    return NULL;
+  }
+
+  int num_vendors = 0;
+  char* ptr = dt;
+
+  for (int ptrpos = 0; ptrpos < len; ptrpos = (ptr-dt)) {
+    ptr = memchr(ptr, '\0', len);
+    if (ptr == NULL) {
+      printBug("get_devtree_compatible_struct: Unable to find delimiter (1) (num_vendors=%d)", num_vendors);
+      return NULL;
+    }
+    ptr++;
+    num_vendors++;
+  }
+
+  struct devtree** vendors = emalloc(sizeof(struct devtree *) * num_vendors);
+  ptr = dt;
+
+  for (int ptrpos = 0, i = 0; ptrpos < len; ptrpos = (ptr-dt), i++) {
+    char* comma_ptr = strstr(ptr, ",");
+    if (comma_ptr == NULL) {
+      printBug("get_devtree_compatible_struct: Unable to find comma (num_vendors=%d)", num_vendors);
+      return NULL;
+    }
+    comma_ptr = comma_ptr-1; // Point right before comma
+
+    char* end_ptr = memchr(comma_ptr, '\0', len - ptrpos);
+    if (end_ptr == NULL) {
+      printBug("get_devtree_compatible_struct: Unable to find delimiter (2) (num_vendors=%d)", num_vendors);
+      return NULL;
+    }
+
+    int vendor_str_len = (comma_ptr-ptr)+1;
+    int model_str_len = (end_ptr-(comma_ptr+2))+1;
+
+    vendors[i] = emalloc(sizeof(struct devtree));
+    vendors[i]->vendor = ecalloc(vendor_str_len, sizeof(char));
+    vendors[i]->model = ecalloc(model_str_len, sizeof(char));
+
+    strncpy(vendors[i]->vendor, ptr, vendor_str_len);
+    strncpy(vendors[i]->model, comma_ptr+2, model_str_len);
+
+    ptr = memchr(ptr, '\0', len);
+    if (ptr == NULL) {
+      printBug("get_devtree_compatible_struct: Unable to find delimiter (3) (num_vendors=%d)", num_vendors);
+      return NULL;
+    }
+    ptr++; // Point right after delimiter
+  }
+
+  *num_vendors_ptr = num_vendors;
+  return vendors;
+}

src/common/udev.h

@@ -31,6 +31,11 @@
 #define _PATH_CACHE_MAX_LEN     200
 #define _PATH_PACKAGE_MAX_LEN   200
 
+struct devtree {
+  char* vendor;
+  char* model;
+};
+
 char* read_file(char* path, int* len);
 long get_max_freq_from_file(uint32_t core);
 long get_min_freq_from_file(uint32_t core);
@@ -44,5 +49,6 @@ int get_ncores_from_cpuinfo(void);
 char* get_field_from_cpuinfo(char* CPUINFO_FIELD);
 bool is_devtree_compatible(char* str);
 char* get_devtree_compatible(int *filelen);
+struct devtree** get_devtree_compatible_struct(int *num_vendors);
 
 #endif

src/riscv/riscv.c

@@ -12,7 +12,7 @@
 #define SET_ISA_EXT_MAP(name, bit)          \
   if(strncmp(multi_letter_extension, name,  \
         multi_letter_extension_len) == 0) { \
-    ext->mask |= 1UL << bit;                \
+    ext->mask[bit] = true;                  \
     maskset = true;                         \
   }                                         \
 
@@ -71,6 +71,65 @@ int parse_multi_letter_extension(struct extensions* ext, char* e) {
   SET_ISA_EXT_MAP("zicsr",       RISCV_ISA_EXT_ZICSR)
   SET_ISA_EXT_MAP("zifencei",    RISCV_ISA_EXT_ZIFENCEI)
   SET_ISA_EXT_MAP("zihpm",       RISCV_ISA_EXT_ZIHPM)
+  SET_ISA_EXT_MAP("smstateen",   RISCV_ISA_EXT_SMSTATEEN)
+  SET_ISA_EXT_MAP("zicond",      RISCV_ISA_EXT_ZICOND)
+  SET_ISA_EXT_MAP("zbc",         RISCV_ISA_EXT_ZBC)
+  SET_ISA_EXT_MAP("zbkb",        RISCV_ISA_EXT_ZBKB)
+  SET_ISA_EXT_MAP("zbkc",        RISCV_ISA_EXT_ZBKC)
+  SET_ISA_EXT_MAP("zbkx",        RISCV_ISA_EXT_ZBKX)
+  SET_ISA_EXT_MAP("zknd",        RISCV_ISA_EXT_ZKND)
+  SET_ISA_EXT_MAP("zkne",        RISCV_ISA_EXT_ZKNE)
+  SET_ISA_EXT_MAP("zknh",        RISCV_ISA_EXT_ZKNH)
+  SET_ISA_EXT_MAP("zkr",         RISCV_ISA_EXT_ZKR)
+  SET_ISA_EXT_MAP("zksed",       RISCV_ISA_EXT_ZKSED)
+  SET_ISA_EXT_MAP("zksh",        RISCV_ISA_EXT_ZKSH)
+  SET_ISA_EXT_MAP("zkt",         RISCV_ISA_EXT_ZKT)
+  SET_ISA_EXT_MAP("zvbb",        RISCV_ISA_EXT_ZVBB)
+  SET_ISA_EXT_MAP("zvbc",        RISCV_ISA_EXT_ZVBC)
+  SET_ISA_EXT_MAP("zvkb",        RISCV_ISA_EXT_ZVKB)
+  SET_ISA_EXT_MAP("zvkg",        RISCV_ISA_EXT_ZVKG)
+  SET_ISA_EXT_MAP("zvkned",      RISCV_ISA_EXT_ZVKNED)
+  SET_ISA_EXT_MAP("zvknha",      RISCV_ISA_EXT_ZVKNHA)
+  SET_ISA_EXT_MAP("zvknhb",      RISCV_ISA_EXT_ZVKNHB)
+  SET_ISA_EXT_MAP("zvksed",      RISCV_ISA_EXT_ZVKSED)
+  SET_ISA_EXT_MAP("zvksh",       RISCV_ISA_EXT_ZVKSH)
+  SET_ISA_EXT_MAP("zvkt",        RISCV_ISA_EXT_ZVKT)
+  SET_ISA_EXT_MAP("zfh",         RISCV_ISA_EXT_ZFH)
+  SET_ISA_EXT_MAP("zfhmin",      RISCV_ISA_EXT_ZFHMIN)
+  SET_ISA_EXT_MAP("zihintntl",   RISCV_ISA_EXT_ZIHINTNTL)
+  SET_ISA_EXT_MAP("zvfh",        RISCV_ISA_EXT_ZVFH)
+  SET_ISA_EXT_MAP("zvfhmin",     RISCV_ISA_EXT_ZVFHMIN)
+  SET_ISA_EXT_MAP("zfa",         RISCV_ISA_EXT_ZFA)
+  SET_ISA_EXT_MAP("ztso",        RISCV_ISA_EXT_ZTSO)
+  SET_ISA_EXT_MAP("zacas",       RISCV_ISA_EXT_ZACAS)
+  SET_ISA_EXT_MAP("zve32x",      RISCV_ISA_EXT_ZVE32X)
+  SET_ISA_EXT_MAP("zve32f",      RISCV_ISA_EXT_ZVE32F)
+  SET_ISA_EXT_MAP("zve64x",      RISCV_ISA_EXT_ZVE64X)
+  SET_ISA_EXT_MAP("zve64f",      RISCV_ISA_EXT_ZVE64F)
+  SET_ISA_EXT_MAP("zve64d",      RISCV_ISA_EXT_ZVE64D)
+  SET_ISA_EXT_MAP("zimop",       RISCV_ISA_EXT_ZIMOP)
+  SET_ISA_EXT_MAP("zca",         RISCV_ISA_EXT_ZCA)
+  SET_ISA_EXT_MAP("zcb",         RISCV_ISA_EXT_ZCB)
+  SET_ISA_EXT_MAP("zcd",         RISCV_ISA_EXT_ZCD)
+  SET_ISA_EXT_MAP("zcf",         RISCV_ISA_EXT_ZCF)
+  SET_ISA_EXT_MAP("zcmop",       RISCV_ISA_EXT_ZCMOP)
+  SET_ISA_EXT_MAP("zawrs",       RISCV_ISA_EXT_ZAWRS)
+  SET_ISA_EXT_MAP("svvptc",      RISCV_ISA_EXT_SVVPTC)
+  SET_ISA_EXT_MAP("smmpm",       RISCV_ISA_EXT_SMMPM)
+  SET_ISA_EXT_MAP("smnpm",       RISCV_ISA_EXT_SMNPM)
+  SET_ISA_EXT_MAP("ssnpm",       RISCV_ISA_EXT_SSNPM)
+  SET_ISA_EXT_MAP("zabha",       RISCV_ISA_EXT_ZABHA)
+  SET_ISA_EXT_MAP("ziccrse",     RISCV_ISA_EXT_ZICCRSE)
+  SET_ISA_EXT_MAP("svade",       RISCV_ISA_EXT_SVADE)
+  SET_ISA_EXT_MAP("svadu",       RISCV_ISA_EXT_SVADU)
+  SET_ISA_EXT_MAP("zfbfmin",     RISCV_ISA_EXT_ZFBFMIN)
+  SET_ISA_EXT_MAP("zvfbfmin",    RISCV_ISA_EXT_ZVFBFMIN)
+  SET_ISA_EXT_MAP("zvfbfwma",    RISCV_ISA_EXT_ZVFBFWMA)
+  SET_ISA_EXT_MAP("zaamo",       RISCV_ISA_EXT_ZAAMO)
+  SET_ISA_EXT_MAP("zalrsc",      RISCV_ISA_EXT_ZALRSC)
+  SET_ISA_EXT_MAP("zicbop",      RISCV_ISA_EXT_ZICBOP)
+  SET_ISA_EXT_MAP("ime",         RISCV_ISA_EXT_IME)
+
   if(!maskset) {
     printBug("parse_multi_letter_extension: Unknown multi-letter extension: %s", multi_letter_extension);
     return -1;
@@ -93,19 +152,21 @@ bool valid_extension(char ext) {
 
 struct extensions* get_extensions_from_str(char* str) {
   struct extensions* ext = emalloc(sizeof(struct extensions));
-  ext->mask = 0;
+  ext->mask = ecalloc(RISCV_ISA_EXT_ID_MAX, sizeof(bool));
   ext->str = NULL;
 
   if(str == NULL) {
     return ext;
   }
 
-  int len = strlen(str);
+  int len = strlen(str)+1;
-  ext->str = ecalloc(len+1, sizeof(char));
+  ext->str = emalloc(len * sizeof(char));
   strncpy(ext->str, str, sizeof(char) * len);
 
   // Code inspired in Linux kernel (riscv_fill_hwcap):
   // https://elixir.bootlin.com/linux/v6.2.10/source/arch/riscv/kernel/cpufeature.c
+  // Now it seems to be here in riscv_parse_isa_string:
+  // https://elixir.bootlin.com/linux/v6.16/source/arch/riscv/kernel/cpufeature.c
   char* isa = str;
   if (!strncmp(isa, "rv32", 4))
     isa += 4;
@@ -137,7 +198,7 @@ struct extensions* get_extensions_from_str(char* str) {
       // adding it to the mask
       if(valid_extension(*e)) {
         int n = *e - 'a';
-        ext->mask |= 1UL << n;
+        ext->mask[n] = true;
       }
       else {
         printBug("get_extensions_from_str: Invalid extension: '%c'", *e);
@@ -148,6 +209,18 @@ struct extensions* get_extensions_from_str(char* str) {
   return ext;
 }
 
+uint32_t get_num_extensions(bool* mask) {
+  uint32_t num = 0;
+  for (int i=0; i < RISCV_ISA_EXT_ID_MAX; i++) {
+    if (mask[i]) num++;
+  }
+  return num;
+}
+
+bool is_mask_empty(bool* mask) {
+  return get_num_extensions(mask) == 0;
+}
+
 struct cpuInfo* get_cpu_info(void) {
   struct cpuInfo* cpu = malloc(sizeof(struct cpuInfo));
   //init_cpu_info(cpu);
@@ -156,13 +229,12 @@ struct cpuInfo* get_cpu_info(void) {
   topo->cach = NULL;
   cpu->topo = topo;
 
-  char* cpuinfo_str = get_uarch_from_cpuinfo();
   char* ext_str = get_extensions_from_cpuinfo();
   cpu->hv = emalloc(sizeof(struct hypervisor));
   cpu->hv->present = false;
   cpu->ext = get_extensions_from_str(ext_str);
-  if(cpu->ext->str != NULL && cpu->ext->mask == 0) return NULL;
+  if(cpu->ext->str != NULL && is_mask_empty(cpu->ext->mask)) return NULL;
-  cpu->arch = get_uarch_from_cpuinfo_str(cpuinfo_str, cpu);
+  cpu->arch = get_uarch(cpu);
   cpu->soc = get_soc(cpu);
   cpu->freq = get_frequency_info(0);
   cpu->peak_performance = get_peak_performance(cpu);

src/riscv/riscv.h

@@ -32,11 +32,73 @@ enum riscv_isa_ext_id {
   RISCV_ISA_EXT_ZICSR,
   RISCV_ISA_EXT_ZIFENCEI,
   RISCV_ISA_EXT_ZIHPM,
+  RISCV_ISA_EXT_SMSTATEEN,
+  RISCV_ISA_EXT_ZICOND,
+  RISCV_ISA_EXT_ZBC,
+  RISCV_ISA_EXT_ZBKB,
+  RISCV_ISA_EXT_ZBKC,
+  RISCV_ISA_EXT_ZBKX,
+  RISCV_ISA_EXT_ZKND,
+  RISCV_ISA_EXT_ZKNE,
+  RISCV_ISA_EXT_ZKNH,
+  RISCV_ISA_EXT_ZKR,
+  RISCV_ISA_EXT_ZKSED,
+  RISCV_ISA_EXT_ZKSH,
+  RISCV_ISA_EXT_ZKT,
+  RISCV_ISA_EXT_ZVBB,
+  RISCV_ISA_EXT_ZVBC,
+  RISCV_ISA_EXT_ZVKB,
+  RISCV_ISA_EXT_ZVKG,
+  RISCV_ISA_EXT_ZVKNED,
+  RISCV_ISA_EXT_ZVKNHA,
+  RISCV_ISA_EXT_ZVKNHB,
+  RISCV_ISA_EXT_ZVKSED,
+  RISCV_ISA_EXT_ZVKSH,
+  RISCV_ISA_EXT_ZVKT,
+  RISCV_ISA_EXT_ZFH,
+  RISCV_ISA_EXT_ZFHMIN,
+  RISCV_ISA_EXT_ZIHINTNTL,
+  RISCV_ISA_EXT_ZVFH,
+  RISCV_ISA_EXT_ZVFHMIN,
+  RISCV_ISA_EXT_ZFA,
+  RISCV_ISA_EXT_ZTSO,
+  RISCV_ISA_EXT_ZACAS,
+  RISCV_ISA_EXT_ZVE32X,
+  RISCV_ISA_EXT_ZVE32F,
+  RISCV_ISA_EXT_ZVE64X,
+  RISCV_ISA_EXT_ZVE64F,
+  RISCV_ISA_EXT_ZVE64D,
+  RISCV_ISA_EXT_ZIMOP,
+  RISCV_ISA_EXT_ZCA,
+  RISCV_ISA_EXT_ZCB,
+  RISCV_ISA_EXT_ZCD,
+  RISCV_ISA_EXT_ZCF,
+  RISCV_ISA_EXT_ZCMOP,
+  RISCV_ISA_EXT_ZAWRS,
+  RISCV_ISA_EXT_SVVPTC,
+  RISCV_ISA_EXT_SMMPM,
+  RISCV_ISA_EXT_SMNPM,
+  RISCV_ISA_EXT_SSNPM,
+  RISCV_ISA_EXT_ZABHA,
+  RISCV_ISA_EXT_ZICCRSE,
+  RISCV_ISA_EXT_SVADE,
+  RISCV_ISA_EXT_SVADU,
+  RISCV_ISA_EXT_ZFBFMIN,
+  RISCV_ISA_EXT_ZVFBFMIN,
+  RISCV_ISA_EXT_ZVFBFWMA,
+  RISCV_ISA_EXT_ZAAMO,
+  RISCV_ISA_EXT_ZALRSC,
+  RISCV_ISA_EXT_ZICBOP,
+  RISCV_ISA_EXT_IME,      // This is not in the kernel! but it was seen on a Muse Pi Pro board
   RISCV_ISA_EXT_ID_MAX
 };
 
 // https://five-embeddev.com/riscv-isa-manual/latest/preface.html#preface
 // https://en.wikichip.org/wiki/risc-v/standard_extensions
+// (Zicbop) https://github.com/riscv/riscv-CMOs/blob/master/cmobase/Zicbop.adoc
+// https://raw.githubusercontent.com/riscv/riscv-CMOs/master/specifications/cmobase-v1.0.1.pdf
+// https://www.kernel.org/doc/Documentation/devicetree/bindings/riscv/extensions.yaml
+// (Ime) https://github.com/riscv/integrated-matrix-extension (not confirmed, just a guess...)
 // Included all except for G
 static const struct extension extension_list[] = {
   { 'i' - 'a', "(I) Integer Instruction Set" },
@@ -64,6 +126,7 @@ static const struct extension extension_list[] = {
   { RISCV_ISA_EXT_ZIHINTPAUSE, "(Zihintpause) Pause Hint" },
   { RISCV_ISA_EXT_SVNAPOT,     "(Svnapot) Naturally Aligned Power of Two Pages" },
   { RISCV_ISA_EXT_ZICBOZ,      "(Zicboz) Cache Block Zero Operations" },
+  { RISCV_ISA_EXT_ZICBOP,      "(Zicbop) Cache Block Prefetch Operations" },
   { RISCV_ISA_EXT_SMAIA,       "(Smaia) Advanced Interrupt Architecture" },
   { RISCV_ISA_EXT_SSAIA,       "(Ssaia) Advanced Interrupt Architecture" },
   { RISCV_ISA_EXT_ZBA,         "(Zba) Address Generation" },
@@ -71,12 +134,71 @@ static const struct extension extension_list[] = {
   { RISCV_ISA_EXT_ZICNTR,      "(Zicntr) Base Counters and Timers" },
   { RISCV_ISA_EXT_ZICSR,       "(Zicsr) Control and Status Register" },
   { RISCV_ISA_EXT_ZIFENCEI,    "(Zifencei) Instruction-Fetch Fence" },
-  { RISCV_ISA_EXT_ZIHPM,       "(Zihpm) Hardware Performance Counters" }
+  { RISCV_ISA_EXT_ZIHPM,       "(Zihpm) Hardware Performance Counters" },
+  { RISCV_ISA_EXT_SMSTATEEN,   "(Smstateen) " },
+  { RISCV_ISA_EXT_ZICOND,      "(Zicond) Integer Conditional Operations" },
+  { RISCV_ISA_EXT_ZBC,         "(Zbc) Carry-Less Multiplication" },
+  { RISCV_ISA_EXT_ZBKB,        "(Zbkb) " },
+  { RISCV_ISA_EXT_ZBKC,        "(Zbkc) " },
+  { RISCV_ISA_EXT_ZBKX,        "(Zbkx) " },
+  { RISCV_ISA_EXT_ZKND,        "(Zknd) " },
+  { RISCV_ISA_EXT_ZKNE,        "(Zkne) " },
+  { RISCV_ISA_EXT_ZKNH,        "(Zknh) " },
+  { RISCV_ISA_EXT_ZKR,         "(Zkr) " },
+  { RISCV_ISA_EXT_ZKSED,       "(Zksed) " },
+  { RISCV_ISA_EXT_ZKSH,        "(Zksh) " },
+  { RISCV_ISA_EXT_ZKT,         "(Zkt) Data-Independent Execution Latency" },
+  { RISCV_ISA_EXT_ZVBB,        "(Zvbb) " },
+  { RISCV_ISA_EXT_ZVBC,        "(Zvbc) " },
+  { RISCV_ISA_EXT_ZVKB,        "(Zvkb) " },
+  { RISCV_ISA_EXT_ZVKG,        "(Zvkg) " },
+  { RISCV_ISA_EXT_ZVKNED,      "(Zvkned) " },
+  { RISCV_ISA_EXT_ZVKNHA,      "(Zvknha) " },
+  { RISCV_ISA_EXT_ZVKNHB,      "(Zvknhb) " },
+  { RISCV_ISA_EXT_ZVKSED,      "(Zvksed) " },
+  { RISCV_ISA_EXT_ZVKSH,       "(Zvksh) " },
+  { RISCV_ISA_EXT_ZVKT,        "(Zvkt) " },
+  { RISCV_ISA_EXT_ZFH,         "(Zfh) " },
+  { RISCV_ISA_EXT_ZFHMIN,      "(Zfhmin) " },
+  { RISCV_ISA_EXT_ZIHINTNTL,   "(Zihintntl) " },
+  { RISCV_ISA_EXT_ZVFH,        "(Zvfh) " },
+  { RISCV_ISA_EXT_ZVFHMIN,     "(Zvfhmin) " },
+  { RISCV_ISA_EXT_ZFA,         "(Zfa) " },
+  { RISCV_ISA_EXT_ZTSO,        "(Ztso) " },
+  { RISCV_ISA_EXT_ZACAS,       "(Zacas) " },
+  { RISCV_ISA_EXT_ZVE32X,      "(Zve32x) Vector Extensions (i32)" },
+  { RISCV_ISA_EXT_ZVE32F,      "(Zve32f) Vector Extensions (f32)" },
+  { RISCV_ISA_EXT_ZVE64X,      "(Zve64x) Vector Extensions (i64)" },
+  { RISCV_ISA_EXT_ZVE64F,      "(Zve64f) Vector Extensions (f64)" },
+  { RISCV_ISA_EXT_ZVE64D,      "(Zve64d) Vector Extensions (???)" },
+  { RISCV_ISA_EXT_ZIMOP,       "(Zimop) " },
+  { RISCV_ISA_EXT_ZCA,         "(Zca) " },
+  { RISCV_ISA_EXT_ZCB,         "(Zcb) " },
+  { RISCV_ISA_EXT_ZCD,         "(Zcd) " },
+  { RISCV_ISA_EXT_ZCF,         "(Zcf) " },
+  { RISCV_ISA_EXT_ZCMOP,       "(Zcmop) " },
+  { RISCV_ISA_EXT_ZAWRS,       "(Zawrs) " },
+  { RISCV_ISA_EXT_SVVPTC,      "(Svvptc) " },
+  { RISCV_ISA_EXT_SMMPM,       "(Smmpm) " },
+  { RISCV_ISA_EXT_SMNPM,       "(Smnpm) " },
+  { RISCV_ISA_EXT_SSNPM,       "(Ssnpm) " },
+  { RISCV_ISA_EXT_ZABHA,       "(Zabha) " },
+  { RISCV_ISA_EXT_ZICCRSE,     "(Ziccrse) " },
+  { RISCV_ISA_EXT_SVADE,       "(Svade) " },
+  { RISCV_ISA_EXT_SVADU,       "(Svadu) " },
+  { RISCV_ISA_EXT_ZFBFMIN,     "(Zfbfmin) " },
+  { RISCV_ISA_EXT_ZVFBFMIN,    "(Zvfbfmin) " },
+  { RISCV_ISA_EXT_ZVFBFWMA,    "(Zvfbfwma) " },
+  { RISCV_ISA_EXT_ZAAMO,       "(Zaamo) " },
+  { RISCV_ISA_EXT_ZALRSC,      "(Zalrsc) " },
+  { RISCV_ISA_EXT_ZICBOP,      "(Zicbop) " },
+  { RISCV_ISA_EXT_IME,         "(Ime) Integrated Matrix Extension" },
 };
 
 struct cpuInfo* get_cpu_info(void);
 char* get_str_topology(struct cpuInfo* cpu, struct topology* topo);
 char* get_str_extensions(struct cpuInfo* cpu);
+uint32_t get_num_extensions(bool* mask);
 void print_debug(struct cpuInfo* cpu);
 
 #endif

src/riscv/soc.c

@@ -38,6 +38,12 @@ bool match_sipeed(char* soc_name, struct system_on_chip* soc) {
   SOC_END
 }
 
+bool match_spacemit(char* soc_name, struct system_on_chip* soc) {
+  SOC_START
+  SOC_EQ(soc_name, "k1-x", "K1-X", SOC_SPACEMIT_K1X, soc, 22) // https://github.com/Dr-Noob/cpufetch/issues/286 https://www.spacemit.com/en/spacemit-x60-core/
+  SOC_END
+}
+
 struct system_on_chip* parse_soc_from_string(struct system_on_chip* soc) {
   char* raw_name = soc->raw_name;
 
@@ -50,6 +56,9 @@ struct system_on_chip* parse_soc_from_string(struct system_on_chip* soc) {
   if(match_sifive(raw_name, soc))
     return soc;
 
+  if(match_spacemit(raw_name, soc))
+    return soc;
+
   match_sipeed(raw_name, soc);
   return soc;
 }

src/riscv/socs.h

@@ -13,6 +13,8 @@ enum {
   SOC_ALLWINNER_D1H,
   // SIPEED
   SOC_SIPEED_LICHEEPI4A,
+  // SPACEMIT
+  SOC_SPACEMIT_K1X,
   // UNKNOWN
   SOC_MODEL_UNKNOWN
 };
@@ -22,6 +24,7 @@ inline static VENDOR get_soc_vendor_from_soc(SOC soc) {
   if(soc >= SOC_STARFIVE_VF2 && soc <= SOC_STARFIVE_VF2) return SOC_VENDOR_STARFIVE;
   if(soc >= SOC_ALLWINNER_D1H && soc <= SOC_ALLWINNER_D1H) return SOC_VENDOR_ALLWINNER;
   if(soc >= SOC_SIPEED_LICHEEPI4A && soc <= SOC_SIPEED_LICHEEPI4A) return SOC_VENDOR_SIPEED;
+  if(soc >= SOC_SPACEMIT_K1X && soc <= SOC_SPACEMIT_K1X) return SOC_VENDOR_SPACEMIT;
   return SOC_VENDOR_UNKNOWN;
 }
 

src/riscv/uarch.c

@@ -4,6 +4,7 @@
 #include <string.h>
 
 #include "uarch.h"
+#include "udev.h"
 #include "../common/global.h"
 
 typedef uint32_t MICROARCH;
@@ -12,6 +13,7 @@ struct uarch {
   MICROARCH uarch;
   char* uarch_str;
   char* cpuinfo_str;
+  struct riscv_cpuinfo* ci;
 };
 
 enum {
@@ -21,13 +23,20 @@ enum {
   UARCH_U74,
   // THEAD
   UARCH_C906,
-  UARCH_C910
+  UARCH_C910,
+  // SPACEMIT
+  UARCH_X60
 };
 
 #define UARCH_START if (false) {}
 #define CHECK_UARCH(arch, cpu, cpuinfo_str, uarch_str, str, uarch, vendor) \
    else if (strcmp(cpuinfo_str, uarch_str) == 0) fill_uarch(arch, cpu, str, uarch, vendor);
-#define UARCH_END else { printBug("Unknown microarchitecture detected: uarch='%s'", cpuinfo_str); fill_uarch(arch, cpu, "Unknown", UARCH_UNKNOWN, CPU_VENDOR_UNKNOWN); }
+#define UARCH_END else { printWarn("Unknown microarchitecture detected: uarch='%s'", cpuinfo_str); fill_uarch(arch, cpu, "Unknown", UARCH_UNKNOWN, CPU_VENDOR_UNKNOWN); }
+
+#define ARCHID_START if (false) {}
+#define CHECK_ARCHID(arch, marchid_val, str, uarch, vendor) \
+  else if (arch->ci->marchid == (unsigned long) marchid_val) fill_uarch(arch, cpu, str, uarch, vendor);
+#define ARCHID_END else { printWarn("Unknown microarchitecture detected: marchid=0x%.8X", arch->ci->marchid); fill_uarch(arch, cpu, "Unknown", UARCH_UNKNOWN, CPU_VENDOR_UNKNOWN); }
 
 void fill_uarch(struct uarch* arch, struct cpuInfo* cpu, char* str, MICROARCH u, VENDOR vendor) {
   arch->uarch = u;
@@ -39,14 +48,8 @@ void fill_uarch(struct uarch* arch, struct cpuInfo* cpu, char* str, MICROARCH u,
 // https://elixir.bootlin.com/linux/latest/source/Documentation/devicetree/bindings/riscv/cpus.yaml
 // SiFive: https://www.sifive.com/risc-v-core-ip
 // T-Head: https://www.t-head.cn/product/c906
-struct uarch* get_uarch_from_cpuinfo_str(char* cpuinfo_str, struct cpuInfo* cpu) {
+struct uarch* get_uarch_from_cpuinfo_str(char* cpuinfo_str, struct cpuInfo* cpu, struct uarch* arch) {
-  struct uarch* arch = emalloc(sizeof(struct uarch));
   arch->cpuinfo_str = cpuinfo_str;
-  if(cpuinfo_str == NULL) {
-    printWarn("get_uarch_from_cpuinfo: Unable to detect microarchitecture, cpuinfo_str is NULL");
-    fill_uarch(arch, cpu, "Unknown", UARCH_UNKNOWN, CPU_VENDOR_UNKNOWN);
-    return arch;
-  }
 
   // U74/U74-MC:
   // SiFive says that U74-MC is "Multicore: four U74 cores and one S76 core" while
@@ -70,6 +73,41 @@ struct uarch* get_uarch_from_cpuinfo_str(char* cpuinfo_str, struct cpuInfo* cpu)
   return arch;
 }
 
+// Use marchid to get the microarchitecture
+struct uarch* get_uarch_from_riscv_cpuinfo(struct cpuInfo* cpu, struct uarch* arch) {
+
+  ARCHID_START
+  CHECK_ARCHID(arch, 0x8000000058000001, "X60", UARCH_X60, CPU_VENDOR_SPACEMIT) // https://github.com/Dr-Noob/cpufetch/issues/286
+  ARCHID_END
+
+  return arch;
+}
+
+struct uarch* get_uarch(struct cpuInfo* cpu) {
+  char* cpuinfo_str = get_uarch_from_cpuinfo();
+  struct uarch* arch = emalloc(sizeof(struct uarch));
+  arch->uarch = UARCH_UNKNOWN;
+  arch->ci = NULL;
+
+  if (cpuinfo_str == NULL) {
+    printWarn("get_uarch_from_cpuinfo: Unable to detect microarchitecture using uarch: cpuinfo_str is NULL");
+    arch->ci = get_riscv_cpuinfo();
+
+    if (arch->ci == NULL || arch->ci->marchid == 0)
+      printWarn("get_riscv_cpuinfo: Unable to get marchid from udev");
+    else
+      arch = get_uarch_from_riscv_cpuinfo(cpu, arch);
+  }
+  else {
+    arch = get_uarch_from_cpuinfo_str(cpuinfo_str, cpu, arch);
+  }
+
+  if (arch->uarch == UARCH_UNKNOWN)
+    fill_uarch(arch, cpu, "Unknown", UARCH_UNKNOWN, CPU_VENDOR_UNKNOWN);
+
+  return arch;
+}
+
 char* get_str_uarch(struct cpuInfo* cpu) {
   return cpu->arch->uarch_str;
 }

src/riscv/uarch.h

@@ -9,6 +9,6 @@ struct uarch;
 char* get_arch_cpuinfo_str(struct cpuInfo* cpu);
 char* get_str_uarch(struct cpuInfo* cpu);
 void free_uarch_struct(struct uarch* arch);
-struct uarch* get_uarch_from_cpuinfo_str(char* cpuinfo_str, struct cpuInfo* cpu);
+struct uarch* get_uarch(struct cpuInfo* cpu);
 
 #endif

src/riscv/udev.c

@@ -7,6 +7,9 @@
 #define _PATH_DEVTREE          "/proc/device-tree/compatible"
 #define CPUINFO_UARCH_STR      "uarch\t\t: "
 #define CPUINFO_EXTENSIONS_STR "isa\t\t: "
+#define CPUINFO_RISCV_MVENDORID "mvendorid\t:"
+#define CPUINFO_RISCV_MARCHID   "marchid\t\t:"
+#define CPUINFO_RISCV_MIMPID    "mimpid\t\t:"
 #define DEVTREE_HARDWARE_FIELD 0
 
 char* get_field_from_devtree(int DEVTREE_FIELD) {
@@ -75,6 +78,52 @@ char* parse_cpuinfo_field(char* field_str) {
   return ret;
 }
 
+unsigned long parse_cpuinfo_field_uint64(char* field_str) {
+  int filelen;
+  char* buf;
+  if((buf = read_file(_PATH_CPUINFO, &filelen)) == NULL) {
+    printWarn("read_file: %s: %s", _PATH_CPUINFO, strerror(errno));
+    return 0;
+  }
+
+  char* tmp = strstr(buf, field_str);
+  if(tmp == NULL) return 0;
+  tmp += strlen(field_str);
+
+  char* end;
+  errno = 0;
+  unsigned long ret = strtoul(tmp, &end, 16);
+  if (errno != 0) {
+    printWarn("strtoul: %s: %s", strerror(errno), tmp);
+    return 0;
+  }
+
+  return ret;
+}
+
+// Creates and fills in the riscv_cpuinfo struct (which contains
+// mvendorid, marchid and mimpid) using cpuinfo to fetch the values.
+//
+// Every RISC-V hart (hardware thread) [1] provides a
+// marchid (Machine Architecture ID register) CSR that encodes its
+// base microarchitecture [2]. For more information about
+// marchid and the rest of values, see [3].
+// [1] https://groups.google.com/a/groups.riscv.org/g/sw-dev/c/QKjUDjz_vKo
+// [2] https://github.com/riscv/riscv-isa-manual/blob/main/marchid.md
+// [3] https://five-embeddev.com/riscv-priv-isa-manual/Priv-v1.12/machine.html#machine-architecture-id-register-marchid
+struct riscv_cpuinfo *get_riscv_cpuinfo(void) {
+  struct riscv_cpuinfo* ci = emalloc(sizeof(struct riscv_cpuinfo));
+
+  ci->mvendorid = parse_cpuinfo_field_uint64(CPUINFO_RISCV_MVENDORID);
+  ci->marchid = parse_cpuinfo_field_uint64(CPUINFO_RISCV_MARCHID);
+  ci->mimpid = parse_cpuinfo_field_uint64(CPUINFO_RISCV_MIMPID);
+
+  if (ci->mvendorid == 0 && ci->mvendorid == 0 && ci->mvendorid == 0)
+    return NULL;
+
+  return ci;
+}
+
 char* get_hardware_from_devtree(void) {
   return get_field_from_devtree(DEVTREE_HARDWARE_FIELD);
 }

src/riscv/udev.h

@@ -5,8 +5,16 @@
 
 #define UNKNOWN -1
 
+// https://elixir.bootlin.com/linux/v6.10.6/source/arch/riscv/include/asm/cpufeature.h#L21
+struct riscv_cpuinfo {
+  unsigned long mvendorid;
+  unsigned long marchid;
+  unsigned long mimpid;
+};
+
 char* get_hardware_from_devtree(void);
 char* get_uarch_from_cpuinfo(void);
 char* get_extensions_from_cpuinfo(void);
+struct riscv_cpuinfo *get_riscv_cpuinfo(void);
 
 #endif

src/x86/cpuid.c

@@ -210,18 +210,14 @@ int64_t get_peak_performance(struct cpuInfo* cpu, bool accurate_pp) {
 
   for(int i=0; i < cpu->num_cpus; ptr = ptr->next_cpu, i++) {
     struct topology* topo = ptr->topo;
-    int64_t max_freq = get_freq(ptr->freq);
+    int64_t freq = get_freq(ptr->freq);
 
-    int64_t freq;
   #ifdef __linux__
     if(accurate_pp)
-      freq = measure_frequency(ptr);
+      freq = get_freq_pp(ptr->freq);
-    else
-      freq = max_freq;
   #else
     // Silence compiler warning
     (void)(accurate_pp);
-    freq = max_freq;
   #endif
 
     //First, check we have consistent data
@@ -337,6 +333,15 @@ struct features* get_features_info(struct cpuInfo* cpu) {
     bool hv_present = (ecx & (1U << 31)) != 0;
     if((cpu->hv = get_hp_info(hv_present)) == NULL)
       return NULL;
+    if(cpu->hv->present) {
+      // Hypervisor will likely mess up something and users will think that
+      // there is something wrong with cpufetch whereas actually cpufetch has
+      // nothing to do with it.
+      // https://github.com/Dr-Noob/cpufetch/issues/96
+      // https://github.com/Dr-Noob/cpufetch/issues/267
+      // https://github.com/Dr-Noob/cpufetch/issues/293
+      printWarn("You are running an hypervisor. Please note that it will likely tamper your results, so do not post an issue if you find anything incorrect");
+    }
   }
   else {
     printWarn("Can't read features information from cpuid (needed level is 0x%.8X, max is 0x%.8X)", 0x00000001, cpu->maxLevels);
@@ -450,6 +455,23 @@ int32_t get_core_type(void) {
   }
 }
 
+#ifdef __linux__
+// Gets the max frequency for estimating the peak performance,
+// filling in the passed cpuInfo parameter with this information.
+void fill_frequency_info_pp(struct cpuInfo* cpu) {
+  int32_t unused;
+  int32_t *max_freq_pp_vec = malloc(sizeof(int32_t) * cpu->num_cpus);
+  struct cpuInfo* ptr = cpu;
+
+  for (uint32_t i=0; i < cpu->num_cpus; i++) {
+    set_cpu_module(i, cpu->num_cpus, &unused);
+
+    ptr->freq->max_pp = measure_frequency(ptr, max_freq_pp_vec);
+    ptr = ptr->next_cpu;
+  }
+}
+#endif
+
 struct cpuInfo* get_cpu_info(void) {
   struct cpuInfo* cpu = emalloc(sizeof(struct cpuInfo));
   cpu->peak_performance = -1;
@@ -546,6 +568,7 @@ struct cpuInfo* get_cpu_info(void) {
       ptr->core_type = get_core_type();
     }
     ptr->first_core_id = first_core;
+    ptr->module_id = i;
     ptr->feat = get_features_info(ptr);
 
     ptr->arch = get_cpu_uarch(ptr);
@@ -570,6 +593,13 @@ struct cpuInfo* get_cpu_info(void) {
     if(ptr->topo == NULL) return cpu;
   }
 
+#ifdef __linux__
+  // If accurate_pp is requested, we need to get the max frequency
+  // after fetching the topology for all CPU modules, since the topology
+  // is required by fill_frequency_info_pp
+  if (accurate_pp()) fill_frequency_info_pp(cpu);
+#endif
+
   cpu->peak_performance = get_peak_performance(cpu, accurate_pp());
 
   return cpu;
@@ -1005,6 +1035,7 @@ struct frequency* get_frequency_info(struct cpuInfo* cpu) {
     }
   #endif
 
+  freq->max_pp = UNKNOWN_DATA;
   return freq;
 }
 

src/x86/freq/freq.c

@@ -21,9 +21,12 @@
 #define FREQ_VECTOR_SIZE         1<<16
 
 struct freq_thread {
+  // Inputs
+  struct cpuInfo* cpu;
   bool end;
   bool measure;
-  double freq;
+  // Output
+  int32_t *max_pp;
 };
 
 double vector_average_harmonic(double* v, int len) {
@@ -48,6 +51,7 @@ void* measure_freq(void *freq_ptr) {
   char* line = NULL;
   size_t len = 0;
   ssize_t read;
+  struct cpuInfo* cpu = freq->cpu;
 
   int v = 0;
   double* freq_vector = malloc(sizeof(double) * FREQ_VECTOR_SIZE);
@@ -76,18 +80,43 @@ void* measure_freq(void *freq_ptr) {
     sleep_ms(500);
   }
 
-  freq->freq = vector_average_harmonic(freq_vector, v);
+  if (cpu->hybrid_flag) {
-  printWarn("AVX2 measured freq=%f\n", freq->freq);
+    // We have an heterogeneous architecture. After measuring the
+    // frequency for all cores, we now need to compute the average
+    // independently for each CPU module.
+    struct cpuInfo* ptr = cpu;
+    double* freq_vector_ptr = freq_vector;
+
+    for (int i=0; i < cpu->num_cpus; ptr = ptr->next_cpu, i++) {
+      freq->max_pp[i] = vector_average_harmonic(freq_vector_ptr, ptr->topo->total_cores_module);
+      printWarn("AVX2 measured freq=%d (module %d)", freq->max_pp[i], i);
+
+      freq_vector_ptr = freq_vector_ptr + ptr->topo->total_cores_module;
+    }
+  }
+  else {
+    freq->max_pp[0] = vector_average_harmonic(freq_vector, v);
+    printWarn("AVX2 measured freq=%d\n", freq->max_pp[0]);
+  }
 
   return NULL;
 }
 
-int64_t measure_frequency(struct cpuInfo* cpu) {
+int32_t measure_frequency(struct cpuInfo* cpu, int32_t *max_freq_pp_vec) {
+  if (cpu->hybrid_flag && cpu->module_id > 0) {
+    // We have a hybrid architecture and we have already
+    // measured the frequency for this module in a previous
+    // call to this function, so now just return it.
+    return max_freq_pp_vec[cpu->module_id];
+  }
+
   int ret;
   int num_spaces;
   struct freq_thread* freq_struct = malloc(sizeof(struct freq_thread));
   freq_struct->end = false;
   freq_struct->measure = false;
+  freq_struct->cpu = cpu;
+  freq_struct->max_pp = max_freq_pp_vec;
 
   void* (*compute_function)(void*);
 
@@ -159,5 +188,5 @@ int64_t measure_frequency(struct cpuInfo* cpu) {
   }
 
   printf("\r%*c", num_spaces, ' ');
-  return freq_struct->freq;
+  return max_freq_pp_vec[0];
 }

src/x86/freq/freq.h

@@ -8,6 +8,6 @@
 #define MEASURE_TIME_SECONDS         5
 #define LOOP_ITERS           100000000
 
-int64_t measure_frequency(struct cpuInfo* cpu);
+int32_t measure_frequency(struct cpuInfo* cpu, int32_t *max_freq_pp_vec);
 
 #endif

src/x86/uarch.c

@@ -93,6 +93,7 @@ enum {
   UARCH_CEDAR_MILL,
   UARCH_ITANIUM2,
   UARCH_ICE_LAKE,
+  UARCH_SAPPHIRE_RAPIDS,
   UARCH_TIGER_LAKE,
   UARCH_ALDER_LAKE,
   UARCH_RAPTOR_LAKE,
@@ -119,7 +120,9 @@ enum {
   UARCH_ZEN3,
   UARCH_ZEN3_PLUS,
   UARCH_ZEN4,
-  UARCH_ZEN4C
+  UARCH_ZEN4C,
+  UARCH_ZEN5,
+  UARCH_ZEN5C,
 };
 
 struct uarch {
@@ -252,7 +255,8 @@ struct uarch* get_uarch_from_cpuid_intel(uint32_t ef, uint32_t f, uint32_t em, u
   // CHECK_UARCH(arch, 0,  6,  8, 14,  9, ...) It is not possible to determine uarch only from CPUID dump (can be Kaby Lake or Amber Lake)
   // CHECK_UARCH(arch, 0,  6,  8, 14, 10, ...) It is not possible to determine uarch only from CPUID dump (can be Kaby Lake R or Coffee Lake U)
   CHECK_UARCH(arch, 0,  6,  8, 14, 11, "Whiskey Lake",      UARCH_WHISKEY_LAKE,     14) // wikichip
-  CHECK_UARCH(arch, 0,  6,  8, 14, 12, "Comet Lake",        UARCH_COMET_LAKE,       14) // wikichip
+  // CHECK_UARCH(arch, 0,  6,  8, 14, 12, ...) It is not possible to determine uarch only from CPUID dump (can be Comet Lake U or Whiskey Lake U)
+  CHECK_UARCH(arch, 0,  6,  8, 15,  8, "Sapphire Rapids",   UARCH_SAPPHIRE_RAPIDS,   7) // wikichip
   CHECK_UARCH(arch, 0,  6,  9,  6, NA, "Tremont",           UARCH_TREMONT,          10) // LX*
   CHECK_UARCH(arch, 0,  6,  9,  7, NA, "Alder Lake",        UARCH_ALDER_LAKE,       10) // instlatx64 (Alder Lake-S)
   CHECK_UARCH(arch, 0,  6,  9, 10, NA, "Alder Lake",        UARCH_ALDER_LAKE,       10) // instlatx64 (Alder Lake-P)
@@ -410,6 +414,12 @@ struct uarch* get_uarch_from_cpuid_amd(uint32_t ef, uint32_t f, uint32_t em, uin
   CHECK_UARCH(arch, 10, 15,  8, NA, NA, "Zen 4",       UARCH_ZEN4,         5) // instlatx64 (AMD MI300C)
   CHECK_UARCH(arch, 10, 15,  9, NA, NA, "Zen 4",       UARCH_ZEN4,         5) // instlatx64 (AMD MI300A)
   CHECK_UARCH(arch, 10, 15, 10, NA, NA, "Zen 4c",      UARCH_ZEN4C,        5) // instlatx64
+  CHECK_UARCH(arch, 11, 15,  0, NA, NA, "Zen 5",       UARCH_ZEN5,         4) // Turin/EPYC (instlatx64)
+  CHECK_UARCH(arch, 11, 15,  1, NA, NA, "Zen 5c",      UARCH_ZEN5C,        3) // Zen5c EPYC (instlatx64, https://en.wikipedia.org/wiki/Zen_5#cite_note-10)
+  CHECK_UARCH(arch, 11, 15,  2, NA, NA, "Zen 5",       UARCH_ZEN5,         4) // Strix Point (instlatx64)
+  CHECK_UARCH(arch, 11, 15,  4, NA, NA, "Zen 5",       UARCH_ZEN5,         4) // Granite Ridge (instlatx64)
+  CHECK_UARCH(arch, 11, 15,  6, NA, NA, "Zen 5",       UARCH_ZEN5,         4) // Krackan Point (instlatx64)
+  CHECK_UARCH(arch, 11, 15,  7, NA, NA, "Zen 5",       UARCH_ZEN5,         4) // Strix Halo (instlatx64)
   UARCH_END
 
   return arch;
@@ -437,6 +447,7 @@ struct uarch* get_uarch_from_cpuid_hygon(uint32_t ef, uint32_t f, uint32_t em, u
 struct uarch* get_uarch_from_cpuid(struct cpuInfo* cpu, uint32_t dump, uint32_t ef, uint32_t f, uint32_t em, uint32_t m, int s) {
   if(cpu->cpu_vendor == CPU_VENDOR_INTEL) {
     struct uarch* arch = emalloc(sizeof(struct uarch));
+    // TODO: Refactor these 3 checks in a common function.
     if(dump == 0x000806E9) {
       if (cpu->cpu_name == NULL) {
         printErr("Unable to find uarch without CPU name");
@@ -476,6 +487,30 @@ struct uarch* get_uarch_from_cpuid(struct cpuInfo* cpu, uint32_t dump, uint32_t
 
       return arch;
     }
+    else if (dump == 0x000806EC) {
+      if (cpu->cpu_name == NULL) {
+        printErr("Unable to find uarch without CPU name");
+        fill_uarch(arch, STRING_UNKNOWN, UARCH_UNKNOWN, UNK);
+        return arch;
+      }
+
+      // It is not possible to determine uarch only from CPUID dump (can be Comet Lake U or Whiskey Lake U)
+      // https://github.com/Dr-Noob/cpufetch/issues/298
+      if (strstr(cpu->cpu_name, "i3-8145U") != NULL ||
+          strstr(cpu->cpu_name, "i5-8265U") != NULL ||
+          strstr(cpu->cpu_name, "i5-8365U") != NULL ||
+          strstr(cpu->cpu_name, "i7-8565U") != NULL ||
+          strstr(cpu->cpu_name, "i7-8665U") != NULL ||
+          strstr(cpu->cpu_name, "5405U")    != NULL ||
+          strstr(cpu->cpu_name, "4205U")    != NULL) {
+        fill_uarch(arch, "Whiskey Lake", UARCH_WHISKEY_LAKE, 14);
+      }
+      else {
+        fill_uarch(arch, "Comet Lake", UARCH_COMET_LAKE, 14);
+      }
+
+      return arch;
+    }
     return get_uarch_from_cpuid_intel(ef, f, em, m, s);
   }
   else if(cpu->cpu_vendor == CPU_VENDOR_AMD) {
@@ -552,6 +587,8 @@ char* infer_cpu_name_from_uarch(struct uarch* arch) {
 }
 
 bool vpus_are_AVX512(struct cpuInfo* cpu) {
+  // Zen5 actually has 2 x AVX512 units
+  // https://www.anandtech.com/show/21469/amd-details-ryzen-ai-300-series-for-mobile-strix-point-with-rdna-35-igpu-xdna-2-npu
   return cpu->arch->uarch != UARCH_ICE_LAKE &&
          cpu->arch->uarch != UARCH_TIGER_LAKE &&
          cpu->arch->uarch != UARCH_ZEN4 &&
@@ -581,6 +618,7 @@ int get_number_of_vpus(struct cpuInfo* cpu) {
       case UARCH_KNIGHTS_LANDING:
       case UARCH_KNIGHTS_MILL:
 
+      case UARCH_SAPPHIRE_RAPIDS:
       case UARCH_ICE_LAKE:
       case UARCH_TIGER_LAKE:
       case UARCH_ALDER_LAKE:
@@ -592,6 +630,8 @@ int get_number_of_vpus(struct cpuInfo* cpu) {
       case UARCH_ZEN3_PLUS:
       case UARCH_ZEN4:
       case UARCH_ZEN4C:
+      case UARCH_ZEN5:
+      case UARCH_ZEN5C:
         return 2;
       default:
         return 1;