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5 Commits
i277 ... i279

Author SHA1 Message Date
Dr-Noob
5c4702bc1e [v1.06][ARM] Make Marvell logo shorter 2024-09-09 19:21:48 +01:00
Dr-Noob
177a92ba86 [v1.06][ARM] Add support for Marvell SoC (#279) 2024-09-09 19:17:27 +01:00
Dr-Noob
343150e516 [v1.06][ARM] Add Tegra Orin (#275) 2024-09-09 08:19:18 +01:00
Dr-Noob
1e2c7e565c [v1.06][ARM] Add SC8280XP (on device tree) (#272) 2024-09-09 07:11:57 +01:00
Dr-Noob
977c35a9af [v1.06][X86] Add Zen5 uarch 2024-09-05 20:14:52 +01:00
7 changed files with 44 additions and 3 deletions

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@@ -971,6 +971,11 @@ struct system_on_chip* guess_soc_from_devtree(struct system_on_chip* soc) {
DT_EQ(dt, len, soc, "apple,t6030", "M3 Pro", SOC_APPLE_M3_PRO, 3) DT_EQ(dt, len, soc, "apple,t6030", "M3 Pro", SOC_APPLE_M3_PRO, 3)
DT_EQ(dt, len, soc, "apple,t6031", "M3 Max", SOC_APPLE_M3_MAX, 3) DT_EQ(dt, len, soc, "apple,t6031", "M3 Max", SOC_APPLE_M3_MAX, 3)
DT_EQ(dt, len, soc, "apple,t6034", "M3 Max", SOC_APPLE_M3_MAX, 3) DT_EQ(dt, len, soc, "apple,t6034", "M3 Max", SOC_APPLE_M3_MAX, 3)
// NVIDIA
DT_EQ(dt, len, soc, "nvidia,tegra234", "Tegra Orin", SOC_TEGRA_ORIN, 8) // https://www.phoronix.com/news/NVIDIA-Orin-Tegra234-Audio, https://github.com/Dr-Noob/cpufetch/issues/275, https://en.wikipedia.org/wiki/Tegra#Orin
// Qualcomm now also in devtree...
// TODO: Integrate this with SOC_EQ
DT_EQ(dt, len, soc, "qcom,sc8280", "8cx Gen 3", SOC_SNAPD_SC8280XP, 5)
// grep -oR -h --color -E '"fsl,.*' *.dtsi | sort | uniq | cut -d ',' -f1-2 | grep -v '-' // grep -oR -h --color -E '"fsl,.*' *.dtsi | sort | uniq | cut -d ',' -f1-2 | grep -v '-'
// https://elixir.bootlin.com/linux/v6.10.6/source/arch/arm64/boot/dts/freescale // https://elixir.bootlin.com/linux/v6.10.6/source/arch/arm64/boot/dts/freescale
DT_EQ(dt, len, soc, "fsl,imx8qm", "i.MX 8QuadMax", SOC_NXP_IMX8QM, 28) // https://www.nxp.com/docs/en/fact-sheet/IMX8FAMFS.pdf DT_EQ(dt, len, soc, "fsl,imx8qm", "i.MX 8QuadMax", SOC_NXP_IMX8QM, 28) // https://www.nxp.com/docs/en/fact-sheet/IMX8FAMFS.pdf
@@ -986,6 +991,8 @@ struct system_on_chip* guess_soc_from_devtree(struct system_on_chip* soc) {
// https://www.amlogic.com/#Products/393/index.html // https://www.amlogic.com/#Products/393/index.html
// https://wikimovel.com/index.php/Amlogic_A311D // https://wikimovel.com/index.php/Amlogic_A311D
DT_EQ(dt, len, soc, "amlogic,a311d", "A311D", SOC_AMLOGIC_A311D, 12) DT_EQ(dt, len, soc, "amlogic,a311d", "A311D", SOC_AMLOGIC_A311D, 12)
// Marvell
DT_EQ(dt, len, soc, "marvell,armada3700", "Armada 3700", SOC_MARVELL_A3700, 28) // http://wiki.espressobin.net/tiki-index.php?page=Armada+3700 (pdf), https://github.com/Dr-Noob/cpufetch/issues/279
DT_END(dt, len) DT_END(dt, len)
} }

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@@ -318,6 +318,7 @@ enum {
SOC_SNAPD_SM8550_AB, SOC_SNAPD_SM8550_AB,
SOC_SNAPD_SM8635, SOC_SNAPD_SM8635,
SOC_SNAPD_SM8650_AB, SOC_SNAPD_SM8650_AB,
SOC_SNAPD_SC8280XP,
// APPLE // APPLE
SOC_APPLE_M1, SOC_APPLE_M1,
SOC_APPLE_M1_PRO, SOC_APPLE_M1_PRO,
@@ -380,6 +381,7 @@ enum {
SOC_GOOGLE_TENSOR_G3, SOC_GOOGLE_TENSOR_G3,
// NVIDIA, // NVIDIA,
SOC_TEGRA_X1, SOC_TEGRA_X1,
SOC_TEGRA_ORIN,
// ALTRA // ALTRA
SOC_AMPERE_ALTRA, SOC_AMPERE_ALTRA,
// NXP // NXP
@@ -393,6 +395,8 @@ enum {
SOC_NXP_IMX93, SOC_NXP_IMX93,
// AMLOGIC // AMLOGIC
SOC_AMLOGIC_A311D, SOC_AMLOGIC_A311D,
// MARVELL
SOC_MARVELL_A3700,
// UNKNOWN // UNKNOWN
SOC_MODEL_UNKNOWN SOC_MODEL_UNKNOWN
}; };
@@ -403,15 +407,16 @@ inline static VENDOR get_soc_vendor_from_soc(SOC soc) {
else if(soc >= SOC_KUNPENG_920 && soc <= SOC_KUNPENG_930) return SOC_VENDOR_KUNPENG; else if(soc >= SOC_KUNPENG_920 && soc <= SOC_KUNPENG_930) return SOC_VENDOR_KUNPENG;
else if(soc >= SOC_EXYNOS_3475 && soc <= SOC_EXYNOS_880) return SOC_VENDOR_EXYNOS; else if(soc >= SOC_EXYNOS_3475 && soc <= SOC_EXYNOS_880) return SOC_VENDOR_EXYNOS;
else if(soc >= SOC_MTK_MT6893 && soc <= SOC_MTK_MT8783) return SOC_VENDOR_MEDIATEK; else if(soc >= SOC_MTK_MT6893 && soc <= SOC_MTK_MT8783) return SOC_VENDOR_MEDIATEK;
else if(soc >= SOC_SNAPD_QSD8650 && soc <= SOC_SNAPD_SM8650_AB) return SOC_VENDOR_SNAPDRAGON; else if(soc >= SOC_SNAPD_QSD8650 && soc <= SOC_SNAPD_SC8280XP) return SOC_VENDOR_SNAPDRAGON;
else if(soc >= SOC_APPLE_M1 && soc <= SOC_APPLE_M3_MAX) return SOC_VENDOR_APPLE; else if(soc >= SOC_APPLE_M1 && soc <= SOC_APPLE_M3_MAX) return SOC_VENDOR_APPLE;
else if(soc >= SOC_ALLWINNER_A10 && soc <= SOC_ALLWINNER_R328) return SOC_VENDOR_ALLWINNER; else if(soc >= SOC_ALLWINNER_A10 && soc <= SOC_ALLWINNER_R328) return SOC_VENDOR_ALLWINNER;
else if(soc >= SOC_ROCKCHIP_3288 && soc <= SOC_ROCKCHIP_3588) return SOC_VENDOR_ROCKCHIP; else if(soc >= SOC_ROCKCHIP_3288 && soc <= SOC_ROCKCHIP_3588) return SOC_VENDOR_ROCKCHIP;
else if(soc >= SOC_GOOGLE_TENSOR && soc <= SOC_GOOGLE_TENSOR_G3) return SOC_VENDOR_GOOGLE; else if(soc >= SOC_GOOGLE_TENSOR && soc <= SOC_GOOGLE_TENSOR_G3) return SOC_VENDOR_GOOGLE;
else if(soc >= SOC_TEGRA_X1 && soc <= SOC_TEGRA_X1) return SOC_VENDOR_NVIDIA; else if(soc >= SOC_TEGRA_X1 && soc <= SOC_TEGRA_ORIN) return SOC_VENDOR_NVIDIA;
else if(soc >= SOC_AMPERE_ALTRA && soc <= SOC_AMPERE_ALTRA) return SOC_VENDOR_AMPERE; else if(soc >= SOC_AMPERE_ALTRA && soc <= SOC_AMPERE_ALTRA) return SOC_VENDOR_AMPERE;
else if(soc >= SOC_NXP_IMX8QM && soc <= SOC_NXP_IMX93) return SOC_VENDOR_NXP; else if(soc >= SOC_NXP_IMX8QM && soc <= SOC_NXP_IMX93) return SOC_VENDOR_NXP;
else if(soc >= SOC_AMLOGIC_A311D && soc <= SOC_AMLOGIC_A311D) return SOC_VENDOR_AMLOGIC; else if(soc >= SOC_AMLOGIC_A311D && soc <= SOC_AMLOGIC_A311D) return SOC_VENDOR_AMLOGIC;
else if(soc >= SOC_MARVELL_A3700 && soc <= SOC_MARVELL_A3700) return SOC_VENDOR_MARVELL;
return SOC_VENDOR_UNKNOWN; return SOC_VENDOR_UNKNOWN;
} }

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@@ -433,6 +433,18 @@ $C1#########.### ## ## ## ## ### ###### ## ### \
$C1 ### \ $C1 ### \
$C1 ### " $C1 ### "
#define ASCII_MARVELL \
"$C1 ........... ........... \
$C1 .### . .## . \
$C1 .##### . #### . \
$C1 ####### . ####### . \
$C1 .#########__________. #########__________. \
$C1 .###########|__________|#########|__________| \
$C1 ############ ______############ __________ \
$C1 .######### |__________|###### |__________| \
$C1 ########### ___########### __________ \
$C1.########## |__________| |__________| "
// --------------------- LONG LOGOS ------------------------- // // --------------------- LONG LOGOS ------------------------- //
#define ASCII_AMD_L \ #define ASCII_AMD_L \
"$C1 \ "$C1 \
@@ -611,6 +623,7 @@ asciiL logo_nvidia = { ASCII_NVIDIA, 45, 19, false, {C_FG_GREEN, C_FG_
asciiL logo_ampere = { ASCII_AMPERE, 50, 17, false, {C_FG_RED}, {C_FG_WHITE, C_FG_RED} }; asciiL logo_ampere = { ASCII_AMPERE, 50, 17, false, {C_FG_RED}, {C_FG_WHITE, C_FG_RED} };
asciiL logo_nxp = { ASCII_NXP, 55, 8, false, {C_FG_YELLOW, C_FG_CYAN, C_FG_GREEN}, {C_FG_CYAN, C_FG_WHITE} }; asciiL logo_nxp = { ASCII_NXP, 55, 8, false, {C_FG_YELLOW, C_FG_CYAN, C_FG_GREEN}, {C_FG_CYAN, C_FG_WHITE} };
asciiL logo_amlogic = { ASCII_AMLOGIC, 58, 8, false, {C_FG_BLUE}, {C_FG_BLUE, C_FG_B_WHITE} }; asciiL logo_amlogic = { ASCII_AMLOGIC, 58, 8, false, {C_FG_BLUE}, {C_FG_BLUE, C_FG_B_WHITE} };
asciiL logo_marvell = { ASCII_MARVELL, 56, 10, false, {C_FG_B_BLACK}, {C_FG_B_BLACK, C_FG_B_WHITE} };
// Long variants | ----------------------------------------------------------------------------------------------------------------| // Long variants | ----------------------------------------------------------------------------------------------------------------|
asciiL logo_amd_l = { ASCII_AMD_L, 62, 19, true, {C_BG_WHITE, C_BG_GREEN}, {C_FG_WHITE, C_FG_GREEN} }; asciiL logo_amd_l = { ASCII_AMD_L, 62, 19, true, {C_BG_WHITE, C_BG_GREEN}, {C_FG_WHITE, C_FG_GREEN} };

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@@ -395,6 +395,8 @@ void choose_ascii_art(struct ascii* art, struct color** cs, struct terminal* ter
art->art = &logo_nxp; art->art = &logo_nxp;
else if(art->vendor == SOC_VENDOR_AMLOGIC) else if(art->vendor == SOC_VENDOR_AMLOGIC)
art->art = &logo_amlogic; art->art = &logo_amlogic;
else if(art->vendor == SOC_VENDOR_MARVELL)
art->art = &logo_marvell;
else if(art->vendor == SOC_VENDOR_NVIDIA) else if(art->vendor == SOC_VENDOR_NVIDIA)
art->art = choose_ascii_art_aux(&logo_nvidia_l, &logo_nvidia, term, lf); art->art = choose_ascii_art_aux(&logo_nvidia_l, &logo_nvidia, term, lf);
else { else {

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@@ -24,6 +24,7 @@ static char* soc_trademark_string[] = {
[SOC_VENDOR_AMPERE] = "Ampere ", [SOC_VENDOR_AMPERE] = "Ampere ",
[SOC_VENDOR_NXP] = "NXP ", [SOC_VENDOR_NXP] = "NXP ",
[SOC_VENDOR_AMLOGIC] = "Amlogic ", [SOC_VENDOR_AMLOGIC] = "Amlogic ",
[SOC_VENDOR_MARVELL] = "Marvell",
// RISC-V // RISC-V
[SOC_VENDOR_SIFIVE] = "SiFive ", [SOC_VENDOR_SIFIVE] = "SiFive ",
[SOC_VENDOR_STARFIVE] = "StarFive ", [SOC_VENDOR_STARFIVE] = "StarFive ",

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@@ -28,6 +28,7 @@ enum {
SOC_VENDOR_AMPERE, SOC_VENDOR_AMPERE,
SOC_VENDOR_NXP, SOC_VENDOR_NXP,
SOC_VENDOR_AMLOGIC, SOC_VENDOR_AMLOGIC,
SOC_VENDOR_MARVELL,
// RISC-V // RISC-V
SOC_VENDOR_SIFIVE, SOC_VENDOR_SIFIVE,
SOC_VENDOR_STARFIVE, SOC_VENDOR_STARFIVE,

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@@ -119,7 +119,9 @@ enum {
UARCH_ZEN3, UARCH_ZEN3,
UARCH_ZEN3_PLUS, UARCH_ZEN3_PLUS,
UARCH_ZEN4, UARCH_ZEN4,
UARCH_ZEN4C UARCH_ZEN4C,
UARCH_ZEN5,
UARCH_ZEN5C,
}; };
struct uarch { struct uarch {
@@ -410,6 +412,12 @@ struct uarch* get_uarch_from_cpuid_amd(uint32_t ef, uint32_t f, uint32_t em, uin
CHECK_UARCH(arch, 10, 15, 8, NA, NA, "Zen 4", UARCH_ZEN4, 5) // instlatx64 (AMD MI300C) CHECK_UARCH(arch, 10, 15, 8, NA, NA, "Zen 4", UARCH_ZEN4, 5) // instlatx64 (AMD MI300C)
CHECK_UARCH(arch, 10, 15, 9, NA, NA, "Zen 4", UARCH_ZEN4, 5) // instlatx64 (AMD MI300A) CHECK_UARCH(arch, 10, 15, 9, NA, NA, "Zen 4", UARCH_ZEN4, 5) // instlatx64 (AMD MI300A)
CHECK_UARCH(arch, 10, 15, 10, NA, NA, "Zen 4c", UARCH_ZEN4C, 5) // instlatx64 CHECK_UARCH(arch, 10, 15, 10, NA, NA, "Zen 4c", UARCH_ZEN4C, 5) // instlatx64
CHECK_UARCH(arch, 11, 15, 0, NA, NA, "Zen 5", UARCH_ZEN5, 4) // Turin/EPYC (instlatx64)
CHECK_UARCH(arch, 11, 15, 1, NA, NA, "Zen 5c", UARCH_ZEN5C, 3) // Zen5c EPYC (instlatx64, https://en.wikipedia.org/wiki/Zen_5#cite_note-10)
CHECK_UARCH(arch, 11, 15, 2, NA, NA, "Zen 5", UARCH_ZEN5, 4) // Strix Point (instlatx64)
CHECK_UARCH(arch, 11, 15, 4, NA, NA, "Zen 5", UARCH_ZEN5, 4) // Granite Ridge (instlatx64)
CHECK_UARCH(arch, 11, 15, 6, NA, NA, "Zen 5", UARCH_ZEN5, 4) // Krackan Point (instlatx64)
CHECK_UARCH(arch, 11, 15, 7, NA, NA, "Zen 5", UARCH_ZEN5, 4) // Strix Halo (instlatx64)
UARCH_END UARCH_END
return arch; return arch;
@@ -552,6 +560,8 @@ char* infer_cpu_name_from_uarch(struct uarch* arch) {
} }
bool vpus_are_AVX512(struct cpuInfo* cpu) { bool vpus_are_AVX512(struct cpuInfo* cpu) {
// Zen5 actually has 2 x AVX512 units
// https://www.anandtech.com/show/21469/amd-details-ryzen-ai-300-series-for-mobile-strix-point-with-rdna-35-igpu-xdna-2-npu
return cpu->arch->uarch != UARCH_ICE_LAKE && return cpu->arch->uarch != UARCH_ICE_LAKE &&
cpu->arch->uarch != UARCH_TIGER_LAKE && cpu->arch->uarch != UARCH_TIGER_LAKE &&
cpu->arch->uarch != UARCH_ZEN4 && cpu->arch->uarch != UARCH_ZEN4 &&
@@ -592,6 +602,8 @@ int get_number_of_vpus(struct cpuInfo* cpu) {
case UARCH_ZEN3_PLUS: case UARCH_ZEN3_PLUS:
case UARCH_ZEN4: case UARCH_ZEN4:
case UARCH_ZEN4C: case UARCH_ZEN4C:
case UARCH_ZEN5:
case UARCH_ZEN5C:
return 2; return 2;
default: default:
return 1; return 1;