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riscv-new-
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a5d52b59df | ||
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f09454d442 |
@@ -445,6 +445,26 @@ $C1 .######### |__________|###### |__________| \
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$C1 ########### ___########### __________ \
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$C1.########## |__________| |__________| "
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#define ASCII_SPACEMIT \
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"$C1 :#: \
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$C1 :####: \
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$C1 :#######: \
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$C1 :#########: \
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$C1 :#########: \
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$C1 :#######: \
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$C1 :####: \
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$C1 :#: \
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$C1:##: :#: \
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$C1:####: :###: \
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$C1:#######: :####: \
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$C1:##########: :###: \
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$C1:###########: :#: \
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$C1:###########: \
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$C1 :##########: \
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$C1 :#######: \
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$C1 :####: \
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$C1 :##: "
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// --------------------- LONG LOGOS ------------------------- //
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#define ASCII_AMD_L \
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"$C1 \
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@@ -624,6 +644,7 @@ asciiL logo_ampere = { ASCII_AMPERE, 50, 17, false, {C_FG_RED},
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asciiL logo_nxp = { ASCII_NXP, 55, 8, false, {C_FG_YELLOW, C_FG_CYAN, C_FG_GREEN}, {C_FG_CYAN, C_FG_WHITE} };
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asciiL logo_amlogic = { ASCII_AMLOGIC, 58, 8, false, {C_FG_BLUE}, {C_FG_BLUE, C_FG_B_WHITE} };
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asciiL logo_marvell = { ASCII_MARVELL, 56, 10, false, {C_FG_B_BLACK}, {C_FG_B_BLACK, C_FG_B_WHITE} };
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asciiL logo_spacemit = { ASCII_SPACEMIT, 27, 18, false, {C_FG_B_GREEN}, {C_FG_B_GREEN, C_FG_B_WHITE} };
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// Long variants | ----------------------------------------------------------------------------------------------------------------|
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asciiL logo_amd_l = { ASCII_AMD_L, 62, 19, true, {C_BG_WHITE, C_BG_GREEN}, {C_FG_WHITE, C_FG_GREEN} };
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@@ -25,6 +25,7 @@ enum {
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CPU_VENDOR_RISCV,
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CPU_VENDOR_SIFIVE,
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CPU_VENDOR_THEAD,
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CPU_VENDOR_SPACEMIT,
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// OTHERS
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CPU_VENDOR_UNKNOWN,
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CPU_VENDOR_INVALID
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@@ -137,7 +138,7 @@ struct features {
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struct extensions {
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char* str;
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uint64_t mask;
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bool* mask; // allocated at runtime with size RISCV_ISA_EXT_ID_MAX-1
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};
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struct cpuInfo {
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@@ -45,9 +45,17 @@
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#define MAX_ATTRIBUTES 100
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#define MAX_TERM_SIZE 1024
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typedef struct {
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int id;
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const char *name;
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const char *shortname;
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} AttributeField;
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enum {
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#if defined(ARCH_X86) || defined(ARCH_PPC)
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#if defined(ARCH_X86)
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ATTRIBUTE_NAME,
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#elif defined(ARCH_PPC)
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ATTRIBUTE_PART_NUMBER,
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#elif defined(ARCH_ARM) || defined(ARCH_RISCV)
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ATTRIBUTE_SOC,
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#endif
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@@ -79,76 +87,40 @@ enum {
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ATTRIBUTE_PEAK
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};
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static const char* ATTRIBUTE_FIELDS [] = {
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#ifdef ARCH_X86
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"Name:",
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#elif ARCH_PPC
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"Part Number:",
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#elif defined(ARCH_ARM) || defined(ARCH_RISCV)
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"SoC:",
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#endif
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#if defined(ARCH_X86) || defined(ARCH_ARM)
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"",
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#endif
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"Hypervisor:",
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"Microarchitecture:",
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"Technology:",
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"Max Frequency:",
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"Sockets:",
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"Cores:",
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"Cores (Total):",
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#ifdef ARCH_X86
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"SSE:",
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"AVX:",
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"FMA:",
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#elif ARCH_PPC
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"Altivec: ",
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#elif defined(ARCH_ARM)
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"Features: ",
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#elif defined(ARCH_RISCV)
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"Extensions: ",
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#endif
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"L1i Size:",
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"L1d Size:",
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"L2 Size:",
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"L3 Size:",
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"Peak Performance:",
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};
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static const char* ATTRIBUTE_FIELDS_SHORT [] = {
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static const AttributeField ATTRIBUTE_INFO[] = {
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#if defined(ARCH_X86)
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"Name:",
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#elif ARCH_PPC
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"P/N:",
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#elif ARCH_ARM
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"SoC:",
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{ ATTRIBUTE_NAME, "Name:", "Name:" },
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#elif defined(ARCH_PPC)
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{ ATTRIBUTE_PART_NUMBER, "Part Number:", "P/N:" },
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#elif defined(ARCH_ARM) || defined(ARCH_RISCV)
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{ ATTRIBUTE_SOC, "SoC:", "SoC:" },
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#endif
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#if defined(ARCH_X86) || defined(ARCH_ARM)
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"",
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{ ATTRIBUTE_CPU_NUM, "", "" },
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#endif
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"Hypervisor:",
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"uArch:",
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"Technology:",
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"Max Freq:",
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"Sockets:",
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"Cores:",
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"Cores (Total):",
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{ ATTRIBUTE_HYPERVISOR, "Hypervisor:", "Hypervisor:" },
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{ ATTRIBUTE_UARCH, "Microarchitecture:", "uArch:" },
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{ ATTRIBUTE_TECHNOLOGY, "Technology:", "Technology:" },
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{ ATTRIBUTE_FREQUENCY, "Max Frequency:", "Max Freq:" },
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{ ATTRIBUTE_SOCKETS, "Sockets:", "Sockets:" },
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{ ATTRIBUTE_NCORES, "Cores:", "Cores:" },
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{ ATTRIBUTE_NCORES_DUAL, "Cores (Total):", "Cores (Total):" },
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#ifdef ARCH_X86
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"SSE:",
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"AVX:",
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"FMA:",
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{ ATTRIBUTE_SSE, "SSE:", "SSE:" },
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{ ATTRIBUTE_AVX, "AVX:", "AVX:" },
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{ ATTRIBUTE_FMA, "FMA:", "FMA:" },
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#elif ARCH_PPC
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"Altivec: ",
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#elif defined(ARCH_ARM)
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"Features: ",
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#elif defined(ARCH_RISCV)
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"Extensions: ",
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{ ATTRIBUTE_ALTIVEC, "Altivec: ", "Altivec: " },
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#elif ARCH_ARM
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{ ATTRIBUTE_FEATURES, "Features: ", "Features: " },
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#elif ARCH_RISCV
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{ ATTRIBUTE_EXTENSIONS, "Extensions: ", "Extensions: " },
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#endif
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"L1i Size:",
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"L1d Size:",
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"L2 Size:",
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"L3 Size:",
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"Peak Perf.:",
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{ ATTRIBUTE_L1i, "L1i Size:", "L1i Size:" },
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{ ATTRIBUTE_L1d, "L1d Size:", "L1d Size:" },
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{ ATTRIBUTE_L2, "L2 Size:", "L2 Size:" },
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{ ATTRIBUTE_L3, "L3 Size:", "L3 Size:" },
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{ ATTRIBUTE_PEAK, "Peak Performance:", "Peak Perf.:" },
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};
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struct terminal {
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@@ -412,6 +384,8 @@ void choose_ascii_art(struct ascii* art, struct color** cs, struct terminal* ter
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art->art = &logo_allwinner;
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else if(art->vendor == SOC_VENDOR_SIPEED)
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art->art = &logo_sipeed;
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else if(art->vendor == SOC_VENDOR_SPACEMIT)
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art->art = &logo_spacemit;
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else
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art->art = &logo_riscv;
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#endif
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@@ -452,13 +426,14 @@ void choose_ascii_art(struct ascii* art, struct color** cs, struct terminal* ter
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}
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}
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uint32_t longest_attribute_length(struct ascii* art, const char** attribute_fields) {
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uint32_t longest_attribute_length(struct ascii* art, bool use_short) {
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uint32_t max = 0;
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uint64_t len = 0;
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for(uint32_t i=0; i < art->n_attributes_set; i++) {
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if(art->attributes[i]->value != NULL) {
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len = strlen(attribute_fields[art->attributes[i]->type]);
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const char* str = use_short ? ATTRIBUTE_INFO[art->attributes[i]->type].shortname : ATTRIBUTE_INFO[art->attributes[i]->type].name;
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len = strlen(str);
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if(len > max) max = len;
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}
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}
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@@ -483,7 +458,7 @@ uint32_t longest_field_length(struct ascii* art, int la) {
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}
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#if defined(ARCH_X86) || defined(ARCH_PPC)
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void print_ascii_generic(struct ascii* art, uint32_t la, int32_t termw, const char** attribute_fields, bool hybrid_architecture) {
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void print_ascii_generic(struct ascii* art, uint32_t la, int32_t termw, bool use_short, bool hybrid_architecture) {
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struct ascii_logo* logo = art->art;
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int attr_to_print = 0;
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int attr_type;
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@@ -545,14 +520,15 @@ void print_ascii_generic(struct ascii* art, uint32_t la, int32_t termw, const ch
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else {
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#endif
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beg_space = 0;
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space_right = 2 + 1 + (la - strlen(attribute_fields[attr_type]));
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const char* attr_str = use_short ? ATTRIBUTE_INFO[attr_type].shortname : ATTRIBUTE_INFO[attr_type].name;
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space_right = 2 + 1 + (la - strlen(attr_str));
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if(hybrid_architecture && add_space) {
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beg_space = 2;
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space_right -= 2;
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}
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printOut(lbuf, beg_space + strlen(attribute_fields[attr_type]) + space_right + strlen(attr_value),
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"%*s%s%s%s%*s%s%s%s", beg_space, "", logo->color_text[0], attribute_fields[attr_type], art->reset, space_right, "", logo->color_text[1], attr_value, art->reset);
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printOut(lbuf, beg_space + strlen(attr_str) + space_right + strlen(attr_value),
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"%*s%s%s%s%*s%s%s%s", beg_space, "", logo->color_text[0], attr_str, art->reset, space_right, "", logo->color_text[1], attr_value, art->reset);
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#ifdef ARCH_X86
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}
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#endif
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@@ -661,19 +637,19 @@ bool print_cpufetch_x86(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
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setAttribute(art, ATTRIBUTE_PEAK, pp);
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// Step 3. Print output
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const char** attribute_fields = ATTRIBUTE_FIELDS;
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uint32_t longest_attribute = longest_attribute_length(art, attribute_fields);
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bool use_short = false;
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uint32_t longest_attribute = longest_attribute_length(art, use_short);
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uint32_t longest_field = longest_field_length(art, longest_attribute);
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choose_ascii_art(art, cs, term, longest_field);
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if(!ascii_fits_screen(term->w, *art->art, longest_field)) {
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// Despite of choosing the smallest logo, the output does not fit
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// Choose the shorter field names and recalculate the longest attr
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attribute_fields = ATTRIBUTE_FIELDS_SHORT;
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longest_attribute = longest_attribute_length(art, attribute_fields);
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use_short = true;
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longest_attribute = longest_attribute_length(art, use_short);
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}
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print_ascii_generic(art, longest_attribute, term->w, attribute_fields, hybrid_architecture);
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print_ascii_generic(art, longest_attribute, term->w, use_short, hybrid_architecture);
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free(manufacturing_process);
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free(sockets);
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@@ -722,7 +698,7 @@ bool print_cpufetch_ppc(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
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// Step 2. Set attributes
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if(cpu_name != NULL) {
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setAttribute(art, ATTRIBUTE_NAME, cpu_name);
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setAttribute(art, ATTRIBUTE_PART_NUMBER, cpu_name);
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}
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setAttribute(art, ATTRIBUTE_UARCH, uarch);
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if(cpu->hv->present) {
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@@ -749,19 +725,19 @@ bool print_cpufetch_ppc(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
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setAttribute(art, ATTRIBUTE_PEAK, pp);
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// Step 3. Print output
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const char** attribute_fields = ATTRIBUTE_FIELDS;
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uint32_t longest_attribute = longest_attribute_length(art, attribute_fields);
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bool use_short = false;
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uint32_t longest_attribute = longest_attribute_length(art, use_short);
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uint32_t longest_field = longest_field_length(art, longest_attribute);
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choose_ascii_art(art, cs, term, longest_field);
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if(!ascii_fits_screen(term->w, *art->art, longest_field)) {
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// Despite of choosing the smallest logo, the output does not fit
|
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// Choose the shorter field names and recalculate the longest attr
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attribute_fields = ATTRIBUTE_FIELDS_SHORT;
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longest_attribute = longest_attribute_length(art, attribute_fields);
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use_short = true;
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longest_attribute = longest_attribute_length(art, use_short);
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}
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print_ascii_generic(art, longest_attribute, term->w, attribute_fields, false);
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print_ascii_generic(art, longest_attribute, term->w, use_short, false);
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return true;
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}
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@@ -789,7 +765,7 @@ uint32_t longest_field_length_arm(struct ascii* art, int la) {
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return max;
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}
|
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|
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void print_ascii_arm(struct ascii* art, uint32_t la, int32_t termw, const char** attribute_fields) {
|
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void print_ascii_arm(struct ascii* art, uint32_t la, int32_t termw, bool use_short) {
|
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struct ascii_logo* logo = art->art;
|
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int attr_to_print = 0;
|
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int attr_type;
|
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@@ -860,14 +836,15 @@ void print_ascii_arm(struct ascii* art, uint32_t la, int32_t termw, const char**
|
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}
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else {
|
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beg_space = 0;
|
||||
space_right = 2 + 1 + (la - strlen(attribute_fields[attr_type]));
|
||||
const char* attr_str = use_short ? ATTRIBUTE_INFO[attr_type].shortname : ATTRIBUTE_INFO[attr_type].name;
|
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space_right = 2 + 1 + (la - strlen(attr_str));
|
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if(add_space) {
|
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beg_space = 2;
|
||||
space_right -= 2;
|
||||
}
|
||||
|
||||
printOut(lbuf, beg_space + strlen(attribute_fields[attr_type]) + space_right + strlen(attr_value),
|
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"%*s%s%s%s%*s%s%s%s", beg_space, "", logo->color_text[0], attribute_fields[attr_type], art->reset, space_right, "", logo->color_text[1], attr_value, art->reset);
|
||||
printOut(lbuf, beg_space + strlen(attr_str) + space_right + strlen(attr_value),
|
||||
"%*s%s%s%s%*s%s%s%s", beg_space, "", logo->color_text[0], attr_str, art->reset, space_right, "", logo->color_text[1], attr_value, art->reset);
|
||||
}
|
||||
}
|
||||
printOutLine(lbuf, art, termw);
|
||||
@@ -937,8 +914,8 @@ bool print_cpufetch_arm(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
|
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setAttribute(art, ATTRIBUTE_HYPERVISOR, cpu->hv->hv_name);
|
||||
}
|
||||
|
||||
const char** attribute_fields = ATTRIBUTE_FIELDS;
|
||||
uint32_t longest_attribute = longest_attribute_length(art, attribute_fields);
|
||||
bool use_short = false;
|
||||
uint32_t longest_attribute = longest_attribute_length(art, use_short);
|
||||
uint32_t longest_field = longest_field_length_arm(art, longest_attribute);
|
||||
choose_ascii_art(art, cs, term, longest_field);
|
||||
|
||||
@@ -950,11 +927,11 @@ bool print_cpufetch_arm(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
|
||||
if(!ascii_fits_screen(term->w, *art->art, longest_field)) {
|
||||
// Despite of choosing the smallest logo, the output does not fit
|
||||
// Choose the shorter field names and recalculate the longest attr
|
||||
attribute_fields = ATTRIBUTE_FIELDS_SHORT;
|
||||
longest_attribute = longest_attribute_length(art, attribute_fields);
|
||||
use_short = true;
|
||||
longest_attribute = longest_attribute_length(art, use_short);
|
||||
}
|
||||
|
||||
print_ascii_arm(art, longest_attribute, term->w, attribute_fields);
|
||||
print_ascii_arm(art, longest_attribute, term->w, use_short);
|
||||
|
||||
free(manufacturing_process);
|
||||
free(pp);
|
||||
@@ -972,14 +949,7 @@ bool print_cpufetch_arm(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
|
||||
#endif
|
||||
|
||||
#ifdef ARCH_RISCV
|
||||
// https://stackoverflow.com/a/2709523
|
||||
uint64_t number_of_bits(uint64_t i) {
|
||||
i = i - ((i >> 1) & 0x5555555555555555);
|
||||
i = (i & 0x3333333333333333) + ((i >> 2) & 0x3333333333333333);
|
||||
return (((i + (i >> 4)) & 0xF0F0F0F0F0F0F0F) * 0x101010101010101) >> 56;
|
||||
}
|
||||
|
||||
void print_ascii_riscv(struct ascii* art, uint32_t la, int32_t termw, const char** attribute_fields, uint64_t extensions_mask) {
|
||||
void print_ascii_riscv(struct ascii* art, uint32_t la, int32_t termw, bool use_short, bool* extensions_mask) {
|
||||
struct ascii_logo* logo = art->art;
|
||||
int attr_to_print = 0;
|
||||
int attr_type;
|
||||
@@ -989,7 +959,7 @@ void print_ascii_riscv(struct ascii* art, uint32_t la, int32_t termw, const char
|
||||
int32_t ext_list_size = sizeof(extension_list)/sizeof(extension_list[0]);
|
||||
int32_t ext_num = 0;
|
||||
int32_t ext_to_print = 0;
|
||||
int32_t num_extensions = number_of_bits(extensions_mask);
|
||||
int32_t num_extensions = get_num_extensions(extensions_mask);
|
||||
int32_t space_up = ((int)logo->height - (int)(art->n_attributes_set + num_extensions))/2;
|
||||
int32_t space_down = (int)logo->height - (int)(art->n_attributes_set + num_extensions) - (int)space_up;
|
||||
uint32_t logo_pos = 0;
|
||||
@@ -1035,7 +1005,9 @@ void print_ascii_riscv(struct ascii* art, uint32_t la, int32_t termw, const char
|
||||
// Print extension
|
||||
if(attr_to_print > 0 && art->attributes[attr_to_print-1]->type == ATTRIBUTE_EXTENSIONS && ext_num != num_extensions) {
|
||||
// Search for the extension to print
|
||||
while(ext_to_print < ext_list_size && !((extensions_mask >> extension_list[ext_to_print].id) & 1U)) ext_to_print++;
|
||||
while (ext_to_print < ext_list_size && !((extensions_mask[extension_list[ext_to_print].id])))
|
||||
ext_to_print++;
|
||||
|
||||
if(ext_to_print == ext_list_size) {
|
||||
printBug("print_ascii_riscv: Unable to find the extension to print");
|
||||
}
|
||||
@@ -1047,10 +1019,11 @@ void print_ascii_riscv(struct ascii* art, uint32_t la, int32_t termw, const char
|
||||
else {
|
||||
attr_to_print++;
|
||||
beg_space = 0;
|
||||
space_right = 2 + 1 + (la - strlen(attribute_fields[attr_type]));
|
||||
const char* attr_str = use_short ? ATTRIBUTE_INFO[attr_type].shortname : ATTRIBUTE_INFO[attr_type].name;
|
||||
space_right = 2 + 1 + (la - strlen(attr_str));
|
||||
|
||||
printOut(lbuf, beg_space + strlen(attribute_fields[attr_type]) + space_right + strlen(attr_value),
|
||||
"%*s%s%s%s%*s%s%s%s", beg_space, "", logo->color_text[0], attribute_fields[attr_type], art->reset, space_right, "", logo->color_text[1], attr_value, art->reset);
|
||||
printOut(lbuf, beg_space + strlen(attr_str) + space_right + strlen(attr_value),
|
||||
"%*s%s%s%s%*s%s%s%s", beg_space, "", logo->color_text[0], attr_str, art->reset, space_right, "", logo->color_text[1], attr_value, art->reset);
|
||||
}
|
||||
}
|
||||
printOutLine(lbuf, art, termw);
|
||||
@@ -1088,19 +1061,19 @@ bool print_cpufetch_riscv(struct cpuInfo* cpu, STYLE s, struct color** cs, struc
|
||||
setAttribute(art, ATTRIBUTE_PEAK, pp);
|
||||
|
||||
// Step 3. Print output
|
||||
const char** attribute_fields = ATTRIBUTE_FIELDS;
|
||||
uint32_t longest_attribute = longest_attribute_length(art, attribute_fields);
|
||||
bool use_short = false;
|
||||
uint32_t longest_attribute = longest_attribute_length(art, use_short);
|
||||
uint32_t longest_field = longest_field_length(art, longest_attribute);
|
||||
choose_ascii_art(art, cs, term, longest_field);
|
||||
|
||||
if(!ascii_fits_screen(term->w, *art->art, longest_field)) {
|
||||
// Despite of choosing the smallest logo, the output does not fit
|
||||
// Choose the shorter field names and recalculate the longest attr
|
||||
attribute_fields = ATTRIBUTE_FIELDS_SHORT;
|
||||
longest_attribute = longest_attribute_length(art, attribute_fields);
|
||||
use_short = true;
|
||||
longest_attribute = longest_attribute_length(art, use_short);
|
||||
}
|
||||
|
||||
print_ascii_riscv(art, longest_attribute, term->w, attribute_fields, cpu->ext->mask);
|
||||
print_ascii_riscv(art, longest_attribute, term->w, use_short, cpu->ext->mask);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
@@ -29,6 +29,7 @@ static char* soc_trademark_string[] = {
|
||||
[SOC_VENDOR_SIFIVE] = "SiFive ",
|
||||
[SOC_VENDOR_STARFIVE] = "StarFive ",
|
||||
[SOC_VENDOR_SIPEED] = "Sipeed ",
|
||||
[SOC_VENDOR_SPACEMIT] = "SpacemiT ",
|
||||
// ARM & RISC-V
|
||||
[SOC_VENDOR_ALLWINNER] = "Allwinner "
|
||||
};
|
||||
|
||||
@@ -33,6 +33,7 @@ enum {
|
||||
SOC_VENDOR_SIFIVE,
|
||||
SOC_VENDOR_STARFIVE,
|
||||
SOC_VENDOR_SIPEED,
|
||||
SOC_VENDOR_SPACEMIT,
|
||||
// ARM & RISC-V
|
||||
SOC_VENDOR_ALLWINNER
|
||||
};
|
||||
|
||||
@@ -12,7 +12,7 @@
|
||||
#define SET_ISA_EXT_MAP(name, bit) \
|
||||
if(strncmp(multi_letter_extension, name, \
|
||||
multi_letter_extension_len) == 0) { \
|
||||
ext->mask |= 1UL << bit; \
|
||||
ext->mask[bit] = true; \
|
||||
maskset = true; \
|
||||
} \
|
||||
|
||||
@@ -62,7 +62,6 @@ int parse_multi_letter_extension(struct extensions* ext, char* e) {
|
||||
SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM)
|
||||
SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE)
|
||||
SET_ISA_EXT_MAP("svnapot", RISCV_ISA_EXT_SVNAPOT)
|
||||
SET_ISA_EXT_MAP("zicbop", RISCV_ISA_EXT_ZICBOP)
|
||||
SET_ISA_EXT_MAP("zicboz", RISCV_ISA_EXT_ZICBOZ)
|
||||
SET_ISA_EXT_MAP("smaia", RISCV_ISA_EXT_SMAIA)
|
||||
SET_ISA_EXT_MAP("ssaia", RISCV_ISA_EXT_SSAIA)
|
||||
@@ -72,6 +71,65 @@ int parse_multi_letter_extension(struct extensions* ext, char* e) {
|
||||
SET_ISA_EXT_MAP("zicsr", RISCV_ISA_EXT_ZICSR)
|
||||
SET_ISA_EXT_MAP("zifencei", RISCV_ISA_EXT_ZIFENCEI)
|
||||
SET_ISA_EXT_MAP("zihpm", RISCV_ISA_EXT_ZIHPM)
|
||||
SET_ISA_EXT_MAP("smstateen", RISCV_ISA_EXT_SMSTATEEN)
|
||||
SET_ISA_EXT_MAP("zicond", RISCV_ISA_EXT_ZICOND)
|
||||
SET_ISA_EXT_MAP("zbc", RISCV_ISA_EXT_ZBC)
|
||||
SET_ISA_EXT_MAP("zbkb", RISCV_ISA_EXT_ZBKB)
|
||||
SET_ISA_EXT_MAP("zbkc", RISCV_ISA_EXT_ZBKC)
|
||||
SET_ISA_EXT_MAP("zbkx", RISCV_ISA_EXT_ZBKX)
|
||||
SET_ISA_EXT_MAP("zknd", RISCV_ISA_EXT_ZKND)
|
||||
SET_ISA_EXT_MAP("zkne", RISCV_ISA_EXT_ZKNE)
|
||||
SET_ISA_EXT_MAP("zknh", RISCV_ISA_EXT_ZKNH)
|
||||
SET_ISA_EXT_MAP("zkr", RISCV_ISA_EXT_ZKR)
|
||||
SET_ISA_EXT_MAP("zksed", RISCV_ISA_EXT_ZKSED)
|
||||
SET_ISA_EXT_MAP("zksh", RISCV_ISA_EXT_ZKSH)
|
||||
SET_ISA_EXT_MAP("zkt", RISCV_ISA_EXT_ZKT)
|
||||
SET_ISA_EXT_MAP("zvbb", RISCV_ISA_EXT_ZVBB)
|
||||
SET_ISA_EXT_MAP("zvbc", RISCV_ISA_EXT_ZVBC)
|
||||
SET_ISA_EXT_MAP("zvkb", RISCV_ISA_EXT_ZVKB)
|
||||
SET_ISA_EXT_MAP("zvkg", RISCV_ISA_EXT_ZVKG)
|
||||
SET_ISA_EXT_MAP("zvkned", RISCV_ISA_EXT_ZVKNED)
|
||||
SET_ISA_EXT_MAP("zvknha", RISCV_ISA_EXT_ZVKNHA)
|
||||
SET_ISA_EXT_MAP("zvknhb", RISCV_ISA_EXT_ZVKNHB)
|
||||
SET_ISA_EXT_MAP("zvksed", RISCV_ISA_EXT_ZVKSED)
|
||||
SET_ISA_EXT_MAP("zvksh", RISCV_ISA_EXT_ZVKSH)
|
||||
SET_ISA_EXT_MAP("zvkt", RISCV_ISA_EXT_ZVKT)
|
||||
SET_ISA_EXT_MAP("zfh", RISCV_ISA_EXT_ZFH)
|
||||
SET_ISA_EXT_MAP("zfhmin", RISCV_ISA_EXT_ZFHMIN)
|
||||
SET_ISA_EXT_MAP("zihintntl", RISCV_ISA_EXT_ZIHINTNTL)
|
||||
SET_ISA_EXT_MAP("zvfh", RISCV_ISA_EXT_ZVFH)
|
||||
SET_ISA_EXT_MAP("zvfhmin", RISCV_ISA_EXT_ZVFHMIN)
|
||||
SET_ISA_EXT_MAP("zfa", RISCV_ISA_EXT_ZFA)
|
||||
SET_ISA_EXT_MAP("ztso", RISCV_ISA_EXT_ZTSO)
|
||||
SET_ISA_EXT_MAP("zacas", RISCV_ISA_EXT_ZACAS)
|
||||
SET_ISA_EXT_MAP("zve32x", RISCV_ISA_EXT_ZVE32X)
|
||||
SET_ISA_EXT_MAP("zve32f", RISCV_ISA_EXT_ZVE32F)
|
||||
SET_ISA_EXT_MAP("zve64x", RISCV_ISA_EXT_ZVE64X)
|
||||
SET_ISA_EXT_MAP("zve64f", RISCV_ISA_EXT_ZVE64F)
|
||||
SET_ISA_EXT_MAP("zve64d", RISCV_ISA_EXT_ZVE64D)
|
||||
SET_ISA_EXT_MAP("zimop", RISCV_ISA_EXT_ZIMOP)
|
||||
SET_ISA_EXT_MAP("zca", RISCV_ISA_EXT_ZCA)
|
||||
SET_ISA_EXT_MAP("zcb", RISCV_ISA_EXT_ZCB)
|
||||
SET_ISA_EXT_MAP("zcd", RISCV_ISA_EXT_ZCD)
|
||||
SET_ISA_EXT_MAP("zcf", RISCV_ISA_EXT_ZCF)
|
||||
SET_ISA_EXT_MAP("zcmop", RISCV_ISA_EXT_ZCMOP)
|
||||
SET_ISA_EXT_MAP("zawrs", RISCV_ISA_EXT_ZAWRS)
|
||||
SET_ISA_EXT_MAP("svvptc", RISCV_ISA_EXT_SVVPTC)
|
||||
SET_ISA_EXT_MAP("smmpm", RISCV_ISA_EXT_SMMPM)
|
||||
SET_ISA_EXT_MAP("smnpm", RISCV_ISA_EXT_SMNPM)
|
||||
SET_ISA_EXT_MAP("ssnpm", RISCV_ISA_EXT_SSNPM)
|
||||
SET_ISA_EXT_MAP("zabha", RISCV_ISA_EXT_ZABHA)
|
||||
SET_ISA_EXT_MAP("ziccrse", RISCV_ISA_EXT_ZICCRSE)
|
||||
SET_ISA_EXT_MAP("svade", RISCV_ISA_EXT_SVADE)
|
||||
SET_ISA_EXT_MAP("svadu", RISCV_ISA_EXT_SVADU)
|
||||
SET_ISA_EXT_MAP("zfbfmin", RISCV_ISA_EXT_ZFBFMIN)
|
||||
SET_ISA_EXT_MAP("zvfbfmin", RISCV_ISA_EXT_ZVFBFMIN)
|
||||
SET_ISA_EXT_MAP("zvfbfwma", RISCV_ISA_EXT_ZVFBFWMA)
|
||||
SET_ISA_EXT_MAP("zaamo", RISCV_ISA_EXT_ZAAMO)
|
||||
SET_ISA_EXT_MAP("zalrsc", RISCV_ISA_EXT_ZALRSC)
|
||||
SET_ISA_EXT_MAP("zicbop", RISCV_ISA_EXT_ZICBOP)
|
||||
SET_ISA_EXT_MAP("ime", RISCV_ISA_EXT_IME)
|
||||
|
||||
if(!maskset) {
|
||||
printBug("parse_multi_letter_extension: Unknown multi-letter extension: %s", multi_letter_extension);
|
||||
return -1;
|
||||
@@ -94,19 +152,21 @@ bool valid_extension(char ext) {
|
||||
|
||||
struct extensions* get_extensions_from_str(char* str) {
|
||||
struct extensions* ext = emalloc(sizeof(struct extensions));
|
||||
ext->mask = 0;
|
||||
ext->mask = ecalloc(RISCV_ISA_EXT_ID_MAX, sizeof(bool));
|
||||
ext->str = NULL;
|
||||
|
||||
if(str == NULL) {
|
||||
return ext;
|
||||
}
|
||||
|
||||
int len = strlen(str);
|
||||
ext->str = ecalloc(len+1, sizeof(char));
|
||||
int len = strlen(str)+1;
|
||||
ext->str = emalloc(len * sizeof(char));
|
||||
strncpy(ext->str, str, sizeof(char) * len);
|
||||
|
||||
// Code inspired in Linux kernel (riscv_fill_hwcap):
|
||||
// https://elixir.bootlin.com/linux/v6.2.10/source/arch/riscv/kernel/cpufeature.c
|
||||
// Now it seems to be here in riscv_parse_isa_string:
|
||||
// https://elixir.bootlin.com/linux/v6.16/source/arch/riscv/kernel/cpufeature.c
|
||||
char* isa = str;
|
||||
if (!strncmp(isa, "rv32", 4))
|
||||
isa += 4;
|
||||
@@ -138,7 +198,7 @@ struct extensions* get_extensions_from_str(char* str) {
|
||||
// adding it to the mask
|
||||
if(valid_extension(*e)) {
|
||||
int n = *e - 'a';
|
||||
ext->mask |= 1UL << n;
|
||||
ext->mask[n] = true;
|
||||
}
|
||||
else {
|
||||
printBug("get_extensions_from_str: Invalid extension: '%c'", *e);
|
||||
@@ -149,6 +209,18 @@ struct extensions* get_extensions_from_str(char* str) {
|
||||
return ext;
|
||||
}
|
||||
|
||||
uint32_t get_num_extensions(bool* mask) {
|
||||
uint32_t num = 0;
|
||||
for (int i=0; i < RISCV_ISA_EXT_ID_MAX; i++) {
|
||||
if (mask[i]) num++;
|
||||
}
|
||||
return num;
|
||||
}
|
||||
|
||||
bool is_mask_empty(bool* mask) {
|
||||
return get_num_extensions(mask) == 0;
|
||||
}
|
||||
|
||||
struct cpuInfo* get_cpu_info(void) {
|
||||
struct cpuInfo* cpu = malloc(sizeof(struct cpuInfo));
|
||||
//init_cpu_info(cpu);
|
||||
@@ -157,13 +229,12 @@ struct cpuInfo* get_cpu_info(void) {
|
||||
topo->cach = NULL;
|
||||
cpu->topo = topo;
|
||||
|
||||
char* cpuinfo_str = get_uarch_from_cpuinfo();
|
||||
char* ext_str = get_extensions_from_cpuinfo();
|
||||
cpu->hv = emalloc(sizeof(struct hypervisor));
|
||||
cpu->hv->present = false;
|
||||
cpu->ext = get_extensions_from_str(ext_str);
|
||||
if(cpu->ext->str != NULL && cpu->ext->mask == 0) return NULL;
|
||||
cpu->arch = get_uarch_from_cpuinfo_str(cpuinfo_str, cpu);
|
||||
if(cpu->ext->str != NULL && is_mask_empty(cpu->ext->mask)) return NULL;
|
||||
cpu->arch = get_uarch(cpu);
|
||||
cpu->soc = get_soc(cpu);
|
||||
cpu->freq = get_frequency_info(0);
|
||||
cpu->peak_performance = get_peak_performance(cpu);
|
||||
|
||||
@@ -23,7 +23,6 @@ enum riscv_isa_ext_id {
|
||||
RISCV_ISA_EXT_ZICBOM,
|
||||
RISCV_ISA_EXT_ZIHINTPAUSE,
|
||||
RISCV_ISA_EXT_SVNAPOT,
|
||||
RISCV_ISA_EXT_ZICBOP,
|
||||
RISCV_ISA_EXT_ZICBOZ,
|
||||
RISCV_ISA_EXT_SMAIA,
|
||||
RISCV_ISA_EXT_SSAIA,
|
||||
@@ -33,12 +32,74 @@ enum riscv_isa_ext_id {
|
||||
RISCV_ISA_EXT_ZICSR,
|
||||
RISCV_ISA_EXT_ZIFENCEI,
|
||||
RISCV_ISA_EXT_ZIHPM,
|
||||
RISCV_ISA_EXT_SMSTATEEN,
|
||||
RISCV_ISA_EXT_ZICOND,
|
||||
RISCV_ISA_EXT_ZBC,
|
||||
RISCV_ISA_EXT_ZBKB,
|
||||
RISCV_ISA_EXT_ZBKC,
|
||||
RISCV_ISA_EXT_ZBKX,
|
||||
RISCV_ISA_EXT_ZKND,
|
||||
RISCV_ISA_EXT_ZKNE,
|
||||
RISCV_ISA_EXT_ZKNH,
|
||||
RISCV_ISA_EXT_ZKR,
|
||||
RISCV_ISA_EXT_ZKSED,
|
||||
RISCV_ISA_EXT_ZKSH,
|
||||
RISCV_ISA_EXT_ZKT,
|
||||
RISCV_ISA_EXT_ZVBB,
|
||||
RISCV_ISA_EXT_ZVBC,
|
||||
RISCV_ISA_EXT_ZVKB,
|
||||
RISCV_ISA_EXT_ZVKG,
|
||||
RISCV_ISA_EXT_ZVKNED,
|
||||
RISCV_ISA_EXT_ZVKNHA,
|
||||
RISCV_ISA_EXT_ZVKNHB,
|
||||
RISCV_ISA_EXT_ZVKSED,
|
||||
RISCV_ISA_EXT_ZVKSH,
|
||||
RISCV_ISA_EXT_ZVKT,
|
||||
RISCV_ISA_EXT_ZFH,
|
||||
RISCV_ISA_EXT_ZFHMIN,
|
||||
RISCV_ISA_EXT_ZIHINTNTL,
|
||||
RISCV_ISA_EXT_ZVFH,
|
||||
RISCV_ISA_EXT_ZVFHMIN,
|
||||
RISCV_ISA_EXT_ZFA,
|
||||
RISCV_ISA_EXT_ZTSO,
|
||||
RISCV_ISA_EXT_ZACAS,
|
||||
RISCV_ISA_EXT_ZVE32X,
|
||||
RISCV_ISA_EXT_ZVE32F,
|
||||
RISCV_ISA_EXT_ZVE64X,
|
||||
RISCV_ISA_EXT_ZVE64F,
|
||||
RISCV_ISA_EXT_ZVE64D,
|
||||
RISCV_ISA_EXT_ZIMOP,
|
||||
RISCV_ISA_EXT_ZCA,
|
||||
RISCV_ISA_EXT_ZCB,
|
||||
RISCV_ISA_EXT_ZCD,
|
||||
RISCV_ISA_EXT_ZCF,
|
||||
RISCV_ISA_EXT_ZCMOP,
|
||||
RISCV_ISA_EXT_ZAWRS,
|
||||
RISCV_ISA_EXT_SVVPTC,
|
||||
RISCV_ISA_EXT_SMMPM,
|
||||
RISCV_ISA_EXT_SMNPM,
|
||||
RISCV_ISA_EXT_SSNPM,
|
||||
RISCV_ISA_EXT_ZABHA,
|
||||
RISCV_ISA_EXT_ZICCRSE,
|
||||
RISCV_ISA_EXT_SVADE,
|
||||
RISCV_ISA_EXT_SVADU,
|
||||
RISCV_ISA_EXT_ZFBFMIN,
|
||||
RISCV_ISA_EXT_ZVFBFMIN,
|
||||
RISCV_ISA_EXT_ZVFBFWMA,
|
||||
RISCV_ISA_EXT_ZAAMO,
|
||||
RISCV_ISA_EXT_ZALRSC,
|
||||
RISCV_ISA_EXT_ZICBOP,
|
||||
RISCV_ISA_EXT_IME, // This is not in the kernel! but it was seen on a Muse Pi Pro board
|
||||
RISCV_ISA_EXT_ID_MAX
|
||||
};
|
||||
|
||||
// https://five-embeddev.com/riscv-isa-manual/latest/preface.html#preface
|
||||
// https://en.wikichip.org/wiki/risc-v/standard_extensions
|
||||
// (Zicbop) https://github.com/riscv/riscv-CMOs/blob/master/cmobase/Zicbop.adoc
|
||||
// https://raw.githubusercontent.com/riscv/riscv-CMOs/master/specifications/cmobase-v1.0.1.pdf
|
||||
// https://www.kernel.org/doc/Documentation/devicetree/bindings/riscv/extensions.yaml
|
||||
// https://gcc.gnu.org/onlinedocs/gcc/RISC-V-Options.html
|
||||
// (Ime) https://github.com/riscv/integrated-matrix-extension (not confirmed, just a guess...)
|
||||
// Included all except for G
|
||||
static const struct extension extension_list[] = {
|
||||
{ 'i' - 'a', "(I) Integer Instruction Set" },
|
||||
@@ -74,12 +135,71 @@ static const struct extension extension_list[] = {
|
||||
{ RISCV_ISA_EXT_ZICNTR, "(Zicntr) Base Counters and Timers" },
|
||||
{ RISCV_ISA_EXT_ZICSR, "(Zicsr) Control and Status Register" },
|
||||
{ RISCV_ISA_EXT_ZIFENCEI, "(Zifencei) Instruction-Fetch Fence" },
|
||||
{ RISCV_ISA_EXT_ZIHPM, "(Zihpm) Hardware Performance Counters" }
|
||||
{ RISCV_ISA_EXT_ZIHPM, "(Zihpm) Hardware Performance Counters" },
|
||||
{ RISCV_ISA_EXT_SMSTATEEN, "(Smstateen) Supervisor/Hypervisor State Enable" },
|
||||
{ RISCV_ISA_EXT_ZICOND, "(Zicond) Integer Conditional Operations" },
|
||||
{ RISCV_ISA_EXT_ZBC, "(Zbc) Carry-Less Multiplication" },
|
||||
{ RISCV_ISA_EXT_ZBKB, "(Zbkb) Bit-Manipulation for Cryptography (Byte ops)" },
|
||||
{ RISCV_ISA_EXT_ZBKC, "(Zbkc) Bit-Manipulation for Cryptography (Carry-less ops)" },
|
||||
{ RISCV_ISA_EXT_ZBKX, "(Zbkx) Bit-Manipulation for Cryptography (Crossbar ops)" },
|
||||
{ RISCV_ISA_EXT_ZKND, "(Zknd) NIST AES Decryption Instructions" },
|
||||
{ RISCV_ISA_EXT_ZKNE, "(Zkne) NIST AES Encryption Instructions" },
|
||||
{ RISCV_ISA_EXT_ZKNH, "(Zknh) NIST Hash (SHA-2/SHA-3) Instructions" },
|
||||
{ RISCV_ISA_EXT_ZKR, "(Zkr) Entropy Source Reading (Random)" },
|
||||
{ RISCV_ISA_EXT_ZKSED, "(Zksed) SM4 Block Cipher Decryption" },
|
||||
{ RISCV_ISA_EXT_ZKSH, "(Zksh) SM3 Hash Instructions" },
|
||||
{ RISCV_ISA_EXT_ZKT, "(Zkt) Data-Independent Execution Latency" },
|
||||
{ RISCV_ISA_EXT_ZVBB, "(Zvbb) Vector Basic Bit-Manipulation" },
|
||||
{ RISCV_ISA_EXT_ZVBC, "(Zvbc) Vector Carry-Less Multiplication" },
|
||||
{ RISCV_ISA_EXT_ZVKB, "(Zvkb) Vector Cryptography (Byte ops)" },
|
||||
{ RISCV_ISA_EXT_ZVKG, "(Zvkg) Vector GCM/GMAC Instructions" },
|
||||
{ RISCV_ISA_EXT_ZVKNED, "(Zvkned) Vector AES Decryption" },
|
||||
{ RISCV_ISA_EXT_ZVKNHA, "(Zvknha) Vector SHA-2 Hash (A variant)" },
|
||||
{ RISCV_ISA_EXT_ZVKNHB, "(Zvknhb) Vector SHA-2 Hash (B variant)" },
|
||||
{ RISCV_ISA_EXT_ZVKSED, "(Zvksed) Vector SM4 Block Cipher Decryption" },
|
||||
{ RISCV_ISA_EXT_ZVKSH, "(Zvksh) Vector SM3 Hash Instructions" },
|
||||
{ RISCV_ISA_EXT_ZVKT, "(Zvkt) Vector Data-Independent Execution Latency" },
|
||||
{ RISCV_ISA_EXT_ZFH, "(Zfh) Half-Precision Floating Point" },
|
||||
{ RISCV_ISA_EXT_ZFHMIN, "(Zfhmin) Minimal Half-Precision Floating Point" },
|
||||
{ RISCV_ISA_EXT_ZIHINTNTL, "(Zihintntl) Non-Temporal Load/Store Hints" },
|
||||
{ RISCV_ISA_EXT_ZVFH, "(Zvfh) Vector Half-Precision Floating Point" },
|
||||
{ RISCV_ISA_EXT_ZVFHMIN, "(Zvfhmin) Minimal Vector Half-Precision Floating Point" },
|
||||
{ RISCV_ISA_EXT_ZFA, "(Zfa) Additional Floating-Point Instructions" },
|
||||
{ RISCV_ISA_EXT_ZTSO, "(Ztso) Total Store Ordering Memory Model" },
|
||||
{ RISCV_ISA_EXT_ZACAS, "(Zacas) Atomic Compare-and-Swap" },
|
||||
{ RISCV_ISA_EXT_ZVE32X, "(Zve32x) Embedded Vector Integer (32-bit elements)" },
|
||||
{ RISCV_ISA_EXT_ZVE32F, "(Zve32f) Embedded Vector Floating Point (f32)" },
|
||||
{ RISCV_ISA_EXT_ZVE64X, "(Zve64x) Embedded Vector Integer (64-bit elements)" },
|
||||
{ RISCV_ISA_EXT_ZVE64F, "(Zve64f) Embedded Vector Floating Point (f64)" },
|
||||
{ RISCV_ISA_EXT_ZVE64D, "(Zve64d) Embedded Vector Double-Precision FP (f64)" },
|
||||
{ RISCV_ISA_EXT_ZIMOP, "(Zimop) Integer Multiply-Only Instructions" },
|
||||
{ RISCV_ISA_EXT_ZCA, "(Zca) Compressed Integer Instructions" },
|
||||
{ RISCV_ISA_EXT_ZCB, "(Zcb) Compressed Bit-Manipulation Instructions" },
|
||||
{ RISCV_ISA_EXT_ZCD, "(Zcd) Compressed Double-Precision FP Instructions" },
|
||||
{ RISCV_ISA_EXT_ZCF, "(Zcf) Compressed Single-Precision FP Instructions" },
|
||||
{ RISCV_ISA_EXT_ZCMOP, "(Zcmop) Compressed Multiply-Only Instructions" },
|
||||
{ RISCV_ISA_EXT_ZAWRS, "(Zawrs) Wait-on-Reservation-Set Instruction" },
|
||||
{ RISCV_ISA_EXT_SVVPTC, "(Svvptc) Supervisor Virtual Page Table Cache Control" },
|
||||
{ RISCV_ISA_EXT_SMMPM, "(Smmpm) Supervisor Memory Protection Modification" },
|
||||
{ RISCV_ISA_EXT_SMNPM, "(Smnpm) Supervisor Non-Privileged Memory Access Control" },
|
||||
{ RISCV_ISA_EXT_SSNPM, "(Ssnpm) Supervisor Secure Non-Privileged Memory" },
|
||||
{ RISCV_ISA_EXT_ZABHA, "(Zabha) Atomic Byte/Halfword Operations" },
|
||||
{ RISCV_ISA_EXT_ZICCRSE, "(Ziccrse) Cache Control Range Start/End Operations" },
|
||||
{ RISCV_ISA_EXT_SVADE, "(Svade) Supervisor Virtual Address Deferred Exception" },
|
||||
{ RISCV_ISA_EXT_SVADU, "(Svadu) Supervisor Virtual Address Dirty Update" },
|
||||
{ RISCV_ISA_EXT_ZFBFMIN, "(Zfbfmin) Minimal BFloat16 Floating Point" },
|
||||
{ RISCV_ISA_EXT_ZVFBFMIN, "(Zvfbfmin) Vector Minimal BFloat16 Floating Point" },
|
||||
{ RISCV_ISA_EXT_ZVFBFWMA, "(Zvfbfwma) Vector BFloat16 Widening Multiply-Accumulate" },
|
||||
{ RISCV_ISA_EXT_ZAAMO, "(Zaamo) Atomic Memory Operation (AMO) Instructions" },
|
||||
{ RISCV_ISA_EXT_ZALRSC, "(Zalrsc) Atomic Load-Reserved/Store-Conditional" },
|
||||
{ RISCV_ISA_EXT_ZICBOP, "(Zicbop) Cache Block Prefetch/Zero Operations" },
|
||||
{ RISCV_ISA_EXT_IME, "(Ime) Integrated Matrix Extension" },
|
||||
};
|
||||
|
||||
struct cpuInfo* get_cpu_info(void);
|
||||
char* get_str_topology(struct cpuInfo* cpu, struct topology* topo);
|
||||
char* get_str_extensions(struct cpuInfo* cpu);
|
||||
uint32_t get_num_extensions(bool* mask);
|
||||
void print_debug(struct cpuInfo* cpu);
|
||||
|
||||
#endif
|
||||
|
||||
@@ -38,6 +38,12 @@ bool match_sipeed(char* soc_name, struct system_on_chip* soc) {
|
||||
SOC_END
|
||||
}
|
||||
|
||||
bool match_spacemit(char* soc_name, struct system_on_chip* soc) {
|
||||
SOC_START
|
||||
SOC_EQ(soc_name, "k1-x", "K1-X", SOC_SPACEMIT_K1X, soc, 22) // https://github.com/Dr-Noob/cpufetch/issues/286 https://www.spacemit.com/en/spacemit-x60-core/
|
||||
SOC_END
|
||||
}
|
||||
|
||||
struct system_on_chip* parse_soc_from_string(struct system_on_chip* soc) {
|
||||
char* raw_name = soc->raw_name;
|
||||
|
||||
@@ -50,6 +56,9 @@ struct system_on_chip* parse_soc_from_string(struct system_on_chip* soc) {
|
||||
if(match_sifive(raw_name, soc))
|
||||
return soc;
|
||||
|
||||
if(match_spacemit(raw_name, soc))
|
||||
return soc;
|
||||
|
||||
match_sipeed(raw_name, soc);
|
||||
return soc;
|
||||
}
|
||||
|
||||
@@ -13,6 +13,8 @@ enum {
|
||||
SOC_ALLWINNER_D1H,
|
||||
// SIPEED
|
||||
SOC_SIPEED_LICHEEPI4A,
|
||||
// SPACEMIT
|
||||
SOC_SPACEMIT_K1X,
|
||||
// UNKNOWN
|
||||
SOC_MODEL_UNKNOWN
|
||||
};
|
||||
@@ -22,6 +24,7 @@ inline static VENDOR get_soc_vendor_from_soc(SOC soc) {
|
||||
if(soc >= SOC_STARFIVE_VF2 && soc <= SOC_STARFIVE_VF2) return SOC_VENDOR_STARFIVE;
|
||||
if(soc >= SOC_ALLWINNER_D1H && soc <= SOC_ALLWINNER_D1H) return SOC_VENDOR_ALLWINNER;
|
||||
if(soc >= SOC_SIPEED_LICHEEPI4A && soc <= SOC_SIPEED_LICHEEPI4A) return SOC_VENDOR_SIPEED;
|
||||
if(soc >= SOC_SPACEMIT_K1X && soc <= SOC_SPACEMIT_K1X) return SOC_VENDOR_SPACEMIT;
|
||||
return SOC_VENDOR_UNKNOWN;
|
||||
}
|
||||
|
||||
|
||||
@@ -4,6 +4,7 @@
|
||||
#include <string.h>
|
||||
|
||||
#include "uarch.h"
|
||||
#include "udev.h"
|
||||
#include "../common/global.h"
|
||||
|
||||
typedef uint32_t MICROARCH;
|
||||
@@ -12,6 +13,7 @@ struct uarch {
|
||||
MICROARCH uarch;
|
||||
char* uarch_str;
|
||||
char* cpuinfo_str;
|
||||
struct riscv_cpuinfo* ci;
|
||||
};
|
||||
|
||||
enum {
|
||||
@@ -21,13 +23,20 @@ enum {
|
||||
UARCH_U74,
|
||||
// THEAD
|
||||
UARCH_C906,
|
||||
UARCH_C910
|
||||
UARCH_C910,
|
||||
// SPACEMIT
|
||||
UARCH_X60
|
||||
};
|
||||
|
||||
#define UARCH_START if (false) {}
|
||||
#define CHECK_UARCH(arch, cpu, cpuinfo_str, uarch_str, str, uarch, vendor) \
|
||||
else if (strcmp(cpuinfo_str, uarch_str) == 0) fill_uarch(arch, cpu, str, uarch, vendor);
|
||||
#define UARCH_END else { printBug("Unknown microarchitecture detected: uarch='%s'", cpuinfo_str); fill_uarch(arch, cpu, "Unknown", UARCH_UNKNOWN, CPU_VENDOR_UNKNOWN); }
|
||||
#define UARCH_END else { printWarn("Unknown microarchitecture detected: uarch='%s'", cpuinfo_str); fill_uarch(arch, cpu, "Unknown", UARCH_UNKNOWN, CPU_VENDOR_UNKNOWN); }
|
||||
|
||||
#define ARCHID_START if (false) {}
|
||||
#define CHECK_ARCHID(arch, marchid_val, str, uarch, vendor) \
|
||||
else if (arch->ci->marchid == (unsigned long) marchid_val) fill_uarch(arch, cpu, str, uarch, vendor);
|
||||
#define ARCHID_END else { printWarn("Unknown microarchitecture detected: marchid=0x%.8X", arch->ci->marchid); fill_uarch(arch, cpu, "Unknown", UARCH_UNKNOWN, CPU_VENDOR_UNKNOWN); }
|
||||
|
||||
void fill_uarch(struct uarch* arch, struct cpuInfo* cpu, char* str, MICROARCH u, VENDOR vendor) {
|
||||
arch->uarch = u;
|
||||
@@ -39,14 +48,8 @@ void fill_uarch(struct uarch* arch, struct cpuInfo* cpu, char* str, MICROARCH u,
|
||||
// https://elixir.bootlin.com/linux/latest/source/Documentation/devicetree/bindings/riscv/cpus.yaml
|
||||
// SiFive: https://www.sifive.com/risc-v-core-ip
|
||||
// T-Head: https://www.t-head.cn/product/c906
|
||||
struct uarch* get_uarch_from_cpuinfo_str(char* cpuinfo_str, struct cpuInfo* cpu) {
|
||||
struct uarch* arch = emalloc(sizeof(struct uarch));
|
||||
struct uarch* get_uarch_from_cpuinfo_str(char* cpuinfo_str, struct cpuInfo* cpu, struct uarch* arch) {
|
||||
arch->cpuinfo_str = cpuinfo_str;
|
||||
if(cpuinfo_str == NULL) {
|
||||
printWarn("get_uarch_from_cpuinfo: Unable to detect microarchitecture, cpuinfo_str is NULL");
|
||||
fill_uarch(arch, cpu, "Unknown", UARCH_UNKNOWN, CPU_VENDOR_UNKNOWN);
|
||||
return arch;
|
||||
}
|
||||
|
||||
// U74/U74-MC:
|
||||
// SiFive says that U74-MC is "Multicore: four U74 cores and one S76 core" while
|
||||
@@ -70,6 +73,41 @@ struct uarch* get_uarch_from_cpuinfo_str(char* cpuinfo_str, struct cpuInfo* cpu)
|
||||
return arch;
|
||||
}
|
||||
|
||||
// Use marchid to get the microarchitecture
|
||||
struct uarch* get_uarch_from_riscv_cpuinfo(struct cpuInfo* cpu, struct uarch* arch) {
|
||||
|
||||
ARCHID_START
|
||||
CHECK_ARCHID(arch, 0x8000000058000001, "X60", UARCH_X60, CPU_VENDOR_SPACEMIT) // https://github.com/Dr-Noob/cpufetch/issues/286
|
||||
ARCHID_END
|
||||
|
||||
return arch;
|
||||
}
|
||||
|
||||
struct uarch* get_uarch(struct cpuInfo* cpu) {
|
||||
char* cpuinfo_str = get_uarch_from_cpuinfo();
|
||||
struct uarch* arch = emalloc(sizeof(struct uarch));
|
||||
arch->uarch = UARCH_UNKNOWN;
|
||||
arch->ci = NULL;
|
||||
|
||||
if (cpuinfo_str == NULL) {
|
||||
printWarn("get_uarch_from_cpuinfo: Unable to detect microarchitecture using uarch: cpuinfo_str is NULL");
|
||||
arch->ci = get_riscv_cpuinfo();
|
||||
|
||||
if (arch->ci == NULL || arch->ci->marchid == 0)
|
||||
printWarn("get_riscv_cpuinfo: Unable to get marchid from udev");
|
||||
else
|
||||
arch = get_uarch_from_riscv_cpuinfo(cpu, arch);
|
||||
}
|
||||
else {
|
||||
arch = get_uarch_from_cpuinfo_str(cpuinfo_str, cpu, arch);
|
||||
}
|
||||
|
||||
if (arch->uarch == UARCH_UNKNOWN)
|
||||
fill_uarch(arch, cpu, "Unknown", UARCH_UNKNOWN, CPU_VENDOR_UNKNOWN);
|
||||
|
||||
return arch;
|
||||
}
|
||||
|
||||
char* get_str_uarch(struct cpuInfo* cpu) {
|
||||
return cpu->arch->uarch_str;
|
||||
}
|
||||
|
||||
@@ -9,6 +9,6 @@ struct uarch;
|
||||
char* get_arch_cpuinfo_str(struct cpuInfo* cpu);
|
||||
char* get_str_uarch(struct cpuInfo* cpu);
|
||||
void free_uarch_struct(struct uarch* arch);
|
||||
struct uarch* get_uarch_from_cpuinfo_str(char* cpuinfo_str, struct cpuInfo* cpu);
|
||||
struct uarch* get_uarch(struct cpuInfo* cpu);
|
||||
|
||||
#endif
|
||||
|
||||
@@ -7,6 +7,9 @@
|
||||
#define _PATH_DEVTREE "/proc/device-tree/compatible"
|
||||
#define CPUINFO_UARCH_STR "uarch\t\t: "
|
||||
#define CPUINFO_EXTENSIONS_STR "isa\t\t: "
|
||||
#define CPUINFO_RISCV_MVENDORID "mvendorid\t:"
|
||||
#define CPUINFO_RISCV_MARCHID "marchid\t\t:"
|
||||
#define CPUINFO_RISCV_MIMPID "mimpid\t\t:"
|
||||
#define DEVTREE_HARDWARE_FIELD 0
|
||||
|
||||
char* get_field_from_devtree(int DEVTREE_FIELD) {
|
||||
@@ -75,6 +78,52 @@ char* parse_cpuinfo_field(char* field_str) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
unsigned long parse_cpuinfo_field_uint64(char* field_str) {
|
||||
int filelen;
|
||||
char* buf;
|
||||
if((buf = read_file(_PATH_CPUINFO, &filelen)) == NULL) {
|
||||
printWarn("read_file: %s: %s", _PATH_CPUINFO, strerror(errno));
|
||||
return 0;
|
||||
}
|
||||
|
||||
char* tmp = strstr(buf, field_str);
|
||||
if(tmp == NULL) return 0;
|
||||
tmp += strlen(field_str);
|
||||
|
||||
char* end;
|
||||
errno = 0;
|
||||
unsigned long ret = strtoul(tmp, &end, 16);
|
||||
if (errno != 0) {
|
||||
printWarn("strtoul: %s: %s", strerror(errno), tmp);
|
||||
return 0;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
// Creates and fills in the riscv_cpuinfo struct (which contains
|
||||
// mvendorid, marchid and mimpid) using cpuinfo to fetch the values.
|
||||
//
|
||||
// Every RISC-V hart (hardware thread) [1] provides a
|
||||
// marchid (Machine Architecture ID register) CSR that encodes its
|
||||
// base microarchitecture [2]. For more information about
|
||||
// marchid and the rest of values, see [3].
|
||||
// [1] https://groups.google.com/a/groups.riscv.org/g/sw-dev/c/QKjUDjz_vKo
|
||||
// [2] https://github.com/riscv/riscv-isa-manual/blob/main/marchid.md
|
||||
// [3] https://five-embeddev.com/riscv-priv-isa-manual/Priv-v1.12/machine.html#machine-architecture-id-register-marchid
|
||||
struct riscv_cpuinfo *get_riscv_cpuinfo(void) {
|
||||
struct riscv_cpuinfo* ci = emalloc(sizeof(struct riscv_cpuinfo));
|
||||
|
||||
ci->mvendorid = parse_cpuinfo_field_uint64(CPUINFO_RISCV_MVENDORID);
|
||||
ci->marchid = parse_cpuinfo_field_uint64(CPUINFO_RISCV_MARCHID);
|
||||
ci->mimpid = parse_cpuinfo_field_uint64(CPUINFO_RISCV_MIMPID);
|
||||
|
||||
if (ci->mvendorid == 0 && ci->mvendorid == 0 && ci->mvendorid == 0)
|
||||
return NULL;
|
||||
|
||||
return ci;
|
||||
}
|
||||
|
||||
char* get_hardware_from_devtree(void) {
|
||||
return get_field_from_devtree(DEVTREE_HARDWARE_FIELD);
|
||||
}
|
||||
|
||||
@@ -5,8 +5,16 @@
|
||||
|
||||
#define UNKNOWN -1
|
||||
|
||||
// https://elixir.bootlin.com/linux/v6.10.6/source/arch/riscv/include/asm/cpufeature.h#L21
|
||||
struct riscv_cpuinfo {
|
||||
unsigned long mvendorid;
|
||||
unsigned long marchid;
|
||||
unsigned long mimpid;
|
||||
};
|
||||
|
||||
char* get_hardware_from_devtree(void);
|
||||
char* get_uarch_from_cpuinfo(void);
|
||||
char* get_extensions_from_cpuinfo(void);
|
||||
struct riscv_cpuinfo *get_riscv_cpuinfo(void);
|
||||
|
||||
#endif
|
||||
|
||||
@@ -333,6 +333,15 @@ struct features* get_features_info(struct cpuInfo* cpu) {
|
||||
bool hv_present = (ecx & (1U << 31)) != 0;
|
||||
if((cpu->hv = get_hp_info(hv_present)) == NULL)
|
||||
return NULL;
|
||||
if(cpu->hv->present) {
|
||||
// Hypervisor will likely mess up something and users will think that
|
||||
// there is something wrong with cpufetch whereas actually cpufetch has
|
||||
// nothing to do with it.
|
||||
// https://github.com/Dr-Noob/cpufetch/issues/96
|
||||
// https://github.com/Dr-Noob/cpufetch/issues/267
|
||||
// https://github.com/Dr-Noob/cpufetch/issues/293
|
||||
printWarn("You are running an hypervisor. Please note that it will likely tamper your results, so do not post an issue if you find anything incorrect");
|
||||
}
|
||||
}
|
||||
else {
|
||||
printWarn("Can't read features information from cpuid (needed level is 0x%.8X, max is 0x%.8X)", 0x00000001, cpu->maxLevels);
|
||||
|
||||
@@ -255,7 +255,7 @@ struct uarch* get_uarch_from_cpuid_intel(uint32_t ef, uint32_t f, uint32_t em, u
|
||||
// CHECK_UARCH(arch, 0, 6, 8, 14, 9, ...) It is not possible to determine uarch only from CPUID dump (can be Kaby Lake or Amber Lake)
|
||||
// CHECK_UARCH(arch, 0, 6, 8, 14, 10, ...) It is not possible to determine uarch only from CPUID dump (can be Kaby Lake R or Coffee Lake U)
|
||||
CHECK_UARCH(arch, 0, 6, 8, 14, 11, "Whiskey Lake", UARCH_WHISKEY_LAKE, 14) // wikichip
|
||||
CHECK_UARCH(arch, 0, 6, 8, 14, 12, "Comet Lake", UARCH_COMET_LAKE, 14) // wikichip
|
||||
// CHECK_UARCH(arch, 0, 6, 8, 14, 12, ...) It is not possible to determine uarch only from CPUID dump (can be Comet Lake U or Whiskey Lake U)
|
||||
CHECK_UARCH(arch, 0, 6, 8, 15, 8, "Sapphire Rapids", UARCH_SAPPHIRE_RAPIDS, 7) // wikichip
|
||||
CHECK_UARCH(arch, 0, 6, 9, 6, NA, "Tremont", UARCH_TREMONT, 10) // LX*
|
||||
CHECK_UARCH(arch, 0, 6, 9, 7, NA, "Alder Lake", UARCH_ALDER_LAKE, 10) // instlatx64 (Alder Lake-S)
|
||||
@@ -447,6 +447,7 @@ struct uarch* get_uarch_from_cpuid_hygon(uint32_t ef, uint32_t f, uint32_t em, u
|
||||
struct uarch* get_uarch_from_cpuid(struct cpuInfo* cpu, uint32_t dump, uint32_t ef, uint32_t f, uint32_t em, uint32_t m, int s) {
|
||||
if(cpu->cpu_vendor == CPU_VENDOR_INTEL) {
|
||||
struct uarch* arch = emalloc(sizeof(struct uarch));
|
||||
// TODO: Refactor these 3 checks in a common function.
|
||||
if(dump == 0x000806E9) {
|
||||
if (cpu->cpu_name == NULL) {
|
||||
printErr("Unable to find uarch without CPU name");
|
||||
@@ -486,6 +487,30 @@ struct uarch* get_uarch_from_cpuid(struct cpuInfo* cpu, uint32_t dump, uint32_t
|
||||
|
||||
return arch;
|
||||
}
|
||||
else if (dump == 0x000806EC) {
|
||||
if (cpu->cpu_name == NULL) {
|
||||
printErr("Unable to find uarch without CPU name");
|
||||
fill_uarch(arch, STRING_UNKNOWN, UARCH_UNKNOWN, UNK);
|
||||
return arch;
|
||||
}
|
||||
|
||||
// It is not possible to determine uarch only from CPUID dump (can be Comet Lake U or Whiskey Lake U)
|
||||
// https://github.com/Dr-Noob/cpufetch/issues/298
|
||||
if (strstr(cpu->cpu_name, "i3-8145U") != NULL ||
|
||||
strstr(cpu->cpu_name, "i5-8265U") != NULL ||
|
||||
strstr(cpu->cpu_name, "i5-8365U") != NULL ||
|
||||
strstr(cpu->cpu_name, "i7-8565U") != NULL ||
|
||||
strstr(cpu->cpu_name, "i7-8665U") != NULL ||
|
||||
strstr(cpu->cpu_name, "5405U") != NULL ||
|
||||
strstr(cpu->cpu_name, "4205U") != NULL) {
|
||||
fill_uarch(arch, "Whiskey Lake", UARCH_WHISKEY_LAKE, 14);
|
||||
}
|
||||
else {
|
||||
fill_uarch(arch, "Comet Lake", UARCH_COMET_LAKE, 14);
|
||||
}
|
||||
|
||||
return arch;
|
||||
}
|
||||
return get_uarch_from_cpuid_intel(ef, f, em, m, s);
|
||||
}
|
||||
else if(cpu->cpu_vendor == CPU_VENDOR_AMD) {
|
||||
|
||||
Reference in New Issue
Block a user