[v0.99] Update version

Latest versions of windows have support for the parsing VT100 escape
code sequences, allowing for terminal colors similar to Linux.

https://docs.microsoft.com/en-us/windows/console/console-virtual-terminal-sequences#screen-colors

Here I have it get the console mode, set the
`ENABLE_VIRTUAL_TERMINAL_PROCESSING` flag, and then grab the console
mode again to both verify that VT100 escape sequences are supported and
that it is enabled after setting it to determine if the printer should
allow for fancy-color mode.

.github/workflows/lockdown.yml

@@ -0,0 +1,36 @@
+name: 'Disable PR in cpufetch'
+
+on:
+  issues:
+    types: opened
+  pull_request:
+    types: opened
+
+permissions:
+  issues: write
+  pull-requests: write
+
+jobs:
+  action:
+    runs-on: ubuntu-latest
+    steps:
+      - uses: dessant/repo-lockdown@v2
+        with:
+          github-token: ${{ github.token }}
+          exclude-issue-created-before: ''
+          exclude-issue-labels: ''
+          issue-labels: ''
+          issue-comment: ''
+          skip-closed-issue-comment: false
+          close-issue: false
+          lock-issue: true
+          issue-lock-reason: ''
+          exclude-pr-created-before: ''
+          exclude-pr-labels: ''
+          pr-labels: ''
+          pr-comment: 'cpufetch does not accept pull requests, see [the contributing guidelines](https://github.com/Dr-Noob/cpufetch/blob/master/CONTRIBUTING.md) for details'
+          skip-closed-pr-comment: false
+          close-pr: true
+          lock-pr: false
+          pr-lock-reason: ''
+          process-only: 'prs'

CONTRIBUTING.md

@@ -0,0 +1,52 @@
+# cpufetch contributing guidelines
+
+<!-- START doctoc generated TOC please keep comment here to allow auto update -->
+<!-- DON'T EDIT THIS SECTION, INSTEAD RE-RUN doctoc TO UPDATE -->
+
+- [1. cpufetch does not accept pull requests](#1-cpufetch-does-not-accept-pull-requests)
+- [2. Creating an issue](#2-creating-an-issue)
+  - [2.1: I found a bug in cpufetch (the program provides incorrect / invalid information)](#21-i-found-a-bug-in-cpufetch-the-program-provides-incorrect--invalid-information)
+  - [2.2: I found a bug in cpufetch (the program crashes / does not work properly)](#22-i-found-a-bug-in-cpufetch-the-program-crashes--does-not-work-properly)
+    - [Stacktrace option 1 (best)](#stacktrace-option-1-best)
+    - [Stacktrace option 2 (use this option if option 1 does not work)](#stacktrace-option-2-use-this-option-if-option-1-does-not-work)
+  - [2.3: I have an idea for a new feature in cpufetch / I want to suggest a change in cpufetch](#23-i-have-an-idea-for-a-new-feature-in-cpufetch--i-want-to-suggest-a-change-in-cpufetch)
+
+<!-- END doctoc generated TOC please keep comment here to allow auto update -->
+Thanks for your interest in contributing to cpufetch! Please, read this page carefully to understand how to contribute to cpufetch.
+
+## 1. cpufetch does not accept pull requests
+cpufetch is a small project, and I enjoy developing it. There are for sure some bugs and exciting features to add, but I prefer to make these
+changes myself. For that reason, you should always use the issues page to report anything related to cpufetch. In the rare case that there is
+a concise bug or feature that I am unable to implement myself, I will enable pull requests for this.
+
+## 2. Creating an issue
+
+### 2.1: I found a bug in cpufetch (the program provides incorrect / invalid information)
+In the github issue **you must include**:
+- Exact CPU model.
+- Operating system.
+- The output of `cpufetch`.
+- The output of `cpufetch --debug`.
+
+### 2.2: I found a bug in cpufetch (the program crashes / does not work properly)
+- Exact CPU model.
+- Operating system.
+- The output of `cpufetch`.
+- The output of `cpufetch --debug`.
+- A stacktrace (if program crashes):
+
+#### Stacktrace option 1 (best)
+1. Build cpufetch with debug symbols (`make clean; make debug`).
+2. Install valgrind (if it is not already installed)
+3. Run cpufetch with valgrind (`valgrind ./cpufetch`)
+4. Paste the complete output (preferably on a platform like pastebin)
+
+#### Stacktrace option 2 (use this option if option 1 does not work)
+1. Build cpufetch with debug symbols (`make clean; make debug`).
+2. Install gdb (if it is not already installed)
+3. Debug cpufetch with gdb (`gdb cpufetch`)
+3. Run cpufetch (just r inside gdb console)
+4. Paste the complete output (preferably on a platform like pastebin)
+
+### 2.3: I have an idea for a new feature in cpufetch / I want to suggest a change in cpufetch
+Just explain the feature in the issue and include references (links) to relevant sources if appropriate.

Makefile

@@ -1,34 +1,73 @@
-CXX=gcc
+CC ?= gcc
 
-CXXFLAGS=-Wall -Wextra -Werror -pedantic -fstack-protector-all -pedantic -std=c99
-SANITY_FLAGS=-Wfloat-equal -Wshadow -Wpointer-arith -Wstrict-overflow=5 -Wformat=2
+CFLAGS+=-Wall -Wextra -pedantic -fstack-protector-all -pedantic
+SANITY_FLAGS=-Wfloat-equal -Wshadow -Wpointer-arith
 
-SRC_DIR=src/
-SOURCE=$(SRC_DIR)main.c $(SRC_DIR)cpuid.c $(SRC_DIR)apic.c $(SRC_DIR)cpuid_asm.c $(SRC_DIR)printer.c $(SRC_DIR)args.c $(SRC_DIR)global.c $(SRC_DIR)uarch.c
-HEADERS=$(SRC_DIR)cpuid.h $(SRC_DIR)apic.h $(SRC_DIR)cpuid_asm.h $(SRC_DIR)printer.h $(SRC_DIR)ascii.h $(SRC_DIR)args.h $(SRC_DIR)global.h $(SRC_DIR)uarch.h
+PREFIX ?= /usr
+
+SRC_COMMON=src/common/
+
+COMMON_SRC = $(SRC_COMMON)main.c $(SRC_COMMON)cpu.c $(SRC_COMMON)udev.c $(SRC_COMMON)printer.c $(SRC_COMMON)args.c $(SRC_COMMON)global.c
+COMMON_HDR = $(SRC_COMMON)ascii.h $(SRC_COMMON)cpu.h $(SRC_COMMON)udev.h $(SRC_COMMON)printer.h $(SRC_COMMON)args.h $(SRC_COMMON)global.h
 
 ifneq ($(OS),Windows_NT)
-	SOURCE += $(SRC_DIR)udev.c
-	HEADERS += $(SRC_DIR)udev.h
+	arch := $(shell uname -m)
+	ifeq ($(arch), $(filter $(arch), x86_64 amd64 i686))
+		SRC_DIR=src/x86/
+		SOURCE += $(COMMON_SRC) $(SRC_DIR)cpuid.c $(SRC_DIR)apic.c $(SRC_DIR)cpuid_asm.c $(SRC_DIR)uarch.c
+		HEADERS += $(COMMON_HDR) $(SRC_DIR)cpuid.h $(SRC_DIR)apic.h $(SRC_DIR)cpuid_asm.h $(SRC_DIR)uarch.h
+		CFLAGS += -DARCH_X86 -std=c99
+	else ifeq ($(arch), $(filter $(arch), ppc64le ppc64 ppcle ppc))
+		SRC_DIR=src/ppc/
+		SOURCE += $(COMMON_SRC) $(SRC_DIR)ppc.c $(SRC_DIR)uarch.c $(SRC_DIR)udev.c
+		HEADERS += $(COMMON_HDR) $(SRC_DIR)ppc.h $(SRC_DIR)uarch.h  $(SRC_DIR)udev.c
+		CFLAGS += -DARCH_PPC -std=gnu99
+	else
+		# Assume ARM
+		SRC_DIR=src/arm/
+		SOURCE += $(COMMON_SRC) $(SRC_DIR)midr.c $(SRC_DIR)uarch.c $(SRC_DIR)soc.c $(SRC_DIR)udev.c
+		HEADERS += $(COMMON_HDR) $(SRC_DIR)midr.h $(SRC_DIR)uarch.h  $(SRC_DIR)soc.h $(SRC_DIR)udev.c $(SRC_DIR)socs.h
+		CFLAGS += -DARCH_ARM -Wno-unused-parameter -std=c99
+	endif
+
 	OUTPUT=cpufetch
 else
-	SANITY_FLAGS += -Wno-pedantic-ms-format
+	# Assume x86_64
+	SRC_DIR=src/x86/
+	SOURCE += $(COMMON_SRC) $(SRC_DIR)cpuid.c $(SRC_DIR)apic.c $(SRC_DIR)cpuid_asm.c $(SRC_DIR)uarch.c
+	HEADERS += $(COMMON_HDR) $(SRC_DIR)cpuid.h $(SRC_DIR)apic.h $(SRC_DIR)cpuid_asm.h $(SRC_DIR)uarch.h
+	CFLAGS += -DARCH_X86
+	SANITY_FLAGS += -Wno-pedantic-ms-format -std=c99
 	OUTPUT=cpufetch.exe
 endif
 
+all: CFLAGS += -O3
 all: $(OUTPUT)
 
-debug: CXXFLAGS += -g -O0
+debug: CFLAGS += -g -O0
 debug: $(OUTPUT)
 
-release: CXXFLAGS += -static -O3
-release: $(OUTPUT)
+static: CFLAGS += -static -O3
+static: $(OUTPUT)
+
+strict: CFLAGS += -O3 -Werror -fsanitize=undefined -D_FORTIFY_SOURCE=2
+strict: $(OUTPUT)
 
 $(OUTPUT): Makefile $(SOURCE) $(HEADERS)
-	$(CXX) $(CXXFLAGS) $(SANITY_FLAGS) $(SOURCE) -o $(OUTPUT)
+	$(CC) $(CFLAGS) $(SANITY_FLAGS) $(SOURCE) -o $(OUTPUT)
 
-run:
+run: $(OUTPUT)
 	./$(OUTPUT)
 
 clean:
-	@rm $(OUTPUT)
+	@rm -f $(OUTPUT)
+
+install: $(OUTPUT)
+	install -Dm755 "cpufetch"   "$(DESTDIR)$(PREFIX)/bin/cpufetch"
+	install -Dm644 "LICENSE"    "$(DESTDIR)$(PREFIX)/share/licenses/cpufetch-git/LICENSE"
+	install -Dm644 "cpufetch.1" "$(DESTDIR)$(PREFIX)/share/man/man1/cpufetch.1.gz"
+
+uninstall:
+	rm -f "$(DESTDIR)$(PREFIX)/bin/cpufetch"
+	rm -f "$(DESTDIR)$(PREFIX)/share/licenses/cpufetch-git/LICENSE"
+	rm -f "$(DESTDIR)$(PREFIX)/share/man/man1/cpufetch.1.gz"

README.md

@@ -1,28 +1,65 @@
-# cpufetch
+<p align="center"><img width=50% src="./pictures/cpufetch.png"></p>
 
-Prints a fancy summary of the CPU with some advanced information
-![cpu1](i9.png)
+<div align="center">
 
-### Platforms
-cpufetch currently supports x86 CPUs (both Intel and AMD CPUs)
+![GitHub tag (latest by date)](https://img.shields.io/github/v/tag/Dr-Noob/cpufetch?label=cpufetch)
+[![GitHub Repo stars](https://img.shields.io/github/stars/Dr-Noob/cpufetch?color=4CC61F)](https://github.com/Dr-Noob/cpufetch/stargazers)
+[![GitHub issues](https://img.shields.io/github/issues/Dr-Noob/cpufetch)](https://github.com/Dr-Noob/cpufetch/issues)
+[![Packaging status](https://repology.org/badge/tiny-repos/cpufetch.svg)](https://repology.org/project/cpufetch/versions)
+[![License](https://img.shields.io/github/license/Dr-Noob/cpufetch?color=orange)](https://github.com/Dr-Noob/cpufetch/blob/master/LICENSE)
 
-| Platform  | Intel                     | AMD                      | Notes             |
-|:---------:|:-------------------------:|:------------------------:|:-----------------:|
-| Linux     | :heavy_check_mark:        | :heavy_check_mark:       | Prefered platform |
-| Windows   | :heavy_check_mark:        | :heavy_check_mark:       | Some information may be missing. <br> No colors and worse CPU art |
-| macOS     | :heavy_exclamation_mark:  | :heavy_exclamation_mark: | Untested |
+<h4 align="center">Simple yet fancy CPU architecture fetching tool</h4>
+&nbsp;
+
+![cpu1](pictures/i9.png)
+
+</div>
+
+# Table of contents
+<!-- UPDATE with: doctoc --notitle README.md -->
+<!-- START doctoc generated TOC please keep comment here to allow auto update -->
+<!-- DON'T EDIT THIS SECTION, INSTEAD RE-RUN doctoc TO UPDATE -->
 
 
-### Usage and installation
-#### Linux
-There is a cpufetch package available in Arch Linux ([cpufetch-git](https://aur.archlinux.org/packages/cpufetch-git)).
+- [1. Support](#1-support)
+- [2. Installation](#2-installation)
+  - [2.1 Installing from a package](#21-installing-from-a-package)
+  - [2.2 Building from source (Linux/Windows/macOS)](#22-building-from-source-linuxwindowsmacos)
+  - [2.3 Android](#23-android)
+- [3. Examples](#3-examples)
+  - [3.1 x86_64 CPUs](#31-x86_64-cpus)
+  - [3.2 ARM CPUs](#32-arm-cpus)
+- [4. Colors and style](#4-colors-and-style)
+- [5. Implementation](#5-implementation)
+- [6. Bugs or improvements](#6-bugs-or-improvements)
+- [7. Acknowledgements](#7-acknowledgements)
 
-If you are in other distro, you can build `cpufetch` from source (see below)
+<!-- END doctoc generated TOC please keep comment here to allow auto update -->
 
-#### Windows
-In the [releases](https://github.com/Dr-Noob/cpufetch/releases) section you will find some cpufetch executables compiled for Windows. Just download and run it from Windows CMD.
+# 1. Support
 
-#### Building from source
+cpufetch supports the following architectures:
+- x86 / x86_64
+- ARM
+- PowerPC
+
+| OS        | x86_64 / x86              | ARM                | PowerPC            | Notes             |
+|:---------:|:------------------------:|:-------------------:|:------------------:|:----------:|
+| GNU/Linux | :heavy_check_mark:        | :heavy_check_mark: | :heavy_check_mark: | Best support      |
+| Windows   | :heavy_check_mark:        | :x:                | :x:                | Some information may be missing. <br> Colors will be used if supported |
+| Android   | :heavy_exclamation_mark:  | :heavy_check_mark: | :x:                | Some information may be missing. <br> Not tested under x86_64 |
+| macOS     | :heavy_check_mark:        | :x:                | :x:                | Some information may be missing. <br> Apple M1 support may be added <br> in the future (see [#47](https://github.com/Dr-Noob/cpufetch/issues/47))|
+| FreeBSD   | :heavy_check_mark:        | :x:                | :x:                | Some information may be missing.  |
+
+# 2. Installation
+## 2.1 Installing from a package
+Choose the right package for your operating system:
+
+[![Packaging status](https://repology.org/badge/vertical-allrepos/cpufetch.svg)](https://repology.org/project/cpufetch/versions)
+
+If there is no available package for your OS, you can download the cpufetch binary from [the releases page](https://github.com/Dr-Noob/cpufetch/releases), or [build cpufetch from source](#22-building-from-source-linuxwindowsmacos) (see below).
+
+## 2.2 Building from source (Linux/Windows/macOS)
 Just clone the repo and use `make` to compile it
 
 ```
@@ -32,34 +69,51 @@ make
 ./cpufetch
 ```
 
-The Makefile is designed to work on both Linux and Windows.
+The Makefile is designed to work on Linux, Windows and macOS.
 
-### Example
+## 2.3 Android
+1. Install `termux` app (terminal emulator)
+2. Run `pkg install -y git make clang` inside termux.
+3. Build from source normally:
+  - git clone https://github.com/Dr-Noob/cpufetch
+  - cd cpufetch
+  - make
+  - ./cpufetch
 
+# 3. Examples
 Here are more examples of how `cpufetch` looks on different CPUs.
 
-![cpu2](epyc.png)
+## 3.1 x86_64 CPUs
 
-![cpu3](cascade_lake.png)
+![cpu2](pictures/epyc.png)
 
-### Colors and style
+![cpu3](pictures/cascade_lake.png)
+
+## 3.2 ARM CPUs
+
+![cpu4](pictures/exynos.png)
+
+![cpu5](pictures/snapdragon.png)
+
+# 4. Colors and style
 By default, `cpufetch` will print the CPU art with the system colorscheme. However, you can always set a custom color scheme, either
 specifying Intel or AMD, or specifying the colors in RGB format:
 
 ```
 ./cpufetch --color intel (default color for Intel)
-./cpufetch --color amd (default color for AND)
+./cpufetch --color amd (default color for AMD)
 ./cpufetch --color 239,90,45:210,200,200:100,200,45:0,200,200 (example)
 ```
 
 In the case of setting the colors using RGB, 4 colors must be given in with the format: ``[R,G,B:R,G,B:R,G,B:R,G,B]``. These colors correspond to CPU art color (2 colors) and for the text colors (following 2). Thus, you can customize all the colors.
 
-### Implementation
+# 5. Implementation
+See [cpufetch programming documentation](https://github.com/Dr-Noob/cpufetch/doc/README.md).
 
-`cpufetch` fetches all of the information using the `CPUID` x86 instruction. There are, however, some cases where the CPU does not support fetching some needed information. In this case, `cpufetch` will use `/sys/devices/system/cpu` in Linux as a fallback. If `cpufetch` is running on Windows and `CPUID` does not give all the data, `cpufetch` won't be able to show it. [I hope this can be fixed in the future](https://github.com/Dr-Noob/cpufetch/issues/30)
+# 6. Bugs or improvements
+See [cpufetch contributing guidelines](https://github.com/Dr-Noob/cpufetch/CONTRIBUTING.md)
 
-### Bugs or improvements
-There are many open issues in github (see [issues](https://github.com/Dr-Noob/cpufetch/issues)). Feel free to open a new one report a issue or propose any improvement in `cpufetch`
+# 7. Acknowledgements
+Special thanks to [Gonzalocl](https://github.com/Gonzalocl) and [OdnetninI](https://github.com/OdnetninI). They tested `cpufetch` in its beginnings in many different CPUs they have access to, which made it easier to debug and check the correctness of `cpufetch`.
 
-### Testers
-I would like to thank [Gonzalocl](https://github.com/Gonzalocl) and [OdnetninI](https://github.com/OdnetninI) for their help, running `cpufeth` in many different CPUs they have access to, which makes it easier to debug and check the correctness of `cpufetch`.
+Special thanks too to the fellow contributors and interested people in the project!

ascii/amdASCII

@@ -1,21 +0,0 @@
-
-
-
-
-
-
-     @@@@      @@@%      @@@.  @@@@@@@@(      .############
-    @@@@@@     @@@@@   %@@@@.  @@@    @@@@      .((((((####
-   @@@  @@@    @@@/@@@@@@&@@.  @@@     %@@%     #      ####
-  @@@,  (@@#   @@@  @@@/ @@@.  @@@     .@@@   ###      ####
- ,@@@@@@@@@@,  @@@       @@@.  @@@     @@@   ####      ####
- @@@      @@@  @@@       @@@.  @@@@@@@@@&    #######/   .##
-
-
-
-
-
-
-
-
- 

ascii/intelASCII

@@ -1,19 +0,0 @@
-                              ################
-                      #######                #######
-                 ####                              ####
-             ###                                     ####
-        ###                                             ###
-        ###                                  ###        ###
-     #                    ###                ###        ###
-   ##   ###   #########   ######   ######    ###        ###
-  ##    ###   ###    ###  ###    ####  ####  ###        ###
- ##     ###   ###    ###  ###    ###    ###  ###       ###
-##      ###   ###    ###  ###    ##########  ###     ####
-##      ###   ###    ###  ###    ###         ###   #####
-##       ##   ###    ###   #####  #########   ##  ###
-###
-(###
- ####                                        ####
-   #####                               ##########
-     ##########               ################
-         ###############################

cpufetch.1

@@ -0,0 +1,73 @@
+.\" DO NOT MODIFY THIS FILE!  It was generated by help2man 1.48.2.
+.TH CPUFETCH "1" "June 2021" "cpufetch v0.97 (x86_64 build)" "User Commands"
+.SH NAME
+cpufetch \- Simple yet fancy CPU architecture fetching tool
+.SH SYNOPSIS
+.B cpufetch
+[\fI\,OPTION\/\fR]...
+.SH DESCRIPTION
+Print detailed information about the CPU architecture. cpufetch displays information like the number of cores, microarchitecture, frequency, cache and peak performance. The program supports x86, x86_64 and ARM architectures and runs on GNU/Linux, Windows, Android and macOS (see https://github.com/Dr-Noob/cpufetch#1-support for more information)
+.SH OPTIONS
+.TP
+\fB\-c\fR, \fB\-\-color\fR
+Set the color scheme (by default, cpufetch uses the system color scheme)
+.TP
+\fB\-s\fR, \fB\-\-style\fR
+Set the style of CPU art
+.TP
+\fB\-d\fR, \fB\-\-debug\fR
+Prints CPU model and cpuid levels (debug purposes)
+.TP
+\fB\-v\fR, \fB\-\-verbose\fR
+Prints extra information (if available) about how cpufetch tried fetching information
+.TP
+\fB\-r\fR, \fB\-\-raw\fR
+Prints raw cpuid data
+.TP
+\fB\-h\fR, \fB\-\-help\fR
+Prints this help and exit
+.TP
+\fB\-V\fR, \fB\-\-version\fR
+Prints cpufetch version and exit
+.SH "COLORS:"
+.TP
+* "intel":
+Use Intel default color scheme
+.TP
+* "amd":
+Use AMD default color scheme
+.TP
+* "ibm":
+Use IBM default color scheme
+.TP
+* "arm":
+Use ARM default color scheme
+.TP
+* custom:
+If color argument do not match "intel", "amd" or "arm", a custom scheme can be specified.
+4 colors must be given in RGB with the format: R,G,B:R,G,B:...The first 2 colors are the CPU art color and the next 2 colors are the text colors
+.SH "STYLES:"
+.TP
+* "fancy":
+Default style
+.TP
+* "retro":
+Old cpufetch style
+.TP
+* "legacy":
+Fallback style for terminals that do not support colors
+.SH "EXAMPLES:"
+Run cpufetch with Intel color scheme:
+.PP
+\&./cpufetch \fB\-\-color\fR intel
+.PP
+Run cpufetch with a custom color scheme:
+.PP
+\&./cpufetch \fB\-\-color\fR 239,90,45:210,200,200:100,200,45:0,200,200
+.SH "BUGS:"
+Report bugs to https://github.com/Dr\-Noob/cpufetch/issues
+.SH "NOTE:"
+Peak performance information is NOT accurate. cpufetch computes peak performance using the max frequency. However, to properly compute peak performance, you need to know the frequency of the CPU running AVX code, which is not be fetched by cpufetch since it depends on each specific CPU. For peak performance measurement see peakperf (https://github.com/Dr\-Noob/peakperf)
+.SH "AUTHOR:"
+Dr-Noob (https://github.com/Dr-Noob)
+

cpufetch.8

@@ -1,57 +0,0 @@
-.TH man 8 "1 Sep 2020" "0.7" "cpufetch man page"
-.SH NAME
-cpufetch \- Prints a fancy summary of the CPU with some advanced information
-.SH SYNOPSIS
-cpufetch [--version] [--help] [--levels] [--style fancy|retro|legacy] [--color intel|amd|'R,G,B:R,G,B:R,G,B:R,G,B']
-.SH DESCRIPTION
-cpufetch will print CPU information, for which will query CPUID instructions and udev directories on Linux as a fallback method. Some of this features are:
-.IP \[bu] 2
-Name
-.IP \[bu]
-Frequency
-.IP \[bu]
-Number of cores (Physical and Logical)
-.IP \[bu]
-Cache sizes
-.IP \[bu]
-Theoretical peak performance in floating point operations per second (FLOP/s)
-.SH OPTIONS
-.TP
-\fB\-\-style\fR \f[I][intel|amd|R,G,B:R,G,B:R,G,B:R,G,B]\f[]
-Set the color scheme. By default, cpufetch uses the system color scheme. This option lets the user use different colors to print the CPU art:
-.IP \[bu]
-\fB"intel"\fR: Use intel color scheme
-.IP \[bu]
-\fB"amd"\fR: Use amd color scheme
-.IP \[bu]
-\fBcustom\fR: If color do not match "intel" or "amd", a custom scheme can be specified: 4 colors must be given in RGB with the format: R,G,B:R,G,B:... 
-             These colors correspond to CPU art color (2 colors) and for the text colors (following 2) 
-.TP
-\fB\-\-style\fR \f[I]STYLE\f[]
-Specify the style of ascii logo:
-.IP \[bu] 
-\fB"fancy"\fR:  Default style
-.IP \[bu]
-\fB"retro"\fR:  Old cpufetch style
-.IP \[bu]
-\fB"legacy"\fR: Fallback style for terminals that does not support colors
-.TP
-\fB\-\-levels\fR
-Prints CPUID levels and CPU name
-.TP
-\fB\-\-verbose\fR
-Prints extra information (if available) about how cpufetch tried fetching information
-.TP
-\fB\-\-help\fR
-Prints help
-.TP
-\fB\-\-version\fR
-Prints cpufetch version
-.SH BUGS
-Bugs should be posted on: https://github.com/Dr-Noob/cpufetch/issues
-.SH NOTES
-Peak performance information is NOT accurate. cpufetch computes peak performance using the max   
-frequency. However, to properly compute peak performance, you need to know the frequency of the  
-CPU running AVX code, which is not be fetched by cpufetch since it depends on each specific CPU.
-.SH AUTHOR
-Dr-Noob (https://github.com/Dr-Noob)

doc/DOCUMENTATION_ARM.md

@@ -0,0 +1,60 @@
+### 2. Why ARM cpufetch works on Linux based systems?
+CPUID instructions (present in x86 architectures) [[1](#references)] allow user level applications to obtain information about the CPU. In ARM architectures, there are many registers (MIDR [[2](#references)], CCSIDR [[3](#references)]) that provide information about the CPU too. However, those registers can only be read from privilege mode (PL1 or higher). Therefore, any user level tool which can actually read information about the running CPU must use the operating system to do so. cpufetch uses some Linux kernel features (see the remaining sections). Therefore, cpufetch in ARM processors is limited to Linux kernel based systems, such as __GNU/Linux__ and __Android__
+
+### 3. How to get CPU microarchitecture?
+__Involved code: [get_midr_from_cpuinfo (udev.c)](https://github.com/Dr-Noob/cpufetch/blob/master/src/arm/udev.c), [midr.c](https://github.com/Dr-Noob/cpufetch/blob/master/src/arm/midr.c)__
+
+Microarchitecture information is acquired from the Main ID Register (MIDR) [[2](#references)]. Currently, cpufetch rebuilds this register using `/proc/cpuinfo` file. While this file does not contain the value of the register per se, it contains the following fields:
+- `CPU implementer`,
+- `CPU architecture`
+- `CPU variant`
+- `CPU part`
+- `CPU revision`
+
+The MIDR register can be built with this information. Another posible approach is to read MIDR directly from `/sys/devices/system/cpu/cpu*/regs/identification/midr_el1`
+
+With the MIDR available, the approach is the same as the one used in x86_64 architectures. cpufetch has a file that acts like a database that tries to match the MIDR register with the specific CPU microarchitecture.
+
+### 4. How to get CPU topology?
+__Involved code: [get_ncores_from_cpuinfo (udev.c)](https://github.com/Dr-Noob/cpufetch/blob/master/src/arm/udev.c), [midr.c](https://github.com/Dr-Noob/cpufetch/blob/master/src/arm/midr.c)__
+
+ARM provides a new interesting architecture feature: big.LITTLE architectures [[4](#references)]. An ARM CPU can be organized like a typical x86_64 CPU, where all cores share the same microarchitecture. However, ARM big.LITTLE architecture breaks this schema. In a big.LITTLE CPU, two or more CPUs microarchitecture live in the same chip.
+
+This means that cpufetch can't just read which microarchitecture is the first core and assume that the rest of them shares the same microarchitecture. To get the CPU topology, cpufetch first reads the number of CPU cores. This can be obtained from `/sys/devices/system/cpu/present`
+
+Then, for each core, cpufetch reads the MIDR and also the frequency (see section 5). Then, cpufetch assumes that two cores are different when their MIDR are different. This idea allows cpufetch to detect big.LITTLE architectures, and to know how many cores of each architecture the running CPU has.
+
+### 5. How to get the frequency?
+Frequency is read directly from `/sys/devices/system/cpu/cpu*/cpufreq/cpuinfo_max_freq`
+
+### 6. How to get system on chip model?
+__Involved code: [soc.c](https://github.com/Dr-Noob/cpufetch/blob/master/src/arm/soc.c)__
+
+System on chip (SoC) model is obtained using the same idea as the microarchitecture. First, SoC string is read. Then, the string has to be matched against a database-like function (__parse_soc_from_string__). The SoC string of the running CPU can be obtained using two different approaches:
+
+- Using `/proc/cpuinfo`. This is the first thing to try. Linux kernel usually provides the string under the `Hardware` keyword. However, the Linux kernel may be unable to provide this information, or this string may not be found in the database-like function.
+- Using Android properties: This only works on Android systems. Android properties can be read using `__system_property_get` function. cpufetch tries to read two properties:
+  - `ro.mediatek.platform`
+  - `ro.product.board`
+
+  If any string is returned, cpufetch tries to find a match in the database (using the same database as in the case of `/proc/cpuinfo`).
+
+The expected strings have to be hardcoded. I found two ways of knowing which string should correspond to which SoC:
+
+  - Searching on the internet. Manufacturers __usually__ provide this information. For example, Qualcomm usually publishes the chip name along with other characteristics (under the `Part` or `Part number` keyword [[6](#references)]).
+  - "Hunting" for the strings. For example, finding smartphones with a given SoC and manually reading the `/proc/cpuinfo` or the `build.prop` file. A very good resource to do this is the SpecDevice webpage [[7](#references)]).
+
+### 7. How to get cache size and topology?
+ARM architecture supports reading the cache information via some registers (for example, the CCSIDR register  [[3](#references)]). As mentioned earlier, user level applications are not able to read these registers directly. The remaining option is to ask the operating system for this information. However, at the moment, the __Linux kernel does not provide cache information__. Therefore, cpufetch does not print any cache information on ARM CPUs at the moment. There are, however, other approaches to be explored:
+
+- Read the registers in kernel mode. This can be accomplished by running a kernel module [[4](#references)]. Unfortunately, running a custom kernel module is tricky, and sometimes impossible to do reasonably (for example, in Android devices). In any case, my decision is to run cpufetch on user level only.
+- Hardcode the cache information for each SoC: Sometimes, manufacturers publish technical information about the chips, where cache topology and size are shown. This method is impractical, since this kind of information is very hard (or impossible) to find online, and the number of SoC is huge.
+
+#### References
+- [1] [cpufetch x86_64 documentation](https://github.com/Dr-Noob/cpufetch/blob/master/doc/DOCUMENTATION_X86.md)
+- [2] [Main ID Register](https://developer.arm.com/documentation/ddi0433/c/system-control/register-descriptions/main-id-register)
+- [3] [Cache size ID Register](https://developer.arm.com/documentation/100403/0200/register-descriptions/aarch32-system-registers/ccsidr--cache-size-id-register)
+- [4] [How to get the size of the CPU cache in Linux](https://stackoverflow.com/a/63474811/9975463)
+- [5] [ARM big.LITTLE](https://en.wikipedia.org/wiki/ARM_big.LITTLE)
+- [6] [Snapdragon 855+ Mobile Platform](https://www.qualcomm.com/products/snapdragon-855-plus-mobile-platform)
+- [7] [SpecDevice](http://specdevice.com/unmoderated.php)

doc/DOCUMENTATION_PPC.md

@@ -0,0 +1,26 @@
+### 2. How to get CPU microarchitecture?
+__Involved code: [get_uarch_from_pvr (uarch.c)](https://github.com/Dr-Noob/cpufetch/src/ppc/uarch.c)__
+
+Microarchitecture is deduced from the PVR register, which is read using the `mfpvr` instruction. The correspondence between the PVR and the specific microarchitecture has been implemented using the values in `arch/powerpc/kernel/cputable.c` in the Linux kernel. Some of them have been removed. The manufacturing process has been queried by searching on the internet.
+
+### 3. How to get CPU topology?
+__Involved code: [get_topology_info (ppc.c)](https://github.com/Dr-Noob/cpufetch/src/ppc/ppc.c)__
+
+The total number of cores is queried using `sysconf(_SC_NPROCESSORS_ONLN)`. Then, with the number of sockets and the number of physical cores, we can calculate the number of threads per core.
+
+The number of sockets is queried using `/sys/devices/system/cpu/cpu*/topology/physical_package_id`. Once this file has been read for all of the cores, a simple custom algorithm is used to determine the number of sockets.
+
+The number of physical cores is queried using `/sys/devices/system/cpu/cpu*/topology/core_id`. Again, a custom algorithm is used to determine the number of physical cores.
+
+### 4. How to get the frequency?
+Frequency is read directly from `/sys/devices/system/cpu/cpu*/cpufreq/cpuinfo_max_freq`
+
+### 5. How to get cache size and topology?
+Cache size is retrieved directly from Linux (using `/sys/devices/system/cpu/cpu0/cache/index*/size`).
+
+To find the cache topology, the files `/sys/devices/system/cpu/cpu0/cache/index*/shared_cpu_map` are used, and a custom algorithm is used to determine how many caches are there at each level.
+
+_NOTE_: To avoid Linux dependencies at this point, it looks like it is possible to derive the cache size and topology from the microarchitecture. For example, in the POWER9 architecture, wikichip assumes that all the POWER9 CPUs have the same cache size for each core and topology [[1](#references)].
+
+#### References
+- [1] [POWER9 - wikichip](https://en.wikichip.org/wiki/ibm/microarchitectures/power9)

doc/DOCUMENTATION_X86.md

@@ -0,0 +1,120 @@
+### 2. Why differences between Intel and AMD?
+There are many different CPUID leaves [[1](#references)]. In some cases, a given leaf does the same thing in Intel and AMD processors, but in the majority of them, they don't. For example, leaf 0x4 gives you the caches information, but in AMD is a reserved (invalid) leaf! In the case of AMD, is more common to fetch information using extended levels than using the standard levels (the other way around with Intel).
+
+### 3. How to get the frequency?
+__Involved code: [get_frequency_info (cpuid.c)](https://github.com/Dr-Noob/cpufetch/blob/master/src/x86/cpuid.c)__
+
+CPUID leaf 0x16 is used.
+
+If the CPU does not support supports such level:
+- Linux: cpufetch will try to obtain this information using `/sys` filesystem in Linux. I think that Linux knows the frequency using model specific registers (MSRs), which you can't read at the user level.
+- Windows: cpufetch can't obtain CPU frequency. This means that peak performance can't be computed because the frequency is needed to compute it.
+
+### 4. How to get cache sizes?
+__Involved code: [get_cache_info (cpuid.c)](https://github.com/Dr-Noob/cpufetch/blob/master/src/x86/cpuid.c)__
+
+- Intel: CPUID leaf 0x4 is used (using __get_cache_info_general__). If the CPU does not support it, cpufetch can't get this information.
+- AMD: Extended CPUID leaf 0x1D is used (using __get_cache_info_general__). If the CPU does not support this level, cpufetch uses a fallback method, which uses extended leaves 0x5 and 0x6. This fallback method uses __get_cache_info_amd_fallback__.
+
+
+### 5. How to get CPU microarchitecture?
+__Involved code: [get_cpu_uarch (cpuid.c)](https://github.com/Dr-Noob/cpufetch/blob/master/src/x86/cpuid.c), [get_uarch_from_cpuid (uarch.c)](https://github.com/Dr-Noob/cpufetch/blob/master/src/x86/uarch.c)__
+
+CPUID leaf 0x1 is used. From there, we get:
+- Model
+- Extended Model
+- Family
+- Extended Family
+- Stepping
+
+Knowing this information, we can distinguish any CPU microarchitecture. Inside __uarch.c__ there is a function that behaves like a database or a lookup table. The function of this database is to find a match between the information obtained from 0x1 and what kind of microarchitecture the current CPU is. I got the data using and adapting the code from Todd Allen's cpuid program [[5](#references)]. Knowing the microarchitecture, we can obtain the manufacturing process (or technology, the size in nm of the transistors).
+
+### 6. How to get CPU topology?
+__Involved code: [cpuid.h](https://github.com/Dr-Noob/cpufetch/blob/master/src/x86/cpuid.h), [get_topology_info (cpuid.c)](https://github.com/Dr-Noob/cpufetch/blob/master/src/x86/cpuid.c), [apic.c](https://github.com/Dr-Noob/cpufetch/blob/master/src/x86/apic.c)__
+
+cpufetch aims to support the most complex systems, so it supports multi-socket CPUs and detailed SMT (Intel HyperThreading) information. The CPU topology is stored in the following struct:
+
+```
+struct topology {
+  int64_t total_cores;
+  uint32_t physical_cores;
+  uint32_t logical_cores;
+  uint32_t smt_available;
+  uint32_t smt_supported;
+  uint32_t sockets;
+};
+```
+
+This structure needs a bit of explanation, to know what are we looking for:
+- `physical_cores`: Number of physical cores. In a multi socket system, this field stores the number of cores for just one socket.
+- `logical_cores`: Number of logical cores. In a multi socket system, this field stores the number of logical cores for just one socket.
+- `total_cores`: Total number of logical cores. In a multi socket system, this field stores the number of logical cores for the entire system.
+- `sockets`: How many sockets the system has.
+- `smt_supported`: Stores if SMT (or Intel HT) is supported in the CPU, storing the number of threads per core. So, if `smt_supported == 1`, it means that there is 1 thread per core, and SMT is not supported. If SMT is supported, then `smt_supported >= 1`. Note this field tells if the CPU if supports it, but not if SMT is activated or not.
+- `smt_available`: The same idea as `smt_supported`, but it stores if SMT is available. If SMT is not supported, then `smt_available` is always `1`. The differentiation between supported and available lets cpufetch distinguish when a CPU has SMT capabilities, but are disabled (probably in the BIOS).
+
+Let's give two CPU examples and the values that `struct topology` would have in these CPUs.
+- Example 1: Dual Socket Intel Xeon 6248:
+
+```
+total_cores = 80
+physical_cores = 20
+logical_cores = 40
+smt_available = 2
+smt_supported = 2
+sockets = 2
+```
+
+- Example 2: Intel Core i7-4790K with SMT disabled in BIOS:
+
+```
+total_cores = 8
+physical_cores = 4
+logical_cores = 8
+smt_available = 1
+smt_supported = 2
+sockets = 1
+```
+
+Now that we know what data are we looking for, let's see how we get it:
+
+- __Intel__: The methodology used is explained in the Intel webpage [[2](#references)]. Intel explains how to do it and also gives an example source code. I used it and modified it to fit cpufetch style. The core of this methodology is the usage of the APIC id, so the code is inside __apic.c__.
+- __AMD__: Intel's algorithm using APIC does not work for AMD. To get the same information in AMD, I used the reference from OSdev [[3](#references)] and also ideas from lscpu [[4](#references)]. This uses:
+  - CPUID extended leaf 0x8: Fill `logical_cores`
+  - CPUID extended leaf 0x1E: Fill `smt_supported`
+  - CPUID standard leaf 0x1 (APIC): Fill `smt_available`
+
+  If any of these levels are not supported, these fields are just guessed. For example, if we are not able to know if SMT is supported, we guess it is not. With all of these data, we can calculate the rest of the fields:
+
+  ```
+  physical_cores = logical_cores / smt_available;  
+  if(topo->smt_supported > 1)
+    sockets = total_cores / smt_supported / physical_cores; // Idea borrowed from lscpu
+  else
+    sockets = total_cores / physical_cores;    
+  ```
+
+### 7. How to get cache topology?
+__Involved code: [get_cache_topology_amd (cpuid.c)](https://github.com/Dr-Noob/cpufetch/blob/master/src/x86/cpuid.c), [apic.c](https://github.com/Dr-Noob/cpufetch/blob/master/src/x86/apic.c)__
+
+The topology of a cache gives us information about how many caches we have at a given level. It usually follows the rule of:
+- L1: The same as the number of cores (one L1i and one L1d per core).
+- L2: If L2 is the last level cache, one L2. If not, the same as the number of cores (one L2 per core).
+- L3: One L3 cache per socket (shared among all cores).
+
+These assumptions are generally (but not always) true. For example, for the AMD Zen generation, or the Intel Xeon Phi KNL. Thus, cpufetch does not assume the topology but obtains it instead.
+
+- __Intel__: The idea is similar to the mentioned in CPU topology [[2](#references)](it also covers how to get cache topology using APIC id).
+
+- __AMD__: Again, we have to look for another path for AMD. This time, the way to do it is easier and (I think) more solid and future proof. The idea is to use extended CPUID leaf 0x1D. If the CPU does not support it, we can still guess the topology of the caches (as mentioned earlier). If it does, CPUID can give us how many cores shares a given level of cache. So, if we have the number of cores, we can guess how many caches are there for any given level (see __get_cache_topology_amd__).
+
+#### References
+- [1] [sandpile CPUID webpage](https://www.sandpile.org/x86/cpuid.htm)
+- [2] [CPU topology and cache topology: Intel](https://software.intel.com/content/www/us/en/develop/articles/intel-64-architecture-processor-topology-enumeration.html)
+- [3] [CPU topology: AMD](https://wiki.osdev.org/Detecting_CPU_Topology_(80x86))
+- [4] [lscpu](https://github.com/karelzak/util-linux/blob/master/sys-utils/lscpu.c)
+- [5] [Todd Allen's cpuid](http://www.etallen.com/cpuid.html)
+- [6] [AMD specific CPUID specification](https://www.amd.com/system/files/TechDocs/25481.pdf)
+- [7] [Intel vs AMD CPU Architectural Differences: Chips and Chiplets](https://c.mi.com/thread-2585048-1-0.html)
+
+In addition to all these resources, I found it very interesting to search in the Linux kernel source code (for example, the directory [`arch/x86/kernel/cpu/`](https://elixir.bootlin.com/linux/latest/source/arch/x86/kernel/cpu)), because sometimes you can find ideas that cannot be found anywhere else!

doc/README.md

@@ -0,0 +1,69 @@
+# cpufetch programming documentation (v0.98)
+This documentation explains how cpufetch works internally and all the design decisions I made. This document intends to be useful for me in the future, for everyone interested in the project, and for anyone who is trying to obtain any specific information from the CPU. In this way, this can be used as a manual or a page that collects interesting material in this area.
+
+### 1. Basics
+cpufetch works for __x86_64__ (Intel and AMD),  __ARM__ and __PowerPC__ CPUs. However, cpufetch is expected to work better on x86_64, because the codebase is older and has been tested much more than the ARM and PowerPC versions. Depending on the architecture, cpufetch choose certain files to be compiled. A summarized tree of the source code of cpufetch is shown below.
+
+```
+cpufetch/
+├── doc
+│   ├── DOCUMENTATION_ARM.md
+|   ├── DOCUMENTATION_PPC.md
+│   ├── DOCUMENTATION_X86.md
+│   └── README.md
+├── Makefile
+├── README.md
+└── src/
+    ├── arm/
+    │   ├── midr.c
+    │   ├── midr.h
+    │   └── other files ...
+    ├── common/
+    │   └── common files ...
+    ├── ppc/
+    |   ├── ppc.c
+    |   ├── ppc.h
+    |   └── other files ...
+    └── x86/
+        ├── cpuid.c
+        ├── cpuid.h
+        └── other files ...
+```
+
+Source code is divided into four directories:
+
+- `common/`: Source code shared between all architectures
+- `arm/`: ARM source code
+- `ppc/`: PowerPC source code
+- `x86/`: x86 source code
+
+##### 1.1 Basics (x86_64)
+
+In x86, __cpufetch works using the CPUID instruction__. It is called directly using assembly (see `src/x86/cpuid_asm.c`). To understand how CPUID works, see [DOCUMENTATION_X86.md](https://github.com/Dr-Noob/cpufetch/blob/master/doc/DOCUMENTATION_X86.md).
+
+At the beginning of execution, cpufetch needs to know the max standard CPUID level and max CPUID extended level supported in the running CPU. We also need to know if the x86 CPU is Intel or AMD because sometimes, the way to obtain the information depends on the manufacturer. This information will be stored in:
+
+```
+struct cpuInfo {
+  ...
+  VENDOR cpu_vendor;
+  uint32_t maxLevels;  
+  uint32_t maxExtendedLevels;
+  ...
+};
+```
+
+To use any CPUID leaf, cpufetch always needs to check that it is supported in the current CPU.
+
+##### 1.2 Basics (ARM)
+In ARM, __cpufetch works using the MIDR register and Linux filesystem__. MIDR (Main ID Register) is read from `/proc/cpuinfo`. It allows the detection of the microarchitecture of the cores. Furthermore, Linux filesystem `/sys/devices/system/cpu/` is used to fetch the number of cores and other information. This is the main reason to explain __why `cpufetch` for ARM only works on Linux systems.__
+
+##### 1.3 Basics (PowerPC)
+In PowerPC, __cpufetch works using the PVR register and Linux filesystem__. PVR (Processor Version Register) is read using assembly and it is used to identify the microarchitecture of the CPU. Linux is also used to query the rest of the information, like the CPU topology, frequency, etc. This is the main reason to explain __why `cpufetch` for PowerPC only works on Linux systems.__
+
+##### 1.4 Documentation organization
+The rest of the documentation is divided in specific files for each architecture, since each one needs different implementations:
+
+- [DOCUMENTATION_ARM.md](https://github.com/Dr-Noob/cpufetch/blob/master/doc/DOCUMENTATION_ARM.md)
+- [DOCUMENTATION_PPC.md](https://github.com/Dr-Noob/cpufetch/blob/master/doc/DOCUMENTATION_PPC.md)
+- [DOCUMENTATION_X86.md](https://github.com/Dr-Noob/cpufetch/blob/master/doc/DOCUMENTATION_X86.md)

src/args.c

@@ -1,252 +0,0 @@
-#include <getopt.h>
-#include <stdio.h>
-#include <string.h>
-#include <stdlib.h>
-#include "args.h"
-#include "global.h"
-
-#define ARG_STR_STYLE    "style"
-#define ARG_STR_COLOR    "color"
-#define ARG_STR_HELP     "help"
-#define ARG_STR_LEVELS   "levels"
-#define ARG_STR_VERBOSE  "verbose"
-#define ARG_STR_VERSION  "version"
-
-#define ARG_CHAR_STYLE    0
-#define ARG_CHAR_COLOR    1
-#define ARG_CHAR_HELP     2
-#define ARG_CHAR_LEVELS   3
-#define ARG_CHAR_VERBOSE  4
-#define ARG_CHAR_VERSION  5
-
-#define STYLE_STR_1      "fancy"
-#define STYLE_STR_2      "retro"
-#define STYLE_STR_3      "legacy"
-
-#define COLOR_STR_INTEL "intel"
-#define COLOR_STR_AMD   "amd"
-
-struct args_struct {
-  bool levels_flag;
-  bool help_flag;
-  bool verbose_flag;
-  bool version_flag;
-  STYLE style;
-  struct colors* colors;
-};
-
-static const char* SYTLES_STR_LIST[STYLES_COUNT] = { STYLE_STR_1, STYLE_STR_2, STYLE_STR_3 };
-static struct args_struct args;
-
-STYLE get_style() {
-  return args.style;
-}
-
-struct colors* get_colors() {
-  return args.colors;
-}
-
-bool show_help() {
-  return args.help_flag;
-}
-
-bool show_version() {
-  return args.version_flag;
-}
-
-bool show_levels() {
-  return args.levels_flag;
-}
-
-bool verbose_enabled() {
-  return args.verbose_flag;
-}
-
-STYLE parse_style(char* style) {
-  int i = 0;
-  while(i != STYLES_COUNT && strcmp(SYTLES_STR_LIST[i],style) != 0)
-    i++;
-
-  if(i == STYLES_COUNT)
-    return STYLE_INVALID;
-  return i;
-}
-
-void free_colors_struct(struct colors* cs) {
-  free(cs->c1);
-  free(cs->c2);
-  free(cs->c3);
-  free(cs->c4);
-  free(cs);
-}
-
-bool parse_color(char* optarg, struct colors** cs) {
-  *cs = malloc(sizeof(struct colors));        
-  (*cs)->c1 = malloc(sizeof(struct color));
-  (*cs)->c2 = malloc(sizeof(struct color));
-  (*cs)->c3 = malloc(sizeof(struct color));
-  (*cs)->c4 = malloc(sizeof(struct color));
-  struct color** c1 = &((*cs)->c1);
-  struct color** c2 = &((*cs)->c2);
-  struct color** c3 = &((*cs)->c3);
-  struct color** c4 = &((*cs)->c4);
-  int32_t ret;
-  char* str_to_parse = NULL;
-  bool free_ptr;
-  
-  if(strcmp(optarg, COLOR_STR_INTEL) == 0) {
-    str_to_parse = malloc(sizeof(char) * 46);
-    strcpy(str_to_parse, COLOR_DEFAULT_INTEL);
-    free_ptr = true;
-  }
-  else if(strcmp(optarg, COLOR_STR_AMD) == 0) {
-    str_to_parse = malloc(sizeof(char) * 44);
-    strcpy(str_to_parse, COLOR_DEFAULT_AMD);  
-    free_ptr = true;
-  }
-  else {  
-    str_to_parse = optarg;
-    free_ptr = false;
-  }
-  
-  ret = sscanf(str_to_parse, "%d,%d,%d:%d,%d,%d:%d,%d,%d:%d,%d,%d", 
-               &(*c1)->R, &(*c1)->G, &(*c1)->B,
-               &(*c2)->R, &(*c2)->G, &(*c2)->B,
-               &(*c3)->R, &(*c3)->G, &(*c3)->B,
-               &(*c4)->R, &(*c4)->G, &(*c4)->B);
-  
-  if(ret != 12) {
-    printErr("Expected to read 12 values for color but read %d", ret);
-    return false;    
-  }
-  
-  //TODO: Refactor c1->R c2->R ... to c[i]->R
-  if((*c1)->R < 0 || (*c1)->R > 255) {
-    printErr("Red in color 1 is invalid. Must be in range (0, 255)");
-    return false;
-  }
-  if((*c1)->G < 0 || (*c1)->G > 255) {
-    printErr("Green in color 1 is invalid. Must be in range (0, 255)");
-    return false;
-  }
-  if((*c1)->B < 0 || (*c1)->B > 255) {
-    printErr("Blue in color 1 is invalid. Must be in range (0, 255)");
-    return false;
-  }
-  if((*c2)->R < 0 || (*c2)->R > 255) {
-    printErr("Red in color 2 is invalid. Must be in range (0, 255)");
-    return false;
-  }
-  if((*c2)->G < 0 || (*c2)->G > 255) {
-    printErr("Green in color 2 is invalid. Must be in range (0, 255)");
-    return false;
-  }
-  if((*c2)->B < 0 || (*c2)->B > 255) {
-    printErr("Blue in color 2 is invalid. Must be in range (0, 255)");
-    return false;
-  }  
-  
-  if(free_ptr) free (str_to_parse);
-  
-  return true;      
-}
-
-bool parse_args(int argc, char* argv[]) {
-  int c;
-  int option_index = 0;  
-  opterr = 0;
-
-  bool color_flag = false;
-  args.levels_flag = false;
-  args.verbose_flag = false;
-  args.help_flag = false;
-  args.style = STYLE_EMPTY;
-  args.colors = NULL;
-
-  static struct option long_options[] = {
-      {ARG_STR_STYLE,    required_argument, 0, ARG_CHAR_STYLE   },
-      {ARG_STR_COLOR,    required_argument, 0, ARG_CHAR_COLOR   },
-      {ARG_STR_HELP,     no_argument,       0, ARG_CHAR_HELP    },
-      {ARG_STR_LEVELS,   no_argument,       0, ARG_CHAR_LEVELS  },
-      {ARG_STR_VERBOSE,  no_argument,       0, ARG_CHAR_VERBOSE },
-      {ARG_STR_VERSION,  no_argument,       0, ARG_CHAR_VERSION },
-      {0, 0, 0, 0}
-  };
-
-  c = getopt_long(argc, argv, "", long_options, &option_index);
-
-  while (c != -1) {
-     if(c == ARG_CHAR_COLOR) {
-       if(color_flag) {
-         printErr("Color option specified more than once");
-         return false;
-       }
-       color_flag  = true;       
-       if(!parse_color(optarg, &args.colors)) {
-         printErr("Color parsing failed");
-         return false;
-       }
-     }
-     else if(c == ARG_CHAR_STYLE) {
-       if(args.style != STYLE_EMPTY) {
-         printErr("Style option specified more than once");
-         return false;
-       }
-       args.style = parse_style(optarg);
-       if(args.style == STYLE_INVALID) {
-         printErr("Invalid style '%s'",optarg);
-         return false;
-       }
-     }
-     else if(c == ARG_CHAR_HELP) {
-       if(args.help_flag) {
-         printErr("Help option specified more than once");
-         return false;
-       }
-       args.help_flag  = true;
-     }
-     else if(c == ARG_CHAR_VERBOSE) {
-       if(args.verbose_flag) {
-         printErr("Verbose option specified more than once");
-         return false;
-       }
-       args.verbose_flag  = true;
-     }
-     else if(c == ARG_CHAR_LEVELS) {
-       if(args.levels_flag) {
-         printErr("Levels option specified more than once");
-         return false;
-       }
-       args.levels_flag  = true;
-     }
-     else if (c == ARG_CHAR_VERSION) {
-       if(args.version_flag) {
-         printErr("Version option specified more than once");
-         return false;
-       }
-       args.version_flag = true;
-     }
-     else if(c == '?') {
-       printWarn("Invalid options");
-       args.help_flag  = true;
-       break;
-     }
-     else
-      printBug("Bug at line number %d in file %s", __LINE__, __FILE__);
-
-    option_index = 0;
-    c = getopt_long(argc, argv,"",long_options, &option_index);
-  }
-
-  if (optind < argc) {
-    printWarn("Invalid options");
-    args.help_flag  = true;
-  }
-
-  if((args.help_flag + args.version_flag + color_flag) > 1) {
-    printWarn("You should specify just one option");
-    args.help_flag  = true;
-  }
-
-  return true;
-}

src/args.h

@@ -1,31 +0,0 @@
-#ifndef __ARGS__
-#define __ARGS__
-
-#include <stdbool.h>
-#include <stdint.h>
-
-struct color {
-  int32_t R;
-  int32_t G;
-  int32_t B;
-};
-
-struct colors {
-  struct color* c1;
-  struct color* c2;
-  struct color* c3;
-  struct color* c4;
-};
-
-#include "printer.h"
-
-bool parse_args(int argc, char* argv[]);
-bool show_help();
-bool show_levels();
-bool show_version();
-bool verbose_enabled();
-void free_colors_struct(struct colors* cs);
-struct colors* get_colors();
-STYLE get_style();
-
-#endif

src/arm/midr.c

@@ -0,0 +1,296 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <assert.h>
+#include <stdbool.h>
+#include <errno.h>
+#include <sys/auxv.h>
+#include <asm/hwcap.h>
+
+#include "../common/global.h"
+#include "udev.h"
+#include "midr.h"
+#include "uarch.h"
+#include "soc.h"
+
+struct cache* get_cache_info(struct cpuInfo* cpu) {
+  struct cache* cach = emalloc(sizeof(struct cache));
+  init_cache_struct(cach);
+
+  cach->max_cache_level = 2;
+  for(int i=0; i < cach->max_cache_level + 1; i++) {
+    cach->cach_arr[i]->exists = true;
+    cach->cach_arr[i]->num_caches = 1;
+    cach->cach_arr[i]->size = 0;
+  }
+
+  return cach;
+}
+
+struct frequency* get_frequency_info(uint32_t core) {
+  struct frequency* freq = emalloc(sizeof(struct frequency));
+
+  freq->base = UNKNOWN_FREQ;
+  freq->max = get_max_freq_from_file(core);
+
+  return freq;
+}
+
+struct topology* get_topology_info(struct cpuInfo* cpu, struct cache* cach, uint32_t* midr_array, int socket_idx, int ncores) {
+  struct topology* topo = emalloc(sizeof(struct topology));
+  init_topology_struct(topo, cach);
+
+  int sockets_seen = 0;
+  int first_core_idx = 0;
+  int currrent_core_idx = 0;
+  int cores_in_socket = 0;
+
+  while(socket_idx + 1 > sockets_seen) {
+    if(midr_array[first_core_idx] == midr_array[currrent_core_idx] && currrent_core_idx < ncores) {
+      currrent_core_idx++;
+      cores_in_socket++;
+    }
+    else {
+      topo->total_cores = cores_in_socket;
+      cores_in_socket = 0;
+      first_core_idx = currrent_core_idx;
+      sockets_seen++;
+    }
+  }
+
+  return topo;
+}
+
+int64_t get_peak_performance(struct cpuInfo* cpu) {
+  struct cpuInfo* ptr = cpu;
+
+  //First check we have consistent data
+  for(int i=0; i < cpu->num_cpus; ptr = ptr->next_cpu, i++) {
+    if(get_freq(ptr->freq) == UNKNOWN_FREQ) {
+      return -1;
+    }
+  }
+
+  int64_t flops = 0;
+
+  ptr = cpu;
+  for(int i=0; i < cpu->num_cpus; ptr = ptr->next_cpu, i++) {
+    flops += ptr->topo->total_cores * (get_freq(ptr->freq) * 1000000);
+  }
+  if(cpu->feat->NEON) flops = flops * 4;
+
+  return flops;
+}
+
+bool cores_are_equal(int c1pos, int c2pos, uint32_t* midr_array, int32_t* freq_array) {
+  return midr_array[c1pos] == midr_array[c2pos] && freq_array[c1pos] == freq_array[c2pos];
+}
+
+uint32_t fill_ids_from_midr(uint32_t* midr_array, int32_t* freq_array, uint32_t* ids_array, int len) {
+  uint32_t latest_id = 0;
+  bool found;
+  ids_array[0] = latest_id;
+
+  for (int i = 1; i < len; i++) {
+    int j = 0;
+    found = false;
+
+    for (j = 0; j < len && !found; j++) {
+      if (i != j && cores_are_equal(i, j, midr_array, freq_array)) {
+        if(j > i) {
+          latest_id++;
+          ids_array[i] = latest_id;
+        }
+        else {
+          ids_array[i] = ids_array[j];
+        }
+        found = true;
+      }
+    }
+    if(!found) {
+      latest_id++;
+      ids_array[i] = latest_id;
+    }
+  }
+
+  return latest_id+1;
+}
+
+void init_cpu_info(struct cpuInfo* cpu) {
+  cpu->next_cpu = NULL;
+}
+
+// We assume all cpus share the same hardware
+// capabilities but I'm not sure it is always
+// true...
+// ARM32 https://elixir.bootlin.com/linux/latest/source/arch/arm/include/uapi/asm/hwcap.h
+// ARM64 https://elixir.bootlin.com/linux/latest/source/arch/arm64/include/uapi/asm/hwcap.h
+struct features* get_features_info() {
+  struct features* feat = emalloc(sizeof(struct features));
+  bool *ptr = &(feat->AES);
+  for(uint32_t i = 0; i < sizeof(struct features)/sizeof(bool); i++, ptr++) {
+    *ptr = false;
+  }
+
+  errno = 0;
+  long hwcaps = getauxval(AT_HWCAP);
+
+  if(errno == ENOENT) {
+    printWarn("Unable to retrieve AT_HWCAP using getauxval");
+  }
+#ifdef __aarch64__
+  else {
+    feat->AES = hwcaps & HWCAP_AES;
+    feat->CRC32 = hwcaps & HWCAP_CRC32;
+    feat->SHA1 = hwcaps & HWCAP_SHA1;
+    feat->SHA2 = hwcaps & HWCAP_SHA2;
+    feat->NEON = hwcaps & HWCAP_ASIMD;
+  }
+#else
+  else {
+    feat->NEON = hwcaps & HWCAP_NEON;
+  }
+
+  hwcaps = getauxval(AT_HWCAP2);
+  if(errno == ENOENT) {
+    printWarn("Unable to retrieve AT_HWCAP2 using getauxval");
+  }
+  else {
+    feat->AES = hwcaps & HWCAP2_AES;
+    feat->CRC32 = hwcaps & HWCAP2_CRC32;
+    feat->SHA1 = hwcaps & HWCAP2_SHA1;
+    feat->SHA2 = hwcaps & HWCAP2_SHA2;
+  }
+#endif
+
+  return feat;
+}
+
+struct cpuInfo* get_cpu_info() {
+  struct cpuInfo* cpu = emalloc(sizeof(struct cpuInfo));
+  init_cpu_info(cpu);
+
+  int ncores = get_ncores_from_cpuinfo();
+  bool success = false;
+  int32_t* freq_array = emalloc(sizeof(uint32_t) * ncores);
+  uint32_t* midr_array = emalloc(sizeof(uint32_t) * ncores);
+  uint32_t* ids_array = emalloc(sizeof(uint32_t) * ncores);
+
+  for(int i=0; i < ncores; i++) {
+    midr_array[i] = get_midr_from_cpuinfo(i, &success);
+
+    if(!success) {
+      printWarn("Unable to fetch MIDR for core %d. This is probably because the core is offline", i);
+      midr_array[i] = midr_array[0];
+    }
+
+    freq_array[i] = get_max_freq_from_file(i);
+    if(freq_array[i] == UNKNOWN_FREQ) {
+      printWarn("Unable to fetch max frequency for core %d. This is probably because the core is offline", i);
+      freq_array[i] = freq_array[0];
+    }
+  }
+  uint32_t sockets = fill_ids_from_midr(midr_array, freq_array, ids_array, ncores);
+
+  struct cpuInfo* ptr = cpu;
+  int midr_idx = 0;
+  int tmp_midr_idx = 0;
+  for(uint32_t i=0; i < sockets; i++) {
+    if(i > 0) {
+      ptr->next_cpu = emalloc(sizeof(struct cpuInfo));
+      ptr = ptr->next_cpu;
+      init_cpu_info(ptr);
+
+      tmp_midr_idx = midr_idx;
+      while(cores_are_equal(midr_idx, tmp_midr_idx, midr_array, freq_array)) tmp_midr_idx++;
+      midr_idx = tmp_midr_idx;
+    }
+
+    ptr->midr = midr_array[midr_idx];
+    ptr->arch = get_uarch_from_midr(ptr->midr, ptr);
+
+    ptr->feat = get_features_info();
+    ptr->freq = get_frequency_info(midr_idx);
+    ptr->cach = get_cache_info(ptr);
+    ptr->topo = get_topology_info(ptr, ptr->cach, midr_array, i, ncores);
+  }
+
+  cpu->num_cpus = sockets;
+  cpu->hv = emalloc(sizeof(struct hypervisor));
+  cpu->hv->present = false;
+  cpu->soc = get_soc();
+  cpu->peak_performance = get_peak_performance(cpu);
+
+  return cpu;
+}
+
+char* get_str_topology(struct cpuInfo* cpu, struct topology* topo, bool dual_socket) {
+  uint32_t size = 3+7+1;
+  char*  string = emalloc(sizeof(char)*size);
+  snprintf(string, size, "%d cores", topo->total_cores);
+
+  return string;
+}
+
+char* get_str_features(struct cpuInfo* cpu) {
+  struct features* feat = cpu->feat;
+  char* string = emalloc(sizeof(char) * 25);
+  uint32_t len = 0;
+
+  if(feat->NEON) {
+    strcat(string, "NEON,");
+    len += 5;
+  }
+  if(feat->SHA1) {
+    strcat(string, "SHA1,");
+    len += 5;
+  }
+  if(feat->SHA2) {
+    strcat(string, "SHA2,");
+    len += 5;
+  }
+  if(feat->AES) {
+    strcat(string, "AES,");
+    len += 4;
+  }
+  if(feat->CRC32) {
+    strcat(string, "CRC32,");
+    len += 6;
+  }
+
+  if(len > 0) {
+    string[len-1] = '\0';
+    return string;
+  }
+  else
+    return NULL;
+}
+
+void print_debug(struct cpuInfo* cpu) {
+  int ncores = get_ncores_from_cpuinfo();
+  bool success = false;
+
+  for(int i=0; i < ncores; i++) {
+    printf("[Core %d] ", i);
+    long freq = get_max_freq_from_file(i);
+    uint32_t midr = get_midr_from_cpuinfo(i, &success);
+    if(!success) {
+      printWarn("Unable to fetch MIDR for core %d. This is probably because the core is offline", i);
+      printf("0x%.8X ", get_midr_from_cpuinfo(0, &success));
+    }
+    else {
+      printf("0x%.8X ", midr);
+    }
+    if(freq == UNKNOWN_FREQ) {
+      printWarn("Unable to fetch max frequency for core %d. This is probably because the core is offline", i);
+      printf("%ld MHz\n", get_max_freq_from_file(0));
+    }
+    else {
+      printf("%ld MHz\n", freq);
+    }
+  }
+}
+
+void free_topo_struct(struct topology* topo) {
+  free(topo);
+}

src/arm/midr.h

@@ -0,0 +1,69 @@
+#ifndef __MIDR__
+#define __MIDR__
+
+#include "../common/cpu.h"
+
+struct cpuInfo* get_cpu_info();
+
+uint32_t get_nsockets(struct topology* topo);
+char* get_str_topology(struct cpuInfo* cpu, struct topology* topo, bool dual_socket);
+char* get_str_features(struct cpuInfo* cpu);
+
+void print_debug(struct cpuInfo* cpu);
+void free_topo_struct(struct topology* topo);
+
+// Code taken from cpuinfo (https://github.com/pytorch/cpuinfo/blob/master/src/arm/midr.h)
+#define CPUINFO_ARM_MIDR_IMPLEMENTER_MASK  UINT32_C(0xFF000000)
+#define CPUINFO_ARM_MIDR_VARIANT_MASK      UINT32_C(0x00F00000)
+#define CPUINFO_ARM_MIDR_ARCHITECTURE_MASK UINT32_C(0x000F0000)
+#define CPUINFO_ARM_MIDR_PART_MASK         UINT32_C(0x0000FFF0)
+#define CPUINFO_ARM_MIDR_REVISION_MASK     UINT32_C(0x0000000F)
+
+#define CPUINFO_ARM_MIDR_IMPLEMENTER_OFFSET  24
+#define CPUINFO_ARM_MIDR_VARIANT_OFFSET      20
+#define CPUINFO_ARM_MIDR_ARCHITECTURE_OFFSET 16
+#define CPUINFO_ARM_MIDR_PART_OFFSET          4
+#define CPUINFO_ARM_MIDR_REVISION_OFFSET      0
+
+inline static uint32_t midr_set_implementer(uint32_t midr, uint32_t implementer) {
+        return (midr & ~CPUINFO_ARM_MIDR_IMPLEMENTER_MASK) |
+                ((implementer << CPUINFO_ARM_MIDR_IMPLEMENTER_OFFSET) & CPUINFO_ARM_MIDR_IMPLEMENTER_MASK);
+}
+
+inline static uint32_t midr_set_variant(uint32_t midr, uint32_t variant) {
+        return (midr & ~CPUINFO_ARM_MIDR_VARIANT_MASK) |
+                ((variant << CPUINFO_ARM_MIDR_VARIANT_OFFSET) & CPUINFO_ARM_MIDR_VARIANT_MASK);
+}
+
+inline static uint32_t midr_set_architecture(uint32_t midr, uint32_t architecture) {
+        return (midr & ~CPUINFO_ARM_MIDR_ARCHITECTURE_MASK) |
+                ((architecture << CPUINFO_ARM_MIDR_ARCHITECTURE_OFFSET) & CPUINFO_ARM_MIDR_ARCHITECTURE_MASK);
+}
+
+inline static uint32_t midr_set_part(uint32_t midr, uint32_t part) {
+        return (midr & ~CPUINFO_ARM_MIDR_PART_MASK) |
+                ((part << CPUINFO_ARM_MIDR_PART_OFFSET) & CPUINFO_ARM_MIDR_PART_MASK);
+}
+
+inline static uint32_t midr_set_revision(uint32_t midr, uint32_t revision) {
+        return (midr & ~CPUINFO_ARM_MIDR_REVISION_MASK) |
+                ((revision << CPUINFO_ARM_MIDR_REVISION_OFFSET) & CPUINFO_ARM_MIDR_REVISION_MASK);
+}
+
+inline static uint32_t midr_get_variant(uint32_t midr) {
+	return (midr & CPUINFO_ARM_MIDR_VARIANT_MASK) >> CPUINFO_ARM_MIDR_VARIANT_OFFSET;
+}
+
+inline static uint32_t midr_get_implementer(uint32_t midr) {
+	return (midr & CPUINFO_ARM_MIDR_IMPLEMENTER_MASK) >> CPUINFO_ARM_MIDR_IMPLEMENTER_OFFSET;
+}
+
+inline static uint32_t midr_get_part(uint32_t midr) {
+	return (midr & CPUINFO_ARM_MIDR_PART_MASK) >> CPUINFO_ARM_MIDR_PART_OFFSET;
+}
+
+inline static uint32_t midr_get_revision(uint32_t midr) {
+	return (midr & CPUINFO_ARM_MIDR_REVISION_MASK) >> CPUINFO_ARM_MIDR_REVISION_OFFSET;
+}
+
+#endif

src/arm/soc.c

@@ -0,0 +1,646 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <ctype.h>
+
+#include "soc.h"
+#include "socs.h"
+#include "udev.h"
+#include "../common/global.h"
+
+#define min(a,b) (((a)<(b))?(a):(b))
+#define ARRAY_SIZE(arr)     (sizeof(arr) / sizeof((arr)[0]))
+
+static char* soc_trademark_string[] = {
+  [SOC_VENDOR_SNAPDRAGON] = "Snapdragon ",
+  [SOC_VENDOR_MEDIATEK]   = "MediaTek ",
+  [SOC_VENDOR_EXYNOS]     = "Exynos ",
+  [SOC_VENDOR_KIRIN]      = "Kirin ",
+  [SOC_VENDOR_BROADCOM]   = "Broadcom BCM",
+};
+
+static char* soc_rpi_string[] = {
+  "BCM2835",
+  "BCM2836",
+  "BCM2837",
+  "BCM2711"
+};
+
+void fill_soc(struct system_on_chip* soc, char* soc_name, SOC soc_model, int32_t process) {
+  soc->soc_model = soc_model;
+  soc->soc_vendor = get_soc_vendor_from_soc(soc_model);
+  soc->process = process;
+  int len = strlen(soc_name) + strlen(soc_trademark_string[soc->soc_vendor]) + 1;
+  soc->soc_name = emalloc(sizeof(char) * len);
+  memset(soc->soc_name, 0, sizeof(char) * len);
+  sprintf(soc->soc_name, "%s%s", soc_trademark_string[soc->soc_vendor], soc_name);
+}
+
+bool match_soc(struct system_on_chip* soc, char* raw_name, char* expected_name, char* soc_name, SOC soc_model, int32_t process) {
+  if(strlen(raw_name) > strlen(expected_name))
+    return false;
+
+  int len = strlen(raw_name);
+  if(strncmp(raw_name, expected_name, len) != 0) {
+    return false;
+  }
+  else {
+    fill_soc(soc, soc_name, soc_model, process);
+    return true;
+  }
+}
+
+char* toupperstr(char* str) {
+  int len = strlen(str) + 1;
+  char* ret = emalloc(sizeof(char) * len);
+  memset(ret, 0, sizeof(char) * len);
+
+  for(int i=0; i < len; i++) {
+    ret[i] = toupper((unsigned char) str[i]);
+  }
+
+  return ret;
+}
+
+#define SOC_START if (false) {}
+#define SOC_EQ(raw_name, expected_name, soc_name, soc_model, soc, process) \
+   else if (match_soc(soc, raw_name, expected_name, soc_name, soc_model, process)) return true;
+#define SOC_END else { return false; }
+// Exynos special define
+#define SOC_EXY_EQ(raw_name, tmpsoc, soc_name, soc_model, soc, process)             \
+   sprintf(tmpsoc, "exynos%s", soc_name);                                           \
+   if (match_soc(soc, raw_name, tmpsoc, soc_name, soc_model, process)) return true; \
+   sprintf(tmpsoc, "universal%s", soc_name);                                        \
+   if (match_soc(soc, raw_name, tmpsoc, soc_name, soc_model, process)) return true;
+
+// https://en.wikipedia.org/wiki/Raspberry_Pi
+// http://phonedb.net/index.php?m=processor&id=562&c=broadcom_bcm21663
+// https://hwbot.org/hardware/processors#key=bcmxxx
+bool match_broadcom(char* soc_name, struct system_on_chip* soc) {
+  char* tmp;
+
+  if((tmp = strstr(soc_name, "BCM")) == NULL)
+    return false;
+
+  SOC_START
+  SOC_EQ(tmp, "BCM2835",              "2835",              SOC_BCM_2835,   soc, 65)
+  SOC_EQ(tmp, "BCM2836",              "2836",              SOC_BCM_2836,   soc, 40)
+  SOC_EQ(tmp, "BCM2837",              "2837",              SOC_BCM_2837,   soc, 40)
+  SOC_EQ(tmp, "BCM2837B0",            "2837B0",            SOC_BCM_2837B0, soc, 40)
+  SOC_EQ(tmp, "BCM2711",              "2711",              SOC_BCM_2711,   soc, 28)
+  SOC_EQ(tmp, "BCM21553",             "21553",             SOC_BCM_21553,  soc, 65)
+  SOC_EQ(tmp, "BCM21553-Thunderbird", "21553 Thunderbird", SOC_BCM_21553T, soc, 65)
+  SOC_EQ(tmp, "BCM21663",             "21663",             SOC_BCM_21663,  soc, 40)
+  SOC_EQ(tmp, "BCM21664",             "21664",             SOC_BCM_21664,  soc, 40)
+  SOC_EQ(tmp, "BCM28155",             "28155",             SOC_BCM_28155,  soc, 40)
+  SOC_EQ(tmp, "BCM23550",             "23550",             SOC_BCM_23550,  soc, 40)
+  SOC_EQ(tmp, "BCM28145",             "28145",             SOC_BCM_28145,  soc, 40)
+  SOC_EQ(tmp, "BCM2157",              "2157",              SOC_BCM_2157,   soc, 65)
+  SOC_EQ(tmp, "BCM21654",             "21654",             SOC_BCM_21654,  soc, 40)
+  SOC_END
+}
+
+// https://www.techinsights.com/
+// https://datasheetspdf.com/pdf-file/1316605/HiSilicon/Hi3660/1
+bool match_hisilicon(char* soc_name, struct system_on_chip* soc) {
+  char* tmp;
+
+  if((tmp = strstr(soc_name, "Hi")) == NULL)
+    return false;
+
+  SOC_START
+  SOC_EQ(tmp, "Hi3620GFC",  "K3V2",  SOC_HISILICON_3620, soc, 40)
+  //SOC_EQ(tmp, "?",        "K3V2E", SOC_KIRIN, soc,  ?)
+  //SOC_EQ(tmp, "?",        "620",   SOC_KIRIN, soc, 28)
+  //SOC_EQ(tmp, "?",        "650",   SOC_KIRIN, soc, 16)
+  //SOC_EQ(tmp, "?",        "655",   SOC_KIRIN, soc, 16)
+  //SOC_EQ(tmp, "?",        "658",   SOC_KIRIN, soc, 16)
+  //SOC_EQ(tmp, "?",        "659",   SOC_KIRIN, soc, 16)
+  //SOC_EQ(tmp, "?",        "710",   SOC_KIRIN, soc, 12)
+  //SOC_EQ(tmp, "?",        "710A",  SOC_KIRIN, soc, 12)
+  //SOC_EQ(tmp, "?",        "710F",  SOC_KIRIN, soc, 12)
+  //SOC_EQ(tmp, "?",        "810",   SOC_KIRIN, soc,  7)
+  //SOC_EQ(tmp, "?",        "820",   SOC_KIRIN, soc,  7)
+  //SOC_EQ(tmp, "?",        "9000",  SOC_KIRIN, soc,  5)
+  //SOC_EQ(tmp, "?",        "9000E", SOC_KIRIN, soc,  5)
+  //SOC_EQ(tmp, "?",        "910",   SOC_KIRIN, soc, 28)
+  //SOC_EQ(tmp, "?",        "910T",  SOC_KIRIN, soc, 28)
+  SOC_EQ(tmp, "Hi3630",     "920",   SOC_HISILICON_3630, soc, 28)
+  //SOC_EQ(tmp, "?",        "925",   SOC_KIRIN, soc, 28)
+  //SOC_EQ(tmp, "?",        "930",   SOC_KIRIN, soc, ?)
+  //SOC_EQ(tmp, "?",        "935",   SOC_KIRIN, soc, ?)
+  SOC_EQ(tmp, "Hi3650",     "950",   SOC_HISILICON_3650, soc, 16)
+  //SOC_EQ(tmp, "?",        "955",   SOC_KIRIN, soc, ?)
+  SOC_EQ(tmp, "Hi3660",     "960",   SOC_HISILICON_3660, soc, 16)
+  //SOC_EQ(tmp, "?",        "960S",  SOC_KIRIN, soc, 16)
+  SOC_EQ(tmp, "Hi3670",     "970",   SOC_HISILICON_3670, soc, 10)
+  SOC_EQ(tmp, "Hi3680",     "980",   SOC_HISILICON_3680, soc,  7)
+  //SOC_EQ(tmp, "?",        "985",   SOC_KIRIN, soc,  7)
+  SOC_EQ(tmp, "Hi3690",     "990",   SOC_HISILICON_3690, soc,  7)
+  SOC_END
+}
+
+bool match_exynos(char* soc_name, struct system_on_chip* soc) {
+  char* tmp;
+
+  if((tmp = strstr(soc_name, "universal")) != NULL);
+  else if((tmp = strstr(soc_name, "exynos")) != NULL);
+  else return false;
+
+  // Because exynos are recently using "exynosXXXX" instead
+  // of "universalXXXX" as codenames, SOC_EXY_EQ will check for
+  // both cases, since it seems that there are some SoCs that
+  // can appear with both codenames
+
+  // Used by SOC_EXY_EQ
+  char tmpsoc[14];
+
+  SOC_START
+  SOC_EXY_EQ(tmp, tmpsoc, "3475", SOC_EXYNOS_3475, soc, 28)
+  SOC_EXY_EQ(tmp, tmpsoc, "4210", SOC_EXYNOS_4210, soc, 45)
+  SOC_EXY_EQ(tmp, tmpsoc, "4212", SOC_EXYNOS_4212, soc, 32)
+  SOC_EXY_EQ(tmp, tmpsoc, "4412", SOC_EXYNOS_4412, soc, 32)
+  SOC_EXY_EQ(tmp, tmpsoc, "5250", SOC_EXYNOS_5250, soc, 32)
+  SOC_EXY_EQ(tmp, tmpsoc, "5410", SOC_EXYNOS_5410, soc, 28)
+  SOC_EXY_EQ(tmp, tmpsoc, "5420", SOC_EXYNOS_5420, soc, 28)
+  SOC_EXY_EQ(tmp, tmpsoc, "5422", SOC_EXYNOS_5422, soc, 28)
+  SOC_EXY_EQ(tmp, tmpsoc, "5430", SOC_EXYNOS_5430, soc, 20)
+  SOC_EXY_EQ(tmp, tmpsoc, "5433", SOC_EXYNOS_5433, soc, 20)
+  SOC_EXY_EQ(tmp, tmpsoc, "5260", SOC_EXYNOS_5260, soc, 28)
+  SOC_EXY_EQ(tmp, tmpsoc, "7270", SOC_EXYNOS_7270, soc, 14)
+  SOC_EXY_EQ(tmp, tmpsoc, "7420", SOC_EXYNOS_7420, soc, 14)
+  SOC_EXY_EQ(tmp, tmpsoc, "7570", SOC_EXYNOS_7570, soc, 14)
+  SOC_EXY_EQ(tmp, tmpsoc, "7570", SOC_EXYNOS_7570, soc, 14)
+  SOC_EXY_EQ(tmp, tmpsoc, "7870", SOC_EXYNOS_7870, soc, 14)
+  SOC_EXY_EQ(tmp, tmpsoc, "7870", SOC_EXYNOS_7870, soc, 14)
+  SOC_EXY_EQ(tmp, tmpsoc, "7872", SOC_EXYNOS_7872, soc, 14)
+  SOC_EXY_EQ(tmp, tmpsoc, "7880", SOC_EXYNOS_7880, soc, 14)
+  SOC_EXY_EQ(tmp, tmpsoc, "7884", SOC_EXYNOS_7884, soc, 14)
+  SOC_EXY_EQ(tmp, tmpsoc, "7885", SOC_EXYNOS_7885, soc, 14)
+  SOC_EXY_EQ(tmp, tmpsoc, "7904", SOC_EXYNOS_7904, soc, 14)
+  SOC_EXY_EQ(tmp, tmpsoc, "8890", SOC_EXYNOS_8890, soc, 14)
+  SOC_EXY_EQ(tmp, tmpsoc, "8895", SOC_EXYNOS_8895, soc, 10)
+  SOC_EXY_EQ(tmp, tmpsoc, "9110", SOC_EXYNOS_9110, soc, 14)
+  SOC_EXY_EQ(tmp, tmpsoc, "9609", SOC_EXYNOS_9609, soc, 10)
+  SOC_EXY_EQ(tmp, tmpsoc, "9610", SOC_EXYNOS_9610, soc, 10)
+  SOC_EXY_EQ(tmp, tmpsoc, "9611", SOC_EXYNOS_9611, soc, 10)
+  SOC_EXY_EQ(tmp, tmpsoc, "9810", SOC_EXYNOS_9810, soc, 10)
+  SOC_EXY_EQ(tmp, tmpsoc, "9820", SOC_EXYNOS_9820, soc,  8)
+  SOC_EXY_EQ(tmp, tmpsoc, "9825", SOC_EXYNOS_9825, soc,  7)
+  SOC_EXY_EQ(tmp, tmpsoc, "1080", SOC_EXYNOS_1080, soc,  5)
+  SOC_EXY_EQ(tmp, tmpsoc, "990",  SOC_EXYNOS_990,  soc,  7)
+  SOC_EXY_EQ(tmp, tmpsoc, "980",  SOC_EXYNOS_980,  soc,  8)
+  SOC_EXY_EQ(tmp, tmpsoc, "880",  SOC_EXYNOS_880,  soc,  8)
+  SOC_END
+}
+
+bool match_mediatek(char* soc_name, struct system_on_chip* soc) {
+  char* tmp;
+
+  if((tmp = strstr(soc_name, "MT")) == NULL)
+    return false;
+
+  SOC_START
+  // Dimensity //
+  SOC_EQ(tmp, "MT6889",   "Dimensity 1000",  SOC_MTK_MT6889,   soc, 7)
+  SOC_EQ(tmp, "MT6885Z",  "Dimensity 1000L", SOC_MTK_MT6885Z,  soc, 7)
+  //SOC_EQ(tmp, "?",      "Dimensity 700",   SOC_MTK_,         soc, 7)
+  SOC_EQ(tmp, "MT6853",   "Dimensity 720",   SOC_MTK_MT6853,   soc, 7)
+  SOC_EQ(tmp, "MT6873",   "Dimensity 800",   SOC_MTK_MT6873,   soc, 7)
+  SOC_EQ(tmp, "MT6875",   "Dimensity 820",   SOC_MTK_MT6875,   soc, 7)
+  // Helio //
+  SOC_EQ(tmp, "MT6761D",  "Helio A20",       SOC_MTK_MT6761D,  soc, 12)
+  SOC_EQ(tmp, "MT6761",   "Helio A22",       SOC_MTK_MT6761,   soc, 12)
+  SOC_EQ(tmp, "MT6762D",  "Helio A25",       SOC_MTK_MT6762D,  soc, 12)
+  //SOC_EQ(tmp, "?",      "Helio G25",       SOC_MTK_,         soc, 12)
+  //SOC_EQ(tmp, "?",      "Helio G35",       SOC_MTK_,         soc, 12)
+  //SOC_EQ(tmp, "?",      "Helio G70",       SOC_MTK_,         soc, 12)
+  //SOC_EQ(tmp, "?",      "Helio G80",       SOC_MTK_,         soc, 12)
+  //SOC_EQ(tmp, "?",      "Helio G90",       SOC_MTK_,         soc, 12)
+  //SOC_EQ(tmp, "?",      "Helio G90T",      SOC_MTK_,         soc, 12)
+  //SOC_EQ(tmp, "?",      "Helio G95",       SOC_MTK_,         soc, 12)
+  SOC_EQ(tmp, "MT6755",   "Helio P10",       SOC_MTK_MT6755M,  soc, 28)
+  SOC_EQ(tmp, "MT6755M",  "Helio P10 M",     SOC_MTK_MT6755M,  soc, 28)
+  SOC_EQ(tmp, "MT6755T",  "Helio P15",       SOC_MTK_MT6755T,  soc, 28)
+  SOC_EQ(tmp, "MT6757",   "Helio P20",       SOC_MTK_MT6757,   soc, 16)
+  SOC_EQ(tmp, "MT6762",   "Helio P22",       SOC_MTK_MT6762,   soc, 12)
+  SOC_EQ(tmp, "MT6763V",  "Helio P23",       SOC_MTK_MT6763V,  soc, 16)
+  SOC_EQ(tmp, "MT6763T",  "Helio P23",       SOC_MTK_MT6763T,  soc, 16)
+  SOC_EQ(tmp, "MT6757CD", "Helio P25",       SOC_MTK_MT6757CD, soc, 16)
+  SOC_EQ(tmp, "MT6758",   "Helio P30",       SOC_MTK_MT6758,   soc, 16)
+  SOC_EQ(tmp, "MT6765",   "Helio P35",       SOC_MTK_MT6765,   soc, 12)
+  SOC_EQ(tmp, "MT6771",   "Helio P60",       SOC_MTK_MT6771,   soc, 12)
+  SOC_EQ(tmp, "MT6768",   "Helio P65",       SOC_MTK_MT6768,   soc, 12)
+  SOC_EQ(tmp, "MT6771T",  "Helio P70",       SOC_MTK_MT6771,   soc, 12)
+  SOC_EQ(tmp, "MT6771V",  "Helio P70",       SOC_MTK_MT6771,   soc, 12)
+  SOC_EQ(tmp, "MT6779",   "Helio P90",       SOC_MTK_MT6779,   soc, 12)
+  //SOC_EQ(tmp, "?",      "Helio P95",       SOC_MTK_,         soc, 12)
+  SOC_EQ(tmp, "MT6795",   "Helio X10",       SOC_MTK_MT6795,   soc, 28)
+  SOC_EQ(tmp, "MT6795T",  "Helio X10 T",     SOC_MTK_MT6795,   soc, 28)
+  SOC_EQ(tmp, "MT6797",   "Helio X20",       SOC_MTK_MT6797,   soc, 20)
+  SOC_EQ(tmp, "MT6797M",  "Helio X20 M",     SOC_MTK_MT6797,   soc, 20)
+  SOC_EQ(tmp, "MT6797D",  "Helio X23",       SOC_MTK_MT6797,   soc, 20)
+  SOC_EQ(tmp, "MT6797T",  "Helio X25",       SOC_MTK_MT6797T,  soc, 20)
+  SOC_EQ(tmp, "MT6797X",  "Helio X27",       SOC_MTK_MT6797X,  soc, 20)
+  SOC_EQ(tmp, "MT6799",   "Helio X30",       SOC_MTK_MT6799,   soc, 10)
+  // MT XXXX //
+  SOC_EQ(tmp, "MT6515",   "MT6515",          SOC_MTK_MT6515,   soc, 40)
+  SOC_EQ(tmp, "MT6516",   "MT6516",          SOC_MTK_MT6516,   soc, 65)
+  SOC_EQ(tmp, "MT6517",   "MT6517",          SOC_MTK_MT6517,   soc, 40)
+  SOC_EQ(tmp, "MT6572",   "MT6572",          SOC_MTK_MT6572,   soc, 28)
+  SOC_EQ(tmp, "MT6572M",  "MT6572M",         SOC_MTK_MT6572M,  soc, 28)
+  SOC_EQ(tmp, "MT6573",   "MT6573",          SOC_MTK_MT6573,   soc, 65)
+  SOC_EQ(tmp, "MT6575",   "MT6575",          SOC_MTK_MT6575,   soc, 40)
+  SOC_EQ(tmp, "MT6577",   "MT6577",          SOC_MTK_MT6577,   soc, 40)
+  SOC_EQ(tmp, "MT6577T",  "MT6577T",         SOC_MTK_MT6577T,  soc, 40)
+  SOC_EQ(tmp, "MT6580",   "MT6580",          SOC_MTK_MT6580,   soc, 28)
+  SOC_EQ(tmp, "MT6582",   "MT6582",          SOC_MTK_MT6582,   soc, 28)
+  SOC_EQ(tmp, "MT6582M",  "MT6582M",         SOC_MTK_MT6582M,  soc, 28)
+  SOC_EQ(tmp, "MT6589",   "MT6589",          SOC_MTK_MT6589,   soc, 28)
+  SOC_EQ(tmp, "MT6589T",  "MT6589T",         SOC_MTK_MT6589T,  soc, 28)
+  SOC_EQ(tmp, "MT6592",   "MT6592",          SOC_MTK_MT6592,   soc, 28)
+  SOC_EQ(tmp, "MT6595",   "MT6595",          SOC_MTK_MT6595,   soc, 28)
+  SOC_EQ(tmp, "MT6732",   "MT6732",          SOC_MTK_MT6732,   soc, 28)
+  SOC_EQ(tmp, "MT6735",   "MT6735",          SOC_MTK_MT6735,   soc, 28)
+  SOC_EQ(tmp, "MT6735M",  "MT6735M",         SOC_MTK_MT6735M,  soc, 28)
+  SOC_EQ(tmp, "MT6735P",  "MT6735P",         SOC_MTK_MT6735P,  soc, 28)
+  SOC_EQ(tmp, "MT6737",   "MT6737",          SOC_MTK_MT6737,   soc, 28)
+  SOC_EQ(tmp, "MT6737M",  "MT6737M",         SOC_MTK_MT6737M,  soc, 28)
+  SOC_EQ(tmp, "MT6737T",  "MT6737T",         SOC_MTK_MT6737T,  soc, 28)
+  SOC_EQ(tmp, "MT6739",   "MT6739",          SOC_MTK_MT6739,   soc, 28)
+  SOC_EQ(tmp, "MT6750",   "MT6750",          SOC_MTK_MT6750,   soc, 28)
+  SOC_EQ(tmp, "MT6750S",  "MT6750S",         SOC_MTK_MT6750S,  soc, 28)
+  SOC_EQ(tmp, "MT6750T",  "MT6750T",         SOC_MTK_MT6750T,  soc, 28)
+  SOC_EQ(tmp, "MT6752",   "MT6752",          SOC_MTK_MT6752,   soc, 28)
+  SOC_EQ(tmp, "MT6753",   "MT6753",          SOC_MTK_MT6753,   soc, 28)
+  SOC_EQ(tmp, "MT6850",   "MT6850",          SOC_MTK_MT6850,   soc, 28)
+  SOC_EQ(tmp, "MT8121",   "MT8121",          SOC_MTK_MT8121,   soc, 40)
+  SOC_EQ(tmp, "MT8125",   "MT8125",          SOC_MTK_MT8125,   soc, 40)
+  SOC_EQ(tmp, "MT8127",   "MT8127",          SOC_MTK_MT8127,   soc, 32)
+  SOC_EQ(tmp, "MT8135",   "MT8135",          SOC_MTK_MT8135,   soc, 28)
+  SOC_EQ(tmp, "MT8163A",  "MT8163A",         SOC_MTK_MT8163A,  soc, 28)
+  SOC_EQ(tmp, "MT8163B",  "MT8163B",         SOC_MTK_MT8163B,  soc, 28)
+  SOC_EQ(tmp, "MT8167B",  "MT8167B",         SOC_MTK_MT8167B,  soc, 28)
+  SOC_EQ(tmp, "MT8173",   "MT8173",          SOC_MTK_MT8173,   soc, 28)
+  SOC_EQ(tmp, "MT8176",   "MT8176",          SOC_MTK_MT8176,   soc, 28)
+  SOC_EQ(tmp, "MT8321",   "MT8321",          SOC_MTK_MT8321,   soc, 28)
+  SOC_EQ(tmp, "MT8382",   "MT8382",          SOC_MTK_MT8382,   soc, 28)
+  SOC_EQ(tmp, "MT8581",   "MT8581",          SOC_MTK_MT8581,   soc, 28)
+  SOC_EQ(tmp, "MT8735",   "MT8735",          SOC_MTK_MT8735,   soc, 28)
+  SOC_EQ(tmp, "MT8765B",  "MT8765B",         SOC_MTK_MT8765B,  soc, 28)
+  SOC_EQ(tmp, "MT8783",   "MT8783",          SOC_MTK_MT8783,   soc, 28)
+  SOC_END
+}
+
+/*
+ * APQ: Application Processor Qualcomm
+ * MSM: Mobile Station Modem
+ * In a APQXXXX or MSMXXXX, the second digit represents:
+ * *------------------*
+ * | Value | Meaning  |
+ * *------------------*
+ * |     0 | No modem |
+ * |     2 | HPSA+    |
+ * |     6 | CDMA     |
+ * |     9 | LTE      |
+ * *------------------*
+ * Ref: https://www.tomshardware.com/reviews/snapdragon-801-performance-xperia-z2,3777-2.html
+ *      TWO-HEADED SNAPDRAGON TAKES FLIGHT By Linley Gwennap
+ *
+ * If Qualcomm official website reports the SoC name without the initial two or three SKU name,
+ * we assume APQ if second number is 0, or MSM if second number is different than 0
+ *
+ * All SoC names here have been retrieved from official Qualcomm resources. However, Linux kernel
+ * and Android may report the SoC with slightly different. Therefore, this function needs some
+ * rework (e.g, debug with http://specdevice.com/unmoderated.php?lang=en)
+ */
+bool match_qualcomm(char* soc_name, struct system_on_chip* soc) {
+  char* tmp;
+  char* soc_name_upper = toupperstr(soc_name);
+
+  if((tmp = strstr(soc_name_upper, "MSM")) != NULL);
+  else if((tmp = strstr(soc_name_upper, "SDM")) != NULL);
+  else if((tmp = strstr(soc_name_upper, "APQ")) != NULL);
+  else if((tmp = strstr(soc_name_upper, "SM")) != NULL);
+  else if((tmp = strstr(soc_name_upper, "QM")) != NULL);
+  else if((tmp = strstr(soc_name_upper, "QSD")) != NULL);
+  else return false;
+
+  SOC_START
+  // Snapdragon S1 //
+  SOC_EQ(tmp, "QSD8650",        "S1",        SOC_SNAPD_QSD8650,        soc, 65)
+  SOC_EQ(tmp, "QSD8250",        "S1",        SOC_SNAPD_QSD8250,        soc, 65)
+  SOC_EQ(tmp, "MSM7627",        "S1",        SOC_SNAPD_MSM7627,        soc, 65)
+  SOC_EQ(tmp, "MSM7227",        "S1",        SOC_SNAPD_MSM7227,        soc, 65)
+  SOC_EQ(tmp, "MSM7627A",       "S1",        SOC_SNAPD_MSM7627A,       soc, 45)
+  SOC_EQ(tmp, "MSM7227A",       "S1",        SOC_SNAPD_MSM7227A,       soc, 45)
+  SOC_EQ(tmp, "MSM7625",        "S1",        SOC_SNAPD_MSM7625,        soc, 65)
+  SOC_EQ(tmp, "MSM7225",        "S1",        SOC_SNAPD_MSM7225,        soc, 65)
+  SOC_EQ(tmp, "MSM7625A",       "S1",        SOC_SNAPD_MSM7625A,       soc, 45)
+  SOC_EQ(tmp, "MSM7225A",       "S1",        SOC_SNAPD_MSM7225A,       soc, 45)
+  // Snapdragon S2 //
+  SOC_EQ(tmp, "MSM8655",        "S2",        SOC_SNAPD_MSM8655,        soc, 45)
+  SOC_EQ(tmp, "MSM8255",        "S2",        SOC_SNAPD_MSM8255,        soc, 45)
+  SOC_EQ(tmp, "APQ8055",        "S2",        SOC_SNAPD_APQ8055,        soc, 45)
+  SOC_EQ(tmp, "MSM7630",        "S2",        SOC_SNAPD_MSM7630,        soc, 45)
+  SOC_EQ(tmp, "MSM7230",        "S2",        SOC_SNAPD_MSM7230,        soc, 45)
+  // Snapdragon S3 //
+  SOC_EQ(tmp, "MSM8660",        "S3",        SOC_SNAPD_MSM8660,        soc, 45)
+  SOC_EQ(tmp, "MSM8260",        "S3",        SOC_SNAPD_MSM8260,        soc, 45)
+  SOC_EQ(tmp, "APQ8060",        "S3",        SOC_SNAPD_APQ8060,        soc, 45)
+  // Snapdragon S4 //
+  SOC_EQ(tmp, "MSM8225",        "S4 Play",   SOC_SNAPD_MSM8225,        soc, 45)
+  SOC_EQ(tmp, "MSM8625",        "S4 Play",   SOC_SNAPD_MSM8625,        soc, 45)
+  SOC_EQ(tmp, "APQ8060A",       "S4 Plus",   SOC_SNAPD_APQ8060A,       soc, 28)
+  SOC_EQ(tmp, "MSM8960",        "S4 Plus",   SOC_SNAPD_MSM8960,        soc, 28)
+  SOC_EQ(tmp, "MSM8260A",       "S4 Plus",   SOC_SNAPD_MSM8260A,       soc, 28)
+  SOC_EQ(tmp, "MSM8627",        "S4 Plus",   SOC_SNAPD_MSM8627,        soc, 28)
+  SOC_EQ(tmp, "MSM8227",        "S4 Plus",   SOC_SNAPD_MSM8227,        soc, 28)
+  SOC_EQ(tmp, "APQ8064",        "S4 Pro",    SOC_SNAPD_APQ8064,        soc, 28)
+  SOC_EQ(tmp, "MSM8960T",       "S4 Pro",    SOC_SNAPD_MSM8960T,       soc, 28)
+  // Snapdragon 2XX //
+  SOC_EQ(tmp, "MSM8110",        "200",       SOC_SNAPD_MSM8110,        soc, 28)
+  SOC_EQ(tmp, "MSM8210",        "200",       SOC_SNAPD_MSM8210,        soc, 28)
+  SOC_EQ(tmp, "MSM8610",        "200",       SOC_SNAPD_MSM8610,        soc, 28)
+  SOC_EQ(tmp, "MSM8112",        "200",       SOC_SNAPD_MSM8112,        soc, 28)
+  SOC_EQ(tmp, "MSM8212",        "200",       SOC_SNAPD_MSM8212,        soc, 28)
+  SOC_EQ(tmp, "MSM8612",        "200",       SOC_SNAPD_MSM8612,        soc, 28)
+  SOC_EQ(tmp, "MSM8225Q",       "200",       SOC_SNAPD_MSM8225Q,       soc, 45)
+  SOC_EQ(tmp, "MSM8625Q",       "200",       SOC_SNAPD_MSM8625Q,       soc, 45)
+  SOC_EQ(tmp, "MSM8208",        "208",       SOC_SNAPD_MSM8208,        soc, 28)
+  SOC_EQ(tmp, "MSM8905",        "205",       SOC_SNAPD_MSM8905,        soc, 28)
+  SOC_EQ(tmp, "MSM8909",        "210 / 212", SOC_SNAPD_MSM8909,        soc, 28) // In the future, we can differenciate them using frequency
+  SOC_EQ(tmp, "QM215",          "215",       SOC_SNAPD_QM215,          soc, 28)
+  // Snapdragon 4XX //
+  SOC_EQ(tmp, "APQ8028",        "400",       SOC_SNAPD_APQ8028,        soc, 28)
+  SOC_EQ(tmp, "MSM8228",        "400",       SOC_SNAPD_MSM8228,        soc, 28)
+  SOC_EQ(tmp, "MSM8628",        "400",       SOC_SNAPD_MSM8628,        soc, 28)
+  SOC_EQ(tmp, "MSM8928",        "400",       SOC_SNAPD_MSM8928,        soc, 28)
+  SOC_EQ(tmp, "MSM8926",        "400",       SOC_SNAPD_MSM8926,        soc, 28)
+  SOC_EQ(tmp, "APQ8030AB",      "400",       SOC_SNAPD_APQ8030AB,      soc, 28)
+  SOC_EQ(tmp, "MSM8226",        "400",       SOC_SNAPD_MSM8226,        soc, 28)
+  SOC_EQ(tmp, "MSM8230AB",      "400",       SOC_SNAPD_MSM8230AB,      soc, 28)
+  SOC_EQ(tmp, "MSM8626",        "400",       SOC_SNAPD_MSM8626,        soc, 28)
+  SOC_EQ(tmp, "MSM8630",        "400",       SOC_SNAPD_MSM8630,        soc, 28)
+  SOC_EQ(tmp, "MSM8630AB",      "400",       SOC_SNAPD_MSM8630AB,      soc, 28)
+  SOC_EQ(tmp, "MSM8930",        "400",       SOC_SNAPD_MSM8930,        soc, 28)
+  SOC_EQ(tmp, "MSM8930AB",      "400",       SOC_SNAPD_MSM8930AB,      soc, 28)
+  SOC_EQ(tmp, "MSM8916",        "410 / 412", SOC_SNAPD_MSM8916,        soc, 28)
+  SOC_EQ(tmp, "MSM8929",        "415",       SOC_SNAPD_MSM8929,        soc, 28)
+  SOC_EQ(tmp, "MSM8917",        "425",       SOC_SNAPD_MSM8917,        soc, 28)
+  SOC_EQ(tmp, "MSM8920",        "427",       SOC_SNAPD_MSM8920,        soc, 28)
+  SOC_EQ(tmp, "SDM429",         "429",       SOC_SNAPD_SDM429,         soc, 12)
+  SOC_EQ(tmp, "MSM8937",        "430",       SOC_SNAPD_MSM8937,        soc, 28)
+  SOC_EQ(tmp, "MSM8940",        "435",       SOC_SNAPD_MSM8940,        soc, 28)
+  SOC_EQ(tmp, "SDM439",         "439",       SOC_SNAPD_SDM439,         soc, 12)
+  SOC_EQ(tmp, "SDM450",         "450",       SOC_SNAPD_SDM450,         soc, 14)
+  SOC_EQ(tmp, "SM4250-AA",      "460",       SOC_SNAPD_SM4250_AA,      soc, 11)
+  // Snapdragon 6XX //
+  SOC_EQ(tmp, "APQ8064T",       "600",       SOC_SNAPD_APQ8064T,       soc, 28)
+  SOC_EQ(tmp, "APQ8064M",       "600",       SOC_SNAPD_APQ8064M,       soc, 28)
+  SOC_EQ(tmp, "MSM8936",        "610",       SOC_SNAPD_MSM8936,        soc, 28)
+  SOC_EQ(tmp, "MSM8939",        "615 / 616", SOC_SNAPD_MSM8939,        soc, 28)
+  SOC_EQ(tmp, "MSM8952",        "617",       SOC_SNAPD_MSM8952,        soc, 28)
+  SOC_EQ(tmp, "MSM8953",        "625",       SOC_SNAPD_MSM8953,        soc, 14)
+  SOC_EQ(tmp, "MSM8953 PRO",    "626",       SOC_SNAPD_MSM8953_PRO,    soc, 14)
+  SOC_EQ(tmp, "SDM630",         "630",       SOC_SNAPD_SDM630,         soc, 14)
+  SOC_EQ(tmp, "SDM632",         "632",       SOC_SNAPD_SDM632,         soc, 14)
+  SOC_EQ(tmp, "SDM636",         "636",       SOC_SNAPD_SDM636,         soc, 14)
+  SOC_EQ(tmp, "MSM8956",        "650",       SOC_SNAPD_MSM8956,        soc, 28)
+  SOC_EQ(tmp, "MSM8976",        "652",       SOC_SNAPD_MSM8976,        soc, 28)
+  SOC_EQ(tmp, "MSM8976 PRO",    "653",       SOC_SNAPD_MSM8976_PRO,    soc, 28)
+  SOC_EQ(tmp, "SDM660",         "660",       SOC_SNAPD_SDM660,         soc, 14)
+  SOC_EQ(tmp, "SM6115",         "662",       SOC_SNAPD_SM6115,         soc, 11)
+  SOC_EQ(tmp, "SM6125",         "665",       SOC_SNAPD_SM6125,         soc, 11)
+  SOC_EQ(tmp, "SDM670",         "670",       SOC_SNAPD_SDM670,         soc, 10)
+  SOC_EQ(tmp, "SM6150",         "675",       SOC_SNAPD_SM6150,         soc, 11)
+  SOC_EQ(tmp, "SM6350",         "690",       SOC_SNAPD_SM6350,         soc,  8)
+  // Snapdragon 7XX //
+  SOC_EQ(tmp, "SDM710",         "710",       SOC_SNAPD_SDM710,         soc, 10)
+  SOC_EQ(tmp, "SDM712",         "712",       SOC_SNAPD_SDM712,         soc, 10)
+  SOC_EQ(tmp, "SM7125",         "720G",      SOC_SNAPD_SM7125,         soc,  8)
+  SOC_EQ(tmp, "SM7150-AA",      "730",       SOC_SNAPD_SM7150_AA,      soc,  8)
+  SOC_EQ(tmp, "SM7150-AB",      "730G",      SOC_SNAPD_SM7150_AB,      soc,  8)
+  SOC_EQ(tmp, "SM7150-AC",      "732G",      SOC_SNAPD_SM7150_AC,      soc,  8)
+  SOC_EQ(tmp, "SM7225",         "750G",      SOC_SNAPD_SM7225,         soc,  8)
+  SOC_EQ(tmp, "SM7250-AA",      "765",       SOC_SNAPD_SM7250_AA,      soc,  7)
+  SOC_EQ(tmp, "SM7250-AB",      "765G",      SOC_SNAPD_SM7250_AB,      soc,  7)
+  SOC_EQ(tmp, "SM7250-AC",      "768G",      SOC_SNAPD_SM7250_AC,      soc,  7)
+  // Snapdragon 8XX //
+  SOC_EQ(tmp, "MSM8974AA",      "800",       SOC_SNAPD_MSM8974AA,      soc, 28)
+  SOC_EQ(tmp, "MSM8974AB",      "800",       SOC_SNAPD_MSM8974AB,      soc, 28)
+  SOC_EQ(tmp, "MSM8974AC",      "800",       SOC_SNAPD_MSM8974AC,      soc, 28)
+  SOC_EQ(tmp, "MSM8974PRO-AB",  "801",       SOC_SNAPD_MSM8974PRO_AB,  soc, 28)
+  SOC_EQ(tmp, "MSM8974PRO-AC",  "801",       SOC_SNAPD_MSM8974PRO_AC,  soc, 28)
+  SOC_EQ(tmp, "APQ8084",        "805",       SOC_SNAPD_APQ8084,        soc, 28)
+  SOC_EQ(tmp, "MSM8992",        "808",       SOC_SNAPD_MSM8992,        soc, 20)
+  SOC_EQ(tmp, "MSM8994",        "810",       SOC_SNAPD_MSM8994,        soc, 20)
+  SOC_EQ(tmp, "MSM8996",        "820",       SOC_SNAPD_MSM8996,        soc, 14)
+  SOC_EQ(tmp, "MSM8996 PRO A",  "821",       SOC_SNAPD_MSM8996_PRO_A,  soc, 14)
+  SOC_EQ(tmp, "MSM8998",        "835",       SOC_SNAPD_MSM8998,        soc, 10)
+  SOC_EQ(tmp, "APQ8098",        "835",       SOC_SNAPD_APQ8098,        soc, 10)
+  SOC_EQ(tmp, "SDM845",         "845",       SOC_SNAPD_SDM845,         soc, 10)
+  SOC_EQ(tmp, "SDM850",         "850",       SOC_SNAPD_SDM850,         soc, 10)
+  SOC_EQ(tmp, "SM8150",         "855",       SOC_SNAPD_SM8150,         soc,  7)
+  SOC_EQ(tmp, "SM8150-AC",      "855+",      SOC_SNAPD_SM8150_AC,      soc,  7)
+  SOC_EQ(tmp, "SM8250",         "865",       SOC_SNAPD_SM8250,         soc,  7)
+  SOC_EQ(tmp, "SM8250-AB",      "865+",      SOC_SNAPD_SM8250_AB,      soc,  7)
+  SOC_EQ(tmp, "SM8350",         "888",       SOC_SNAPD_SM8350,         soc,  5)
+  SOC_END
+}
+
+bool match_special(char* soc_name, struct system_on_chip* soc) {
+  char* tmp;
+
+  // Xiaomi hides Redmi Note 8/8T under "Qualcomm Technologies, Inc TRINKET"
+  if((tmp = strstr(soc_name, "TRINKET")) != NULL) {
+    fill_soc(soc, "665", SOC_SNAPD_SM6125, 11);
+    return true;
+  }
+
+  // Snapdragon 730 reported as "Qualcomm Technologies, Inc. SDMMAGPIE"
+  if((tmp = strstr(soc_name, "SDMMAGPIE")) != NULL) {
+    fill_soc(soc, "730", SOC_SNAPD_SM7150_AA, 8);
+    return true;
+  }
+
+  return false;
+}
+
+struct system_on_chip* parse_soc_from_string(struct system_on_chip* soc) {
+  char* raw_name = soc->raw_name;
+
+  if(match_special(raw_name, soc))
+    return soc;
+
+  if (match_qualcomm(raw_name, soc))
+    return soc;
+
+  if(match_mediatek(raw_name, soc))
+    return soc;
+
+  if(match_exynos(raw_name, soc))
+    return soc;
+
+  if(match_hisilicon(raw_name, soc))
+    return soc;
+
+  match_broadcom(raw_name, soc);
+
+  return soc;
+}
+
+#ifdef __ANDROID__
+#include <sys/system_properties.h>
+
+static inline int android_property_get(const char* key, char* value) {
+  return __system_property_get(key, value);
+}
+
+struct system_on_chip* guess_soc_from_android(struct system_on_chip* soc) {
+  char tmp[100];
+  int property_len = 0;
+
+  property_len = android_property_get("ro.mediatek.platform", (char *) &tmp);
+  if(property_len > 0) {
+    soc->raw_name = emalloc(sizeof(char) * (property_len + 1));
+    strncpy(soc->raw_name, tmp, property_len + 1);
+    soc->raw_name[property_len] = '\0';
+    soc->soc_vendor = SOC_VENDOR_UNKNOWN;
+    return parse_soc_from_string(soc);
+  }
+
+  property_len = android_property_get("ro.product.board", (char *) &tmp);
+  if(property_len > 0) {
+    soc->raw_name = emalloc(sizeof(char) * (property_len + 1));
+    strncpy(soc->raw_name, tmp, property_len + 1);
+    soc->raw_name[property_len] = '\0';
+    soc->soc_vendor = SOC_VENDOR_UNKNOWN;
+    return parse_soc_from_string(soc);
+  }
+
+  return soc;
+}
+#endif
+
+struct system_on_chip* guess_soc_from_cpuinfo(struct system_on_chip* soc) {
+  char* tmp = get_hardware_from_cpuinfo();
+
+  if(tmp != NULL) {
+    soc->raw_name = tmp;
+    return parse_soc_from_string(soc);
+  }
+
+  return soc;
+}
+
+int hex2int(char c) {
+  if (c >= '0' && c <= '9')
+    return c - '0';
+  if (c >= 'A' && c <= 'F')
+    return c - 'A' + 10;
+  if (c >= 'a' && c <= 'f')
+    return c - 'a' + 10;
+
+  return -1;
+}
+
+// https://www.raspberrypi.org/documentation/hardware/raspberrypi/revision-codes/README.md
+struct system_on_chip* guess_soc_raspbery_pi(struct system_on_chip* soc) {
+  char* revision = get_revision_from_cpuinfo();
+
+  if(revision == NULL) {
+    printWarn("[RPi] Couldn't find revision field in cpuinfo");
+    return soc;
+  }
+
+  if(strlen(revision) != 6) {
+    printWarn("[RPi] Found invalid RPi revision code: '%s'", revision);
+    return soc;
+  }
+
+  int arr_size = ARRAY_SIZE(soc_rpi_string);
+  int pppp = hex2int(revision[2]);
+  if(pppp == -1) {
+    printErr("[RPi] Found invalid RPi PPPP code: %s", revision[2]);
+    return soc;
+  }
+
+  if(pppp > arr_size) {
+    printErr("[RPi] Found invalid RPi PPPP code: %d while max is %d", pppp, arr_size);
+    return soc;
+  }
+
+  char* soc_raw_name = soc_rpi_string[pppp];
+  /*int soc_len = strlen(soc_raw_name);
+  soc->raw_name = emalloc(sizeof(char) * (soc_len + 1));
+  strncpy(soc->raw_name, soc_raw_name, soc_len + 1);*/
+
+  match_broadcom(soc_raw_name, soc);
+  return soc;
+}
+
+struct system_on_chip* get_soc() {
+  struct system_on_chip* soc = emalloc(sizeof(struct system_on_chip));
+  soc->raw_name = NULL;
+  soc->soc_vendor = SOC_VENDOR_UNKNOWN;
+  soc->process = UNKNOWN;
+
+  bool isRPi = is_raspberry_pi();
+  if(isRPi) {
+    soc = guess_soc_raspbery_pi(soc);
+    if(soc->soc_vendor == SOC_VENDOR_UNKNOWN) {
+      printWarn("SoC detection failed using revision code");
+    }
+    else {
+      return soc;
+    }
+  }
+
+  soc = guess_soc_from_cpuinfo(soc);
+  if(soc->soc_vendor == SOC_VENDOR_UNKNOWN) {
+    if(soc->raw_name != NULL)
+      printWarn("SoC detection failed using /proc/cpuinfo: Found '%s' string", soc->raw_name);
+    else
+      printWarn("SoC detection failed using /proc/cpuinfo: No string found");
+#ifdef __ANDROID__
+    soc = guess_soc_from_android(soc);
+    if(soc->raw_name == NULL)
+      printWarn("SoC detection failed using Android: No string found");
+    else if(soc->soc_vendor == SOC_VENDOR_UNKNOWN)
+      printWarn("SoC detection failed using Android: Found '%s' string", soc->raw_name);
+#endif
+  }
+
+  if(soc->raw_name == NULL) {
+    soc->raw_name = emalloc(sizeof(char) * (strlen(STRING_UNKNOWN)+1));
+    snprintf(soc->raw_name, strlen(STRING_UNKNOWN)+1, STRING_UNKNOWN);
+  }
+
+  return soc;
+}
+
+char* get_soc_name(struct system_on_chip* soc) {
+  if(soc->soc_vendor == SOC_VENDOR_UNKNOWN)
+    return soc->raw_name;
+  return soc->soc_name;
+}
+
+VENDOR get_soc_vendor(struct system_on_chip* soc) {
+  return soc->soc_vendor;
+}
+
+char* get_str_process(struct system_on_chip* soc) {
+  char* str;
+
+  if(soc->process == UNKNOWN) {
+    str = emalloc(sizeof(char) * (strlen(STRING_UNKNOWN)+1));
+    snprintf(str, strlen(STRING_UNKNOWN)+1, STRING_UNKNOWN);
+  }
+  else {
+    str = emalloc(sizeof(char) * 5);
+    memset(str, 0, sizeof(char) * 5);
+    snprintf(str, 5, "%dnm", soc->process);
+  }
+  return str;
+}

src/arm/soc.h

@@ -0,0 +1,31 @@
+#ifndef __SOC__
+#define __SOC__
+
+#include "../common/cpu.h"
+#include <stdint.h>
+
+typedef int32_t SOC;
+
+enum {
+  SOC_VENDOR_UNKNOWN,
+  SOC_VENDOR_SNAPDRAGON,
+  SOC_VENDOR_MEDIATEK,
+  SOC_VENDOR_EXYNOS,
+  SOC_VENDOR_KIRIN,
+  SOC_VENDOR_BROADCOM
+};
+
+struct system_on_chip {
+  SOC soc_model;
+  VENDOR soc_vendor;
+  int32_t process;
+  char* soc_name;
+  char* raw_name;    
+};
+
+struct system_on_chip* get_soc();
+char* get_soc_name(struct system_on_chip* soc);
+VENDOR get_soc_vendor(struct system_on_chip* soc);
+char* get_str_process(struct system_on_chip* soc);
+
+#endif

src/arm/socs.h

@@ -0,0 +1,264 @@
+#ifndef __SOCS__
+#define __SOCS__
+
+#include "soc.h"
+
+// List of supported SOCs
+enum {
+  // Broadcom //
+  SOC_BCM_2835,
+  SOC_BCM_2836,
+  SOC_BCM_2837,
+  SOC_BCM_2837B0,
+  SOC_BCM_2711,
+  SOC_BCM_21553,
+  SOC_BCM_21553T,
+  SOC_BCM_21663,
+  SOC_BCM_21664,
+  SOC_BCM_28155,
+  SOC_BCM_23550,
+  SOC_BCM_28145,
+  SOC_BCM_2157,
+  SOC_BCM_21654,
+  // Hisilicon //
+  SOC_HISILICON_3620,
+  SOC_HISILICON_3630,
+  SOC_HISILICON_3650,
+  SOC_HISILICON_3660,
+  SOC_HISILICON_3670,
+  SOC_HISILICON_3680,
+  SOC_HISILICON_3690,
+  // Exynos //
+  SOC_EXYNOS_3475,
+  SOC_EXYNOS_4210,
+  SOC_EXYNOS_4212,
+  SOC_EXYNOS_4412,
+  SOC_EXYNOS_5250,
+  SOC_EXYNOS_5410,
+  SOC_EXYNOS_5420,
+  SOC_EXYNOS_5422,
+  SOC_EXYNOS_5430,
+  SOC_EXYNOS_5433,
+  SOC_EXYNOS_5260,
+  SOC_EXYNOS_7270,
+  SOC_EXYNOS_7420,
+  SOC_EXYNOS_7570,
+  SOC_EXYNOS_7870,
+  SOC_EXYNOS_7872,
+  SOC_EXYNOS_7880,
+  SOC_EXYNOS_7884,
+  SOC_EXYNOS_7885,
+  SOC_EXYNOS_7904,
+  SOC_EXYNOS_8890,
+  SOC_EXYNOS_8895,
+  SOC_EXYNOS_9110,
+  SOC_EXYNOS_9609,
+  SOC_EXYNOS_9610,
+  SOC_EXYNOS_9611,
+  SOC_EXYNOS_9810,
+  SOC_EXYNOS_9820,
+  SOC_EXYNOS_9825,
+  SOC_EXYNOS_1080,
+  SOC_EXYNOS_990,
+  SOC_EXYNOS_980,
+  SOC_EXYNOS_880,
+  // Mediatek //
+  SOC_MTK_MT6889,
+  SOC_MTK_MT6885Z,
+  SOC_MTK_MT6853,
+  SOC_MTK_MT6873,
+  SOC_MTK_MT6875,
+  SOC_MTK_MT6761D,
+  SOC_MTK_MT6761,
+  SOC_MTK_MT6762D,
+  SOC_MTK_MT6755,
+  SOC_MTK_MT6755M,
+  SOC_MTK_MT6755T,
+  SOC_MTK_MT6757,
+  SOC_MTK_MT6762,
+  SOC_MTK_MT6763V,
+  SOC_MTK_MT6763T,
+  SOC_MTK_MT6757CD,
+  SOC_MTK_MT6758,
+  SOC_MTK_MT6765,
+  SOC_MTK_MT6771,
+  SOC_MTK_MT6768,
+  SOC_MTK_MT6771T,
+  SOC_MTK_MT6771V,
+  SOC_MTK_MT6779,
+  SOC_MTK_MT6795,
+  SOC_MTK_MT6795T,
+  SOC_MTK_MT6797,
+  SOC_MTK_MT6797M,
+  SOC_MTK_MT6797D,
+  SOC_MTK_MT6797T,
+  SOC_MTK_MT6797X,
+  SOC_MTK_MT6799,
+  SOC_MTK_MT6515,
+  SOC_MTK_MT6516,
+  SOC_MTK_MT6517,
+  SOC_MTK_MT6572,
+  SOC_MTK_MT6572M,
+  SOC_MTK_MT6573,
+  SOC_MTK_MT6575,
+  SOC_MTK_MT6577,
+  SOC_MTK_MT6577T,
+  SOC_MTK_MT6580,
+  SOC_MTK_MT6582,
+  SOC_MTK_MT6582M,
+  SOC_MTK_MT6589,
+  SOC_MTK_MT6589T,
+  SOC_MTK_MT6592,
+  SOC_MTK_MT6595,
+  SOC_MTK_MT6732,
+  SOC_MTK_MT6735,
+  SOC_MTK_MT6735M,
+  SOC_MTK_MT6735P,
+  SOC_MTK_MT6737,
+  SOC_MTK_MT6737M,
+  SOC_MTK_MT6737T,
+  SOC_MTK_MT6739,
+  SOC_MTK_MT6750,
+  SOC_MTK_MT6750S,
+  SOC_MTK_MT6750T,
+  SOC_MTK_MT6752,
+  SOC_MTK_MT6753,
+  SOC_MTK_MT6850,
+  SOC_MTK_MT8121,
+  SOC_MTK_MT8125,
+  SOC_MTK_MT8127,
+  SOC_MTK_MT8135,
+  SOC_MTK_MT8163A,
+  SOC_MTK_MT8163B,
+  SOC_MTK_MT8167B,
+  SOC_MTK_MT8173,
+  SOC_MTK_MT8176,
+  SOC_MTK_MT8321,
+  SOC_MTK_MT8382,
+  SOC_MTK_MT8581,
+  SOC_MTK_MT8735,
+  SOC_MTK_MT8765B,
+  SOC_MTK_MT8783,
+  // Snapdragon //
+  SOC_SNAPD_QSD8650,
+  SOC_SNAPD_QSD8250,
+  SOC_SNAPD_MSM7627,
+  SOC_SNAPD_MSM7227,
+  SOC_SNAPD_MSM7627A,
+  SOC_SNAPD_MSM7227A,
+  SOC_SNAPD_MSM7625,
+  SOC_SNAPD_MSM7225,
+  SOC_SNAPD_MSM7625A,
+  SOC_SNAPD_MSM7225A,
+  SOC_SNAPD_MSM8655,
+  SOC_SNAPD_MSM8255,
+  SOC_SNAPD_APQ8055,
+  SOC_SNAPD_MSM7630,
+  SOC_SNAPD_MSM7230,
+  SOC_SNAPD_MSM8660,
+  SOC_SNAPD_MSM8260,
+  SOC_SNAPD_APQ8060,
+  SOC_SNAPD_MSM8225,
+  SOC_SNAPD_MSM8625,
+  SOC_SNAPD_APQ8060A,
+  SOC_SNAPD_MSM8960,
+  SOC_SNAPD_MSM8260A,
+  SOC_SNAPD_MSM8627,
+  SOC_SNAPD_MSM8227,
+  SOC_SNAPD_APQ8064,
+  SOC_SNAPD_MSM8960T,
+  SOC_SNAPD_MSM8110,
+  SOC_SNAPD_MSM8210,
+  SOC_SNAPD_MSM8610,
+  SOC_SNAPD_MSM8112,
+  SOC_SNAPD_MSM8212,
+  SOC_SNAPD_MSM8612,
+  SOC_SNAPD_MSM8225Q,
+  SOC_SNAPD_MSM8625Q,
+  SOC_SNAPD_MSM8208,
+  SOC_SNAPD_MSM8905,
+  SOC_SNAPD_MSM8909,
+  SOC_SNAPD_QM215,
+  SOC_SNAPD_APQ8028,
+  SOC_SNAPD_MSM8228,
+  SOC_SNAPD_MSM8628,
+  SOC_SNAPD_MSM8928,
+  SOC_SNAPD_MSM8926,
+  SOC_SNAPD_APQ8030AB,
+  SOC_SNAPD_MSM8226,
+  SOC_SNAPD_MSM8230AB,
+  SOC_SNAPD_MSM8626,
+  SOC_SNAPD_MSM8630,
+  SOC_SNAPD_MSM8630AB,
+  SOC_SNAPD_MSM8930,
+  SOC_SNAPD_MSM8930AB,
+  SOC_SNAPD_MSM8916,
+  SOC_SNAPD_MSM8929,
+  SOC_SNAPD_MSM8917,
+  SOC_SNAPD_MSM8920,
+  SOC_SNAPD_SDM429,
+  SOC_SNAPD_MSM8937,
+  SOC_SNAPD_MSM8940,
+  SOC_SNAPD_SDM439,
+  SOC_SNAPD_SDM450,
+  SOC_SNAPD_SM4250_AA,
+  SOC_SNAPD_APQ8064T,
+  SOC_SNAPD_APQ8064M,
+  SOC_SNAPD_MSM8936,
+  SOC_SNAPD_MSM8939,
+  SOC_SNAPD_MSM8952,
+  SOC_SNAPD_MSM8953,
+  SOC_SNAPD_MSM8953_PRO,
+  SOC_SNAPD_SDM630,
+  SOC_SNAPD_SDM632,
+  SOC_SNAPD_SDM636,
+  SOC_SNAPD_MSM8956,
+  SOC_SNAPD_MSM8976,
+  SOC_SNAPD_MSM8976_PRO,
+  SOC_SNAPD_SDM660,
+  SOC_SNAPD_SM6115,
+  SOC_SNAPD_SM6125,
+  SOC_SNAPD_SDM670,
+  SOC_SNAPD_SM6150,
+  SOC_SNAPD_SM6350,
+  SOC_SNAPD_SDM710,
+  SOC_SNAPD_SDM712,
+  SOC_SNAPD_SM7125,
+  SOC_SNAPD_SM7150_AA,
+  SOC_SNAPD_SM7150_AB,
+  SOC_SNAPD_SM7150_AC,
+  SOC_SNAPD_SM7225,
+  SOC_SNAPD_SM7250_AA,
+  SOC_SNAPD_SM7250_AB,
+  SOC_SNAPD_SM7250_AC,
+  SOC_SNAPD_MSM8974AA,
+  SOC_SNAPD_MSM8974AB,
+  SOC_SNAPD_MSM8974AC,
+  SOC_SNAPD_MSM8974PRO_AB,
+  SOC_SNAPD_MSM8974PRO_AC,
+  SOC_SNAPD_APQ8084,
+  SOC_SNAPD_MSM8992,
+  SOC_SNAPD_MSM8994,
+  SOC_SNAPD_MSM8996,
+  SOC_SNAPD_MSM8996_PRO_A,
+  SOC_SNAPD_MSM8998,
+  SOC_SNAPD_APQ8098,
+  SOC_SNAPD_SDM845,
+  SOC_SNAPD_SDM850,
+  SOC_SNAPD_SM8150,
+  SOC_SNAPD_SM8150_AC,
+  SOC_SNAPD_SM8250,
+  SOC_SNAPD_SM8250_AB,
+  SOC_SNAPD_SM8350,
+};
+
+inline static VENDOR get_soc_vendor_from_soc(SOC soc) {
+  if(soc >= SOC_BCM_2835 && soc <= SOC_BCM_21654) return SOC_VENDOR_BROADCOM;
+  else if(soc >= SOC_HISILICON_3620 && soc <= SOC_HISILICON_3690) return SOC_VENDOR_KIRIN;
+  else if(soc >= SOC_EXYNOS_3475 && soc <= SOC_EXYNOS_880) return SOC_VENDOR_EXYNOS;
+  else if(soc >= SOC_MTK_MT6889 && soc <= SOC_MTK_MT8783) return SOC_VENDOR_MEDIATEK;
+  else if(soc >= SOC_SNAPD_QSD8650 && soc <= SOC_SNAPD_SM8350) return SOC_VENDOR_SNAPDRAGON;
+  return SOC_VENDOR_UNKNOWN;  
+}
+
+#endif

src/arm/socs_generation.sh

@@ -0,0 +1,23 @@
+#!/bin/bash -u
+
+SOC_LIST="$(grep SOC_EQ soc.c | grep -v '//SOC_EQ' | grep -v 'define' | cut -d',' -f2 | sed 's/"//')"
+
+IFS=$'"'
+
+for soc in $SOC_LIST
+do
+  # CLEAN
+  soc=$(echo $soc | tr -d '\n')
+  soc="${soc:1}"
+  
+  # REPLACE
+  soc=$(echo $soc | sed "s/BCM/BCM_/g")
+  soc=$(echo $soc | sed "s/universal/EXYNOS_/g")
+  soc=$(echo $soc | sed "s/Hi/HISILICON_/g")
+  soc=$(echo $soc | sed "s/^MSM/SNAPD_MSM/g" | sed "s/SDM/SNAPD_SDM/g" | sed "s/APQ/SNAPD_APQ/g" | sed "s/^SM/SNAPD_SM/g" | sed "s/QM/SNAPD_QM/g" | sed "s/QSD/SNAPD_QSD/g")
+  soc=$(echo $soc | sed "s/MT/MTK_MT/g")
+  soc=$(echo $soc | sed "s/-/_/g" | sed "s/ /_/g")
+  echo '  SOC_'"$soc"','
+done
+
+unset IFS

src/arm/uarch.c

@@ -0,0 +1,298 @@
+#include <stdbool.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <inttypes.h>
+
+#include "uarch.h"
+#include "../common/global.h"
+
+// Data not available
+#define NA                   -1
+
+typedef uint32_t MICROARCH;
+typedef uint32_t ISA;
+
+struct uarch {
+  MICROARCH uarch;
+  ISA isa;
+  char* uarch_str;
+  char* isa_str;
+  // int32_t process; process depends on SoC
+};
+
+enum {
+  ISA_ARMv6,
+  ISA_ARMv6_T2,
+  ISA_ARMv6_KZ,
+  ISA_ARMv6_K,
+  ISA_ARMv7_A,
+  ISA_ARMv8_A,
+  ISA_ARMv8_A_AArch32,
+  ISA_ARMv8_1_A,
+  ISA_ARMv8_2_A,
+  ISA_ARMv8_3_A,
+};
+
+enum {
+  UARCH_UNKNOWN,
+  // ARM
+  UARCH_ARM7,
+  UARCH_ARM9,
+  UARCH_ARM1136,
+  UARCH_ARM1156,
+  UARCH_ARM1176,
+  UARCH_ARM11MPCORE,
+  UARCH_CORTEX_A5,
+  UARCH_CORTEX_A7,
+  UARCH_CORTEX_A8,
+  UARCH_CORTEX_A9,
+  UARCH_CORTEX_A12,
+  UARCH_CORTEX_A15,
+  UARCH_CORTEX_A17,
+  UARCH_CORTEX_A32,
+  UARCH_CORTEX_A35,
+  UARCH_CORTEX_A53,
+  UARCH_CORTEX_A55r0, // ARM Cortex-A55 revision 0 (restricted dual-issue capabilities compared to revision 1+).
+  UARCH_CORTEX_A55,
+  UARCH_CORTEX_A57,
+  UARCH_CORTEX_A65,
+  UARCH_CORTEX_A72,
+  UARCH_CORTEX_A73,
+  UARCH_CORTEX_A75,
+  UARCH_CORTEX_A76,
+  UARCH_CORTEX_A77,
+  UARCH_CORTEX_A78,
+  UARCH_NEOVERSE_N1,
+  UARCH_NEOVERSE_E1,
+  UARCH_SCORPION,
+  UARCH_KRAIT,
+  UARCH_KYRO,
+  UARCH_FALKOR,
+  UARCH_SAPHIRA,
+  UARCH_DENVER,
+  UARCH_DENVER2,
+  UARCH_CARMEL,
+  // SAMSUNG
+  UARCH_EXYNOS_M1,  // Samsung Exynos M1 (Exynos 8890 big cores)
+  UARCH_EXYNOS_M2,  // Samsung Exynos M2 (Exynos 8895 big cores)
+  UARCH_EXYNOS_M3,  // Samsung Exynos M3 (Exynos 9810 big cores)
+  UARCH_EXYNOS_M4,  // Samsung Exynos M4 (Exynos 9820 big cores)
+  UARCH_EXYNOS_M5,  // Samsung Exynos M5 (Exynos 9830 big cores)
+  // APPLE
+  UARCH_SWIFT,      // Apple A6 and A6X processors.
+  UARCH_CYCLONE,    // Apple A7 processor.
+  UARCH_TYPHOON,    // Apple A8 and A8X processor
+  UARCH_TWISTER,    // Apple A9 and A9X processor.
+  UARCH_HURRICANE,  // Apple A10 and A10X processor.
+  UARCH_MONSOON,    // Apple A11 processor (big cores).
+  UARCH_MISTRAL,    // Apple A11 processor (little cores).
+  UARCH_VORTEX,     // Apple A12 processor (big cores).
+  UARCH_TEMPEST,    // Apple A12 processor (big cores).
+  UARCH_LIGHTNING,  // Apple A13 processor (big cores).
+  UARCH_THUNDER,    // Apple A13 processor (little cores).
+  // CAVIUM
+  UARCH_THUNDERX,   // Cavium ThunderX
+  UARCH_THUNDERX2,  //  Cavium ThunderX2 (originally Broadcom Vulkan).
+  // MARVELL
+  UARCH_PJ4,
+  UARCH_BRAHMA_B15,
+  UARCH_BRAHMA_B53,
+  UARCH_XGENE,        // Applied Micro X-Gene.
+  UARCH_TAISHAN_V110  // HiSilicon TaiShan v110 (Huawei Kunpeng 920 series processors).
+};
+
+static const ISA isas_uarch[] = {
+  [UARCH_ARM1136]      = ISA_ARMv6,
+  [UARCH_ARM1156]      = ISA_ARMv6_T2,
+  [UARCH_ARM1176]      = ISA_ARMv6_KZ,
+  [UARCH_ARM11MPCORE]  = ISA_ARMv6_K,
+  [UARCH_CORTEX_A5]    = ISA_ARMv7_A,
+  [UARCH_CORTEX_A7]    = ISA_ARMv7_A,
+  [UARCH_CORTEX_A8]    = ISA_ARMv7_A,
+  [UARCH_CORTEX_A9]    = ISA_ARMv7_A,
+  [UARCH_CORTEX_A12]   = ISA_ARMv7_A,
+  [UARCH_CORTEX_A15]   = ISA_ARMv7_A,
+  [UARCH_CORTEX_A17]   = ISA_ARMv7_A,
+  [UARCH_CORTEX_A32]   = ISA_ARMv8_A_AArch32,
+  [UARCH_CORTEX_A35]   = ISA_ARMv8_A,
+  [UARCH_CORTEX_A53]   = ISA_ARMv8_A,
+  [UARCH_CORTEX_A55r0] = ISA_ARMv8_2_A,
+  [UARCH_CORTEX_A55]   = ISA_ARMv8_2_A,
+  [UARCH_CORTEX_A57]   = ISA_ARMv8_A,
+  [UARCH_CORTEX_A65]   = ISA_ARMv8_2_A,
+  [UARCH_CORTEX_A72]   = ISA_ARMv8_A,
+  [UARCH_CORTEX_A73]   = ISA_ARMv8_A,
+  [UARCH_CORTEX_A75]   = ISA_ARMv8_2_A,
+  [UARCH_CORTEX_A76]   = ISA_ARMv8_2_A,
+  [UARCH_CORTEX_A77]   = ISA_ARMv8_2_A,
+  [UARCH_CORTEX_A78]   = ISA_ARMv8_2_A,
+  [UARCH_NEOVERSE_N1]  = ISA_ARMv8_2_A,
+  [UARCH_NEOVERSE_E1]  = ISA_ARMv8_2_A,
+  [UARCH_BRAHMA_B15]   = ISA_ARMv7_A,   // Same as Cortex-A15
+  [UARCH_BRAHMA_B53]   = ISA_ARMv8_A,   // Same as Cortex-A53
+  [UARCH_THUNDERX]     = ISA_ARMv8_A,
+  [UARCH_THUNDERX2]    = ISA_ARMv8_1_A,
+  [UARCH_TAISHAN_V110] = ISA_ARMv8_2_A,
+  [UARCH_DENVER]       = ISA_ARMv8_A,
+  [UARCH_DENVER2]      = ISA_ARMv8_A,
+  [UARCH_CARMEL]       = ISA_ARMv8_A,
+  [UARCH_XGENE]        = ISA_ARMv8_A, // https://en.wikichip.org/wiki/apm/x-gene
+  [UARCH_SCORPION]     = ISA_ARMv7_A, // https://www.geektopia.es/es/product/qualcomm/snapdragon-s3-apq8060/
+  [UARCH_KRAIT]        = ISA_ARMv7_A,
+  [UARCH_KYRO]         = ISA_ARMv8_A,
+  [UARCH_FALKOR]       = ISA_ARMv8_A,
+  [UARCH_SAPHIRA]      = ISA_ARMv8_3_A,
+  [UARCH_EXYNOS_M1]    = ISA_ARMv8_A,
+  [UARCH_EXYNOS_M2]    = ISA_ARMv8_A,
+  [UARCH_EXYNOS_M3]    = ISA_ARMv8_A,
+  [UARCH_EXYNOS_M4]    = ISA_ARMv8_2_A,
+  [UARCH_EXYNOS_M5]    = ISA_ARMv8_2_A,
+  [UARCH_PJ4]          = ISA_ARMv7_A,
+};
+
+static char* isas_string[] = {
+  [ISA_ARMv6]  = "ARMv6",
+  [ISA_ARMv6_T2] = "ARMv6T2",
+  [ISA_ARMv6_KZ] = "ARMv6KZ",
+  [ISA_ARMv6_K] = "ARMv6K",
+  [ISA_ARMv7_A] = "ARMv7",
+  [ISA_ARMv8_A] = "ARMv8",
+  [ISA_ARMv8_A_AArch32] = "ARMv8 AArch32",
+  [ISA_ARMv8_1_A] = "ARMv8.1",
+  [ISA_ARMv8_2_A] = "ARMv8.2",
+  [ISA_ARMv8_3_A] = "ARMv8.3",
+};
+
+#define UARCH_START if (false) {}
+#define CHECK_UARCH(arch, cpu, im_, p_, v_, r_, str, uarch, vendor) \
+   else if (im_ == im && p_ == p && (v_ == NA || v_ == v) && (r_ == NA || r_ == r)) fill_uarch(arch, cpu, str, uarch, vendor);
+#define UARCH_END else { printBug("Unknown microarchitecture detected: IM=0x%.8X P=0x%.8X V=0x%.8X R=0x%.8X", im, p, v, r); fill_uarch(arch, cpu, "Unknown", UARCH_UNKNOWN, CPU_VENDOR_UNKNOWN); }
+
+void fill_uarch(struct uarch* arch, struct cpuInfo* cpu, char* str, MICROARCH u, VENDOR vendor) {
+  arch->uarch = u;
+  arch->isa = isas_uarch[arch->uarch];
+  cpu->cpu_vendor = vendor;
+
+  arch->uarch_str = emalloc(sizeof(char) * (strlen(str)+1));
+  strcpy(arch->uarch_str, str);
+
+  arch->isa_str = emalloc(sizeof(char) * (strlen(isas_string[arch->isa])+1));
+  strcpy(arch->isa_str, isas_string[arch->isa]);
+}
+
+/*
+ * Codes are based on pytorch/cpuinfo, more precisely:
+ * - https://github.com/pytorch/cpuinfo/blob/master/src/arm/uarch.c
+ * Other sources:
+ * - https://elixir.bootlin.com/linux/latest/source/arch/arm64/include/asm/cputype.h
+ * - https://elixir.bootlin.com/linux/latest/source/arch/arm/include/asm/cputype.h
+ */
+struct uarch* get_uarch_from_midr(uint32_t midr, struct cpuInfo* cpu) {
+  struct uarch* arch = emalloc(sizeof(struct uarch));
+  uint32_t im = midr_get_implementer(midr);
+  uint32_t p = midr_get_part(midr);
+  uint32_t v = midr_get_variant(midr);
+  uint32_t r = midr_get_revision(midr);
+
+  // ----------------------------------------------------------------------- //
+  // IM: Implementer                                                         //
+  // P:  Part                                                                //
+  // V:  Variant                                                             //
+  // R:  Revision                                                            //
+  // ----------------------------------------------------------------------- //
+  //                     IM   P      V   R                                   //
+  UARCH_START
+  CHECK_UARCH(arch, cpu, 'A', 0xB36, NA, NA, "ARM1136",               UARCH_ARM1136,      CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xB56, NA, NA, "ARM1156",               UARCH_ARM1156,      CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xB76, NA, NA, "ARM1176",               UARCH_ARM1176,      CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xB02, NA, NA, "ARM11 MPCore",          UARCH_ARM11MPCORE,  CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xC05, NA, NA, "Cortex-A5",             UARCH_CORTEX_A5,    CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xC07, NA, NA, "Cortex-A7",             UARCH_CORTEX_A7,    CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xC08, NA, NA, "Cortex-A8",             UARCH_CORTEX_A8,    CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xC09, NA, NA, "Cortex-A9",             UARCH_CORTEX_A9,    CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xC0C, NA, NA, "Cortex-A12",            UARCH_CORTEX_A12,   CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xC0E, NA, NA, "Cortex-A17",            UARCH_CORTEX_A17,   CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xC0D, NA, NA, "Cortex-A12",            UARCH_CORTEX_A12,   CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xC0F, NA, NA, "Cortex-A15",            UARCH_CORTEX_A15,   CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xD01, NA, NA, "Cortex-A32",            UARCH_CORTEX_A32,   CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xD03, NA, NA, "Cortex-A53",            UARCH_CORTEX_A53,   CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xD04, NA, NA, "Cortex-A35",            UARCH_CORTEX_A35,   CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xD05, NA,  0, "Cortex-A55",            UARCH_CORTEX_A55r0, CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xD05, NA, NA, "Cortex-A55",            UARCH_CORTEX_A55,   CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xD06, NA, NA, "Cortex-A65",            UARCH_CORTEX_A65,   CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xD07, NA, NA, "Cortex-A57",            UARCH_CORTEX_A57,   CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xD08, NA, NA, "Cortex-A72",            UARCH_CORTEX_A72,   CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xD09, NA, NA, "Cortex-A73",            UARCH_CORTEX_A73,   CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xD0A, NA, NA, "Cortex-A75",            UARCH_CORTEX_A75,   CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xD0B, NA, NA, "Cortex-A76",            UARCH_CORTEX_A76,   CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xD0C, NA, NA, "Neoverse N1",           UARCH_NEOVERSE_N1,  CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xD0D, NA, NA, "Cortex-A77",            UARCH_CORTEX_A77,   CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xD0E, NA, NA, "Cortex-A76",            UARCH_CORTEX_A76,   CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xD41, NA, NA, "Cortex-A78",            UARCH_CORTEX_A78,   CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xD4A, NA, NA, "Neoverse E1",           UARCH_NEOVERSE_E1,  CPU_VENDOR_ARM)
+
+  CHECK_UARCH(arch, cpu, 'B', 0x00F, NA, NA, "Brahma B15",            UARCH_BRAHMA_B15,   CPU_VENDOR_BROADCOM)
+  CHECK_UARCH(arch, cpu, 'B', 0x100, NA, NA, "Brahma B53",            UARCH_BRAHMA_B53,   CPU_VENDOR_BROADCOM)
+  CHECK_UARCH(arch, cpu, 'B', 0x516, NA, NA, "ThunderX2",             UARCH_THUNDERX2,    CPU_VENDOR_CAVIUM)
+
+  CHECK_UARCH(arch, cpu, 'C', 0x0A0, NA, NA, "ThunderX",              UARCH_THUNDERX,     CPU_VENDOR_CAVIUM)
+  CHECK_UARCH(arch, cpu, 'C', 0x0A1, NA, NA, "ThunderX 88XX",         UARCH_THUNDERX,     CPU_VENDOR_CAVIUM)
+  CHECK_UARCH(arch, cpu, 'C', 0x0A2, NA, NA, "ThunderX 81XX",         UARCH_THUNDERX,     CPU_VENDOR_CAVIUM)
+  CHECK_UARCH(arch, cpu, 'C', 0x0A3, NA, NA, "ThunderX 81XX",         UARCH_THUNDERX,     CPU_VENDOR_CAVIUM)
+  CHECK_UARCH(arch, cpu, 'C', 0x0AF, NA, NA, "ThunderX2 99XX",        UARCH_THUNDERX2,    CPU_VENDOR_CAVIUM)
+
+  CHECK_UARCH(arch, cpu, 'H', 0xD01, NA, NA, "TaiShan v110",          UARCH_TAISHAN_V110, CPU_VENDOR_HUAWUEI) // Kunpeng 920 series
+  CHECK_UARCH(arch, cpu, 'H', 0xD40, NA, NA, "Cortex-A76",            UARCH_CORTEX_A76,   CPU_VENDOR_ARM)     // Kirin 980 Big/Medium cores -> Cortex-A76
+
+  CHECK_UARCH(arch, cpu, 'N', 0x000, NA, NA, "Denver",                UARCH_DENVER,       CPU_VENDOR_NVIDIA)
+  CHECK_UARCH(arch, cpu, 'N', 0x003, NA, NA, "Denver2",               UARCH_DENVER2,      CPU_VENDOR_NVIDIA)
+  CHECK_UARCH(arch, cpu, 'N', 0x004, NA, NA, "Carmel",                UARCH_CARMEL,       CPU_VENDOR_NVIDIA)
+
+  CHECK_UARCH(arch, cpu, 'P', 0x000, NA, NA, "Xgene",                 UARCH_XGENE,        CPU_VENDOR_APM)
+
+  CHECK_UARCH(arch, cpu, 'Q', 0x00F, NA, NA, "Scorpion",              UARCH_SCORPION,     CPU_VENDOR_QUALCOMM)
+  CHECK_UARCH(arch, cpu, 'Q', 0x02D, NA, NA, "Scorpion",              UARCH_KRAIT,        CPU_VENDOR_QUALCOMM)
+  CHECK_UARCH(arch, cpu, 'Q', 0x04D,  1,  0, "Krait 200",             UARCH_KRAIT,        CPU_VENDOR_QUALCOMM)
+  CHECK_UARCH(arch, cpu, 'Q', 0x04D,  1,  4, "Krait 200",             UARCH_KRAIT,        CPU_VENDOR_QUALCOMM)
+  CHECK_UARCH(arch, cpu, 'Q', 0x04D,  2,  0, "Krait 300",             UARCH_KRAIT,        CPU_VENDOR_QUALCOMM)
+  CHECK_UARCH(arch, cpu, 'Q', 0x06F,  0,  1, "Krait 200",             UARCH_KRAIT,        CPU_VENDOR_QUALCOMM)
+  CHECK_UARCH(arch, cpu, 'Q', 0x06F,  0,  2, "Krait 200",             UARCH_KRAIT,        CPU_VENDOR_QUALCOMM)
+  CHECK_UARCH(arch, cpu, 'Q', 0x06F,  1,  0, "Krait 300",             UARCH_KRAIT,        CPU_VENDOR_QUALCOMM)
+  CHECK_UARCH(arch, cpu, 'Q', 0x06F,  2,  0, "Krait 400",             UARCH_KRAIT,        CPU_VENDOR_QUALCOMM) // Snapdragon 800 MSMxxxx
+  CHECK_UARCH(arch, cpu, 'Q', 0x06F,  2,  1, "Krait 400",             UARCH_KRAIT,        CPU_VENDOR_QUALCOMM) // Snapdragon 801 MSMxxxxPRO
+  CHECK_UARCH(arch, cpu, 'Q', 0x06F,  3,  1, "Krait 450",             UARCH_KRAIT,        CPU_VENDOR_QUALCOMM)
+  CHECK_UARCH(arch, cpu, 'Q', 0x201, NA, NA, "Kryo Silver",           UARCH_KYRO,         CPU_VENDOR_QUALCOMM) // Qualcomm Snapdragon 821: Low-power Kryo "Silver"
+  CHECK_UARCH(arch, cpu, 'Q', 0x205, NA, NA, "Kryo Gold",             UARCH_KYRO,         CPU_VENDOR_QUALCOMM) // Qualcomm Snapdragon 820 & 821: High-performance Kryo "Gold"
+  CHECK_UARCH(arch, cpu, 'Q', 0x211, NA, NA, "Kryo Silver",           UARCH_KYRO,         CPU_VENDOR_QUALCOMM) // Qualcomm Snapdragon 820: Low-power Kryo "Silver"
+  CHECK_UARCH(arch, cpu, 'Q', 0x800, 10, NA, "Kryo 260 / 280 Gold",   UARCH_CORTEX_A73,   CPU_VENDOR_ARM)      // Kryo 260 / Kryo 280 "Gold"
+  CHECK_UARCH(arch, cpu, 'Q', 0x801, 10, NA, "Kryo 260 / 280 Silver", UARCH_CORTEX_A53,   CPU_VENDOR_ARM)      // Kryo 260 / 280 "Silver"
+  CHECK_UARCH(arch, cpu, 'Q', 0x802, NA, NA, "Kryo 385 Gold",         UARCH_CORTEX_A75,   CPU_VENDOR_ARM)      // High-performance Kryo 385 "Gold" -> Cortex-A75
+  CHECK_UARCH(arch, cpu, 'Q', 0x803, NA, NA, "Kryo 385 Silver",       UARCH_CORTEX_A55r0, CPU_VENDOR_ARM)      // Low-power Kryo 385 "Silver" -> Cortex-A55r0
+  CHECK_UARCH(arch, cpu, 'Q', 0x804, NA, NA, "Kryo 485 Gold",         UARCH_CORTEX_A76,   CPU_VENDOR_ARM)      // High-performance Kryo 485 "Gold" / "Gold Prime" -> Cortex-A76
+  CHECK_UARCH(arch, cpu, 'Q', 0x805, NA, NA, "Kryo 485 Silver",       UARCH_CORTEX_A55,   CPU_VENDOR_ARM)      // Low-performance Kryo 485 "Silver" -> Cortex-A55
+  CHECK_UARCH(arch, cpu, 'Q', 0xC00, NA, NA, "Falkor",                UARCH_FALKOR,       CPU_VENDOR_QUALCOMM)
+  CHECK_UARCH(arch, cpu, 'Q', 0xC01, NA, NA, "Saphira",               UARCH_SAPHIRA,      CPU_VENDOR_QUALCOMM)
+
+  CHECK_UARCH(arch, cpu, 'S', 0x001, 1,  NA, "Exynos M1",             UARCH_EXYNOS_M1,    CPU_VENDOR_SAMSUNG)   // Exynos 8890
+  CHECK_UARCH(arch, cpu, 'S', 0x001, 4,  NA, "Exynos M2",             UARCH_EXYNOS_M2,    CPU_VENDOR_SAMSUNG)   // Exynos 8895
+  CHECK_UARCH(arch, cpu, 'S', 0x002, 1,  NA, "Exynos M3",             UARCH_EXYNOS_M3,    CPU_VENDOR_SAMSUNG)   // Exynos 9810
+  CHECK_UARCH(arch, cpu, 'S', 0x003, 1,  NA, "Exynos M4",             UARCH_EXYNOS_M4,    CPU_VENDOR_SAMSUNG)   // Exynos 9820
+  CHECK_UARCH(arch, cpu, 'S', 0x004, 1,  NA, "Exynos M5",             UARCH_EXYNOS_M5,    CPU_VENDOR_SAMSUNG)   // Exynos 9820 (this one looks wrong at uarch.c ...)
+
+  CHECK_UARCH(arch, cpu, 'V', 0x581, NA, NA, "PJ4",                   UARCH_PJ4,          CPU_VENDOR_MARVELL)
+  CHECK_UARCH(arch, cpu, 'V', 0x584, NA, NA, "PJ4B-MP",               UARCH_PJ4,          CPU_VENDOR_MARVELL)
+
+  UARCH_END
+
+  return arch;
+}
+
+char* get_str_uarch(struct cpuInfo* cpu) {
+  return cpu->arch->uarch_str;
+}
+
+void free_uarch_struct(struct uarch* arch) {
+  free(arch->uarch_str);
+  free(arch);
+}

src/arm/uarch.h

@@ -0,0 +1,12 @@
+#ifndef __UARCH__
+#define __UARCH__
+
+#include <stdint.h>
+
+#include "midr.h"
+
+struct uarch* get_uarch_from_midr(uint32_t midr, struct cpuInfo* cpu);
+char* get_str_uarch(struct cpuInfo* cpu);
+void free_uarch_struct(struct uarch* arch);
+
+#endif

src/arm/udev.c

@@ -0,0 +1,195 @@
+#include "../common/global.h"
+#include "udev.h"
+#include "midr.h"
+
+#define _PATH_DEVICETREE_MODEL       "/sys/firmware/devicetree/base/model"
+#define _PATH_CPUS_PRESENT           _PATH_SYS_SYSTEM _PATH_SYS_CPU "/present"
+#define _PATH_CPUINFO                "/proc/cpuinfo"
+//#define _PATH_CPUINFO                "cpuinfo_debug"
+
+#define CPUINFO_CPU_IMPLEMENTER_STR  "CPU implementer\t: "
+#define CPUINFO_CPU_ARCHITECTURE_STR "CPU architecture: "
+#define CPUINFO_CPU_VARIANT_STR      "CPU variant\t: "
+#define CPUINFO_CPU_PART_STR         "CPU part\t: "
+#define CPUINFO_CPU_REVISION_STR     "CPU revision\t: "
+#define CPUINFO_HARDWARE_STR         "Hardware\t: "
+#define CPUINFO_REVISION_STR         "Revision\t: "
+
+#define CPUINFO_CPU_STRING "processor"
+
+// https://www.kernel.org/doc/html/latest/core-api/cpu_hotplug.html
+int get_ncores_from_cpuinfo() {
+  // Examples:
+  // 0-271
+  // 0-7
+  // 0
+
+  int filelen;
+  char* buf;
+  if((buf = read_file(_PATH_CPUS_PRESENT, &filelen)) == NULL) {
+    printWarn("read_file: %s: %s\n", _PATH_CPUS_PRESENT, strerror(errno));
+    return UNKNOWN;
+  }
+
+  int ncores;
+  char* tmp1;
+  if((tmp1 = strstr(buf, "-")) == NULL) {
+    // file contains no - character, we assume that it contains 0,
+    // which means that the CPU contains only one core
+    return 1;
+  }
+  else {
+    tmp1++;
+  }
+  char* tmp2 = strstr(buf, "\n");
+  char ncores_str[filelen];
+  memset(ncores_str, 0, sizeof(char) * filelen);
+  memcpy(ncores_str, tmp1, tmp2-tmp1);
+
+  char* end;
+  errno = 0;
+  ncores = strtol(ncores_str, &end, 10) + 1;
+  if(errno != 0) {
+    printWarn("strtol: %s:\n", strerror(errno));
+    return UNKNOWN;
+  }
+
+  free(buf);
+
+  return ncores;
+}
+
+long parse_cpuinfo_field(char* buf, char* field_str, int field_base) {
+  char* tmp = strstr(buf, field_str);
+  if(tmp == NULL) return -1;
+  tmp += strlen(field_str);
+
+  char* end;
+  errno = 0;
+  long ret = strtol(tmp, &end, field_base);
+  if(errno != 0) {
+    printWarn("strtol: %s:\n", strerror(errno));
+    return -1;
+  }
+
+  return ret;
+}
+// https://developer.arm.com/docs/ddi0595/h/aarch32-system-registers/midr
+// https://static.docs.arm.com/ddi0595/h/SysReg_xml_v86A-2020-06.pdf
+uint32_t get_midr_from_cpuinfo(uint32_t core, bool* success) {
+  int filelen;
+  char* buf;
+  *success = true;
+  if((buf = read_file(_PATH_CPUINFO, &filelen)) == NULL) {
+    printWarn("read_file: %s: %s\n", _PATH_CPUINFO, strerror(errno));
+    *success = false;
+    return 0;
+  }
+
+  char* tmp = strstr(buf, CPUINFO_CPU_STRING);
+  uint32_t current_core = 0;
+  while(core != current_core && tmp != NULL) {
+    tmp++;
+    current_core++;
+    tmp = strstr(tmp, CPUINFO_CPU_STRING);
+  }
+
+  if(tmp == NULL) {
+    *success = false;
+    return 0;
+  }
+
+  uint32_t cpu_implementer;
+  uint32_t cpu_architecture;
+  uint32_t cpu_variant;
+  uint32_t cpu_part;
+  uint32_t cpu_revision;
+  uint32_t midr = 0;
+  long ret;
+
+  if ((ret = parse_cpuinfo_field(tmp, CPUINFO_CPU_IMPLEMENTER_STR, 16)) < 0) {
+    printBug("get_midr_from_cpuinfo: Failed parsing cpu_implementer\n");
+    *success = false;
+    return 0;
+  }
+  cpu_implementer = (uint32_t) ret;
+
+  if ((ret = parse_cpuinfo_field(tmp, CPUINFO_CPU_ARCHITECTURE_STR, 10)) < 0) {
+    printBug("get_midr_from_cpuinfo: Failed parsing cpu_architecture\n");
+    *success = false;
+    return 0;
+  }
+  cpu_architecture = (uint32_t) 0xF; // Why?
+
+  if ((ret = parse_cpuinfo_field(tmp, CPUINFO_CPU_VARIANT_STR, 16)) < 0) {
+    printBug("get_midr_from_cpuinfo: Failed parsing cpu_variant\n");
+    *success = false;
+    return 0;
+  }
+  cpu_variant = (uint32_t) ret;
+
+  if ((ret = parse_cpuinfo_field(tmp, CPUINFO_CPU_PART_STR, 16)) < 0) {
+    printBug("get_midr_from_cpuinfo: Failed parsing cpu_part\n");
+    *success = false;
+    return 0;
+  }
+  cpu_part = (uint32_t) ret;
+
+  if ((ret = parse_cpuinfo_field(tmp, CPUINFO_CPU_REVISION_STR, 10)) < 0) {
+    printBug("get_midr_from_cpuinfo: Failed parsing cpu_revision\n");
+    *success = false;
+    return 0;
+  }
+  cpu_revision = (uint32_t) ret;
+
+  midr = midr_set_implementer(midr, cpu_implementer);
+  midr = midr_set_variant(midr, cpu_variant);
+  midr = midr_set_architecture(midr, cpu_architecture);
+  midr = midr_set_part(midr, cpu_part);
+  midr = midr_set_revision(midr, cpu_revision);
+
+  return midr;
+}
+
+char* get_field_from_cpuinfo(char* CPUINFO_FIELD) {
+  int filelen;
+  char* buf;
+  if((buf = read_file(_PATH_CPUINFO, &filelen)) == NULL) {
+    printWarn("read_file: %s: %s:\n", _PATH_CPUINFO, strerror(errno));
+    return NULL;
+  }
+
+  char* tmp1 = strstr(buf, CPUINFO_FIELD);
+  if(tmp1 == NULL) return NULL;
+  tmp1 = tmp1 + strlen(CPUINFO_FIELD);
+  char* tmp2 = strstr(tmp1, "\n");
+
+  int strlen = (1 + (tmp2-tmp1));
+  char* hardware = emalloc(sizeof(char) * strlen);
+  memset(hardware, 0, sizeof(char) * strlen);
+  strncpy(hardware, tmp1, tmp2-tmp1);
+
+  return hardware;
+}
+
+char* get_hardware_from_cpuinfo() {
+  return get_field_from_cpuinfo(CPUINFO_HARDWARE_STR);
+}
+
+char* get_revision_from_cpuinfo() {
+  return get_field_from_cpuinfo(CPUINFO_REVISION_STR);
+}
+
+bool is_raspberry_pi() {
+  int filelen;
+  char* buf;
+  if((buf = read_file(_PATH_DEVICETREE_MODEL, &filelen)) == NULL) {
+    return false;
+  }
+
+  char* tmp;
+  if((tmp = strstr(buf, "Raspberry Pi")) == NULL) {
+    return false;
+  }
+  return true;
+}

src/arm/udev.h

@@ -0,0 +1,14 @@
+#ifndef __UDEV_ARM__
+#define __UDEV_ARM__
+
+#include "../common/udev.h"
+
+#define UNKNOWN -1
+int get_ncores_from_cpuinfo();
+uint32_t get_midr_from_cpuinfo(uint32_t core, bool* success);
+char* get_hardware_from_cpuinfo();
+char* get_revision_from_cpuinfo();
+bool is_raspberry_pi();
+
+#endif
+

src/ascii.h

@@ -1,49 +0,0 @@
-#ifndef __ASCII__
-#define __ASCII__
-
-#define NUMBER_OF_LINES   19
-#define LINE_SIZE         62
-
-#define AMD_ASCII \
-"                                                              \
-                                                              \
-                                                              \
-                                                              \
-                                                              \
-                                                              \
-     @@@@      @@@       @@@   @@@@@@@@        ############   \
-    @@@@@@     @@@@@    @@@@   @@@    @@@@       ##########   \
-   @@@  @@@    @@@@@@@@@@@@@   @@@      @@      #      ####   \
-  @@@    @@@   @@@  @@@  @@@   @@@      @@@   ###      ####   \
- @@@@@@@@@@@@  @@@       @@@   @@@     @@@   ####    ## ###   \
- @@@      @@@  @@@       @@@   @@@@@@@@@     ########    ##   \
-                                                              \
-                                                              \
-                                                              \
-                                                              \
-                                                              \
-                                                              \
-                                                             "
-
-#define INTEL_ASCII \
-"                              ################                \
-                      #######                #######          \
-                 ####                              ####       \
-             ###                                     ####     \
-        ###                                             ###   \
-        ###                                             ###   \
-     #                    ###                ###        ###   \
-   ##   ###   #########   ######   ######    ###        ###   \
-  ##    ###   ###    ###  ###    ####  ####  ###        ###   \
- ##     ###   ###    ###  ###    ###    ###  ###       ###    \
-##      ###   ###    ###  ###    ##########  ###     ####     \
-##      ###   ###    ###  ###    ###         ###   #####      \
-##       ##   ###    ###   #####  #########   ##  ###         \
-###                                                           \
- ###                                                          \
- ####                                        ####             \
-   #####                               ##########             \
-     ##########               ################                \
-         ###############################                     "
-
-#endif

src/common/args.c

@@ -0,0 +1,275 @@
+#include <getopt.h>
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+#include "args.h"
+#include "global.h"
+
+#define NUM_COLORS      4
+
+#define COLOR_STR_INTEL "intel"
+#define COLOR_STR_AMD   "amd"
+#define COLOR_STR_IBM   "ibm"
+#define COLOR_STR_ARM   "arm"
+
+static const char *SYTLES_STR_LIST[] = {
+  [STYLE_EMPTY]   = NULL,
+  [STYLE_FANCY]   = "fancy",
+  [STYLE_RETRO]   = "retro",
+  [STYLE_LEGACY]  = "legacy",
+  [STYLE_INVALID] = NULL
+};
+
+struct args_struct {
+  bool debug_flag;
+  bool help_flag;
+  bool raw_flag;
+  bool verbose_flag;
+  bool version_flag;
+  STYLE style;
+  struct color** colors;
+};
+
+const char args_chr[] = {
+  /* [ARG_CHAR_STYLE]   = */ 's',
+  /* [ARG_CHAR_COLOR]   = */ 'c',
+  /* [ARG_CHAR_HELP]    = */ 'h',
+  /* [ARG_CHAR_RAW]     = */ 'r',
+  /* [ARG_CHAR_DEBUG]   = */ 'd',
+  /* [ARG_CHAR_VERBOSE] = */ 'v',
+  /* [ARG_CHAR_VERSION] = */ 'V',
+};
+
+const char *args_str[] = {
+  /* [ARG_CHAR_STYLE]   = */ "style",
+  /* [ARG_CHAR_COLOR]   = */ "color",
+  /* [ARG_CHAR_HELP]    = */ "help",
+  /* [ARG_CHAR_RAW]     = */ "raw",
+  /* [ARG_CHAR_DEBUG]   = */ "debug",
+  /* [ARG_CHAR_VERBOSE] = */ "verbose",
+  /* [ARG_CHAR_VERSION] = */ "version",
+};
+
+static struct args_struct args;
+
+STYLE get_style() {
+  return args.style;
+}
+
+struct color** get_colors() {
+  return args.colors;
+}
+
+bool show_help() {
+  return args.help_flag;
+}
+
+bool show_version() {
+  return args.version_flag;
+}
+
+bool show_debug() {
+  return args.debug_flag;
+}
+
+bool show_raw() {
+  return args.raw_flag;
+}
+
+bool verbose_enabled() {
+  return args.verbose_flag;
+}
+
+int max_arg_str_length() {
+  int max_len = -1;
+  int len = sizeof(args_str) / sizeof(args_str[0]);
+  for(int i=0; i < len; i++) {
+    max_len = max(max_len, (int) strlen(args_str[i]));
+  }
+  return max_len;
+}
+
+STYLE parse_style(char* style) {
+  uint8_t i = 0;
+  uint8_t styles_count = sizeof(SYTLES_STR_LIST) / sizeof(SYTLES_STR_LIST[0]);
+
+  while(i != styles_count && (SYTLES_STR_LIST[i] == NULL || strcmp(SYTLES_STR_LIST[i], style) != 0))
+    i++;
+
+  if(i == styles_count)
+    return STYLE_INVALID;
+
+  return i;
+}
+
+void free_colors_struct(struct color** cs) {
+  for(int i=0; i < NUM_COLORS; i++) {
+    free(cs[i]);
+  }
+  free(cs);
+}
+
+bool parse_color(char* optarg_str, struct color*** cs) {
+  for(int i=0; i < NUM_COLORS; i++) {
+    (*cs)[i] = emalloc(sizeof(struct color));
+  }
+
+  struct color** c = *cs;
+  int32_t ret;
+  char* str_to_parse = NULL;
+  char* color_to_copy = NULL;
+  bool free_ptr = true;
+
+  if(strcmp(optarg_str, COLOR_STR_INTEL) == 0) color_to_copy = COLOR_DEFAULT_INTEL;
+  else if(strcmp(optarg_str, COLOR_STR_AMD) == 0) color_to_copy = COLOR_DEFAULT_AMD;
+  else if(strcmp(optarg_str, COLOR_STR_IBM) == 0) color_to_copy = COLOR_DEFAULT_IBM;
+  else if(strcmp(optarg_str, COLOR_STR_ARM) == 0) color_to_copy = COLOR_DEFAULT_ARM;
+  else {
+    str_to_parse = optarg_str;
+    free_ptr = false;
+  }
+
+  if(str_to_parse == NULL) {
+    str_to_parse = emalloc(sizeof(char) * (strlen(color_to_copy) + 1));
+    strcpy(str_to_parse, color_to_copy);
+  }
+
+  ret = sscanf(str_to_parse, "%d,%d,%d:%d,%d,%d:%d,%d,%d:%d,%d,%d",
+               &c[0]->R, &c[0]->G, &c[0]->B,
+               &c[1]->R, &c[1]->G, &c[1]->B,
+               &c[2]->R, &c[2]->G, &c[2]->B,
+               &c[3]->R, &c[3]->G, &c[3]->B);
+
+  if(ret != 12) {
+    printErr("Expected to read 12 values for color but read %d", ret);
+    return false;
+  }
+
+  for(int i=0; i < NUM_COLORS; i++) {
+    if(c[i]->R < 0 || c[i]->R > 255) {
+      printErr("Red in color %d is invalid: %d; must be in range (0, 255)", i+1, c[i]->R);
+      return false;
+    }
+    if(c[i]->G < 0 || c[i]->G > 255) {
+      printErr("Green in color %d is invalid: %d; must be in range (0, 255)", i+1, c[i]->G);
+      return false;
+    }
+    if(c[i]->B < 0 || c[i]->B > 255) {
+      printErr("Blue in color %d is invalid: %d; must be in range (0, 255)", i+1, c[i]->B);
+      return false;
+    }
+  }
+
+  if(free_ptr) free (str_to_parse);
+
+  return true;
+}
+
+char* build_short_options() {
+  const char *c = args_chr;
+  int len = sizeof(args_chr) / sizeof(args_chr[0]);
+  char* str = (char *) emalloc(sizeof(char) * (len*2 + 1));
+  memset(str, 0, sizeof(char) * (len*2 + 1));
+
+#ifdef ARCH_X86
+  sprintf(str, "%c:%c:%c%c%c%c%c",
+  c[ARG_STYLE], c[ARG_COLOR], c[ARG_HELP], c[ARG_RAW],
+  c[ARG_DEBUG], c[ARG_VERBOSE], c[ARG_VERSION]);
+#else
+  sprintf(str, "%c:%c:%c%c%c%c",
+  c[ARG_STYLE], c[ARG_COLOR], c[ARG_HELP],
+  c[ARG_DEBUG], c[ARG_VERBOSE], c[ARG_VERSION]);
+#endif
+
+  return str;
+}
+
+bool parse_args(int argc, char* argv[]) {
+  int opt;
+  int option_index = 0;
+  opterr = 0;
+
+  bool color_flag = false;
+  args.debug_flag = false;
+  args.raw_flag = false;
+  args.verbose_flag = false;
+  args.help_flag = false;
+  args.style = STYLE_EMPTY;
+  args.colors = NULL;
+
+  const struct option long_options[] = {
+    {args_str[ARG_STYLE],   required_argument, 0, args_chr[ARG_STYLE]   },
+    {args_str[ARG_COLOR],   required_argument, 0, args_chr[ARG_COLOR]   },
+    {args_str[ARG_HELP],    no_argument,       0, args_chr[ARG_HELP]    },
+#ifdef ARCH_X86
+    {args_str[ARG_RAW],     no_argument,       0, args_chr[ARG_RAW]     },
+#endif
+    {args_str[ARG_DEBUG],   no_argument,       0, args_chr[ARG_DEBUG]   },
+    {args_str[ARG_VERBOSE], no_argument,       0, args_chr[ARG_VERBOSE] },
+    {args_str[ARG_VERSION], no_argument,       0, args_chr[ARG_VERSION] },
+    {0, 0, 0, 0}
+  };
+
+  char* short_options = build_short_options();
+  opt = getopt_long(argc, argv, short_options, long_options, &option_index);
+
+  while (!args.help_flag && !args.debug_flag && !args.version_flag && opt != -1) {
+    if(opt == args_chr[ARG_COLOR]) {
+      if(color_flag) {
+        printErr("Color option specified more than once");
+        return false;
+      }
+      color_flag  = true;
+      args.colors = emalloc(sizeof(struct color *) * NUM_COLORS);
+      if(!parse_color(optarg, &args.colors)) {
+        return false;
+      }
+    }
+    else if(opt == args_chr[ARG_STYLE]) {
+      if(args.style != STYLE_EMPTY) {
+        printErr("Style option specified more than once");
+        return false;
+      }
+      args.style = parse_style(optarg);
+      if(args.style == STYLE_INVALID) {
+        printErr("Invalid style '%s'",optarg);
+        return false;
+      }
+      break;
+    }
+    else if(opt == args_chr[ARG_HELP]) {
+      args.help_flag  = true;
+    }
+    else if(opt == args_chr[ARG_RAW]) {
+       args.raw_flag  = true;
+    }
+    else if(opt == args_chr[ARG_VERBOSE]) {
+      args.verbose_flag  = true;
+    }
+    else if(opt == args_chr[ARG_DEBUG]) {
+      args.debug_flag  = true;
+    }
+    else if(opt == args_chr[ARG_VERSION]) {
+      args.version_flag = true;
+    }
+    else {
+      printWarn("Invalid options");
+      args.help_flag  = true;
+    }
+
+    option_index = 0;
+    opt = getopt_long(argc, argv, short_options, long_options, &option_index);
+  }
+
+  if(optind < argc) {
+    printWarn("Invalid options");
+    args.help_flag  = true;
+  }
+
+  if((args.help_flag + args.version_flag + color_flag) > 1) {
+    printWarn("You should specify just one option");
+    args.help_flag  = true;
+  }
+
+  return true;
+}

src/common/args.h

@@ -0,0 +1,48 @@
+#ifndef __ARGS__
+#define __ARGS__
+
+#include <stdbool.h>
+#include <stdint.h>
+
+struct color {
+  int32_t R;
+  int32_t G;
+  int32_t B;
+};
+
+enum {
+  STYLE_EMPTY,
+  STYLE_FANCY,
+  STYLE_WILD,
+  STYLE_RETRO,
+  STYLE_LEGACY,
+  STYLE_INVALID
+};
+
+enum {
+  ARG_STYLE,
+  ARG_COLOR,
+  ARG_HELP,
+  ARG_RAW,
+  ARG_DEBUG,
+  ARG_VERBOSE,
+  ARG_VERSION
+};
+
+extern const char args_chr[];
+extern const char *args_str[];
+
+#include "printer.h"
+
+int max_arg_str_length();
+bool parse_args(int argc, char* argv[]);
+bool show_help();
+bool show_raw();
+bool show_debug();
+bool show_version();
+bool verbose_enabled();
+void free_colors_struct(struct color** cs);
+struct color** get_colors();
+STYLE get_style();
+
+#endif

src/common/ascii.h

@@ -0,0 +1,232 @@
+#ifndef __ASCII__
+#define __ASCII__
+
+#define NUMBER_OF_LINES   19
+#define LINE_SIZE         62
+
+#define AMD_ASCII \
+"                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              \
+     @@@@      @@@       @@@   @@@@@@@@        ############   \
+    @@@@@@     @@@@@   @@@@@   @@@    @@@        ##########   \
+   @@@  @@@    @@@@@@@@@@@@@   @@@      @@      #     #####   \
+  @@@    @@@   @@@  @@@  @@@   @@@      @@    ###     #####   \
+ @@@@@@@@@@@@  @@@       @@@   @@@    @@@    #########  ###   \
+ @@@      @@@  @@@       @@@   @@@@@@@@@     ########    ##   \
+                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              "
+
+#define INTEL_ASCII \
+"                              ################                \
+                      #######                #######          \
+                 ####                              ####       \
+             ###                                     ####     \
+        ###                                             ###   \
+        ###                                             ###   \
+     #                    ###                ###        ###   \
+   ##   ###   #########   ######   ######    ###        ###   \
+  ##    ###   ###    ###  ###    ####  ####  ###        ###   \
+ ##     ###   ###    ###  ###    ###    ###  ###       ###    \
+##      ###   ###    ###  ###    ##########  ###     ####     \
+##      ###   ###    ###  ###    ###         ###   #####      \
+##       ##   ###    ###   #####  #########   ##  ###         \
+###                                                           \
+ ###                                                          \
+ ####                                        ####             \
+   #####                               ##########             \
+     ##########               ################                \
+         ###############################                      "
+                                                             
+#define SNAPDRAGON_ASCII \
+"                                                              \
+                     @@########                               \
+                  @@@@@###########                            \
+            @@  @@@@@#################                        \
+          @@@@@@@@@@####################                      \
+         @@@@@@@@@@@@#####################                    \
+        @@@@@@@@@@@@@@@####################                   \
+        @@@@@@@@@@@@@@@@@###################                  \
+        @@@@@@@@@@@@@@@@@@@@################                  \
+           @@@@@@@@@@@@@@@@@@@@#############                  \
+              @@@@@@@@@@@@@@@@@@############                  \
+       @          @@@@@@@@@@@@@@@###########                  \
+        @@@@@       @@@@@@@@@@@@@##########                   \
+         @@@@@@@@@   @@@@@@@@@@@@########                     \
+           @@@@@@@@@  @@@@@@@@@@#######                       \
+              @@@@@@@@@@@@@@@@#######                         \
+                  @@@@###########                             \
+                                                              \
+                                                              "
+                                                             
+#define MEDIATEK_ASCII \
+"                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              \
+      ##  ## ######  ######  #     ### @@@@@@ @@@@@@ @@  @@   \
+     ### ### #       #    #  #    ####   @@   @      @@ @@    \
+    ######## # ###   #    #  #   ## ##   @@   @ @@@  @@@@     \
+   ## ### ## #       #    #  #  ##  ##   @@   @      @@ @@    \
+  ##  ##  ## ######  #####   # ##   ##   @@   @@@@@@ @@  @@   \
+                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              "
+
+#define EXYNOS_ASCII \
+"                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              \
+                         ##  ##  ##                           \
+                           ##  ##                             \
+                             ##                               \
+                           ##  ##                             \
+                         ##  ##  ##                           \
+                                                              \
+                         SAMSUNG                              \
+                         Exynos                               \
+                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              "
+                                                              
+#define KIRIN_ASCII \
+"                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                   #######                    \
+       #####             ####################                 \
+          ######################################              \
+            #######################################           \
+               #######################################        \
+                 ##############################               \
+                ##########################                    \
+             #########################                        \
+           ########################                           \
+        ########################                              \
+     #########################                                \
+   #########################                                  \
+                                                              \
+                                                              "                                                                                                                           
+                                                              
+#define BROADCOM_ASCII \
+"                                                              \
+                    ################                          \
+               ##########################                     \
+            ################################                  \
+          ################@@@@################                \
+         ################@@@@@@################               \
+        #################@@@@@@#################              \
+       #################@@@@@@@@#################             \
+       #################@@@@@@@@#################             \
+       ################@@@@##@@@@################             \
+       ################@@@@##@@@@################             \
+       ###############@@@@####@@@@###############             \
+        @@@@@@@@@@####@@@@####@@@@####@@@@@@@@@@              \
+         ######@@@@@@@@@@######@@@@@@@@@@######               \
+           ##################################                 \
+             ##############################                   \
+                ########################                      \
+                    ###############                           \
+                                                              "
+                                                                                                              
+#define ARM_ASCII \
+"                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              \
+      ############     ##########   ####  ######  ########    \
+   ###############     #########    #######################   \
+  ####        ####     ####         #####   #######   #####   \
+ ####         ####     ####         ####     #####     ####   \
+ ####         ####     ####         ####     ####      ####   \
+  ####       #####     ####         ####     ####      ####   \
+   ###############     ####         ####     ####      ####   \
+    ########  ####     ####         ####     ####      ####   \
+                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              "                                                                                                               
+
+// jp2a --height=17 ibm.jpg
+#define IBM_ASCII \
+"                                                              \
+                                                              \
+                                                              \
+ ############ ################   ##########        ########## \
+                                                              \
+ ############ ################## ############    ############ \
+                                                              \
+    ######       ######    ######    ####################     \
+                                                              \
+    ######       ##############      ####################     \
+                                                              \
+    ######       ######    ######    #####  ######  #####     \
+                                                              \
+ ############ ################## #########   ####   ######### \
+                                                              \
+ ############ ################   #########    ##    ######### \
+                                                              \
+                                                              \
+                                                              "
+
+
+#define UNKNOWN_ASCII \
+"                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              "
+                                                             
+static const char* ASCII_ARRAY [] = {
+  AMD_ASCII,
+  INTEL_ASCII,
+  ARM_ASCII,
+  SNAPDRAGON_ASCII,
+  MEDIATEK_ASCII,
+  EXYNOS_ASCII,
+  KIRIN_ASCII,
+  BROADCOM_ASCII,
+  IBM_ASCII,
+  UNKNOWN_ASCII
+};                                                             
+
+#endif

src/common/cpu.c

@@ -0,0 +1,233 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <assert.h>
+#include <stdbool.h>
+
+#include "../common/global.h"
+#include "cpu.h"
+
+#ifdef ARCH_X86
+  #include "../x86/uarch.h"
+  #include "../x86/apic.h"
+#elif ARCH_PPC
+  #include "../ppc/uarch.h"
+#elif ARCH_ARM
+  #include "../arm/uarch.h"
+#endif
+
+#define STRING_YES        "Yes"
+#define STRING_NO         "No"
+#define STRING_NONE       "None"
+#define STRING_MEGAHERZ   "MHz"
+#define STRING_GIGAHERZ   "GHz"
+#define STRING_KILOBYTES  "KB"
+#define STRING_MEGABYTES  "MB"
+
+VENDOR get_cpu_vendor(struct cpuInfo* cpu) {
+  return cpu->cpu_vendor;
+}
+
+int64_t get_freq(struct frequency* freq) {
+  return freq->max;
+}
+
+#if defined(ARCH_X86) || defined(ARCH_PPC)
+char* get_str_cpu_name(struct cpuInfo* cpu) {
+  return cpu->cpu_name;
+}
+
+char* get_str_sockets(struct topology* topo) {
+  char* string = emalloc(sizeof(char) * 2);
+  int32_t sanity_ret = snprintf(string, 2, "%d", topo->sockets);
+  if(sanity_ret < 0) {
+    printBug("get_str_sockets: snprintf returned a negative value for input: '%d'", topo->sockets);
+    return NULL;
+  }
+  return string;
+}
+
+uint32_t get_nsockets(struct topology* topo) {
+  return topo->sockets;
+}
+#endif
+
+int32_t get_value_as_smallest_unit(char ** str, uint32_t value) {
+  int32_t ret;
+  int max_len = 10; // Max is 8 for digits, 2 for units
+  *str = emalloc(sizeof(char)* (max_len + 1));
+
+  if(value/1024 >= 1024)
+    ret = snprintf(*str, max_len, "%.4g"STRING_MEGABYTES, (double)value/(1<<20));
+  else
+    ret = snprintf(*str, max_len, "%.4g"STRING_KILOBYTES, (double)value/(1<<10));
+
+  return ret;
+}
+
+// String functions
+char* get_str_cache_two(int32_t cache_size, uint32_t physical_cores) {
+  char* tmp1;
+  char* tmp2;
+  int32_t tmp1_len = get_value_as_smallest_unit(&tmp1, cache_size);
+  int32_t tmp2_len = get_value_as_smallest_unit(&tmp2, cache_size * physical_cores);
+
+  // tmp1_len for first output, 2 for ' (', tmp2_len for second output and 7 for ' Total)'
+  uint32_t size = tmp1_len + 2 + tmp2_len + 7 + 1;
+  char* string = emalloc(sizeof(char) * size);
+
+  if(tmp1_len < 0) {
+    printBug("get_value_as_smallest_unit: snprintf failed for input: %d\n", cache_size);
+    return NULL;
+  }
+  if(tmp2_len < 0) {
+    printBug("get_value_as_smallest_unit: snprintf failed for input: %d\n", cache_size * physical_cores);
+    return NULL;
+  }
+
+  if(snprintf(string, size, "%s (%s Total)", tmp1, tmp2) < 0) {
+    printBug("get_str_cache_two: snprintf failed for input: '%s' and '%s'\n", tmp1, tmp2);
+    return NULL;
+  }
+
+  free(tmp1);
+  free(tmp2);
+
+  return string;
+}
+
+char* get_str_cache_one(int32_t cache_size) {
+  char* string;
+  int32_t str_len = get_value_as_smallest_unit(&string, cache_size);
+
+  if(str_len < 0) {
+    printBug("get_value_as_smallest_unit: snprintf failed for input: %d", cache_size);
+    return NULL;
+  }
+
+  return string;
+}
+
+char* get_str_cache(int32_t cache_size, int32_t num_caches) {
+  if(num_caches > 1)
+    return get_str_cache_two(cache_size, num_caches);
+  else
+    return get_str_cache_one(cache_size);
+}
+
+char* get_str_l1i(struct cache* cach) {
+  return get_str_cache(cach->L1i->size, cach->L1i->num_caches);
+}
+
+char* get_str_l1d(struct cache* cach) {
+  return get_str_cache(cach->L1d->size, cach->L1d->num_caches);
+}
+
+char* get_str_l2(struct cache* cach) {
+  assert(cach->L2->exists);
+  return get_str_cache(cach->L2->size, cach->L2->num_caches);
+}
+
+char* get_str_l3(struct cache* cach) {
+  if(!cach->L3->exists)
+    return NULL;
+  return get_str_cache(cach->L3->size, cach->L3->num_caches);
+}
+
+char* get_str_freq(struct frequency* freq) {
+  //Max 3 digits and 3 for '(M/G)Hz' plus 1 for '\0'
+  uint32_t size = (5+1+3+1);
+  assert(strlen(STRING_UNKNOWN)+1 <= size);
+  char* string = emalloc(sizeof(char)*size);
+  memset(string, 0, sizeof(char)*size);
+
+  if(freq->max == UNKNOWN_FREQ || freq->max < 0)
+    snprintf(string,strlen(STRING_UNKNOWN)+1,STRING_UNKNOWN);
+  else if(freq->max >= 1000)
+    snprintf(string,size,"%.3f "STRING_GIGAHERZ,(float)(freq->max)/1000);
+  else
+    snprintf(string,size,"%d "STRING_MEGAHERZ,freq->max);
+
+  return string;
+}
+
+char* get_str_peak_performance(int64_t flops) {
+  char* str;
+
+  if(flops == -1) {
+    str = emalloc(sizeof(char) * (strlen(STRING_UNKNOWN) + 1));
+    strncpy(str, STRING_UNKNOWN, strlen(STRING_UNKNOWN) + 1);
+    return str;
+  }
+
+  // 7 for digits (e.g, XXXX.XX), 7 for XFLOP/s
+  double flopsd = (double) flops;
+  uint32_t max_size = 7+1+7+1;
+  str = ecalloc(max_size, sizeof(char));
+
+  if(flopsd >= (double)1000000000000.0)
+    snprintf(str, max_size, "%.2f TFLOP/s", flopsd/1000000000000);
+  else if(flopsd >= 1000000000.0)
+    snprintf(str, max_size, "%.2f GFLOP/s", flopsd/1000000000);
+  else
+    snprintf(str, max_size, "%.2f MFLOP/s", flopsd/1000000);
+
+  return str;
+}
+
+void init_topology_struct(struct topology* topo, struct cache* cach) {
+  topo->total_cores = 0;
+  topo->cach = cach;
+#if defined(ARCH_X86) || defined(ARCH_PPC)
+  topo->physical_cores = 0;
+  topo->logical_cores = 0;
+  topo->smt_supported = 0;
+  topo->sockets = 0;
+#ifdef ARCH_X86
+  topo->smt_available = 0;
+  topo->apic = emalloc(sizeof(struct apic));
+#endif
+#endif
+}
+
+void init_cache_struct(struct cache* cach) {
+  cach->L1i = emalloc(sizeof(struct cach));
+  cach->L1d = emalloc(sizeof(struct cach));
+  cach->L2 = emalloc(sizeof(struct cach));
+  cach->L3 = emalloc(sizeof(struct cach));
+
+  cach->cach_arr = emalloc(sizeof(struct cach*) * 4);
+  cach->cach_arr[0] = cach->L1i;
+  cach->cach_arr[1] = cach->L1d;
+  cach->cach_arr[2] = cach->L2;
+  cach->cach_arr[3] = cach->L3;
+
+  cach->max_cache_level = 0;
+  cach->L1i->exists = false;
+  cach->L1d->exists = false;
+  cach->L2->exists = false;
+  cach->L3->exists = false;
+}
+
+void free_cache_struct(struct cache* cach) {
+  for(int i=0; i < 4; i++) free(cach->cach_arr[i]);
+  free(cach->cach_arr);
+  free(cach);
+}
+
+void free_freq_struct(struct frequency* freq) {
+  free(freq);
+}
+
+void free_hv_struct(struct hypervisor* hv) {
+  free(hv);
+}
+
+void free_cpuinfo_struct(struct cpuInfo* cpu) {
+  free_uarch_struct(cpu->arch);
+  free_hv_struct(cpu->hv);
+  #ifdef ARCH_X86
+  free(cpu->cpu_name);
+  #endif
+  free(cpu);
+}

src/common/cpu.h

@@ -0,0 +1,174 @@
+#ifndef __CPU__
+#define __CPU__
+
+#include <stdint.h>
+#include <stdbool.h>
+
+enum {
+// ARCH_X86
+  CPU_VENDOR_INTEL,
+  CPU_VENDOR_AMD,
+// ARCH_ARM
+  CPU_VENDOR_ARM,
+  CPU_VENDOR_BROADCOM,
+  CPU_VENDOR_CAVIUM,
+  CPU_VENDOR_NVIDIA,
+  CPU_VENDOR_APM,
+  CPU_VENDOR_QUALCOMM,
+  CPU_VENDOR_HUAWUEI,
+  CPU_VENDOR_SAMSUNG,
+  CPU_VENDOR_MARVELL,
+// OTHERS
+  CPU_VENDOR_UNKNOWN,
+  CPU_VENDOR_INVALID
+};
+
+enum {
+  HV_VENDOR_KVM,
+  HV_VENDOR_QEMU,
+  HV_VENDOR_HYPERV,
+  HV_VENDOR_VMWARE,
+  HV_VENDOR_XEN,
+  HV_VENDOR_PARALLELS,
+  HV_VENDOR_INVALID
+};
+
+#define UNKNOWN_FREQ -1
+#define CPU_NAME_MAX_LENGTH 64
+
+typedef int32_t VENDOR;
+
+struct frequency {
+  int32_t base;
+  int32_t max;
+};
+
+struct hypervisor {
+  bool present;
+  char* hv_name;
+  VENDOR hv_vendor;
+};
+
+struct cach {
+  int32_t size;
+  uint8_t num_caches;
+  bool exists;
+  // plenty of more properties to include in the future...
+};
+
+struct cache {
+  struct cach* L1i;
+  struct cach* L1d;
+  struct cach* L2;
+  struct cach* L3;
+  struct cach** cach_arr;
+
+  uint8_t max_cache_level;
+};
+
+struct topology {
+  int32_t total_cores;  
+  struct cache* cach;
+#if defined(ARCH_X86) || defined(ARCH_PPC)
+  uint32_t physical_cores;
+  uint32_t logical_cores;
+  uint32_t sockets;
+  uint32_t smt_supported; // Number of SMT that CPU supports (equal to smt_available if SMT is enabled)
+#ifdef ARCH_X86
+  uint32_t smt_available; // Number of SMT that is currently enabled
+  struct apic* apic;
+#endif
+#endif
+};
+
+struct features {
+  bool AES; // Must be the first field of features struct!  
+#ifdef ARCH_X86
+  bool AVX;
+  bool AVX2;
+  bool AVX512;
+  bool SSE;
+  bool SSE2;
+  bool SSE3;
+  bool SSSE3;
+  bool SSE4a;
+  bool SSE4_1;
+  bool SSE4_2;
+  bool FMA3;
+  bool FMA4;
+  bool SHA;
+#elif ARCH_PPC
+  bool altivec;
+#elif ARCH_ARM
+  bool NEON;  
+  bool SHA1;
+  bool SHA2;
+  bool CRC32;
+#endif  
+};
+
+struct cpuInfo {
+  VENDOR cpu_vendor;  
+  struct uarch* arch;
+  struct hypervisor* hv;
+  struct frequency* freq;
+  struct cache* cach;
+  struct topology* topo;
+  struct features* feat;
+  int64_t peak_performance;
+
+#if defined(ARCH_X86) || defined(ARCH_PPC)
+  // CPU name from model
+  char* cpu_name;
+#endif
+
+#ifdef ARCH_X86
+  //  Max cpuids levels
+  uint32_t maxLevels;
+  // Max cpuids extended levels
+  uint32_t maxExtendedLevels;
+  // Topology Extensions (AMD only)
+  bool topology_extensions;
+#elif ARCH_PPC
+  uint32_t pvr;
+#elif ARCH_ARM
+  // Main ID register
+  uint32_t midr;
+#endif
+
+#ifdef ARCH_ARM
+  struct system_on_chip* soc;
+  // If SoC contains more than one CPU and they
+  // are different, the others will be stored in
+  // the next_cpu field
+  struct cpuInfo* next_cpu;  
+  uint8_t num_cpus;
+#endif
+};
+
+#if defined(ARCH_X86) || defined(ARCH_PPC)
+char* get_str_cpu_name(struct cpuInfo* cpu);
+char* get_str_sockets(struct topology* topo);
+uint32_t get_nsockets(struct topology* topo);
+#endif
+
+VENDOR get_cpu_vendor(struct cpuInfo* cpu);
+int64_t get_freq(struct frequency* freq);
+
+char* get_str_aes(struct cpuInfo* cpu);
+char* get_str_sha(struct cpuInfo* cpu);
+char* get_str_l1i(struct cache* cach);
+char* get_str_l1d(struct cache* cach);
+char* get_str_l2(struct cache* cach);
+char* get_str_l3(struct cache* cach);
+char* get_str_freq(struct frequency* freq);
+char* get_str_peak_performance(int64_t flops);
+
+void init_topology_struct(struct topology* topo, struct cache* cach);
+void init_cache_struct(struct cache* cach);
+
+void free_cache_struct(struct cache* cach);
+void free_freq_struct(struct frequency* freq);
+void free_cpuinfo_struct(struct cpuInfo* cpu);
+
+#endif

src/common/global.c

@@ -1,5 +1,9 @@
 #include <stdarg.h>
 #include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <errno.h>
+
 #include "global.h"
 
 #ifdef _WIN32
@@ -16,8 +20,10 @@
 
 #endif
 
-#define LOG_LEVEL_NORMAL  0
-#define LOG_LEVEL_VERBOSE 1
+enum {
+  LOG_LEVEL_NORMAL,
+  LOG_LEVEL_VERBOSE
+};
 
 int LOG_LEVEL;
 
@@ -51,10 +57,40 @@ void printBug(const char *fmt, ...) {
   vsnprintf(buffer,buffer_size, fmt, args);
   va_end(args);
   fprintf(stderr,RED "[ERROR]: "RESET "%s\n",buffer);
-  fprintf(stderr,"Please, create a new issue with this error message and your CPU model in https://github.com/Dr-Noob/cpufetch/issues\n");
+#if defined(ARCH_X86) || defined(ARCH_PPC)
+  fprintf(stderr,"Please, create a new issue with this error message and the output of 'cpufetch --debug' in https://github.com/Dr-Noob/cpufetch/issues\n");
+#elif ARCH_ARM
+  fprintf(stderr,"Please, create a new issue with this error message, your smartphone/computer model and the output of 'cpufetch --debug' in https://github.com/Dr-Noob/cpufetch/issues\n");
+#endif
 }
 
 void set_log_level(bool verbose) {
   if(verbose) LOG_LEVEL = LOG_LEVEL_VERBOSE;
   else LOG_LEVEL = LOG_LEVEL_NORMAL;
 }
+
+int max(int a, int b) {
+  return a > b ? a : b;
+}
+
+void* emalloc(size_t size) {
+  void* ptr = malloc(size);
+
+  if(ptr == NULL) {
+    printErr("malloc failed: %s", strerror(errno));
+    exit(1);
+  }
+
+  return ptr;
+}
+
+void* ecalloc(size_t nmemb, size_t size) {
+  void* ptr = calloc(nmemb, size);
+
+  if(ptr == NULL) {
+    printErr("calloc failed: %s", strerror(errno));
+    exit(1);
+  }
+
+  return ptr;
+}

src/common/global.h

@@ -2,10 +2,16 @@
 #define __GLOBAL__
 
 #include <stdbool.h>
+#include <stddef.h>
+
+#define STRING_UNKNOWN "Unknown"
 
 void set_log_level(bool verbose);
 void printWarn(const char *fmt, ...);
 void printErr(const char *fmt, ...);
 void printBug(const char *fmt, ...);
+int max(int a, int b);
+void* emalloc(size_t size);
+void* ecalloc(size_t nmemb, size_t size);
 
 #endif

src/common/main.c

@@ -0,0 +1,136 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "args.h"
+#include "printer.h"
+#include "global.h"
+
+#ifdef ARCH_X86
+  static const char* ARCH_STR = "x86_64 build";
+  #include "../x86/cpuid.h"
+#elif ARCH_PPC
+  static const char* ARCH_STR = "PowerPC build";
+  #include "../ppc/ppc.h"
+#elif ARCH_ARM
+  static const char* ARCH_STR = "ARM build";
+  #include "../arm/midr.h"
+#endif
+
+#ifdef __linux__
+  #ifdef __ANDROID__
+    static const char* OS_STR = "Android";
+  #else
+    static const char* OS_STR = "Linux";
+  #endif
+#elif __FreeBSD__
+  static const char* OS_STR = "FreeBSD";
+#elif _WIN32
+  static const char* OS_STR = "Windows";
+#elif defined __APPLE__ || __MACH__
+  static const char* OS_STR = "macOS";
+#else
+  static const char* OS_STR = "Unknown OS";
+#endif
+
+static const char* VERSION = "0.99";
+
+void print_help(char *argv[]) {
+  const char **t = args_str;
+  const char *c = args_chr;
+  int max_len = max_arg_str_length();
+
+  printf("Usage: %s [OPTION]...\n", argv[0]);
+  printf("Simple yet fancy CPU architecture fetching tool\n\n");
+
+  printf("Options: \n");
+  printf("  -%c, --%s %*s Set the color scheme (by default, cpufetch uses the system color scheme)\n", c[ARG_COLOR], t[ARG_COLOR], (int) (max_len-strlen(t[ARG_COLOR])), "");
+  printf("  -%c, --%s %*s Set the style of CPU art\n", c[ARG_STYLE], t[ARG_STYLE], (int) (max_len-strlen(t[ARG_STYLE])), "");
+#ifdef ARCH_X86
+  printf("  -%c, --%s %*s Prints CPU model and cpuid levels (debug purposes)\n", c[ARG_DEBUG], t[ARG_DEBUG], (int) (max_len-strlen(t[ARG_DEBUG])), "");
+#elif ARCH_ARM
+  printf("  -%c, --%s %*s Prints main ID register values for all cores (debug purposes)\n", c[ARG_DEBUG], t[ARG_DEBUG], (int) (max_len-strlen(t[ARG_DEBUG])), "");
+#endif
+  printf("  -%c, --%s %*s Prints extra information (if available) about how cpufetch tried fetching information\n", c[ARG_VERBOSE], t[ARG_VERBOSE], (int) (max_len-strlen(t[ARG_VERBOSE])), "");
+#ifdef ARCH_X86
+  printf("  -%c, --%s %*s Prints raw cpuid data\n", c[ARG_RAW], t[ARG_RAW], (int) (max_len-strlen(t[ARG_RAW])), "");
+#endif
+  printf("  -%c, --%s %*s Prints this help and exit\n", c[ARG_HELP], t[ARG_HELP], (int) (max_len-strlen(t[ARG_HELP])), "");
+  printf("  -%c, --%s %*s Prints cpufetch version and exit\n", c[ARG_VERSION], t[ARG_VERSION], (int) (max_len-strlen(t[ARG_VERSION])), "");
+  
+  printf("\nCOLORS: \n");
+  printf("  * \"intel\":     Use Intel default color scheme \n");
+  printf("  * \"amd\":       Use AMD default color scheme \n");
+  printf("  * \"ibm\",       Use IBM default color scheme \n");
+  printf("  * \"arm\":       Use ARM default color scheme \n");
+  printf("  * custom:      If color argument do not match \"intel\", \"amd\", \"ibm\" or \"arm\", a custom scheme can be specified.\n");
+  printf("                 4 colors must be given in RGB with the format: R,G,B:R,G,B:...\n");
+  printf("                 The first 2 colors are the CPU art color and the next 2 colors are the text colors\n");
+  
+  printf("\nSTYLES: \n");
+  printf("  * \"fancy\":     Default style\n");
+  printf("  * \"retro\":     Old cpufetch style\n");
+  printf("  * \"legacy\":    Fallback style for terminals that do not support colors\n");
+  
+  printf("\nEXAMPLES: \n");
+  printf("  Run cpufetch with Intel color scheme:\n");
+  printf("    ./cpufetch --color intel\n");
+  printf("  Run cpufetch with a custom color scheme:\n");
+  printf("    ./cpufetch --color 239,90,45:210,200,200:100,200,45:0,200,200\n");
+  
+  printf("\nBUGS: \n");
+  printf("    Report bugs to https://github.com/Dr-Noob/cpufetch/issues\n");
+  
+  printf("\nNOTE: \n");
+  printf("    Peak performance information is NOT accurate. cpufetch computes peak performance using the max\n");
+  printf("    frequency. However, to properly compute peak performance, you need to know the frequency of the\n");
+  printf("    CPU running AVX code, which is not be fetched by cpufetch since it depends on each specific CPU.\n");
+  printf("    For peak performance measurement see: https://github.com/Dr-Noob/peakperf\n");
+}
+
+void print_version() {
+  printf("cpufetch v%s (%s %s)\n",VERSION, OS_STR, ARCH_STR);
+}
+
+int main(int argc, char* argv[]) {
+  if(!parse_args(argc,argv))
+    return EXIT_FAILURE;
+
+  if(show_help()) {
+    print_help(argv);
+    return EXIT_SUCCESS;
+  }
+
+  if(show_version()) {
+    print_version();
+    return EXIT_SUCCESS;
+  }
+
+  set_log_level(verbose_enabled());
+
+  struct cpuInfo* cpu = get_cpu_info();
+  if(cpu == NULL)
+    return EXIT_FAILURE;
+
+  if(show_debug()) {
+    print_version();
+    print_debug(cpu);
+    return EXIT_SUCCESS;
+  }
+  
+  if(show_raw()) {
+  #ifdef ARCH_X86
+    print_version();
+    print_raw(cpu);
+    return EXIT_SUCCESS;
+  #else
+    printErr("raw option is valid only in x86_64");
+    return EXIT_FAILURE;
+  #endif
+  }
+  
+  if(print_cpufetch(cpu, get_style(), get_colors()))
+    return EXIT_SUCCESS;
+  else
+    return EXIT_FAILURE;
+}

src/common/printer.c

@@ -0,0 +1,833 @@
+#include <stdlib.h>
+#include <string.h>
+#include <stdio.h>
+#include <stdbool.h>
+
+#include "printer.h"
+#include "ascii.h"
+#include "../common/global.h"
+#include "../common/cpu.h"
+
+#ifdef ARCH_X86
+  #include "../x86/uarch.h"
+  #include "../x86/cpuid.h"
+#elif ARCH_PPC
+  #include "../ppc/uarch.h"
+  #include "../ppc/ppc.h"
+#else
+  #include "../arm/uarch.h"
+  #include "../arm/midr.h"
+  #include "../arm/soc.h"
+#endif
+
+#ifdef _WIN32
+#define NOMINMAX
+#include <Windows.h>
+#endif
+
+#define max(a,b) (((a)>(b))?(a):(b))
+#define MAX_ATTRIBUTES      100
+
+#define COLOR_NONE       ""
+#define COLOR_FG_BLACK   "\x1b[30;1m"
+#define COLOR_FG_RED     "\x1b[31;1m"
+#define COLOR_FG_GREEN   "\x1b[32;1m"
+#define COLOR_FG_YELLOW  "\x1b[33;1m"
+#define COLOR_FG_BLUE    "\x1b[34;1m"
+#define COLOR_FG_MAGENTA "\x1b[35;1m"
+#define COLOR_FG_CYAN    "\x1b[36;1m"
+#define COLOR_FG_WHITE   "\x1b[37;1m"
+#define COLOR_BG_BLACK   "\x1b[40;1m"
+#define COLOR_BG_RED     "\x1b[41;1m"
+#define COLOR_BG_GREEN   "\x1b[42;1m"
+#define COLOR_BG_YELLOW  "\x1b[43;1m"
+#define COLOR_BG_BLUE    "\x1b[44;1m"
+#define COLOR_BG_MAGENTA "\x1b[45;1m"
+#define COLOR_BG_CYAN    "\x1b[46;1m"
+#define COLOR_BG_WHITE   "\x1b[47;1m"
+#define COLOR_RESET      "\x1b[m"
+
+enum {
+#if defined(ARCH_X86) || defined(ARCH_PPC)
+  ATTRIBUTE_NAME,
+#elif ARCH_ARM
+  ATTRIBUTE_SOC,
+  ATTRIBUTE_CPU_NUM,
+#endif
+  ATTRIBUTE_HYPERVISOR,
+  ATTRIBUTE_UARCH,
+  ATTRIBUTE_TECHNOLOGY,
+  ATTRIBUTE_FREQUENCY,
+  ATTRIBUTE_SOCKETS,
+  ATTRIBUTE_NCORES,
+  ATTRIBUTE_NCORES_DUAL,
+#ifdef ARCH_X86
+  ATTRIBUTE_AVX,
+  ATTRIBUTE_FMA,
+#elif ARCH_PPC
+  ATTRIBUTE_ALTIVEC,
+#elif ARCH_ARM
+  ATTRIBUTE_FEATURES,
+#endif
+  ATTRIBUTE_L1i,
+  ATTRIBUTE_L1d,
+  ATTRIBUTE_L2,
+  ATTRIBUTE_L3,
+  ATTRIBUTE_PEAK
+};
+
+static const char* ATTRIBUTE_FIELDS [] = {
+#if defined(ARCH_X86) || defined(ARCH_PPC)
+  "Name:",
+#elif ARCH_ARM
+  "SoC:",
+  "",
+#endif
+  "Hypervisor:",
+  "Microarchitecture:",
+  "Technology:",
+  "Max Frequency:",
+  "Sockets:",
+  "Cores:",
+  "Cores (Total):",
+#ifdef ARCH_X86
+  "AVX:",
+  "FMA:",
+#elif ARCH_PPC
+  "Altivec: ",
+#elif defined(ARCH_ARM)
+  "Features: ",
+#endif
+  "L1i Size:",
+  "L1d Size:",
+  "L2 Size:",
+  "L3 Size:",
+  "Peak Performance:",
+};
+
+struct attribute {
+  int type;
+  char* value;
+};
+
+struct ascii {
+  char art[NUMBER_OF_LINES][LINE_SIZE+1];
+  char color1_ascii[100];
+  char color2_ascii[100];
+  char color1_text[100];
+  char color2_text[100];
+  char ascii_chars[2];
+  char reset[100];
+  struct attribute** attributes;
+  uint32_t n_attributes_set;
+  uint32_t additional_spaces;
+  VENDOR vendor;
+  STYLE style;
+};
+
+void setAttribute(struct ascii* art, int type, char* value) {
+  art->attributes[art->n_attributes_set]->value = value;
+  art->attributes[art->n_attributes_set]->type = type;
+  art->n_attributes_set++;
+
+  if(art->n_attributes_set > MAX_ATTRIBUTES) {
+    printBug("Set %d attributes, while max value is %d!", art->n_attributes_set, MAX_ATTRIBUTES);
+  }
+}
+
+char* rgb_to_ansi(struct color* c, bool background, bool bold) {
+  char* str = emalloc(sizeof(char) * 100);
+  if(background) {
+    snprintf(str, 44, "\x1b[48;2;%.3d;%.3d;%.3dm", c->R, c->G, c->B);
+  }
+  else {
+    if(bold)
+      snprintf(str, 48, "\x1b[1m\x1b[38;2;%.3d;%.3d;%.3dm", c->R, c->G, c->B);
+    else
+      snprintf(str, 44, "\x1b[38;2;%.3d;%.3d;%.3dm", c->R, c->G, c->B);
+  }
+
+  return str;
+}
+
+struct ascii* set_ascii(VENDOR vendor, STYLE style, struct color** cs) {
+  char *COL_FANCY_1, *COL_FANCY_2, *COL_FANCY_3, *COL_FANCY_4, *COL_RETRO_1, *COL_RETRO_2, *COL_RETRO_3, *COL_RETRO_4;
+  struct ascii* art = emalloc(sizeof(struct ascii));
+  art->n_attributes_set = 0;
+  art->additional_spaces = 0;
+  art->vendor = vendor;
+  art->attributes = emalloc(sizeof(struct attribute *) * MAX_ATTRIBUTES);
+  for(uint32_t i=0; i < MAX_ATTRIBUTES; i++) {
+    art->attributes[i] = emalloc(sizeof(struct attribute));
+    art->attributes[i]->type = 0;
+    art->attributes[i]->value = NULL;
+  }
+  strcpy(art->reset, COLOR_RESET);
+
+#ifdef ARCH_X86
+  if(art->vendor == CPU_VENDOR_INTEL) {
+    COL_FANCY_1 = COLOR_BG_CYAN;
+    COL_FANCY_2 = COLOR_BG_WHITE;
+    COL_FANCY_3 = COLOR_FG_CYAN;
+    COL_FANCY_4 = COLOR_FG_WHITE;
+    art->ascii_chars[0] = '#';
+  }
+  else if(art->vendor == CPU_VENDOR_AMD) {
+    COL_FANCY_1 = COLOR_BG_WHITE;
+    COL_FANCY_2 = COLOR_BG_GREEN;
+    COL_FANCY_3 = COLOR_FG_WHITE;
+    COL_FANCY_4 = COLOR_FG_GREEN;
+    art->ascii_chars[0] = '@';
+  }
+  else {
+    printBug("Invalid CPU vendor in set_ascii (%d)", art->vendor);
+    return NULL;
+  }
+#elif ARCH_PPC
+  COL_FANCY_1 = COLOR_BG_CYAN;
+  COL_FANCY_2 = COLOR_BG_WHITE;
+  COL_FANCY_3 = COLOR_FG_CYAN;
+  COL_FANCY_4 = COLOR_FG_WHITE;
+  art->ascii_chars[0] = '#';
+#elif ARCH_ARM
+  if(art->vendor == SOC_VENDOR_SNAPDRAGON) {
+    COL_FANCY_1 = COLOR_BG_RED;
+    COL_FANCY_2 = COLOR_BG_WHITE;
+    COL_FANCY_3 = COLOR_FG_RED;
+    COL_FANCY_4 = COLOR_FG_WHITE;
+    art->ascii_chars[0] = '@';
+  }
+  else if(art->vendor == SOC_VENDOR_MEDIATEK) {
+    COL_FANCY_1 = COLOR_BG_BLUE;
+    COL_FANCY_2 = COLOR_BG_YELLOW;
+    COL_FANCY_3 = COLOR_FG_WHITE;
+    COL_FANCY_4 = COLOR_FG_BLUE;
+    art->ascii_chars[0] = '@';
+  }
+  else if(art->vendor == SOC_VENDOR_EXYNOS) {
+    COL_FANCY_1 = COLOR_BG_BLUE;
+    COL_FANCY_2 = COLOR_BG_WHITE;
+    COL_FANCY_3 = COLOR_FG_BLUE;
+    COL_FANCY_4 = COLOR_FG_WHITE;
+    art->ascii_chars[0] = '@';
+  }
+  else if(art->vendor == SOC_VENDOR_KIRIN) {
+    COL_FANCY_1 = COLOR_BG_WHITE;
+    COL_FANCY_2 = COLOR_BG_RED;
+    COL_FANCY_3 = COLOR_FG_WHITE;
+    COL_FANCY_4 = COLOR_FG_RED;
+    art->ascii_chars[0] = '@';
+  }
+  else if(art->vendor == SOC_VENDOR_BROADCOM) {
+    COL_FANCY_1 = COLOR_BG_WHITE;
+    COL_FANCY_2 = COLOR_BG_RED;
+    COL_FANCY_3 = COLOR_FG_WHITE;
+    COL_FANCY_4 = COLOR_FG_RED;
+    art->ascii_chars[0] = '@';
+  }
+  else {
+    COL_FANCY_1 = COLOR_BG_CYAN;
+    COL_FANCY_2 = COLOR_BG_CYAN;
+    COL_FANCY_3 = COLOR_FG_WHITE;
+    COL_FANCY_4 = COLOR_FG_CYAN;
+    art->ascii_chars[0] = '#';
+  }
+#endif
+  COL_RETRO_1 = COL_FANCY_3;
+  COL_RETRO_2 = COL_FANCY_4;
+  COL_RETRO_3 = COL_RETRO_1;
+  COL_RETRO_4 = COL_RETRO_2;
+  art->ascii_chars[1] = '#';
+
+  #ifdef _WIN32
+    // Old Windows do not define the flag
+    #ifndef ENABLE_VIRTUAL_TERMINAL_PROCESSING
+      #define ENABLE_VIRTUAL_TERMINAL_PROCESSING 0x0004
+    #endif
+
+    HANDLE std_handle = GetStdHandle(STD_OUTPUT_HANDLE);
+    DWORD console_mode;
+
+    // Attempt to enable the VT100-processing flag
+    GetConsoleMode(std_handle, &console_mode);
+    SetConsoleMode(std_handle, console_mode | ENABLE_VIRTUAL_TERMINAL_PROCESSING);
+    // Get the console mode flag again, to see if it successfully enabled it
+    GetConsoleMode(std_handle, &console_mode);
+  #endif
+
+  if(style == STYLE_EMPTY) {
+    #ifdef _WIN32
+      // Use fancy style if VT100-processing is enabled,
+      // or legacy style in other case
+      art->style = (console_mode & ENABLE_VIRTUAL_TERMINAL_PROCESSING) ? STYLE_FANCY : STYLE_LEGACY;
+    #else
+      art->style = STYLE_FANCY;
+    #endif
+  }
+  else {
+    art->style = style;
+  }
+
+  switch(art->style) {
+    case STYLE_LEGACY:
+      strcpy(art->color1_ascii, COLOR_NONE);
+      strcpy(art->color2_ascii, COLOR_NONE);
+      strcpy(art->color1_text, COLOR_NONE);
+      strcpy(art->color2_text, COLOR_NONE);
+      art->reset[0] = '\0';
+      break;
+    case STYLE_FANCY:
+      if(cs != NULL) {
+        COL_FANCY_1 = rgb_to_ansi(cs[0], true, true);
+        COL_FANCY_2 = rgb_to_ansi(cs[1], true, true);
+        COL_FANCY_3 = rgb_to_ansi(cs[2], false, true);
+        COL_FANCY_4 = rgb_to_ansi(cs[3], false, true);
+      }
+      art->ascii_chars[0] = ' ';
+      art->ascii_chars[1] = ' ';
+      strcpy(art->color1_ascii,COL_FANCY_1);
+      strcpy(art->color2_ascii,COL_FANCY_2);
+      strcpy(art->color1_text,COL_FANCY_3);
+      strcpy(art->color2_text,COL_FANCY_4);
+      if(cs != NULL) {
+        free(COL_FANCY_1);
+        free(COL_FANCY_2);
+        free(COL_FANCY_3);
+        free(COL_FANCY_4);
+      }
+      break;
+    case STYLE_RETRO:
+      if(cs != NULL) {
+        COL_RETRO_1 = rgb_to_ansi(cs[0], false, true);
+        COL_RETRO_2 = rgb_to_ansi(cs[1], false, true);
+        COL_RETRO_3 = rgb_to_ansi(cs[2], false, true);
+        COL_RETRO_4 = rgb_to_ansi(cs[3], false, true);
+      }
+      strcpy(art->color1_ascii,COL_RETRO_1);
+      strcpy(art->color2_ascii,COL_RETRO_2);
+      strcpy(art->color1_text,COL_RETRO_3);
+      strcpy(art->color2_text,COL_RETRO_4);
+      if(cs != NULL) {
+        free(COL_RETRO_1);
+        free(COL_RETRO_2);
+        free(COL_RETRO_3);
+        free(COL_RETRO_4);
+      }
+      break;
+    case STYLE_INVALID:
+    default:
+      printBug("Found invalid style (%d)", art->style);
+      return NULL;
+  }
+
+  char tmp[NUMBER_OF_LINES * LINE_SIZE + 1];
+#ifdef ARCH_X86
+  if(art->vendor == CPU_VENDOR_INTEL)
+    strcpy(tmp, INTEL_ASCII);
+  else if(art->vendor == CPU_VENDOR_AMD)
+    strcpy(tmp, AMD_ASCII);
+  else
+    strcpy(tmp, UNKNOWN_ASCII);
+#elif ARCH_PPC
+  strcpy(tmp, IBM_ASCII);
+#elif ARCH_ARM
+  if(art->vendor == SOC_VENDOR_SNAPDRAGON)
+    strcpy(tmp, SNAPDRAGON_ASCII);
+  else if(art->vendor == SOC_VENDOR_MEDIATEK)
+    strcpy(tmp, MEDIATEK_ASCII);
+  else if(art->vendor == SOC_VENDOR_EXYNOS)
+    strcpy(tmp, EXYNOS_ASCII);
+  else if(art->vendor == SOC_VENDOR_KIRIN)
+    strcpy(tmp, KIRIN_ASCII);
+  else if(art->vendor == SOC_VENDOR_BROADCOM)
+    strcpy(tmp, BROADCOM_ASCII);
+  else
+    strcpy(tmp, ARM_ASCII);
+#endif
+
+  for(int i=0; i < NUMBER_OF_LINES; i++)
+    memcpy(art->art[i], tmp + i*LINE_SIZE, LINE_SIZE);
+
+  return art;
+}
+
+uint32_t longest_attribute_length(struct ascii* art) {
+  uint32_t max = 0;
+  uint64_t len = 0;
+
+  for(uint32_t i=0; i < art->n_attributes_set; i++) {
+    if(art->attributes[i]->value != NULL) {
+      len = strlen(ATTRIBUTE_FIELDS[art->attributes[i]->type]);
+      if(len > max) max = len;
+    }
+  }
+
+  return max;
+}
+
+#ifdef ARCH_X86
+void print_algorithm_intel(struct ascii* art, int n, bool* flag) {
+  for(int i=0; i < LINE_SIZE; i++) {
+    if(*flag) {
+      if(art->art[n][i] == ' ') {
+        *flag = false;
+        printf("%s%c%s", art->color2_ascii, art->ascii_chars[1], art->reset);
+      }
+      else {
+        printf("%s%c%s", art->color1_ascii, art->ascii_chars[0], art->reset);
+      }
+    }
+    else {
+      if(art->art[n][i] != ' ' && art->art[n][i] != '\0') {
+        *flag = true;
+        printf("%c",' ');
+      }
+      else {
+        printf("%c",' ');
+      }
+    }
+  }
+}
+
+void print_algorithm_amd(struct ascii* art, int n, bool* flag) {
+  *flag = false; // dummy, just silence compiler error
+
+  for(int i=0; i < LINE_SIZE; i++) {
+    if(art->art[n][i] == '@')
+      printf("%s%c%s", art->color1_ascii, art->ascii_chars[0], art->reset);
+    else if(art->art[n][i] == '#')
+      printf("%s%c%s", art->color2_ascii, art->ascii_chars[1], art->reset);
+    else
+      printf("%c",art->art[n][i]);
+  }
+}
+
+void print_ascii_x86(struct ascii* art, uint32_t la, void (*callback_print_algorithm)(struct ascii* art, int i, bool* flag)) {
+  int attr_to_print = 0;
+  int attr_type;
+  char* attr_value;
+  uint32_t space_right;
+  uint32_t space_up = (NUMBER_OF_LINES - art->n_attributes_set)/2;
+  uint32_t space_down = NUMBER_OF_LINES - art->n_attributes_set - space_up;
+  bool flag = false;
+
+  printf("\n");
+  for(uint32_t n=0;n<NUMBER_OF_LINES;n++) {
+    callback_print_algorithm(art, n, &flag);
+
+    if(n > space_up-1 && n < NUMBER_OF_LINES-space_down) {
+      attr_type = art->attributes[attr_to_print]->type;
+      attr_value = art->attributes[attr_to_print]->value;
+      attr_to_print++;
+
+      space_right = 1 + (la - strlen(ATTRIBUTE_FIELDS[attr_type]));
+      printf("%s%s%s%*s%s%s%s\n", art->color1_text, ATTRIBUTE_FIELDS[attr_type], art->reset, space_right, "", art->color2_text, attr_value, art->reset);
+    }
+    else printf("\n");
+  }
+  printf("\n");
+}
+
+void print_ascii(struct ascii* art) {
+  uint32_t longest_attribute = longest_attribute_length(art);
+
+  if(art->vendor == CPU_VENDOR_INTEL)
+    print_ascii_x86(art, longest_attribute, &print_algorithm_intel);
+  else if(art->vendor == CPU_VENDOR_AMD)
+    print_ascii_x86(art, longest_attribute, &print_algorithm_amd);
+  else {
+    printBug("Invalid CPU vendor: %d\n", art->vendor);
+  }
+
+}
+
+bool print_cpufetch_x86(struct cpuInfo* cpu, STYLE s, struct color** cs) {
+  struct ascii* art = set_ascii(get_cpu_vendor(cpu), s, cs);
+  if(art == NULL)
+    return false;
+
+  char* uarch = get_str_uarch(cpu);
+  char* manufacturing_process = get_str_process(cpu);
+  char* sockets = get_str_sockets(cpu->topo);
+  char* max_frequency = get_str_freq(cpu->freq);
+  char* n_cores = get_str_topology(cpu, cpu->topo, false);
+  char* n_cores_dual = get_str_topology(cpu, cpu->topo, true);
+  char* cpu_name = get_str_cpu_name(cpu);
+  char* avx = get_str_avx(cpu);
+  char* fma = get_str_fma(cpu);
+
+  char* l1i = get_str_l1i(cpu->cach);
+  char* l1d = get_str_l1d(cpu->cach);
+  char* l2 = get_str_l2(cpu->cach);
+  char* l3 = get_str_l3(cpu->cach);
+  char* pp = get_str_peak_performance(cpu->peak_performance);
+
+  setAttribute(art,ATTRIBUTE_NAME,cpu_name);
+  if(cpu->hv->present) {
+    setAttribute(art, ATTRIBUTE_HYPERVISOR, cpu->hv->hv_name);
+  }
+  setAttribute(art,ATTRIBUTE_UARCH,uarch);
+  setAttribute(art,ATTRIBUTE_TECHNOLOGY,manufacturing_process);
+  setAttribute(art,ATTRIBUTE_FREQUENCY,max_frequency);
+  uint32_t socket_num = get_nsockets(cpu->topo);
+  if (socket_num > 1) {
+    setAttribute(art, ATTRIBUTE_SOCKETS, sockets);
+    setAttribute(art, ATTRIBUTE_NCORES,n_cores);
+    setAttribute(art, ATTRIBUTE_NCORES_DUAL, n_cores_dual);
+  }
+  else {
+    setAttribute(art,ATTRIBUTE_NCORES,n_cores);
+  }
+  setAttribute(art,ATTRIBUTE_AVX,avx);
+  setAttribute(art,ATTRIBUTE_FMA,fma);
+  setAttribute(art,ATTRIBUTE_L1i,l1i);
+  setAttribute(art,ATTRIBUTE_L1d,l1d);
+  setAttribute(art,ATTRIBUTE_L2,l2);
+  if(l3 != NULL) {
+    setAttribute(art,ATTRIBUTE_L3,l3);
+  }
+  setAttribute(art,ATTRIBUTE_PEAK,pp);
+
+  if(art->n_attributes_set > NUMBER_OF_LINES) {
+    printBug("The number of attributes set is bigger than the max that can be displayed");
+    return false;
+  }
+
+  print_ascii(art);
+
+  free(manufacturing_process);
+  free(max_frequency);
+  free(sockets);
+  free(n_cores);
+  free(n_cores_dual);
+  free(avx);
+  free(fma);
+  free(l1i);
+  free(l1d);
+  free(l2);
+  free(l3);
+  free(pp);
+
+  free(art->attributes);
+  free(art);
+
+  if(cs != NULL) free_colors_struct(cs);
+  free_cache_struct(cpu->cach);
+  free_topo_struct(cpu->topo);
+  free_freq_struct(cpu->freq);
+  free_cpuinfo_struct(cpu);
+
+  return true;
+}
+#endif
+
+#ifdef ARCH_PPC
+void print_algorithm_ppc(struct ascii* art, int n) {
+  for(int i=0; i < LINE_SIZE; i++) {
+    if(art->art[n][i] == '#')
+      printf("%s%c%s", art->color1_ascii, art->ascii_chars[0], art->reset);
+    else
+      printf("%c",art->art[n][i]);
+  }
+}
+
+void print_ascii_ppc(struct ascii* art, uint32_t la) {
+  int attr_to_print = 0;
+  int attr_type;
+  char* attr_value;
+  uint32_t space_right;
+  uint32_t space_up = (NUMBER_OF_LINES - art->n_attributes_set)/2;
+  uint32_t space_down = NUMBER_OF_LINES - art->n_attributes_set - space_up;
+
+  printf("\n");
+  for(uint32_t n=0;n<NUMBER_OF_LINES;n++) {
+    print_algorithm_ppc(art, n);
+
+    if(n > space_up-1 && n < NUMBER_OF_LINES-space_down) {
+      attr_type = art->attributes[attr_to_print]->type;
+      attr_value = art->attributes[attr_to_print]->value;
+      attr_to_print++;
+
+      space_right = 1 + (la - strlen(ATTRIBUTE_FIELDS[attr_type]));
+      printf("%s%s%s%*s%s%s%s\n", art->color1_text, ATTRIBUTE_FIELDS[attr_type], art->reset, space_right, "", art->color2_text, attr_value, art->reset);
+    }
+    else printf("\n");
+  }
+  printf("\n");
+}
+
+void print_ascii(struct ascii* art) {
+  uint32_t longest_attribute = longest_attribute_length(art);
+
+  print_ascii_ppc(art, longest_attribute);
+}
+
+bool print_cpufetch_ppc(struct cpuInfo* cpu, STYLE s, struct color** cs) {
+  struct ascii* art = set_ascii(get_cpu_vendor(cpu), s, cs);
+  if(art == NULL)
+    return false;
+
+  char* uarch = get_str_uarch(cpu);
+  char* manufacturing_process = get_str_process(cpu);
+  char* sockets = get_str_sockets(cpu->topo);
+  char* max_frequency = get_str_freq(cpu->freq);
+  char* cpu_name = get_str_cpu_name(cpu);
+  char* n_cores = get_str_topology(cpu->topo, false);
+  char* n_cores_dual = get_str_topology(cpu->topo, true);
+  char* altivec = get_str_altivec(cpu);
+
+  char* l1i = get_str_l1i(cpu->cach);
+  char* l1d = get_str_l1d(cpu->cach);
+  char* l2 = get_str_l2(cpu->cach);
+  char* l3 = get_str_l3(cpu->cach);
+  char* pp = get_str_peak_performance(cpu->peak_performance);
+
+  if(cpu_name != NULL) {
+    setAttribute(art,ATTRIBUTE_NAME,cpu_name);
+  }
+  setAttribute(art,ATTRIBUTE_UARCH,uarch);
+  setAttribute(art,ATTRIBUTE_TECHNOLOGY,manufacturing_process);
+  setAttribute(art,ATTRIBUTE_FREQUENCY,max_frequency);
+  uint32_t socket_num = get_nsockets(cpu->topo);
+  if (socket_num > 1) {
+    setAttribute(art, ATTRIBUTE_SOCKETS, sockets);
+    setAttribute(art, ATTRIBUTE_NCORES, n_cores);
+    setAttribute(art, ATTRIBUTE_NCORES_DUAL, n_cores_dual);
+  }
+  else {
+    setAttribute(art,ATTRIBUTE_NCORES, n_cores);
+  }
+  setAttribute(art,ATTRIBUTE_ALTIVEC, altivec);
+  setAttribute(art,ATTRIBUTE_L1i,l1i);
+  setAttribute(art,ATTRIBUTE_L1d,l1d);
+  setAttribute(art,ATTRIBUTE_L2,l2);
+  if(l3 != NULL) {
+    setAttribute(art,ATTRIBUTE_L3,l3);
+  }
+  setAttribute(art,ATTRIBUTE_PEAK,pp);
+
+  if(art->n_attributes_set > NUMBER_OF_LINES) {
+    printBug("The number of attributes set is bigger than the max that can be displayed");
+    return false;
+  }
+
+  print_ascii(art);
+
+  return true;
+}
+#endif
+
+#ifdef ARCH_ARM
+void print_algorithm_snapd_mtk(struct ascii* art, int n) {
+  for(int i=0; i < LINE_SIZE; i++) {
+    if(art->art[n][i] == '@')
+      printf("%s%c%s", art->color1_ascii, art->ascii_chars[0], art->reset);
+    else if(art->art[n][i] == '#')
+      printf("%s%c%s", art->color2_ascii, art->ascii_chars[1], art->reset);
+    else
+      printf("%c",art->art[n][i]);
+  }
+}
+
+void print_algorithm_samsung(struct ascii* art, int n) {
+  int y_margin = 2;
+  int x_margin = 2 * y_margin;
+
+  for(int i=0; i < LINE_SIZE; i++) {
+    if(art->art[n][i] == '#') {
+      printf("%s%c%s", art->color1_ascii, art->ascii_chars[0], art->reset);
+    }
+    else if((n >= y_margin && n < NUMBER_OF_LINES-y_margin) && (i >= x_margin && i < LINE_SIZE-x_margin)) {
+      if(art->art[n][i] == '#')
+        printf("%s%c%s", art->color1_ascii, art->ascii_chars[0], art->reset);
+      else
+        printf("%s%c%s","\x1b[48;2;10;10;10m" COLOR_FG_WHITE, art->art[n][i], art->reset);
+    }
+    else
+      printf("%c", art->art[n][i]);
+  }
+}
+
+void print_algorithm_arm(struct ascii* art, int n) {
+  for(int i=0; i < LINE_SIZE; i++) {
+    if(art->art[n][i] == '#')
+      printf("%s%c%s", art->color1_ascii, art->ascii_chars[0], art->reset);
+    else
+      printf("%c",art->art[n][i]);
+  }
+}
+
+void print_ascii_arm(struct ascii* art, uint32_t la, void (*callback_print_algorithm)(struct ascii* art, int n)) {
+  int attr_to_print = 0;
+  int attr_type;
+  char* attr_value;
+  uint32_t limit_up;
+  uint32_t limit_down;
+
+  uint32_t space_right;
+  uint32_t space_up = (NUMBER_OF_LINES - art->n_attributes_set)/2;
+  uint32_t space_down = NUMBER_OF_LINES - art->n_attributes_set - space_up;
+  if(art->n_attributes_set > NUMBER_OF_LINES) {
+    limit_up = 0;
+    limit_down = art->n_attributes_set;
+  }
+  else {
+    limit_up = space_up;
+    limit_down = NUMBER_OF_LINES-space_down;
+  }
+  bool add_space = false;
+  uint32_t len = max(art->n_attributes_set, NUMBER_OF_LINES);
+
+  for(uint32_t n=0; n < len; n++) {
+    if(n >= art->additional_spaces && n < NUMBER_OF_LINES + art->additional_spaces)
+      callback_print_algorithm(art, n - art->additional_spaces);
+    else
+      printf("%*s", LINE_SIZE, "");
+
+    if(n >= limit_up && n < limit_down) {
+      attr_type = art->attributes[attr_to_print]->type;
+      attr_value = art->attributes[attr_to_print]->value;
+      attr_to_print++;
+
+      if(attr_type == ATTRIBUTE_PEAK) {
+        add_space = false;
+      }
+      if(attr_type == ATTRIBUTE_CPU_NUM) {
+        printf("%s%s%s\n", art->color1_text, attr_value, art->reset);
+        add_space = true;
+      }
+      else {
+        if(add_space) {
+          space_right = 1 + (la - strlen(ATTRIBUTE_FIELDS[attr_type]));
+          printf("  %s%s%s%*s%s%s%s\n", art->color1_text, ATTRIBUTE_FIELDS[attr_type], art->reset, space_right, "", art->color2_text, attr_value, art->reset);
+        }
+        else {
+          space_right = 2 + 1 + (la - strlen(ATTRIBUTE_FIELDS[attr_type]));
+          printf("%s%s%s%*s%s%s%s\n", art->color1_text, ATTRIBUTE_FIELDS[attr_type], art->reset, space_right, "", art->color2_text, attr_value, art->reset);
+        }
+      }
+    }
+    else printf("\n");
+  }
+
+}
+
+void print_ascii(struct ascii* art) {
+  uint32_t longest_attribute = longest_attribute_length(art);
+
+  if(art->vendor == SOC_VENDOR_SNAPDRAGON || art->vendor == SOC_VENDOR_MEDIATEK || art->vendor == SOC_VENDOR_KIRIN || art->vendor == SOC_VENDOR_BROADCOM)
+    print_ascii_arm(art, longest_attribute, &print_algorithm_snapd_mtk);
+  else if(art->vendor == SOC_VENDOR_EXYNOS)
+    print_ascii_arm(art, longest_attribute, &print_algorithm_samsung);
+  else {
+    if(art->vendor != SOC_VENDOR_UNKNOWN)
+      printWarn("Invalid SOC vendor: %d\n", art->vendor);
+    print_ascii_arm(art, longest_attribute, &print_algorithm_arm);
+  }
+
+}
+
+bool print_cpufetch_arm(struct cpuInfo* cpu, STYLE s, struct color** cs) {
+  struct ascii* art = set_ascii(get_soc_vendor(cpu->soc), s, cs);
+  if(art == NULL)
+    return false;
+
+  char* manufacturing_process = get_str_process(cpu->soc);
+  char* soc_name = get_soc_name(cpu->soc);
+  char* features = get_str_features(cpu);
+  setAttribute(art,ATTRIBUTE_SOC,soc_name);
+  setAttribute(art,ATTRIBUTE_TECHNOLOGY,manufacturing_process);
+
+  if(cpu->num_cpus == 1) {
+    char* uarch = get_str_uarch(cpu);
+    char* max_frequency = get_str_freq(cpu->freq);
+    char* n_cores = get_str_topology(cpu, cpu->topo, false);
+    /*
+     * char* l1i = get_str_l1i(cpu->cach);
+     * char* l1d = get_str_l1d(cpu->cach);
+     * char* l2 = get_str_l2(cpu->cach);
+     * char* l3 = get_str_l3(cpu->cach);
+     * Do not setAttribute for caches.
+     * Cache functionality may be implemented
+     * in the future
+    */
+
+    setAttribute(art,ATTRIBUTE_UARCH,uarch);
+    setAttribute(art,ATTRIBUTE_FREQUENCY,max_frequency);
+    setAttribute(art,ATTRIBUTE_NCORES,n_cores);
+    if(features != NULL) {
+      setAttribute(art, ATTRIBUTE_FEATURES, features);
+    }
+  }
+  else {
+    struct cpuInfo* ptr = cpu;
+    for(int i = 0; i < cpu->num_cpus; ptr = ptr->next_cpu, i++) {
+      char* uarch = get_str_uarch(ptr);
+      char* max_frequency = get_str_freq(ptr->freq);
+      char* n_cores = get_str_topology(ptr, ptr->topo, false);
+      /*
+       * char* l1i = get_str_l1i(cpu->cach);
+       * char* l1d = get_str_l1d(cpu->cach);
+       * char* l2 = get_str_l2(cpu->cach);
+       * char* l3 = get_str_l3(cpu->cach);
+       * Do not setAttribute for caches.
+       * Cache functionality may be implemented
+       * in the future
+       */
+
+      char* cpu_num = emalloc(sizeof(char) * 9);
+      sprintf(cpu_num, "CPU %d:", i+1);
+      setAttribute(art, ATTRIBUTE_CPU_NUM, cpu_num);
+      setAttribute(art, ATTRIBUTE_UARCH, uarch);
+      setAttribute(art, ATTRIBUTE_FREQUENCY, max_frequency);
+      setAttribute(art, ATTRIBUTE_NCORES, n_cores);
+      if(features != NULL) {
+        setAttribute(art, ATTRIBUTE_FEATURES, features);
+      }
+    }
+  }
+  char* pp = get_str_peak_performance(cpu->peak_performance);
+  setAttribute(art,ATTRIBUTE_PEAK,pp);
+
+  if(art->n_attributes_set > NUMBER_OF_LINES) {
+    art->additional_spaces = (art->n_attributes_set - NUMBER_OF_LINES) / 2;
+  }
+  if(cpu->hv->present)
+    setAttribute(art, ATTRIBUTE_HYPERVISOR, cpu->hv->hv_name);
+
+  print_ascii(art);
+
+  free(manufacturing_process);
+  free(pp);
+
+  free(art->attributes);
+  free(art);
+
+  if(cs != NULL) free_colors_struct(cs);
+  free_cache_struct(cpu->cach);
+  free_topo_struct(cpu->topo);
+  free_cpuinfo_struct(cpu);
+
+  return true;
+}
+#endif
+
+bool print_cpufetch(struct cpuInfo* cpu, STYLE s, struct color** cs) {
+  // Sanity check of ASCII arts
+  int len = sizeof(ASCII_ARRAY) / sizeof(ASCII_ARRAY[0]);
+  for(int i=0; i < len; i++) {
+    const char* ascii = ASCII_ARRAY[i];
+    if(strlen(ascii) != (NUMBER_OF_LINES * LINE_SIZE)) {
+      printBug("ASCII art %d is wrong! ASCII length: %d, expected length: %d", i, strlen(ascii), (NUMBER_OF_LINES * LINE_SIZE));
+      return false;
+    }
+  }
+
+#ifdef ARCH_X86
+  return print_cpufetch_x86(cpu, s, cs);
+#elif ARCH_PPC
+  return print_cpufetch_ppc(cpu, s, cs);
+#elif ARCH_ARM
+  return print_cpufetch_arm(cpu, s, cs);
+#endif
+}

src/common/printer.h

@@ -0,0 +1,27 @@
+#ifndef __PRINTER__
+#define __PRINTER__
+
+typedef int STYLE;
+
+#include "args.h"
+
+#ifdef ARCH_X86
+  #include "../x86/cpuid.h"
+#elif ARCH_PPC
+  #include "../ppc/ppc.h"
+#elif ARCH_ARM
+  #include "../arm/midr.h"
+#endif
+
+#define COLOR_DEFAULT_INTEL "15,125,194:230,230,230:40,150,220:230,230,230"
+#define COLOR_DEFAULT_AMD   "250,250,250:0,154,102:250,250,250:0,154,102"
+#define COLOR_DEFAULT_IBM   "92,119,172:92,119,172:240,240,240:92,119,172"
+#define COLOR_DEFAULT_ARM   "0,145,189:0,145,189:240,240,240:0,145,189"
+
+#ifdef ARCH_X86
+void print_levels(struct cpuInfo* cpu);
+#endif
+
+bool print_cpufetch(struct cpuInfo* cpu, STYLE s, struct color** cs);
+
+#endif

src/common/udev.c

@@ -0,0 +1,196 @@
+#include "udev.h"
+#include "global.h"
+#include "cpu.h"
+
+char* read_file(char* path, int* len) {
+  int fd = open(path, O_RDONLY);
+
+  if(fd == -1) {
+    return NULL;
+  }
+
+  //File exists, read it
+  int bytes_read = 0;
+  int offset = 0;
+  int block = 128;
+  char* buf = emalloc(sizeof(char)*DEFAULT_FILE_SIZE);
+  memset(buf, 0, sizeof(char)*DEFAULT_FILE_SIZE);
+
+  while (  (bytes_read = read(fd, buf+offset, block)) > 0 ) {
+    offset += bytes_read;
+  }
+
+  if (close(fd) == -1) {
+    return NULL;
+  }
+
+  *len = offset;
+  return buf;
+}
+
+long get_freq_from_file(char* path) {
+  int filelen;
+  char* buf;
+  if((buf = read_file(path, &filelen)) == NULL) {
+    printWarn("Could not open '%s'", path);
+    return UNKNOWN_FREQ;
+  }
+
+  char* end;
+  errno = 0;
+  long ret = strtol(buf, &end, 10);
+  if(errno != 0) {
+    printBug("strtol: %s", strerror(errno));
+    free(buf);
+    return UNKNOWN_FREQ;
+  }
+
+  // We will be getting the frequency in KHz
+  // We consider it is an error if frequency is
+  // greater than 10 GHz or less than 100 MHz
+  if(ret > 10000 * 1000 || ret <  100 * 1000) {
+    printBug("Invalid data was read from file '%s': %ld\n", path, ret);
+    return UNKNOWN_FREQ;
+  }
+
+  free(buf);
+
+  return ret/1000;
+}
+
+long get_cache_size_from_file(char* path) {
+  int filelen;
+  char* buf;
+  if((buf = read_file(path, &filelen)) == NULL) {
+    printWarn("Could not open '%s'", path);
+    return -1;
+  }
+
+  buf[filelen] = '\0'; // remove the K at the end
+
+  char* end;
+  errno = 0;
+  long ret = strtol(buf, &end, 10);
+  if(errno != 0) {
+    printBug("strtol: %s", strerror(errno));
+    free(buf);
+    return -1;
+  }
+
+  free(buf);
+
+  return ret * 1024;
+}
+
+long get_max_freq_from_file(uint32_t core) {
+  char path[_PATH_FREQUENCY_MAX_LEN];
+  sprintf(path, "%s%s/cpu%d%s%s", _PATH_SYS_SYSTEM, _PATH_SYS_CPU, core, _PATH_FREQUENCY, _PATH_FREQUENCY_MAX);
+  return get_freq_from_file(path);
+}
+
+long get_min_freq_from_file(uint32_t core) {
+  char path[_PATH_FREQUENCY_MAX_LEN];
+  sprintf(path, "%s%s/cpu%d%s%s", _PATH_SYS_SYSTEM, _PATH_SYS_CPU, core, _PATH_FREQUENCY, _PATH_FREQUENCY_MIN);
+  return get_freq_from_file(path);
+}
+
+long get_l1i_cache_size(uint32_t core) {
+  char path[_PATH_CACHE_MAX_LEN];
+  sprintf(path, "%s%s/cpu%d%s%s",  _PATH_SYS_SYSTEM, _PATH_SYS_CPU, core, _PATH_CACHE_L1I, _PATH_CACHE_SIZE);
+  return get_cache_size_from_file(path);
+}
+
+long get_l1d_cache_size(uint32_t core) {
+  char path[_PATH_CACHE_MAX_LEN];
+  sprintf(path, "%s%s/cpu%d%s%s",  _PATH_SYS_SYSTEM, _PATH_SYS_CPU, core, _PATH_CACHE_L1D, _PATH_CACHE_SIZE);
+  return get_cache_size_from_file(path);
+}
+
+long get_l2_cache_size(uint32_t core) {
+  char path[_PATH_CACHE_MAX_LEN];
+  sprintf(path, "%s%s/cpu%d%s%s",  _PATH_SYS_SYSTEM, _PATH_SYS_CPU, core, _PATH_CACHE_L2, _PATH_CACHE_SIZE);
+  return get_cache_size_from_file(path);
+}
+
+long get_l3_cache_size(uint32_t core) {
+  char path[_PATH_CACHE_MAX_LEN];
+  sprintf(path, "%s%s/cpu%d%s%s",  _PATH_SYS_SYSTEM, _PATH_SYS_CPU, core, _PATH_CACHE_L3, _PATH_CACHE_SIZE);
+  return get_cache_size_from_file(path);
+}
+
+int get_num_caches_from_files(char** paths, int num_paths) {
+  int SHARED_MAP_MAX_LEN = 8 + 1;
+  int filelen;
+  char* buf;
+  uint32_t* shared_maps = emalloc(sizeof(uint32_t *) * num_paths);
+
+  // 1. Read cpu_shared_map from every core
+  for(int i=0; i < num_paths; i++) {
+    if((buf = read_file(paths[i], &filelen)) == NULL) {
+      printWarn("Could not open '%s'", paths[i]);
+      return -1;
+    }
+
+    if(filelen > SHARED_MAP_MAX_LEN) {
+      printBug("Shared map length is %d while the max is be %d", filelen, SHARED_MAP_MAX_LEN);
+      return -1;
+    }
+
+    char* end;
+    errno = 0;
+    long ret = strtol(buf, &end, 16);
+    if(errno != 0) {
+      printBug("strtol: %s", strerror(errno));
+      free(buf);
+      return -1;
+    }
+
+    shared_maps[i] = (uint32_t) ret;
+  }
+
+  // 2. Count number of different masks; this is the number of caches
+  int num_caches = 0;
+  bool found = false;
+  uint32_t* unique_shared_maps = emalloc(sizeof(uint32_t *) * num_paths);
+  for(int i=0; i < num_paths; i++) unique_shared_maps[i] = 0;
+
+  for(int i=0; i < num_paths; i++) {
+    for(int j=0; j < num_paths && !found; j++) {
+      if(shared_maps[i] == unique_shared_maps[j]) found = true;
+    }
+    if(!found) {
+      unique_shared_maps[num_caches] = shared_maps[i];
+      num_caches++;
+    }
+    found = false;
+  }
+
+  return num_caches;
+}
+
+int get_num_caches_by_level(struct cpuInfo* cpu, uint32_t level) {
+  char** paths = emalloc(sizeof(char *) * cpu->topo->total_cores);
+  char* cache_path = NULL;
+
+  if(level == 0) cache_path = _PATH_CACHE_L1I;
+  else if(level == 1) cache_path = _PATH_CACHE_L1D;
+  else if(level == 2) cache_path = _PATH_CACHE_L2;
+  else if(level == 3) cache_path = _PATH_CACHE_L3;
+  else {
+    printBug("Found invalid cache level to inspect: %d\n", level);
+    return -1;
+  }
+
+  for(int i=0; i < cpu->topo->total_cores; i++) {
+    paths[i] = emalloc(sizeof(char) * _PATH_CACHE_MAX_LEN);
+    sprintf(paths[i], "%s%s/cpu%d%s%s",  _PATH_SYS_SYSTEM, _PATH_SYS_CPU, i, cache_path, _PATH_CACHE_SHARED_MAP);
+  }
+
+  int ret = get_num_caches_from_files(paths, cpu->topo->total_cores);
+
+  for(int i=0; i < cpu->topo->total_cores; i++)
+    free(paths[i]);
+  free(paths);
+
+  return ret;
+}

src/common/udev.h

@@ -0,0 +1,40 @@
+#ifndef __UDEV__
+#define __UDEV__
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <string.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <fcntl.h>
+#include <errno.h>
+
+#include "cpu.h"
+
+#define _PATH_SYS_SYSTEM        "/sys/devices/system"
+#define _PATH_SYS_CPU           "/cpu"
+#define _PATH_FREQUENCY         "/cpufreq"
+#define _PATH_FREQUENCY_MAX     "/cpuinfo_max_freq"
+#define _PATH_FREQUENCY_MIN     "/cpuinfo_min_freq"
+#define _PATH_CACHE_L1D         "/cache/index0"
+#define _PATH_CACHE_L1I         "/cache/index1"
+#define _PATH_CACHE_L2          "/cache/index2"
+#define _PATH_CACHE_L3          "/cache/index3"
+#define _PATH_CACHE_SIZE        "/size"
+#define _PATH_CACHE_SHARED_MAP  "/shared_cpu_map"
+
+#define _PATH_FREQUENCY_MAX_LEN 100
+#define _PATH_CACHE_MAX_LEN     200
+#define DEFAULT_FILE_SIZE       4096
+
+char* read_file(char* path, int* len);
+long get_max_freq_from_file(uint32_t core);
+long get_min_freq_from_file(uint32_t core);
+long get_l1i_cache_size(uint32_t core);
+long get_l1d_cache_size(uint32_t core);
+long get_l2_cache_size(uint32_t core);
+long get_l3_cache_size(uint32_t core);
+int get_num_caches_by_level(struct cpuInfo* cpu, uint32_t level);
+
+#endif

src/cpuid.c

@@ -1,978 +0,0 @@
-#ifdef _WIN32
-  #include <windows.h>
-#else
-  #include "udev.h"
-  #include <unistd.h>
-#endif
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <assert.h>
-#include <stdbool.h>
-
-#include "cpuid.h"
-#include "cpuid_asm.h"
-#include "global.h"
-#include "apic.h"
-#include "uarch.h"
-
-#define VENDOR_INTEL_STRING "GenuineIntel"
-#define VENDOR_AMD_STRING   "AuthenticAMD"
-
-#define STRING_YES        "Yes"
-#define STRING_NO         "No"
-#define STRING_UNKNOWN    "Unknown"
-#define STRING_NONE       "None"
-#define STRING_MEGAHERZ   "MHz"
-#define STRING_GIGAHERZ   "GHz"
-#define STRING_KILOBYTES  "KB"
-#define STRING_MEGABYTES  "MB"
-
-#define CPU_NAME_MAX_LENGTH 64
-
-#define MASK 0xFF
-
-/*
- * cpuid reference: http://www.sandpile.org/x86/cpuid.htm
- * cpuid amd: https://www.amd.com/system/files/TechDocs/25481.pdf
- */
-
-struct frequency {
-  int64_t base;
-  int64_t max;
-};
-
-void init_cpu_info(struct cpuInfo* cpu) {
-  cpu->AVX    = false;
-  cpu->AVX2   = false;
-  cpu->AVX512 = false;
-  cpu->SSE    = false;
-  cpu->SSE2   = false;
-  cpu->SSE3   = false;
-  cpu->SSSE3  = false;
-  cpu->SSE4a  = false;
-  cpu->SSE4_1 = false;
-  cpu->SSE4_2 = false;
-  cpu->FMA3   = false;
-  cpu->FMA4   = false;
-  cpu->AES    = false;
-  cpu->SHA    = false;
-}
-
-void init_topology_struct(struct topology* topo, struct cache* cach) {
-  topo->total_cores = 0;
-  topo->physical_cores = 0;
-  topo->logical_cores = 0;
-  topo->smt_available = 0;
-  topo->smt_supported = 0;
-  topo->sockets = 0;
-  topo->apic = malloc(sizeof(struct apic));
-  topo->cach = cach;
-}
-
-void init_cache_struct(struct cache* cach) {
-  cach->L1i = malloc(sizeof(struct cach));
-  cach->L1d = malloc(sizeof(struct cach));
-  cach->L2 = malloc(sizeof(struct cach));
-  cach->L3 = malloc(sizeof(struct cach));
-  
-  cach->cach_arr = malloc(sizeof(struct cach*) * 4);
-  cach->cach_arr[0] = cach->L1i;
-  cach->cach_arr[1] = cach->L1d;
-  cach->cach_arr[2] = cach->L2;
-  cach->cach_arr[3] = cach->L3;
-  
-  cach->max_cache_level = 0;
-  cach->L1i->exists = false;
-  cach->L1d->exists = false;
-  cach->L2->exists = false;
-  cach->L3->exists = false;
-}
-
-void get_cpu_vendor_internal(char* name, uint32_t ebx,uint32_t ecx,uint32_t edx) {
-  name[__COUNTER__] = ebx       & MASK;
-  name[__COUNTER__] = (ebx>>8)  & MASK;
-  name[__COUNTER__] = (ebx>>16) & MASK;
-  name[__COUNTER__] = (ebx>>24) & MASK;
-
-  name[__COUNTER__] = edx       & MASK;
-  name[__COUNTER__] = (edx>>8)  & MASK;
-  name[__COUNTER__] = (edx>>16) & MASK;
-  name[__COUNTER__] = (edx>>24) & MASK;
-
-  name[__COUNTER__] = ecx       & MASK;
-  name[__COUNTER__] = (ecx>>8)  & MASK;
-  name[__COUNTER__] = (ecx>>16) & MASK;
-  name[__COUNTER__] = (ecx>>24) & MASK;
-}
-
-char* get_str_cpu_name_internal() {
-  uint32_t eax = 0;
-  uint32_t ebx = 0;
-  uint32_t ecx = 0;
-  uint32_t edx = 0;
-  uint32_t c = 0;
-  
-  char * name = malloc(sizeof(char) * CPU_NAME_MAX_LENGTH);
-  memset(name, 0, CPU_NAME_MAX_LENGTH);
-  
-  for(int i=0; i < 3; i++) {    
-    eax = 0x80000002 + i;
-    cpuid(&eax, &ebx, &ecx, &edx);
-  
-    name[c++] = eax       & MASK;
-    name[c++] = (eax>>8)  & MASK;
-    name[c++] = (eax>>16) & MASK;
-    name[c++] = (eax>>24) & MASK;
-    name[c++] = ebx       & MASK;
-    name[c++] = (ebx>>8)  & MASK;
-    name[c++] = (ebx>>16) & MASK;
-    name[c++] = (ebx>>24) & MASK;
-    name[c++] = ecx       & MASK;
-    name[c++] = (ecx>>8)  & MASK;
-    name[c++] = (ecx>>16) & MASK;
-    name[c++] = (ecx>>24) & MASK;
-    name[c++] = edx       & MASK;
-    name[c++] = (edx>>8)  & MASK;
-    name[c++] = (edx>>16) & MASK;
-    name[c++] = (edx>>24) & MASK;        
-  }
-  name[c] = '\0';
-  
-  //Remove unused characters  
-  char *str = name;
-  char *dest = name;
-  // Remove spaces before name
-  while (*str != '\0' && *str == ' ')str++; 
-  // Remove spaces between the name and after it
-  while (*str != '\0') {
-    while (*str == ' ' && *(str + 1) == ' ') str++;
-    *dest++ = *str++;
-  }
-  *dest = '\0';
-  
-  return name;
-}
-
-struct uarch* get_cpu_uarch(struct cpuInfo* cpu) {
-  uint32_t eax = 0x00000001;
-  uint32_t ebx = 0;
-  uint32_t ecx = 0;
-  uint32_t edx = 0;
-  
-  cpuid(&eax, &ebx, &ecx, &edx);
-   
-  uint32_t stepping = eax & 0xF;
-  uint32_t model = (eax >> 4) & 0xF;
-  uint32_t emodel = (eax >> 16) & 0xF;
-  uint32_t family = (eax >> 8) & 0xF;
-  uint32_t efamily = (eax >> 20) & 0xFF;
-  
-  return get_uarch_from_cpuid(cpu, efamily, family, emodel, model, (int)stepping);
-}
-
-struct cpuInfo* get_cpu_info() {
-  struct cpuInfo* cpu = malloc(sizeof(struct cpuInfo));
-  init_cpu_info(cpu);
-  uint32_t eax = 0;
-  uint32_t ebx = 0;
-  uint32_t ecx = 0;
-  uint32_t edx = 0;
-
-  //Get max cpuid level
-  cpuid(&eax, &ebx, &ecx, &edx);
-  cpu->maxLevels = eax;
-
-  //Fill vendor
-  char name[13];
-  memset(name,0,13);
-  get_cpu_vendor_internal(name, ebx, ecx, edx);
-  
-  if(strcmp(VENDOR_INTEL_STRING,name) == 0)
-    cpu->cpu_vendor = VENDOR_INTEL;
-  else if (strcmp(VENDOR_AMD_STRING,name) == 0)
-    cpu->cpu_vendor = VENDOR_AMD;  
-  else {
-    cpu->cpu_vendor = VENDOR_INVALID;
-    printErr("Unknown CPU vendor: %s", name);
-    return NULL;
-  }
-
-  //Get max extended level
-  eax = 0x80000000;
-  ebx = 0;
-  ecx = 0;
-  edx = 0;
-  cpuid(&eax, &ebx, &ecx, &edx);
-  cpu->maxExtendedLevels = eax;  
-
-  //Fill instructions support
-  if (cpu->maxLevels >= 0x00000001){
-    eax = 0x00000001;
-    cpuid(&eax, &ebx, &ecx, &edx);
-    cpu->SSE    = (edx & ((int)1 << 25)) != 0;
-    cpu->SSE2   = (edx & ((int)1 << 26)) != 0;
-    cpu->SSE3   = (ecx & ((int)1 <<  0)) != 0;
-
-    cpu->SSSE3  = (ecx & ((int)1 <<  9)) != 0;
-    cpu->SSE4_1 = (ecx & ((int)1 << 19)) != 0;
-    cpu->SSE4_2 = (ecx & ((int)1 << 20)) != 0;
-
-    cpu->AES    = (ecx & ((int)1 << 25)) != 0;
-
-    cpu->AVX    = (ecx & ((int)1 << 28)) != 0;
-    cpu->FMA3   = (ecx & ((int)1 << 12)) != 0;
-  }
-  else {
-    printWarn("Can't read features information from cpuid (needed level is 0x%.8X, max is 0x%.8X)", 0x00000001, cpu->maxLevels);
-  }
-  
-  if (cpu->maxLevels >= 0x00000007){
-    eax = 0x00000007;
-    ecx = 0x00000000;
-    cpuid(&eax, &ebx, &ecx, &edx);
-    cpu->AVX2         = (ebx & ((int)1 <<  5)) != 0;
-    cpu->SHA          = (ebx & ((int)1 << 29)) != 0;
-    cpu->AVX512       = (((ebx & ((int)1 << 16)) != 0) ||
-                        ((ebx & ((int)1 << 28)) != 0)  ||
-                        ((ebx & ((int)1 << 26)) != 0)  ||
-                        ((ebx & ((int)1 << 27)) != 0)  ||
-                        ((ebx & ((int)1 << 31)) != 0)  ||
-                        ((ebx & ((int)1 << 30)) != 0)  ||
-                        ((ebx & ((int)1 << 17)) != 0)  ||
-                        ((ebx & ((int)1 << 21)) != 0));
-  }
-  else {
-    printWarn("Can't read features information from cpuid (needed level is 0x%.8X, max is 0x%.8X)", 0x00000007, cpu->maxLevels);    
-  }
-  
-  if (cpu->maxExtendedLevels >= 0x80000001){
-    eax = 0x80000001;
-    cpuid(&eax, &ebx, &ecx, &edx);
-    cpu->SSE4a = (ecx & ((int)1 <<  6)) != 0;
-    cpu->FMA4  = (ecx & ((int)1 << 16)) != 0;
-  }
-  else {
-    printWarn("Can't read features information from cpuid (needed extended level is 0x%.8X, max is 0x%.8X)", 0x80000001, cpu->maxExtendedLevels);        
-  }
-  
-  if (cpu->maxExtendedLevels >= 0x80000004){
-    cpu->cpu_name = get_str_cpu_name_internal();
-  }
-  else {    
-    cpu->cpu_name = malloc(sizeof(char)*8);
-    sprintf(cpu->cpu_name,"Unknown");
-    printWarn("Can't read cpu name from cpuid (needed extended level is 0x%.8X, max is 0x%.8X)", 0x80000004, cpu->maxExtendedLevels);        
-  }
-  
-  cpu->arch = get_cpu_uarch(cpu);
-
-  return cpu;
-}
-
-bool get_cache_topology_amd(struct cpuInfo* cpu, struct topology* topo) {    
-  if(cpu->maxExtendedLevels >= 0x8000001D) {  
-    uint32_t i, eax, ebx, ecx, edx, num_sharing_cache, cache_type, cache_level;
-    
-    i = 0;
-    do {
-      eax = 0x8000001D;
-      ebx = 0;
-      ecx = i; // cache id
-      edx = 0;
-      
-      cpuid(&eax, &ebx, &ecx, &edx); 
-      
-      cache_type = eax & 0x1F;            
-      
-      if(cache_type > 0) {
-        num_sharing_cache = ((eax >> 14) & 0xFFF) + 1;  
-        cache_level = (eax >>= 5) & 0x7;            
-        
-        switch (cache_type) {                
-          case 1: // Data Cache (We assume this is L1d)
-            if(cache_level != 1) {
-              printBug("Found data cache at level %d (expected 1)", cache_level);
-              return false;
-            }
-            topo->cach->L1d->num_caches = topo->logical_cores / num_sharing_cache;
-            break;
-          
-          case 2: // Instruction Cache (We assume this is L1i)
-            if(cache_level != 1) {
-              printBug("Found instruction cache at level %d (expected 1)", cache_level);
-              return false;
-            }
-            topo->cach->L1i->num_caches = topo->logical_cores / num_sharing_cache;
-            break;
-          
-          case 3: // Unified Cache (This may be L2 or L3)
-            if(cache_level == 2) { 
-              topo->cach->L2->num_caches = topo->logical_cores / num_sharing_cache;
-            }
-            else if(cache_level == 3) {
-              topo->cach->L3->num_caches = topo->logical_cores / num_sharing_cache;
-            }
-            else {
-              printBug("Found unified cache at level %d (expected == 2 or 3)", cache_level);
-              return false;
-            }
-            break;
-          
-          default: // Unknown Type Cache
-            printBug("Unknown Type Cache found at ID %d", i);
-            return false; 
-        }   
-      }
-      
-      i++;
-    } while (cache_type > 0);        
-  }
-  else {
-    printWarn("Can't read topology information from cpuid (needed extended level is 0x%.8X, max is 0x%.8X). Guessing cache sizes", 0x8000001D, cpu->maxExtendedLevels); 
-    topo->cach->L1i->num_caches = topo->physical_cores;
-    topo->cach->L1d->num_caches = topo->physical_cores;
-    
-    if(topo->cach->L3->exists) {
-      topo->cach->L2->num_caches = topo->physical_cores;
-      topo->cach->L3->num_caches = 1;    
-    }
-    else {
-      topo->cach->L2->num_caches = 1;        
-    }
-  }
-  
-  return true;
-}
-
-// Main reference: https://software.intel.com/content/www/us/en/develop/articles/intel-64-architecture-processor-topology-enumeration.html
-// Very interesting resource: https://wiki.osdev.org/Detecting_CPU_Topology_(80x86)
-struct topology* get_topology_info(struct cpuInfo* cpu, struct cache* cach) {
-  struct topology* topo = malloc(sizeof(struct topology));  
-  init_topology_struct(topo, cach);
-  
-  uint32_t eax = 0;
-  uint32_t ebx = 0;
-  uint32_t ecx = 0;
-  uint32_t edx = 0;
-  
-  // Ask the OS the total number of cores it sees
-  // If we have one socket, it will be same as the cpuid,
-  // but in dual socket it will not!
-  // TODO: Replace by apic?
-  #ifdef _WIN32
-    SYSTEM_INFO info;
-    GetSystemInfo(&info);
-    topo->total_cores = info.dwNumberOfProcessors;
-  #else
-    if((topo->total_cores = sysconf(_SC_NPROCESSORS_ONLN)) == -1) {
-      perror("sysconf");
-      topo->total_cores = topo->logical_cores; // fallback
-    }    
-  #endif 
-  
-  switch(cpu->cpu_vendor) {
-    case VENDOR_INTEL:
-      if (cpu->maxLevels >= 0x00000004) { 
-        get_topology_from_apic(cpu, topo);
-      }
-      else {                
-        printErr("Can't read topology information from cpuid (needed level is 0x%.8X, max is 0x%.8X)", 0x00000001, cpu->maxLevels); 
-        topo->physical_cores = 1;
-        topo->logical_cores = 1;
-        topo->smt_available = 1;
-        topo->smt_supported = 1;
-      }      
-      break;
-    case VENDOR_AMD:       
-      if (cpu->maxExtendedLevels >= 0x80000008) {
-        eax = 0x80000008;  
-        cpuid(&eax, &ebx, &ecx, &edx);        
-        topo->logical_cores = (ecx & 0xFF) + 1;
- 
-        if (cpu->maxExtendedLevels >= 0x8000001E) {
-          eax = 0x8000001E;  
-          cpuid(&eax, &ebx, &ecx, &edx);
-          topo->smt_supported = ((ebx >> 8) & 0x03) + 1;          
-        }
-        else {
-          printWarn("Can't read topology information from cpuid (needed extended level is 0x%.8X, max is 0x%.8X)", 0x8000001E, cpu->maxExtendedLevels); 
-          topo->smt_supported = 1;       
-        }        
-      }
-      else {
-        printErr("Can't read topology information from cpuid (needed extended level is 0x%.8X, max is 0x%.8X)", 0x80000008, cpu->maxExtendedLevels); 
-        topo->physical_cores = 1;
-        topo->logical_cores = 1;
-        topo->smt_supported = 1;         
-      }
-      
-      if (cpu->maxLevels >= 0x00000001) {
-        if(topo->smt_supported > 1)
-          topo->smt_available = is_smt_enabled_amd(topo);
-        else
-          topo->smt_available = 1;
-      }
-      else {
-        printWarn("Can't read topology information from cpuid (needed level is 0x%.8X, max is 0x%.8X)", 0x0000000B, cpu->maxLevels);   
-        topo->smt_available = 1;
-      }
-      topo->physical_cores = topo->logical_cores / topo->smt_available;
-      
-      if(topo->smt_supported > 1)
-        topo->sockets = topo->total_cores / topo->smt_supported / topo->physical_cores; // Idea borrowed from lscpu
-      else
-        topo->sockets = topo->total_cores / topo->physical_cores;    
-      
-      get_cache_topology_amd(cpu, topo);      
-      
-      break;
-      
-    default:
-      printBug("Cant get topology because VENDOR is empty");
-      return NULL;
-  }
-    
-  return topo;
-}
-
-struct cache* get_cache_info(struct cpuInfo* cpu) {
-  struct cache* cach = malloc(sizeof(struct cache));
-  init_cache_struct(cach);
-  
-  uint32_t eax = 0;
-  uint32_t ebx = 0;
-  uint32_t ecx = 0;
-  uint32_t edx = 0;
-  uint32_t level;
-
-  // We use standart 0x00000004 for Intel
-  // We use extended 0x8000001D for AMD
-  if(cpu->cpu_vendor == VENDOR_INTEL) {
-    level = 0x00000004;
-    if(cpu->maxLevels < level) {
-      printErr("Can't read cache information from cpuid (needed level is %d, max is %d)", level, cpu->maxLevels);    
-      return NULL;
-    }
-  }
-  else {
-    level = 0x8000001D;
-    if(cpu->maxExtendedLevels < level) {
-      printErr("Can't read cache information from cpuid (needed extended level is %d, max is %d)", level, cpu->maxExtendedLevels);    
-      return NULL;
-    }
-  }
-  
-  int i=0;
-  int32_t cache_type;
-  do {
-    eax = level; // get cache info
-    ebx = 0;
-    ecx = i; // cache id
-    edx = 0;
-      
-    cpuid(&eax, &ebx, &ecx, &edx); 
-      
-    cache_type = eax & 0x1F;
-      
-    // If its 0, we tried fetching a non existing cache
-    if (cache_type > 0) {
-      int32_t cache_level = (eax >>= 5) & 0x7;
-      uint32_t cache_sets = ecx + 1;
-      uint32_t cache_coherency_line_size = (ebx & 0xFFF) + 1;
-      uint32_t cache_physical_line_partitions = ((ebx >>= 12) & 0x3FF) + 1;
-      uint32_t cache_ways_of_associativity = ((ebx >>= 10) & 0x3FF) + 1;
-        
-      int32_t cache_total_size = cache_ways_of_associativity * cache_physical_line_partitions * cache_coherency_line_size * cache_sets;  
-      cach->max_cache_level++;
-      
-      switch (cache_type) {                
-        case 1: // Data Cache (We assume this is L1d)
-          if(cache_level != 1) {
-            printBug("Found data cache at level %d (expected 1)", cache_level);
-            return NULL;
-          }
-          cach->L1d->size = cache_total_size;
-          cach->L1d->exists = true;
-          break;
-            
-        case 2: // Instruction Cache (We assume this is L1i)
-          if(cache_level != 1) {
-            printBug("Found instruction cache at level %d (expected 1)", cache_level);
-            return NULL;
-          }
-          cach->L1i->size = cache_total_size;
-          cach->L1i->exists = true;
-          break;
-          
-        case 3: // Unified Cache (This may be L2 or L3)
-          if(cache_level == 2) { 
-            cach->L2->size = cache_total_size;
-            cach->L2->exists = true;
-          }
-          else if(cache_level == 3) {
-            cach->L3->size = cache_total_size;
-            cach->L3->exists = true;
-          }
-          else {
-            printBug("Found unified cache at level %d (expected == 2 or 3)", cache_level);
-            return NULL;
-          }
-          break;
-          
-        default: // Unknown Type Cache
-          printBug("Unknown Type Cache found at ID %d", i);
-          return NULL;                  
-      }
-    }    
-    
-    i++;
-  } while (cache_type > 0);
-  
-  // Sanity checks. If we read values greater than this, they can't be valid ones
-  // The values were chosen by me
-  if(cach->L1i->size > 64 * 1024) {
-    printBug("Invalid L1i size: %dKB", cach->L1i->size/1024);
-    return NULL;
-  }
-  if(cach->L1d->size > 64 * 1024) {
-    printBug("Invalid L1d size: %dKB", cach->L1d->size/1024);
-    return NULL;
-  }
-  if(cach->L2->exists) {
-    if(cach->L3->exists && cach->L2->size > 2 * 1048576) {
-      printBug("Invalid L2 size: %dMB", cach->L2->size/(1048576));
-      return NULL;
-    }
-    else if(cach->L2->size > 100 * 1048576) {
-      printBug("Invalid L2 size: %dMB", cach->L2->size/(1048576));
-      return NULL;
-    }
-  }
-  if(cach->L3->exists && cach->L3->size > 100 * 1048576) {
-    printBug("Invalid L3 size: %dMB", cach->L3->size/(1048576));
-    return NULL;
-  }
-  if(!cach->L2->exists) {
-    printBug("Could not find L2 cache");
-    return NULL;    
-  }
-  
-  return cach;
-}
-
-struct frequency* get_frequency_info(struct cpuInfo* cpu) {
-  struct frequency* freq = malloc(sizeof(struct frequency));
-  
-  if(cpu->maxLevels < 0x16) {
-    #ifdef _WIN32
-      printErr("Can't read frequency information from cpuid (needed level is %d, max is %d)", 0x16, cpu->maxLevels);
-      freq->base = UNKNOWN_FREQ;
-      freq->max = UNKNOWN_FREQ;
-    #else
-      printWarn("Can't read frequency information from cpuid (needed level is %d, max is %d). Using udev", 0x16, cpu->maxLevels);
-      freq->base = UNKNOWN_FREQ;
-      freq->max = get_max_freq_from_file();
-    #endif
-  }
-  else {
-    uint32_t eax = 0x16;
-    uint32_t ebx = 0;
-    uint32_t ecx = 0;
-    uint32_t edx = 0;
-    
-    cpuid(&eax, &ebx, &ecx, &edx);
-    
-    freq->base = eax;
-    freq->max = ebx;    
-  }
-  
-  return freq;
-}
-
-uint32_t get_nsockets(struct topology* topo) {
-  return topo->sockets;    
-}
-
-int64_t get_freq(struct frequency* freq) {
-  return freq->max;
-}
-
-VENDOR get_cpu_vendor(struct cpuInfo* cpu) {
-  return cpu->cpu_vendor;
-}
-
-void debug_cpu_info(struct cpuInfo* cpu) {
-  printf("AVX=%s\n", cpu->AVX ? "true" : "false");
-  printf("AVX2=%s\n", cpu->AVX2 ? "true" : "false");
-  printf("AVX512=%s\n\n", cpu->AVX512 ? "true" : "false");
-
-  printf("SSE=%s\n", cpu->SSE ? "true" : "false");
-  printf("SSE2=%s\n", cpu->SSE2 ? "true" : "false");
-  printf("SSE3=%s\n", cpu->SSE3 ? "true" : "false");
-  printf("SSSE3=%s\n", cpu->SSSE3 ? "true" : "false");
-  printf("SSE4a=%s\n", cpu->SSE4a ? "true" : "false");
-  printf("SSE4_1=%s\n", cpu->SSE4_1 ? "true" : "false");
-  printf("SSE4_2=%s\n\n", cpu->SSE4_2 ? "true" : "false");
-
-  printf("FMA3=%s\n", cpu->FMA3 ? "true" : "false");
-  printf("FMA4=%s\n\n", cpu->FMA4 ? "true" : "false");
-
-  printf("AES=%s\n", cpu->AES ? "true" : "false");
-  printf("SHA=%s\n", cpu->SHA ? "true" : "false");
-}
-
-void debug_cache(struct cache* cach) {
-  printf("L1i=%dB\n",cach->L1i->size);
-  printf("L1d=%dB\n",cach->L1d->size);
-  printf("L2=%dB\n",cach->L2->size);
-  printf("L3=%dB\n",cach->L3->size);
-}
-
-void debug_frequency(struct frequency* freq) {
-  #ifdef _WIN32
-    printf("maxf=%I64d Mhz\n",freq->max);
-    printf("basef=%I64d Mhz\n",freq->base);
-  #else
-    printf("maxf=%ld Mhz\n",freq->max);
-    printf("basef=%ld Mhz\n",freq->base);
-  #endif
-}
-
-/*** STRING FUNCTIONS ***/
-
-char* get_str_peak_performance(struct cpuInfo* cpu, struct topology* topo, int64_t freq) {
-  /***
-  PP = PeakPerformance
-  SP = SinglePrecision
-
-  PP(SP) =
-  N_CORES                             *
-  FREQUENCY                           *
-  2(Two vector units)                 *
-  2(If cpu has fma)                   *
-  16(If AVX512), 8(If AVX), 4(If SSE) *
-
-  ***/
-
-  //7 for GFLOP/s and 6 for digits,eg 412.14
-  uint32_t size = 7+6+1+1;
-  assert(strlen(STRING_UNKNOWN)+1 <= size);
-  char* string = malloc(sizeof(char)*size);
-
-  //First check we have consistent data
-  if(freq == UNKNOWN_FREQ) {
-    snprintf(string,strlen(STRING_UNKNOWN)+1,STRING_UNKNOWN);
-    return string;
-  }
-
-  double flops = topo->physical_cores * topo->sockets * (freq*1000000);
-  int vpus = get_number_of_vpus(cpu);
-  
-  flops = flops * vpus; 
-
-  if(cpu->FMA3 || cpu->FMA4)
-    flops = flops*2;
-
-  // Ice Lake has AVX512, but it has 1 VPU for AVX512, while
-  // it has 2 for AVX2. If this is a Ice Lake CPU, we are computing
-  // the peak performance supposing AVX2, not AVX512
-  if(cpu->AVX512 && vpus_are_AVX512(cpu))
-    flops = flops*16;
-  else if(cpu->AVX || cpu->AVX2)
-    flops = flops*8;
-  else if(cpu->SSE)
-    flops = flops*4;
-
-  if(flops >= (double)1000000000000.0)
-    snprintf(string,size,"%.2f TFLOP/s",flops/1000000000000);
-  else if(flops >= 1000000000.0)
-    snprintf(string,size,"%.2f GFLOP/s",flops/1000000000);
-  else
-    snprintf(string,size,"%.2f MFLOP/s",flops/1000000);
-  return string;
-}
-
-// TODO: Refactoring
-char* get_str_topology(struct cpuInfo* cpu, struct topology* topo, bool dual_socket) {
-  char* string;
-  if(topo->smt_supported > 1) {
-    //3 for digits, 21 for ' cores (SMT disabled)' which is the longest possible output
-    uint32_t size = 3+21+1;
-    string = malloc(sizeof(char)*size);
-    if(dual_socket) {
-      if(topo->smt_available > 1)
-        snprintf(string, size, "%d cores (%d threads)",topo->physical_cores * topo->sockets, topo->logical_cores * topo->sockets);
-      else {
-        if(cpu->cpu_vendor == VENDOR_AMD)
-          snprintf(string, size, "%d cores (SMT disabled)",topo->physical_cores * topo->sockets);
-        else
-          snprintf(string, size, "%d cores (HT disabled)",topo->physical_cores * topo->sockets);
-      }
-    }
-    else {
-      if(topo->smt_available > 1)
-        snprintf(string, size, "%d cores (%d threads)",topo->physical_cores,topo->logical_cores);
-      else {
-        if(cpu->cpu_vendor == VENDOR_AMD)
-          snprintf(string, size, "%d cores (SMT disabled)",topo->physical_cores);
-        else
-          snprintf(string, size, "%d cores (HT disabled)",topo->physical_cores);
-      }
-    }
-  }
-  else {
-    uint32_t size = 3+7+1;
-    string = malloc(sizeof(char)*size);
-    if(dual_socket)
-      snprintf(string, size, "%d cores",topo->physical_cores * topo->sockets);
-    else
-      snprintf(string, size, "%d cores",topo->physical_cores);
-  }
-  return string;
-}
-
-char* get_str_sockets(struct topology* topo) {
-  char* string = malloc(sizeof(char) * 2);
-  int32_t sanity_ret = snprintf(string, 2, "%d", topo->sockets);
-  if(sanity_ret < 0) {
-    printBug("get_str_sockets: snprintf returned a negative value for input: '%d'", topo->sockets);
-    return NULL;    
-  }
-  return string;
-}
-
-char* get_str_cpu_name(struct cpuInfo* cpu) {
-  return cpu->cpu_name;    
-}
-
-char* get_str_avx(struct cpuInfo* cpu) {
-  //If all AVX are available, it will use up to 15
-  char* string = malloc(sizeof(char)*17+1);
-  if(!cpu->AVX)
-    snprintf(string,2+1,"No");
-  else if(!cpu->AVX2)
-    snprintf(string,3+1,"AVX");
-  else if(!cpu->AVX512)
-    snprintf(string,8+1,"AVX,AVX2");
-  else
-    snprintf(string,15+1,"AVX,AVX2,AVX512");
-
-  return string;
-}
-
-char* get_str_sse(struct cpuInfo* cpu) {
-  uint32_t last = 0;
-  uint32_t SSE_sl = 4;
-  uint32_t SSE2_sl = 5;
-  uint32_t SSE3_sl = 5;
-  uint32_t SSSE3_sl = 6;
-  uint32_t SSE4a_sl = 6;
-  uint32_t SSE4_1_sl = 7;
-  uint32_t SSE4_2_sl = 7;
-  char* string = malloc(sizeof(char)*SSE_sl+SSE2_sl+SSE3_sl+SSSE3_sl+SSE4a_sl+SSE4_1_sl+SSE4_2_sl+1);
-
-  if(cpu->SSE) {
-      snprintf(string+last,SSE_sl+1,"SSE,");
-      last+=SSE_sl;
-  }
-  if(cpu->SSE2) {
-      snprintf(string+last,SSE2_sl+1,"SSE2,");
-      last+=SSE2_sl;
-  }
-  if(cpu->SSE3) {
-      snprintf(string+last,SSE3_sl+1,"SSE3,");
-      last+=SSE3_sl;
-  }
-  if(cpu->SSSE3) {
-      snprintf(string+last,SSSE3_sl+1,"SSSE3,");
-      last+=SSSE3_sl;
-  }
-  if(cpu->SSE4a) {
-      snprintf(string+last,SSE4a_sl+1,"SSE4a,");
-      last+=SSE4a_sl;
-  }
-  if(cpu->SSE4_1) {
-      snprintf(string+last,SSE4_1_sl+1,"SSE4.1,");
-      last+=SSE4_1_sl;
-  }
-  if(cpu->SSE4_2) {
-      snprintf(string+last,SSE4_2_sl+1,"SSE4.2,");
-      last+=SSE4_2_sl;
-  }
-
-  //Purge last comma
-  string[last-1] = '\0';
-  return string;
-}
-
-char* get_str_fma(struct cpuInfo* cpu) {
-  char* string = malloc(sizeof(char)*9+1);
-  if(!cpu->FMA3)
-    snprintf(string,2+1,"No");
-  else if(!cpu->FMA4)
-    snprintf(string,4+1,"FMA3");
-  else
-    snprintf(string,9+1,"FMA3,FMA4");
-
-  return string;
-}
-
-char* get_str_aes(struct cpuInfo* cpu) {
-  char* string = malloc(sizeof(char)*3+1);
-  if(cpu->AES)
-    snprintf(string,3+1,STRING_YES);
-  else
-    snprintf(string,2+1,STRING_NO);
-  return string;
-}
-
-char* get_str_sha(struct cpuInfo* cpu) {
-  char* string = malloc(sizeof(char)*3+1);
-  if(cpu->SHA)
-    snprintf(string,3+1,STRING_YES);
-  else
-    snprintf(string,2+1,STRING_NO);
-  return string;
-}
-
-int32_t get_value_as_smallest_unit(char ** str, uint32_t value) {
-  int32_t sanity_ret;    
-  *str = malloc(sizeof(char)* 11); //8 for digits, 2 for units
-
-  if(value/1024 >= 1024)
-    sanity_ret = snprintf(*str, 10,"%.4g"STRING_MEGABYTES, (double)value/(1<<20));    
-  else
-    sanity_ret = snprintf(*str, 10,"%.4g"STRING_KILOBYTES, (double)value/(1<<10));  
-  
-  return sanity_ret;
-}
-
-// String functions 
-char* get_str_cache_two(int32_t cache_size, uint32_t physical_cores) {
-  // 4 for digits, 2 for units, 2 for ' (', 3 digits, 2 for units and 7 for ' Total)'
-  uint32_t max_size = 4+2 + 2 + 4+2 + 7 + 1;
-  int32_t sanity_ret;
-  char* string = malloc(sizeof(char) * max_size);  
-  char* tmp1;
-  char* tmp2;  
-  int32_t tmp1_len = get_value_as_smallest_unit(&tmp1, cache_size);
-  int32_t tmp2_len = get_value_as_smallest_unit(&tmp2, cache_size * physical_cores);
-  
-  if(tmp1_len < 0) {
-    printBug("get_value_as_smallest_unit: snprintf returned a negative value for input: %d\n", cache_size);
-    return NULL;    
-  }
-  if(tmp2_len < 0) {
-    printBug("get_value_as_smallest_unit: snprintf returned a negative value for input: %d\n", cache_size * physical_cores);
-    return NULL;    
-  }
-    
-  uint32_t size = tmp1_len + 2 + tmp2_len + 7 + 1;
-  sanity_ret = snprintf(string, size, "%s (%s Total)", tmp1, tmp2);  
-  
-  if(sanity_ret < 0) {
-    printBug("get_str_cache_two: snprintf returned a negative value for input: '%s' and '%s'\n", tmp1, tmp2);
-    return NULL;    
-  }
-  
-  free(tmp1);
-  free(tmp2);
-  return string;
-}
-
-char* get_str_cache_one(int32_t cache_size) {
-  // 4 for digits, 2 for units, 2 for ' (', 3 digits, 2 for units and 7 for ' Total)'
-  uint32_t max_size = 4+2 + 1;
-  int32_t sanity_ret;
-  char* string = malloc(sizeof(char) * max_size);  
-  char* tmp;
-  int32_t tmp_len = get_value_as_smallest_unit(&tmp, cache_size);
-  
-  if(tmp_len < 0) {
-    printBug("get_value_as_smallest_unit: snprintf returned a negative value for input: %d", cache_size);
-    return NULL;    
-  }
-      
-  uint32_t size = tmp_len + 1;
-  sanity_ret = snprintf(string, size, "%s", tmp);
-  
-  if(sanity_ret < 0) {
-    printBug("get_str_cache_one: snprintf returned a negative value for input: '%s'", tmp);
-    return NULL;    
-  }
-  free(tmp);
-  return string;
-}
-
-char* get_str_cache(int32_t cache_size, int32_t num_caches) {
-  if(num_caches > 1)
-    return get_str_cache_two(cache_size, num_caches);
-  else
-    return get_str_cache_one(cache_size);
-}
-
-char* get_str_l1i(struct cache* cach) {
-  return get_str_cache(cach->L1i->size, cach->L1i->num_caches);
-}
-
-char* get_str_l1d(struct cache* cach) {
-  return get_str_cache(cach->L1d->size, cach->L1d->num_caches);
-}
-
-char* get_str_l2(struct cache* cach) {
-  assert(cach->L2->exists);
-  return get_str_cache(cach->L2->size, cach->L2->num_caches);
-}
-
-char* get_str_l3(struct cache* cach) {
-  if(!cach->L3->exists)
-    return NULL;  
-  return get_str_cache(cach->L3->size, cach->L3->num_caches);
-}
-
-char* get_str_freq(struct frequency* freq) {
-  //Max 3 digits and 3 for '(M/G)Hz' plus 1 for '\0'
-  uint32_t size = (4+3+1);
-  assert(strlen(STRING_UNKNOWN)+1 <= size);
-  char* string = malloc(sizeof(char)*size);
-  if(freq->max == UNKNOWN_FREQ)
-    snprintf(string,strlen(STRING_UNKNOWN)+1,STRING_UNKNOWN);
-  else if(freq->max >= 1000)
-    snprintf(string,size,"%.2f"STRING_GIGAHERZ,(float)(freq->max)/1000);
-  else
-    snprintf(string,size,"%.2f"STRING_MEGAHERZ,(float)(freq->max));
-  return string;
-}
-
-void print_levels(struct cpuInfo* cpu) {
-  printf("%s\n", cpu->cpu_name);
-  printf("- Max standart level: 0x%.8X\n", cpu->maxLevels);
-  printf("- Max extended level: 0x%.8X\n", cpu->maxExtendedLevels);
-  
-  free_cpuinfo_struct(cpu);
-}
-
-void free_topo_struct(struct topology* topo) {
-  free(topo->apic->cache_select_mask);
-  free(topo->apic->cache_id_apic);
-  free(topo->apic);
-  free(topo);
-}
-
-void free_cache_struct(struct cache* cach) {
-  for(int i=0; i < 4; i++) free(cach->cach_arr[i]);
-  free(cach->cach_arr);
-  free(cach);
-}
-
-void free_freq_struct(struct frequency* freq) {
-  free(freq);
-}
-
-void free_cpuinfo_struct(struct cpuInfo* cpu) {
-  free_uarch_struct(cpu->arch);
-  free(cpu->cpu_name);
-  free(cpu);
-}

src/cpuid.h

@@ -1,111 +0,0 @@
-#ifndef __CPUID__
-#define __CPUID__
-
-#include <stdint.h>
-
-#define VENDOR_EMPTY   0
-#define VENDOR_INTEL   1
-#define VENDOR_AMD     2
-#define VENDOR_INVALID 3
-
-#define UNKNOWN_FREQ -1
-
-typedef int32_t VENDOR;
-
-struct frequency;
-
-struct cpuInfo {
-  bool AVX;
-  bool AVX2;
-  bool AVX512;
-  bool SSE;
-  bool SSE2;
-  bool SSE3;
-  bool SSSE3;
-  bool SSE4a;
-  bool SSE4_1;
-  bool SSE4_2;
-  bool FMA3;
-  bool FMA4;
-  bool AES;
-  bool SHA;
-
-  VENDOR cpu_vendor;
-  
-  char* cpu_name;
-  //  Max cpuids levels
-  uint32_t maxLevels;
-  // Max cpuids extended levels
-  uint32_t maxExtendedLevels;
-  
-  struct uarch* arch;
-};
-
-struct cach {
-  int32_t size;
-  uint8_t num_caches;
-  bool exists;
-  // plenty of more properties to include in the future...
-};
-
-struct cache {
-  struct cach* L1i;
-  struct cach* L1d;
-  struct cach* L2;
-  struct cach* L3;
-  struct cach** cach_arr;
-  
-  uint8_t max_cache_level;
-};
-
-struct topology {
-  int64_t total_cores;
-  uint32_t physical_cores;
-  uint32_t logical_cores;
-  uint32_t smt_available; // Number of SMT that is currently enabled 
-  uint32_t smt_supported; // Number of SMT that CPU supports (equal to smt_available if SMT is enabled)
-  uint32_t sockets;  
-  struct apic* apic;
-  struct cache* cach;
-};
-
-struct cpuInfo* get_cpu_info();
-VENDOR get_cpu_vendor(struct cpuInfo* cpu);
-uint32_t get_nsockets(struct topology* topo);
-int64_t get_freq(struct frequency* freq);
-struct cache* get_cache_info(struct cpuInfo* cpu);
-struct frequency* get_frequency_info(struct cpuInfo* cpu);
-struct topology* get_topology_info(struct cpuInfo* cpu, struct cache* cach);
-
-char* get_str_cpu_name(struct cpuInfo* cpu);
-char* get_str_ncores(struct cpuInfo* cpu);
-char* get_str_avx(struct cpuInfo* cpu);
-char* get_str_sse(struct cpuInfo* cpu);
-char* get_str_fma(struct cpuInfo* cpu);
-char* get_str_aes(struct cpuInfo* cpu);
-char* get_str_sha(struct cpuInfo* cpu);
-
-char* get_str_l1i(struct cache* cach);
-char* get_str_l1d(struct cache* cach);
-char* get_str_l2(struct cache* cach);
-char* get_str_l3(struct cache* cach);
-
-char* get_str_freq(struct frequency* freq);
-
-char* get_str_sockets(struct topology* topo);
-char* get_str_topology(struct cpuInfo* cpu, struct topology* topo, bool dual_socket);
-
-char* get_str_peak_performance(struct cpuInfo* cpu, struct topology* topo, int64_t freq);
-
-void print_levels(struct cpuInfo* cpu);
-
-void free_cache_struct(struct cache* cach);
-void free_topo_struct(struct topology* topo);
-void free_freq_struct(struct frequency* freq);
-void free_cpuinfo_struct(struct cpuInfo* cpu);
-
-void debug_cpu_info(struct cpuInfo* cpu);
-void debug_cache(struct cache* cach);
-void debug_frequency(struct frequency* freq);
-
-#endif

src/main.c

@@ -1,85 +0,0 @@
-#include <stdio.h>
-#include <stdlib.h>
-
-#include "args.h"
-#include "printer.h"
-#include "cpuid.h"
-#include "global.h"
-
-static const char* VERSION = "0.7";
-
-void print_help(char *argv[]) {
-  printf("Usage: %s [--version] [--help] [--levels] [--style \"fancy\"|\"retro\"|\"legacy\"] [--color \"intel\"|\"amd\"|'R,G,B:R,G,B:R,G,B:R,G,B']\n\n\
-Options: \n\
-  --color       Set the color scheme. By default, cpufetch uses the system color scheme. This option \n\
-                lets the user use different colors to print the CPU art:  \n\
-   * \"intel\":   Use intel default color scheme \n\
-   * \"amd\":     Use amd default color scheme \n\
-   * custom:    If color do not match \"intel\" or \"amd\", a custom scheme can be specified: \n\
-                4 colors must be given in RGB with the format: R,G,B:R,G,B:... \n\
-                These colors correspond to CPU art color (2 colors) and for the text colors (following 2) \n\
-                For example: --color 239,90,45:210,200,200:100,200,45:0,200,200 \n\n\
-  --style       Set the style of CPU art: \n\
-    * \"fancy\":  Default style      \n\
-    * \"retro\":  Old cpufetch style \n\
-    * \"legacy\": Fallback style for terminals that does not support colors                       \n\n\
-  --levels      Prints CPU model and cpuid levels (debug purposes)\n\n\
-  --verbose     Prints extra information (if available) about how cpufetch tried fetching information\n\n\
-  --help        Prints this help and exit\n\n\
-  --version     Prints cpufetch version and exit\n\n\
-                                                   \n\
-NOTES: \n\
-  - Bugs or improvements should be submitted to: github.com/Dr-Noob/cpufetch/issues        \n\
-  - Peak performance information is NOT accurate. cpufetch computes peak performance using the max   \n\
-    frequency. However, to properly compute peak performance, you need to know the frequency of the  \n\
-    CPU running AVX code, which is not be fetched by cpufetch since it depends on each specific CPU. \n",
-  argv[0]);
-}
-
-void print_version() {
-  printf("cpufetch v%s\n",VERSION);
-}
-
-int main(int argc, char* argv[]) {
-  if(!parse_args(argc,argv))
-    return EXIT_FAILURE;
-
-  if(show_help()) {
-    print_help(argv);
-    return EXIT_SUCCESS;
-  }
-
-  if(show_version()) {
-    print_version();
-    return EXIT_SUCCESS;
-  }
-  
-  set_log_level(verbose_enabled());
-
-  struct cpuInfo* cpu = get_cpu_info();
-  if(cpu == NULL)
-    return EXIT_FAILURE;
-  
-  if(show_levels()) {
-    print_version();
-    print_levels(cpu);
-    return EXIT_SUCCESS;    
-  }  
-  
-  struct frequency* freq = get_frequency_info(cpu);
-  if(freq == NULL)
-    return EXIT_FAILURE;
-  
-  struct cache* cach = get_cache_info(cpu);
-  if(cach == NULL)
-    return EXIT_FAILURE;
-  
-  struct topology* topo = get_topology_info(cpu, cach);
-  if(topo == NULL)
-    return EXIT_FAILURE;
-  
-  if(print_cpufetch(cpu, cach, freq, topo, get_style(), get_colors()))  
-    return EXIT_SUCCESS;
-  else
-    return EXIT_FAILURE;
-}

src/ppc/ppc.c

@@ -0,0 +1,223 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+#include <assert.h>
+
+#include "ppc.h"
+#include "uarch.h"
+#include "udev.h"
+#include "../common/udev.h"
+#include "../common/global.h"
+
+struct cache* get_cache_info(struct cpuInfo* cpu) {
+  struct cache* cach = emalloc(sizeof(struct cache));
+  init_cache_struct(cach);
+
+  cach->L1i->size = get_l1i_cache_size(0);
+  cach->L1d->size = get_l1d_cache_size(0);
+  cach->L2->size = get_l2_cache_size(0);
+  cach->L3->size = get_l3_cache_size(0);
+
+  if(cach->L1i->size > 0) {
+    cach->L1i->exists = true;
+    cach->L1i->num_caches = get_num_caches_by_level(cpu, 0);
+    cach->max_cache_level = 1;
+  }
+  if(cach->L1d->size > 0) {
+    cach->L1d->exists = true;
+    cach->L1d->num_caches = get_num_caches_by_level(cpu, 1);
+    cach->max_cache_level = 2;
+  }
+  if(cach->L2->size > 0) {
+    cach->L2->exists = true;
+    cach->L2->num_caches = get_num_caches_by_level(cpu, 2);
+    cach->max_cache_level = 3;
+  }
+  if(cach->L3->size > 0) {
+    cach->L3->exists = true;
+    cach->L3->num_caches = get_num_caches_by_level(cpu, 3);
+    cach->max_cache_level = 4;
+  }
+
+  return cach;
+}
+
+struct topology* get_topology_info(struct cache* cach) {
+  struct topology* topo = emalloc(sizeof(struct topology));
+  init_topology_struct(topo, cach);
+
+  // 1. Total cores detection
+  if((topo->total_cores = sysconf(_SC_NPROCESSORS_ONLN)) == -1) {
+    printWarn("sysconf(_SC_NPROCESSORS_ONLN): %s", strerror(errno));
+    topo->total_cores = 1; // fallback
+  }
+
+  // To find physical cores, we use topo->total_cores and core_ids
+  // To find number of sockets, we use package_ids
+  int* core_ids = emalloc(sizeof(int) * topo->total_cores);
+  int* package_ids = emalloc(sizeof(int) * topo->total_cores);
+
+  if(!fill_core_ids_from_sys(core_ids, topo->total_cores)) {
+    printWarn("fill_core_ids_from_sys failed, output may be incomplete/invalid");
+    for(int i=0; i < topo->total_cores; i++) core_ids[i] = 0;
+  }
+  if(!fill_package_ids_from_sys(package_ids, topo->total_cores)) {
+    printWarn("fill_package_ids_from_sys failed, output may be incomplete/invalid");
+    for(int i=0; i < topo->total_cores; i++) package_ids[i] = 0;
+  }
+
+  // 2. Socket detection
+  int *package_ids_count = emalloc(sizeof(int) * topo->total_cores);
+  for(int i=0; i < topo->total_cores; i++) {
+    package_ids_count[i] = 0;
+  }
+  for(int i=0; i < topo->total_cores; i++) {
+    package_ids_count[package_ids[i]]++;
+  }
+  for(int i=0; i < topo->total_cores; i++) {
+    if(package_ids_count[i] != 0) {
+      topo->sockets++;
+    }
+  }
+
+  // 3. Physical cores detection
+  int *core_ids_unified = emalloc(sizeof(int) * topo->total_cores);
+  for(int i=0; i < topo->total_cores; i++) {
+    core_ids_unified[i] = -1;
+  }
+  bool found = false;
+  for(int i=0; i < topo->total_cores; i++) {
+    for(int j=0; j < topo->total_cores && !found; j++) {
+      if(core_ids_unified[j] == core_ids[i]) found = true;
+    }
+    if(!found) {
+      core_ids_unified[topo->physical_cores] = core_ids[i];
+      topo->physical_cores++;
+    }
+    found = false;
+  }
+
+  topo->physical_cores = topo->physical_cores / topo->sockets; // only count cores on one socket
+  topo->logical_cores = topo->total_cores / topo->sockets;     // only count threads on one socket
+  topo->smt_supported = topo->logical_cores / topo->physical_cores;
+
+  free(core_ids);
+  free(package_ids);
+  free(package_ids_count);
+  free(core_ids_unified);
+
+  return topo;
+}
+
+static inline uint32_t mfpvr() {
+    uint32_t pvr;
+
+    asm ("mfpvr %0"
+         : "=r"(pvr));
+    return pvr;
+}
+
+struct uarch* get_cpu_uarch(struct cpuInfo* cpu) {
+  return get_uarch_from_pvr(cpu->pvr);
+}
+
+struct frequency* get_frequency_info() {
+  struct frequency* freq = emalloc(sizeof(struct frequency));
+
+  freq->max = get_max_freq_from_file(0);
+  freq->base = get_min_freq_from_file(0);
+
+  return freq;
+}
+
+int64_t get_peak_performance(struct cpuInfo* cpu, struct topology* topo, int64_t freq) {
+  /*
+   * Not sure about this
+   * PP(SP) = N_CORES * FREQUENCY * 4(If altivec)
+   */
+
+  //First check we have consistent data
+  if(freq == UNKNOWN_FREQ) {
+    return -1;
+  }
+
+  struct features* feat = cpu->feat;
+  int64_t flops = topo->physical_cores * topo->sockets * (freq * 1000000);
+  if(feat->altivec) flops = flops * 4;
+
+  // POWER9 has the concept called "slices". Each SMT4 core has two super-slices,
+  // and each super-slice is capable of doing two FLOPS per cycle. In the case of
+  // SMT8, it has 4 super-slices, thus four FLOPS per cycle.
+  if(is_power9(cpu->arch)) {
+    int threads_per_core = topo->logical_cores / topo->physical_cores;
+    flops = flops * (threads_per_core / 2);
+  }
+
+  return flops;
+}
+
+struct cpuInfo* get_cpu_info() {
+  struct cpuInfo* cpu = emalloc(sizeof(struct cpuInfo));
+  struct features* feat = emalloc(sizeof(struct features));
+  cpu->feat = feat;
+
+  bool *ptr = &(feat->AES);
+  for(uint32_t i = 0; i < sizeof(struct features)/sizeof(bool); i++, ptr++) {
+    *ptr = false;
+  }
+
+  int len;
+  char* path = emalloc(sizeof(char) * (strlen(_PATH_DT) + strlen(_PATH_DT_PART) + 1));
+  sprintf(path, "%s%s", _PATH_DT, _PATH_DT_PART);
+
+  cpu->cpu_name = read_file(path, &len);
+  cpu->pvr = mfpvr();
+  cpu->arch = get_cpu_uarch(cpu);
+  cpu->freq = get_frequency_info();
+  cpu->topo = get_topology_info(cpu->cach);
+  cpu->cach = get_cache_info(cpu);
+  feat->altivec = has_altivec(cpu->arch);
+  cpu->peak_performance = get_peak_performance(cpu, cpu->topo, get_freq(cpu->freq));
+
+  if(cpu->cach == NULL || cpu->topo == NULL) {
+    return NULL;
+  }
+  return cpu;
+}
+
+char* get_str_altivec(struct cpuInfo* cpu) {
+  char* string = ecalloc(4, sizeof(char));
+
+  if(cpu->feat->altivec) strcpy(string, "Yes");
+  else strcpy(string, "No");
+
+  return string;
+}
+
+char* get_str_topology(struct topology* topo, bool dual_socket) {
+  char* string;
+  if(topo->smt_supported > 1) {
+    uint32_t size = 3+3+17+1;
+    string = emalloc(sizeof(char)*size);
+    if(dual_socket)
+      snprintf(string, size, "%d cores (%d threads)", topo->physical_cores * topo->sockets, topo->logical_cores * topo->sockets);
+    else
+      snprintf(string, size, "%d cores (%d threads)",topo->physical_cores,topo->logical_cores);
+  }
+  else {
+    uint32_t size = 3+7+1;
+    string = emalloc(sizeof(char)*size);
+    if(dual_socket)
+      snprintf(string, size, "%d cores",topo->physical_cores * topo->sockets);
+    else
+      snprintf(string, size, "%d cores",topo->physical_cores);
+  }
+  return string;
+}
+
+
+void print_debug(struct cpuInfo* cpu) {
+  printf("PVR: 0x%.8X\n", cpu->pvr);
+}

src/ppc/ppc.h

@@ -0,0 +1,11 @@
+#ifndef __POWERPC__
+#define __POWERPC__
+
+#include "../common/cpu.h"
+
+struct cpuInfo* get_cpu_info();
+char* get_str_altivec(struct cpuInfo* cpu);
+char* get_str_topology(struct topology* topo, bool dual_socket);
+void print_debug(struct cpuInfo* cpu);
+
+#endif

src/ppc/pvr_kern_to_cpufetch.sh

@@ -0,0 +1,28 @@
+#!/bin/bash
+
+# This script takes as input cputable.c from linux kernel
+# and generates a valid output for cpufetch in src/ppc/uarch.c
+
+CPUTABLE_PATH="linux-5.13.7/arch/powerpc/kernel/cputable.c"
+
+raw_values=$(grep '\.pvr_value' "$CPUTABLE_PATH" | grep -oP "= .*," | cut -d' ' -f2 | tr -d ',')
+raw_masks=$(grep '\.pvr_mask' "$CPUTABLE_PATH" | grep -oE "0x........")
+
+raw_v_len=$(echo "$raw_values" | wc -l)
+raw_m_len=$(echo "$raw_masks" | wc -l)
+
+if [ $raw_v_len -ne $raw_m_len ]
+then
+  echo "Lengths do not match!"
+  echo "values length: $raw_v_len"
+  echo "masks length:  $raw_m_len"
+  exit 1
+fi
+
+IFS=$'\n' read -r -d ' ' -a values <<< "$raw_values"
+IFS=$'\n' read -r -d ' ' -a masks <<< "$raw_masks"
+
+for i in "${!values[@]}"
+do
+  echo '  CHECK_UARCH(arch, pvr, '"${masks[i]}"', '"${values[i]}"', "POWERX", UARCH_POWERX, -1)'
+done

src/ppc/uarch.c

@@ -0,0 +1,286 @@
+#include <stdint.h>
+#include <stdbool.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/auxv.h>
+#include <errno.h>
+
+#include "uarch.h"
+#include "../common/global.h"
+
+typedef uint32_t MICROARCH;
+
+// Data not available
+#define NA                   -1
+
+// Unknown manufacturing process
+#define UNK                  -1
+
+enum {
+  UARCH_UNKNOWN,
+  UARCH_PPC604,
+  UARCH_PPCG3,
+  UARCH_PPCG4,
+  UARCH_PPC405,
+  UARCH_PPC603,
+  UARCH_PPC440,
+  UARCH_PPC470,
+  UARCH_PPC970,
+  UARCH_PPC970FX,
+  UARCH_PPC970MP,
+  UARCH_CELLBE,
+  UARCH_POWER5,
+  UARCH_POWER5PLUS,
+  UARCH_POWER6,
+  UARCH_POWER7,
+  UARCH_POWER7PLUS,
+  UARCH_POWER8,
+  UARCH_POWER9,
+  UARCH_POWER9_DD20,
+  UARCH_POWER9_DD21,
+  UARCH_POWER9_DD22,
+  UARCH_POWER9_DD23,
+  UARCH_POWER10,
+};
+
+struct uarch {
+  MICROARCH uarch;
+  char* uarch_str;
+  int32_t process; // measured in nanometers
+};
+
+#define UARCH_START if (false) {}
+#define CHECK_UARCH(arch, cpu_pvr, pvr_mask, pvr_value, uarch) \
+   else if ((cpu_pvr & pvr_mask) == pvr_value) fill_uarch(arch, uarch);
+#define UARCH_END else { printBug("Unknown microarchitecture detected: 0x%.8X", pvr); fill_uarch(arch, UARCH_UNKNOWN); }
+
+#define FILL_START if (false) {}
+#define FILL_UARCH(u, uarch, uarch_str, uarch_process) \
+   else if(u == uarch) { fill = true; str = uarch_str; process = uarch_process; }
+#define FILL_END else { printBug("Found invalid microarchitecture: %d", u); }
+
+void fill_uarch(struct uarch* arch, MICROARCH u) {
+  arch->uarch = u;
+  char* str = NULL;
+  int32_t process = UNK;
+  bool fill = false;
+
+  FILL_START
+  FILL_UARCH(arch->uarch, UARCH_UNKNOWN,     STRING_UNKNOWN,  UNK)
+  FILL_UARCH(arch->uarch, UARCH_PPC604,      "PowerPC 604",   500)
+  FILL_UARCH(arch->uarch, UARCH_PPCG3,       "PowerPC G3",    UNK) // varies
+  FILL_UARCH(arch->uarch, UARCH_PPCG4,       "PowerPC G4",    UNK) // varies
+  FILL_UARCH(arch->uarch, UARCH_PPC405,      "PowerPC 405",   UNK)
+  FILL_UARCH(arch->uarch, UARCH_PPC603,      "PowerPC 603",   UNK) // varies
+  FILL_UARCH(arch->uarch, UARCH_PPC440,      "PowerPC 440",   UNK)
+  FILL_UARCH(arch->uarch, UARCH_PPC470,      "PowerPC 470",    45) // strange...
+  FILL_UARCH(arch->uarch, UARCH_PPC970,      "PowerPC 970",   130)
+  FILL_UARCH(arch->uarch, UARCH_PPC970FX,    "PowerPC 970FX",  90)
+  FILL_UARCH(arch->uarch, UARCH_PPC970MP,    "PowerPC 970MP",  90)
+  FILL_UARCH(arch->uarch, UARCH_CELLBE,      "Cell BE",       UNK) // varies depending on manufacturer
+  FILL_UARCH(arch->uarch, UARCH_POWER5,      "POWER5",        130)
+  FILL_UARCH(arch->uarch, UARCH_POWER5PLUS,  "POWER5+",        90)
+  FILL_UARCH(arch->uarch, UARCH_POWER6,      "POWER6",         65)
+  FILL_UARCH(arch->uarch, UARCH_POWER7,      "POWER7",         45)
+  FILL_UARCH(arch->uarch, UARCH_POWER7PLUS,  "POWER7+",        32)
+  FILL_UARCH(arch->uarch, UARCH_POWER8,      "POWER8",         22)
+  FILL_UARCH(arch->uarch, UARCH_POWER9,      "POWER9",         14)
+  FILL_UARCH(arch->uarch, UARCH_POWER9_DD20, "POWER9 (DD2.0)", 14)
+  FILL_UARCH(arch->uarch, UARCH_POWER9_DD21, "POWER9 (DD2.1)", 14)
+  FILL_UARCH(arch->uarch, UARCH_POWER9_DD22, "POWER9 (DD2.2)", 14)
+  FILL_UARCH(arch->uarch, UARCH_POWER9_DD23, "POWER9 (DD2.3)", 14)
+  FILL_UARCH(arch->uarch, UARCH_POWER10,     "POWER10",         7)
+  FILL_END
+
+  if(fill) {
+    arch->uarch_str = emalloc(sizeof(char) * (strlen(str)+1));
+    strcpy(arch->uarch_str, str);
+    arch->process= process;
+  }
+}
+
+/*
+ * PVR masks/values from arch/powerpc/kernel/cputable.c (Linux kernel)
+ * This list may be incorrect, incomplete or overly simplified,
+ * specially in the case of 32 bit entries
+ */
+struct uarch* get_uarch_from_pvr(uint32_t pvr) {
+  struct uarch* arch = emalloc(sizeof(struct uarch));
+
+  UARCH_START
+  // 64 bit
+  CHECK_UARCH(arch, pvr, 0xffff0000, 0x00390000, UARCH_PPC970)
+  CHECK_UARCH(arch, pvr, 0xffff0000, 0x003c0000, UARCH_PPC970FX)
+  CHECK_UARCH(arch, pvr, 0xffffffff, 0x00440100, UARCH_PPC970MP)
+  CHECK_UARCH(arch, pvr, 0xffff0000, 0x00440000, UARCH_PPC970MP)
+  CHECK_UARCH(arch, pvr, 0xffff0000, 0x003a0000, UARCH_POWER5)
+  CHECK_UARCH(arch, pvr, 0xffffff00, 0x003b0300, UARCH_POWER5PLUS)
+  CHECK_UARCH(arch, pvr, 0xffff0000, 0x003b0000, UARCH_POWER5)
+  CHECK_UARCH(arch, pvr, 0xffffffff, 0x0f000001, UARCH_POWER5)
+  CHECK_UARCH(arch, pvr, 0xffff0000, 0x003e0000, UARCH_POWER6)
+  CHECK_UARCH(arch, pvr, 0xffffffff, 0x0f000002, UARCH_POWER6)
+  CHECK_UARCH(arch, pvr, 0xffffffff, 0x0f000003, UARCH_POWER7)
+  CHECK_UARCH(arch, pvr, 0xffffffff, 0x0f000004, UARCH_POWER8)
+  CHECK_UARCH(arch, pvr, 0xffffffff, 0x0f000005, UARCH_POWER9)
+  CHECK_UARCH(arch, pvr, 0xffffffff, 0x0f000006, UARCH_POWER10)
+  CHECK_UARCH(arch, pvr, 0xffff0000, 0x003f0000, UARCH_POWER7)
+  CHECK_UARCH(arch, pvr, 0xffff0000, 0x004A0000, UARCH_POWER7PLUS)
+  CHECK_UARCH(arch, pvr, 0xffff0000, 0x004b0000, UARCH_POWER8)
+  CHECK_UARCH(arch, pvr, 0xffff0000, 0x004c0000, UARCH_POWER8)
+  CHECK_UARCH(arch, pvr, 0xffff0000, 0x004d0000, UARCH_POWER8)
+  CHECK_UARCH(arch, pvr, 0xffffefff, 0x004e0200, UARCH_POWER9_DD20)
+  CHECK_UARCH(arch, pvr, 0xffffefff, 0x004e0201, UARCH_POWER9_DD21)
+  CHECK_UARCH(arch, pvr, 0xffffefff, 0x004e0202, UARCH_POWER9_DD22)
+  CHECK_UARCH(arch, pvr, 0xffffefff, 0x004e0203, UARCH_POWER9_DD23)
+  CHECK_UARCH(arch, pvr, 0xffff0000, 0x00800000, UARCH_POWER10)
+  CHECK_UARCH(arch, pvr, 0xffff0000, 0x00700000, UARCH_CELLBE)
+  // 32 bit
+  CHECK_UARCH(arch, pvr, 0xffff0000, 0x00040000, UARCH_PPC604)
+  CHECK_UARCH(arch, pvr, 0xfffff000, 0x00090000, UARCH_PPC604)
+  CHECK_UARCH(arch, pvr, 0xffff0000, 0x00090000, UARCH_PPC604)
+  CHECK_UARCH(arch, pvr, 0xffff0000, 0x000a0000, UARCH_PPC604)
+  CHECK_UARCH(arch, pvr, 0xffffffff, 0x00084202, UARCH_PPCG3)
+  CHECK_UARCH(arch, pvr, 0xfffffff0, 0x00080100, UARCH_PPCG3)
+  CHECK_UARCH(arch, pvr, 0xfffffff0, 0x00082200, UARCH_PPCG3)
+  CHECK_UARCH(arch, pvr, 0xfffffff0, 0x00082210, UARCH_PPCG3)
+  CHECK_UARCH(arch, pvr, 0xffffffff, 0x00083214, UARCH_PPCG3)
+  CHECK_UARCH(arch, pvr, 0xfffff0e0, 0x00087000, UARCH_PPCG3)
+  CHECK_UARCH(arch, pvr, 0xfffff000, 0x00083000, UARCH_PPCG3)
+  CHECK_UARCH(arch, pvr, 0xffffff00, 0x70000100, UARCH_PPCG3)
+  CHECK_UARCH(arch, pvr, 0xffffffff, 0x70000200, UARCH_PPCG3)
+  CHECK_UARCH(arch, pvr, 0xffff0000, 0x70000000, UARCH_PPCG3)
+  CHECK_UARCH(arch, pvr, 0xffff0000, 0x70020000, UARCH_PPCG3)
+  CHECK_UARCH(arch, pvr, 0xffff0000, 0x00080000, UARCH_PPCG3)
+  CHECK_UARCH(arch, pvr, 0xffffffff, 0x000c1101, UARCH_PPCG4)
+  CHECK_UARCH(arch, pvr, 0xffff0000, 0x000c0000, UARCH_PPCG4)
+  CHECK_UARCH(arch, pvr, 0xffff0000, 0x800c0000, UARCH_PPCG4)
+  CHECK_UARCH(arch, pvr, 0xffffffff, 0x80000200, UARCH_PPCG4)
+  CHECK_UARCH(arch, pvr, 0xffffffff, 0x80000201, UARCH_PPCG4)
+  CHECK_UARCH(arch, pvr, 0xffff0000, 0x80000000, UARCH_PPCG4)
+  CHECK_UARCH(arch, pvr, 0xffffff00, 0x80010100, UARCH_PPCG4)
+  CHECK_UARCH(arch, pvr, 0xffffffff, 0x80010200, UARCH_PPCG4)
+  CHECK_UARCH(arch, pvr, 0xffff0000, 0x80010000, UARCH_PPCG4)
+  CHECK_UARCH(arch, pvr, 0xffffffff, 0x80020100, UARCH_PPCG4)
+  CHECK_UARCH(arch, pvr, 0xffffffff, 0x80020101, UARCH_PPCG4)
+  CHECK_UARCH(arch, pvr, 0xffff0000, 0x80020000, UARCH_PPCG4)
+  CHECK_UARCH(arch, pvr, 0xffff0000, 0x80030000, UARCH_PPCG4)
+  CHECK_UARCH(arch, pvr, 0xffff0000, 0x80040000, UARCH_PPCG4)
+  CHECK_UARCH(arch, pvr, 0xffff0000, 0x00030000, UARCH_PPC603)
+  CHECK_UARCH(arch, pvr, 0xffff0000, 0x00060000, UARCH_PPC603)
+  CHECK_UARCH(arch, pvr, 0xffff0000, 0x00070000, UARCH_PPC603)
+  CHECK_UARCH(arch, pvr, 0x7fff0000, 0x00810000, UARCH_PPC603)
+  CHECK_UARCH(arch, pvr, 0x7fff0000, 0x00820000, UARCH_PPC603)
+  CHECK_UARCH(arch, pvr, 0x7fff0000, 0x00830000, UARCH_PPC603)
+  CHECK_UARCH(arch, pvr, 0x7fff0000, 0x00840000, UARCH_PPC603)
+  CHECK_UARCH(arch, pvr, 0x7fff0000, 0x00850000, UARCH_PPC603)
+  CHECK_UARCH(arch, pvr, 0x7fff0000, 0x00860000, UARCH_PPC603)
+  CHECK_UARCH(arch, pvr, 0xffff0000, 0x41810000, UARCH_PPC405)
+  CHECK_UARCH(arch, pvr, 0xffff0000, 0x41610000, UARCH_PPC405)
+  CHECK_UARCH(arch, pvr, 0xffff0000, 0x40B10000, UARCH_PPC405)
+  CHECK_UARCH(arch, pvr, 0xffff0000, 0x41410000, UARCH_PPC405)
+  CHECK_UARCH(arch, pvr, 0xffff0000, 0x50910000, UARCH_PPC405)
+  CHECK_UARCH(arch, pvr, 0xffff0000, 0x51510000, UARCH_PPC405)
+  CHECK_UARCH(arch, pvr, 0xffff0000, 0x41F10000, UARCH_PPC405)
+  CHECK_UARCH(arch, pvr, 0xffff0000, 0x51210000, UARCH_PPC405)
+  CHECK_UARCH(arch, pvr, 0xffff000f, 0x12910007, UARCH_PPC405)
+  CHECK_UARCH(arch, pvr, 0xffff000f, 0x1291000d, UARCH_PPC405)
+  CHECK_UARCH(arch, pvr, 0xffff000f, 0x1291000f, UARCH_PPC405)
+  CHECK_UARCH(arch, pvr, 0xffff000f, 0x12910003, UARCH_PPC405)
+  CHECK_UARCH(arch, pvr, 0xffff000f, 0x12910005, UARCH_PPC405)
+  CHECK_UARCH(arch, pvr, 0xffff000f, 0x12910001, UARCH_PPC405)
+  CHECK_UARCH(arch, pvr, 0xffff000f, 0x12910009, UARCH_PPC405)
+  CHECK_UARCH(arch, pvr, 0xffff000f, 0x1291000b, UARCH_PPC405)
+  CHECK_UARCH(arch, pvr, 0xffff000f, 0x12910000, UARCH_PPC405)
+  CHECK_UARCH(arch, pvr, 0xffff000f, 0x12910002, UARCH_PPC405)
+  CHECK_UARCH(arch, pvr, 0xffff0000, 0x41510000, UARCH_PPC405)
+  CHECK_UARCH(arch, pvr, 0xffff0000, 0x7ff11432, UARCH_PPC405)
+  CHECK_UARCH(arch, pvr, 0xf0000fff, 0x40000850, UARCH_PPC440)
+  CHECK_UARCH(arch, pvr, 0xf0000fff, 0x40000858, UARCH_PPC440)
+  CHECK_UARCH(arch, pvr, 0xf0000fff, 0x400008d3, UARCH_PPC440)
+  CHECK_UARCH(arch, pvr, 0xf0000ff7, 0x400008d4, UARCH_PPC440)
+  CHECK_UARCH(arch, pvr, 0xf0000fff, 0x400008db, UARCH_PPC440)
+  CHECK_UARCH(arch, pvr, 0xf0000ffb, 0x200008D0, UARCH_PPC440)
+  CHECK_UARCH(arch, pvr, 0xf0000ffb, 0x200008D8, UARCH_PPC440)
+  CHECK_UARCH(arch, pvr, 0xf0000fff, 0x40000440, UARCH_PPC440)
+  CHECK_UARCH(arch, pvr, 0xf0000fff, 0x40000481, UARCH_PPC440)
+  CHECK_UARCH(arch, pvr, 0xf0000fff, 0x50000850, UARCH_PPC440)
+  CHECK_UARCH(arch, pvr, 0xf0000fff, 0x50000851, UARCH_PPC440)
+  CHECK_UARCH(arch, pvr, 0xf0000fff, 0x50000892, UARCH_PPC440)
+  CHECK_UARCH(arch, pvr, 0xf0000fff, 0x50000894, UARCH_PPC440)
+  CHECK_UARCH(arch, pvr, 0xfff00fff, 0x53200891, UARCH_PPC440)
+  CHECK_UARCH(arch, pvr, 0xfff00fff, 0x53400890, UARCH_PPC440)
+  CHECK_UARCH(arch, pvr, 0xfff00fff, 0x53400891, UARCH_PPC440)
+  CHECK_UARCH(arch, pvr, 0xffff0006, 0x13020002, UARCH_PPC440)
+  CHECK_UARCH(arch, pvr, 0xffff0007, 0x13020004, UARCH_PPC440)
+  CHECK_UARCH(arch, pvr, 0xffff0006, 0x13020000, UARCH_PPC440)
+  CHECK_UARCH(arch, pvr, 0xffff0007, 0x13020005, UARCH_PPC440)
+  CHECK_UARCH(arch, pvr, 0xffffff00, 0x13541800, UARCH_PPC440)
+  CHECK_UARCH(arch, pvr, 0xfffffff0, 0x12C41C80, UARCH_PPC440)
+  CHECK_UARCH(arch, pvr, 0xffffffff, 0x11a52080, UARCH_PPC470)
+  CHECK_UARCH(arch, pvr, 0xffff0000, 0x7ff50000, UARCH_PPC470)
+  CHECK_UARCH(arch, pvr, 0xffff0000, 0x00050000, UARCH_PPC470)
+  CHECK_UARCH(arch, pvr, 0xffff0000, 0x11a50000, UARCH_PPC470)
+  UARCH_END
+
+  return arch;
+}
+
+bool has_altivec(struct uarch* arch) {
+  switch(arch->uarch) {
+    case UARCH_PPC970FX:
+    case UARCH_PPC970MP:
+    case UARCH_CELLBE:
+    case UARCH_POWER6:
+    case UARCH_POWER7:
+    case UARCH_POWER7PLUS:
+    case UARCH_POWER8:
+    case UARCH_POWER9:
+    case UARCH_POWER9_DD20:
+    case UARCH_POWER9_DD21:
+    case UARCH_POWER9_DD22:
+    case UARCH_POWER9_DD23:
+    case UARCH_POWER10:
+      return true;
+    default:
+      return false;
+  }
+}
+
+bool is_power9(struct uarch* arch) {
+  return arch->uarch == UARCH_POWER9      ||
+         arch->uarch == UARCH_POWER9_DD20 ||
+         arch->uarch == UARCH_POWER9_DD21 ||
+         arch->uarch == UARCH_POWER9_DD22 ||
+         arch->uarch == UARCH_POWER9_DD23;
+}
+
+char* get_str_uarch(struct cpuInfo* cpu) {
+  return cpu->arch->uarch_str;
+}
+
+char* get_str_process(struct cpuInfo* cpu) {
+  char* str = emalloc(sizeof(char) * (strlen(STRING_UNKNOWN)+1));
+  int32_t process = cpu->arch->process;
+
+  if(process == UNK) {
+    snprintf(str, strlen(STRING_UNKNOWN)+1, STRING_UNKNOWN);
+  }
+  else if(process > 100) {
+    sprintf(str, "%.2fum", (double)process/100);
+  }
+  else if(process > 0){
+    sprintf(str, "%dnm", process);
+  }
+  else {
+    snprintf(str, strlen(STRING_UNKNOWN)+1, STRING_UNKNOWN);
+    printBug("Found invalid process: '%d'", process);
+  }
+
+  return str;
+}
+
+void free_uarch_struct(struct uarch* arch) {
+  free(arch->uarch_str);
+  free(arch);
+}

src/ppc/uarch.h

@@ -0,0 +1,16 @@
+#ifndef __UARCH__
+#define __UARCH__
+
+#include <stdint.h>
+#include "ppc.h"
+
+struct uarch;
+
+struct uarch* get_uarch_from_pvr(uint32_t pvr);
+bool has_altivec(struct uarch* arch);
+bool is_power9(struct uarch* arch);
+char* get_str_uarch(struct cpuInfo* cpu);
+char* get_str_process(struct cpuInfo* cpu);
+void free_uarch_struct(struct uarch* arch);
+
+#endif

src/ppc/udev.c

@@ -0,0 +1,40 @@
+#include <errno.h>
+
+#include "../common/global.h"
+#include "udev.h"
+
+#define _PATH_TOPO_CORE_ID    "topology/core_id"
+#define _PATH_TOPO_PACKAGE_ID "topology/physical_package_id"
+
+bool fill_array_from_sys(int *core_ids, int total_cores, char* SYS_PATH) {
+  int filelen;
+  char* buf;
+  char* end;
+  char path[128];
+
+  for(int i=0; i < total_cores; i++) {
+    sprintf(path, "%s%s/cpu%d/%s", _PATH_SYS_SYSTEM, _PATH_SYS_CPU, i, SYS_PATH);
+    if((buf = read_file(path, &filelen)) == NULL) {
+      printWarn("fill_array_from_sys: %s: %s", path, strerror(errno));
+      return false;
+    }
+
+    errno = 0;
+    core_ids[i] = strtol(buf, &end, 10);
+    if(errno != 0) {
+      printWarn("fill_array_from_sys: %s:", strerror(errno));
+      return false;
+    }
+    free(buf);
+  }
+
+  return true;
+}
+
+bool fill_core_ids_from_sys(int *core_ids, int total_cores) {
+  return fill_array_from_sys(core_ids, total_cores, _PATH_TOPO_CORE_ID);
+}
+
+bool fill_package_ids_from_sys(int* package_ids, int total_cores) {
+  return fill_array_from_sys(package_ids, total_cores, _PATH_TOPO_PACKAGE_ID);
+}

src/ppc/udev.h

@@ -0,0 +1,11 @@
+#ifndef __UDEV_PPC__
+#define __UDEV_PPC__
+
+#include "../common/udev.h"
+#define _PATH_DT              "/proc/device-tree/vpd/root-node-vpd@a000/enclosure@1e00/backplane@800/processor@1000"
+#define _PATH_DT_PART         "/part-number"
+
+bool fill_core_ids_from_sys(int *core_ids, int total_cores);
+bool fill_package_ids_from_sys(int* package_ids, int total_cores);
+
+#endif

src/printer.c

@@ -1,388 +0,0 @@
-#include <stdlib.h>
-#include <string.h>
-#include <stdio.h>
-#include <stdbool.h>
-
-#include "printer.h"
-#include "ascii.h"
-#include "global.h"
-#include "cpuid.h"
-#include "uarch.h"
-
-#define COL_NONE          ""
-#define COL_INTEL_FANCY_1 "\x1b[46;1m"
-#define COL_INTEL_FANCY_2 "\x1b[47;1m"
-#define COL_INTEL_FANCY_3 "\x1b[36;1m"
-#define COL_INTEL_FANCY_4 "\x1b[37;1m"
-#define COL_INTEL_RETRO_1 "\x1b[36;1m"
-#define COL_INTEL_RETRO_2 "\x1b[37;1m"
-#define COL_AMD_FANCY_1   "\x1b[47;1m"
-#define COL_AMD_FANCY_2   "\x1b[42;1m"
-#define COL_AMD_FANCY_3   "\x1b[37;1m"
-#define COL_AMD_FANCY_4   "\x1b[32;1m"
-#define COL_AMD_RETRO_1   "\x1b[37;1m"
-#define COL_AMD_RETRO_2   "\x1b[32;1m"
-#define RESET             "\x1b[m"
-
-#define TITLE_NAME          "Name:"
-#define TITLE_FREQUENCY     "Max Frequency:"
-#define TITLE_SOCKETS       "Sockets:" 
-#define TITLE_NCORES        "Cores:" 
-#define TITLE_NCORES_DUAL   "Cores (Total):"
-#define TITLE_AVX           "AVX:"
-#define TITLE_SSE           "SSE:"
-#define TITLE_FMA           "FMA:"
-#define TITLE_AES           "AES:"
-#define TITLE_SHA           "SHA:"
-#define TITLE_L1i           "L1i Size:"
-#define TITLE_L1d           "L1d Size:"
-#define TITLE_L2            "L2 Size:"
-#define TITLE_L3            "L3 Size:"
-#define TITLE_PEAK          "Peak Performance:"
-#define TITLE_UARCH         "Microarchitecture:"
-#define TITLE_TECHNOLOGY    "Technology:"
-
-#define MAX_ATTRIBUTE_COUNT      14
-#define ATTRIBUTE_NAME            0
-#define ATTRIBUTE_UARCH           1
-#define ATTRIBUTE_TECHNOLOGY      2
-#define ATTRIBUTE_FREQUENCY       3
-#define ATTRIBUTE_SOCKETS         4
-#define ATTRIBUTE_NCORES          5
-#define ATTRIBUTE_NCORES_DUAL     6
-#define ATTRIBUTE_AVX             7
-#define ATTRIBUTE_FMA             8
-#define ATTRIBUTE_L1i             9
-#define ATTRIBUTE_L1d            10
-#define ATTRIBUTE_L2             11
-#define ATTRIBUTE_L3             12
-#define ATTRIBUTE_PEAK           13
-
-static const char* ATTRIBUTE_FIELDS [MAX_ATTRIBUTE_COUNT] = { TITLE_NAME, TITLE_UARCH, TITLE_TECHNOLOGY,
-                                                              TITLE_FREQUENCY, TITLE_SOCKETS,
-                                                              TITLE_NCORES, TITLE_NCORES_DUAL, 
-                                                              TITLE_AVX,
-                                                              TITLE_FMA, TITLE_L1i, TITLE_L1d, TITLE_L2, TITLE_L3,
-                                                              TITLE_PEAK, 
-                                                               };
-
-static const int ATTRIBUTE_LIST[MAX_ATTRIBUTE_COUNT] =  { ATTRIBUTE_NAME, ATTRIBUTE_UARCH, ATTRIBUTE_TECHNOLOGY,
-                                                        ATTRIBUTE_FREQUENCY, ATTRIBUTE_SOCKETS,
-                                                        ATTRIBUTE_NCORES, ATTRIBUTE_NCORES_DUAL, ATTRIBUTE_AVX,
-                                                        ATTRIBUTE_FMA, 
-                                                        ATTRIBUTE_L1i, ATTRIBUTE_L1d, ATTRIBUTE_L2, ATTRIBUTE_L3,
-                                                        ATTRIBUTE_PEAK };
-
-struct ascii {
-  char art[NUMBER_OF_LINES][LINE_SIZE];
-  char color1_ascii[100];
-  char color2_ascii[100];
-  char color1_text[100];
-  char color2_text[100];
-  char ascii_chars[2];
-  char reset[100];
-  char* attributes[MAX_ATTRIBUTE_COUNT];
-  uint32_t n_attributes_set;
-  VENDOR vendor;
-};
-
-void setAttribute(struct ascii* art, int type, char* value) {
-  art->attributes[type] = value;  
-  art->n_attributes_set++;
-}
-
-char* rgb_to_ansi(struct color* c, bool background, bool bold) {
-  char* str = malloc(sizeof(char) * 100);
-  if(background) {
-    snprintf(str, 44, "\x1b[48;2;%.3d;%.3d;%.3dm", c->R, c->G, c->B);
-  }
-  else {
-    if(bold)
-      snprintf(str, 48, "\x1b[1m\x1b[38;2;%.3d;%.3d;%.3dm", c->R, c->G, c->B);
-    else
-      snprintf(str, 44, "\x1b[38;2;%.3d;%.3d;%.3dm", c->R, c->G, c->B);
-  }
-  
-  return str;
-}
-
-struct ascii* set_ascii(VENDOR cpuVendor, STYLE style, struct colors* cs) {
-  // Sanity checks //
-  for(int i=0; i < MAX_ATTRIBUTE_COUNT; i++) {
-    if(ATTRIBUTE_FIELDS[i] == NULL) {
-      printBug("Attribute field at position %d is empty", i);    
-      return NULL;
-    }
-    if(i > 0 && ATTRIBUTE_LIST[i] == 0) {
-      printBug("Attribute list at position %d is empty", i);    
-      return NULL;
-    }
-  }
-  
-  char *COL_FANCY_1, *COL_FANCY_2, *COL_FANCY_3, *COL_FANCY_4, *COL_RETRO_1, *COL_RETRO_2, *COL_RETRO_3, *COL_RETRO_4;
-  struct ascii* art = malloc(sizeof(struct ascii));
-  art->n_attributes_set = 0;
-  art->vendor = cpuVendor;
-  for(int i=0; i < MAX_ATTRIBUTE_COUNT; i++)
-    art->attributes[i] = NULL;
-  strcpy(art->reset,RESET);
-  
-  if(cpuVendor == VENDOR_INTEL) {
-    COL_FANCY_1 = COL_INTEL_FANCY_1;
-    COL_FANCY_2 = COL_INTEL_FANCY_2;
-    COL_FANCY_3 = COL_INTEL_FANCY_3;
-    COL_FANCY_4 = COL_INTEL_FANCY_4;
-    COL_RETRO_1 = COL_INTEL_RETRO_1;
-    COL_RETRO_2 = COL_INTEL_RETRO_2;  
-    COL_RETRO_3 = COL_INTEL_RETRO_1;  
-    COL_RETRO_4 = COL_INTEL_RETRO_2;  
-    art->ascii_chars[0] = '#';
-  }
-  else {
-    COL_FANCY_1 = COL_AMD_FANCY_1;
-    COL_FANCY_2 = COL_AMD_FANCY_2;
-    COL_FANCY_3 = COL_AMD_FANCY_3;
-    COL_FANCY_4 = COL_AMD_FANCY_4;
-    COL_RETRO_1 = COL_AMD_RETRO_1;
-    COL_RETRO_2 = COL_AMD_RETRO_2;       
-    COL_RETRO_3 = COL_AMD_RETRO_1;
-    COL_RETRO_4 = COL_AMD_RETRO_2;   
-    art->ascii_chars[0] = '@';    
-  }
-  art->ascii_chars[1] = '#';
-  
-  // If style is emtpy, set the default style
-  if(style == STYLE_EMPTY) {
-    #ifdef _WIN32
-      style = STYLE_LEGACY;
-    #else
-      style = STYLE_FANCY;
-    #endif
-  }
-  
-  switch(style) {
-    case STYLE_LEGACY:
-      strcpy(art->color1_ascii,COL_NONE);
-      strcpy(art->color2_ascii,COL_NONE);  
-      strcpy(art->color1_text,COL_NONE);  
-      strcpy(art->color2_text,COL_NONE);  
-      art->reset[0] = '\0';
-      break;
-    case STYLE_FANCY:
-      if(cs != NULL) {
-        COL_FANCY_1 = rgb_to_ansi(cs->c1, true, true);
-        COL_FANCY_2 = rgb_to_ansi(cs->c2, true, true);
-        COL_FANCY_3 = rgb_to_ansi(cs->c3, false, true);
-        COL_FANCY_4 = rgb_to_ansi(cs->c4, false, true);        
-      } 
-      art->ascii_chars[0] = ' ';
-      art->ascii_chars[1] = ' ';
-      strcpy(art->color1_ascii,COL_FANCY_1);
-      strcpy(art->color2_ascii,COL_FANCY_2);  
-      strcpy(art->color1_text,COL_FANCY_3);  
-      strcpy(art->color2_text,COL_FANCY_4);  
-      if(cs != NULL) {
-        free(COL_FANCY_1);
-        free(COL_FANCY_2);
-        free(COL_FANCY_3);
-        free(COL_FANCY_4);
-      }
-      break;
-    case STYLE_RETRO:  
-      if(cs != NULL) {
-        COL_RETRO_1 = rgb_to_ansi(cs->c1, false, true);
-        COL_RETRO_2 = rgb_to_ansi(cs->c2, false, true);   
-        COL_RETRO_3 = rgb_to_ansi(cs->c3, false, true);
-        COL_RETRO_4 = rgb_to_ansi(cs->c4, false, true);  
-      }   
-      strcpy(art->color1_ascii,COL_RETRO_1);
-      strcpy(art->color2_ascii,COL_RETRO_2);  
-      strcpy(art->color1_text,COL_RETRO_3);  
-      strcpy(art->color2_text,COL_RETRO_4); 
-      if(cs != NULL) {
-        free(COL_RETRO_1);
-        free(COL_RETRO_2);
-        free(COL_RETRO_3);
-        free(COL_RETRO_4);
-      }
-      break;
-    case STYLE_INVALID:  
-    default:
-      printBug("Found invalid style (%d)",style);
-      return NULL;    
-  }
-  
-  char tmp[NUMBER_OF_LINES*LINE_SIZE];
-  if(cpuVendor == VENDOR_INTEL) strcpy(tmp, INTEL_ASCII);    
-  else strcpy(tmp, AMD_ASCII);    
-    for(int i=0; i < NUMBER_OF_LINES; i++)
-      strncpy(art->art[i], tmp + i*LINE_SIZE, LINE_SIZE); 
-    
-  return art;
-}
-
-uint32_t get_next_attribute(struct ascii* art, uint32_t last_attr) {
-  last_attr++;
-  while(art->attributes[last_attr] == NULL) last_attr++;
-  return last_attr;
-}
-
-void print_ascii_intel(struct ascii* art, uint32_t la) {
-  bool flag = false;
-  int attr_to_print = -1;
-  uint32_t space_right;
-  uint32_t space_up = (NUMBER_OF_LINES - art->n_attributes_set)/2;
-  uint32_t space_down = NUMBER_OF_LINES - art->n_attributes_set - space_up;
-
-  printf("\n");
-  for(uint32_t n=0;n<NUMBER_OF_LINES;n++) {
-
-    for(int i=0;i<LINE_SIZE;i++) {
-      if(flag) {
-        if(art->art[n][i] == ' ') {
-          flag = false;
-          printf("%s%c%s", art->color2_ascii, art->ascii_chars[1], art->reset);          
-        }
-        else
-          printf("%s%c%s",  art->color1_ascii, art->ascii_chars[0], art->reset);
-      }
-      else {
-        if(art->art[n][i] != ' ' && art->art[n][i] != '\0') {
-          flag = true;
-          printf("%c",' ');
-        }
-        else
-          printf("%c",' ');
-      }
-    }
-    
-    if(n > space_up-1 && n < NUMBER_OF_LINES-space_down) {      
-      attr_to_print = get_next_attribute(art, attr_to_print);
-      space_right = 1 + (la - strlen(ATTRIBUTE_FIELDS[attr_to_print]));      
-      printf("%s%s%s%*s%s%s%s\n",art->color1_text, ATTRIBUTE_FIELDS[attr_to_print], art->reset, space_right, "", art->color2_text, art->attributes[attr_to_print], art->reset);
-    }
-    else printf("\n");
-  }
-  printf("\n");
-}
-
-void print_ascii_amd(struct ascii* art, uint32_t la) {
-  int attr_to_print = -1;
-  uint32_t space_right;
-  uint32_t space_up = (NUMBER_OF_LINES - art->n_attributes_set)/2;
-  uint32_t space_down = NUMBER_OF_LINES - art->n_attributes_set - space_up;
-  
-  printf("\n");
-  for(uint32_t n=0;n<NUMBER_OF_LINES;n++) {
-    for(int i=0;i<LINE_SIZE;i++) {
-      if(art->art[n][i] == '@')
-        printf("%s%c%s", art->color1_ascii, art->ascii_chars[0], art->reset);
-      else if(art->art[n][i] == '#')
-        printf("%s%c%s", art->color2_ascii, art->ascii_chars[1], art->reset);
-      else
-        printf("%c",art->art[n][i]);
-    }
-
-    if(n > space_up-1 && n < NUMBER_OF_LINES-space_down) {
-      attr_to_print = get_next_attribute(art, attr_to_print);
-      space_right = 1 + (la - strlen(ATTRIBUTE_FIELDS[attr_to_print]));      
-      printf("%s%s%s%*s%s%s%s\n",art->color1_text, ATTRIBUTE_FIELDS[attr_to_print], art->reset, space_right, "", art->color2_text, art->attributes[attr_to_print], art->reset);
-    }
-    else printf("\n");
-  }
-  printf("\n");
-
-}
-
-uint32_t longest_attribute_length(struct ascii* art) {
-  uint32_t max = 0;
-  uint64_t len = 0;
-  
-  for(int i=0; i < MAX_ATTRIBUTE_COUNT; i++) {
-    if(art->attributes[i] != NULL) {
-      len = strlen(ATTRIBUTE_FIELDS[i]);
-      if(len > max) max = len;
-    }
-  }
-  
-  return max;
-}
-
-void print_ascii(struct ascii* art) {
-  uint32_t longest_attribute = longest_attribute_length(art);
-  if(art->vendor == VENDOR_INTEL)
-    print_ascii_intel(art, longest_attribute);
-  else
-    print_ascii_amd(art, longest_attribute);
-}
-
-bool print_cpufetch(struct cpuInfo* cpu, struct cache* cach, struct frequency* freq, struct topology* topo, STYLE s, struct colors* cs) {
-  struct ascii* art = set_ascii(get_cpu_vendor(cpu), s, cs);
-  if(art == NULL)
-    return false;
-  
-  char* cpu_name = get_str_cpu_name(cpu);
-  char* uarch = get_str_uarch(cpu);
-  char* manufacturing_process = get_str_process(cpu);
-  char* sockets = get_str_sockets(topo);
-  char* max_frequency = get_str_freq(freq);
-  char* n_cores = get_str_topology(cpu, topo, false);
-  char* n_cores_dual = get_str_topology(cpu, topo, true);
-  char* avx = get_str_avx(cpu);
-  char* fma = get_str_fma(cpu);  
-  char* l1i = get_str_l1i(topo->cach);
-  char* l1d = get_str_l1d(topo->cach);
-  char* l2 = get_str_l2(topo->cach);
-  char* l3 = get_str_l3(topo->cach);
-  char* pp = get_str_peak_performance(cpu,topo,get_freq(freq));
-
-  setAttribute(art,ATTRIBUTE_NAME,cpu_name);
-  setAttribute(art,ATTRIBUTE_UARCH,uarch);
-  setAttribute(art,ATTRIBUTE_TECHNOLOGY,manufacturing_process);
-  setAttribute(art,ATTRIBUTE_FREQUENCY,max_frequency);
-  setAttribute(art,ATTRIBUTE_NCORES,n_cores);
-  setAttribute(art,ATTRIBUTE_AVX,avx);
-  setAttribute(art,ATTRIBUTE_FMA,fma);
-  setAttribute(art,ATTRIBUTE_L1i,l1i);
-  setAttribute(art,ATTRIBUTE_L1d,l1d);
-  setAttribute(art,ATTRIBUTE_L2,l2);  
-  setAttribute(art,ATTRIBUTE_PEAK,pp);
-  
-  uint32_t socket_num = get_nsockets(topo);
-  if (socket_num > 1) {    
-    setAttribute(art, ATTRIBUTE_SOCKETS, sockets);
-    setAttribute(art, ATTRIBUTE_NCORES_DUAL, n_cores_dual);
-  }
-  if(l3 != NULL) {
-    setAttribute(art,ATTRIBUTE_L3,l3);    
-  }
-  if(art->n_attributes_set > NUMBER_OF_LINES) {
-    printBug("The number of attributes set is bigger than the max that can be displayed");
-    return false;    
-  }
-
-  print_ascii(art);
-
-  free(manufacturing_process);
-  free(max_frequency);
-  free(sockets);
-  free(n_cores);
-  free(n_cores_dual);
-  free(avx);
-  free(fma);
-  free(l1i);
-  free(l1d);
-  free(l2);
-  free(l3);
-  free(pp);  
-  
-  free(art);
-  
-  if(cs != NULL) free_colors_struct(cs);
-  free_cache_struct(cach);
-  free_topo_struct(topo);
-  free_freq_struct(freq);   
-  free_cpuinfo_struct(cpu);    
-  
-  return true;
-}

src/printer.h

@@ -1,22 +0,0 @@
-#ifndef __PRINTER__
-#define __PRINTER__
-
-typedef int STYLE;
-
-#include "args.h"
-#include "cpuid.h"
-
-#define STYLES_COUNT 3
-
-#define STYLE_INVALID -2
-#define STYLE_EMPTY   -1
-#define STYLE_FANCY    0
-#define STYLE_RETRO    1
-#define STYLE_LEGACY   2
-
-#define COLOR_DEFAULT_INTEL "15,125,194:230,230,230:40,150,220:230,230,230"
-#define COLOR_DEFAULT_AMD   "250,250,250:0,154,102:250,250,250:0,154,102"
-
-bool print_cpufetch(struct cpuInfo* cpu, struct cache* cach, struct frequency* freq, struct topology* topo, STYLE s, struct colors* cs);
-
-#endif

src/udev.c

@@ -1,74 +0,0 @@
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <unistd.h>
-#include <fcntl.h>
-#include <errno.h>
-
-#include "global.h"
-#include "cpuid.h"
-
-#define _PATH_SYS_SYSTEM    "/sys/devices/system"
-#define _PATH_SYS_CPU       _PATH_SYS_SYSTEM"/cpu"
-#define _PATH_ONE_CPU       _PATH_SYS_CPU"/cpu0"
-
-#define _PATH_FREQUENCY     _PATH_ONE_CPU"/cpufreq"
-#define _PATH_FREQUENCY_MAX _PATH_FREQUENCY"/cpuinfo_max_freq"
-#define _PATH_FREQUENCY_MIN _PATH_FREQUENCY"/cpuinfo_min_freq"
-
-#define DEFAULT_FILE_SIZE 4096
-
-long get_freq_from_file(char* path) {
-  int fd = open(path, O_RDONLY);
-
-  if(fd == -1) {
-    perror("open");
-    printBug("Could not open '%s'", path);
-    return UNKNOWN_FREQ;
-  }
-
-  //File exists, read it
-  int bytes_read = 0;
-  int offset = 0;
-  int block = 1;
-  char* buf = malloc(sizeof(char)*DEFAULT_FILE_SIZE);
-  memset(buf, 0, sizeof(char)*DEFAULT_FILE_SIZE);
-
-  while (  (bytes_read = read(fd, buf+offset, block)) > 0 ) {
-    offset += bytes_read;
-  }
-
-  char* end;
-  errno = 0;
-  long ret = strtol(buf, &end, 10);
-  if(errno != 0) {
-    perror("strtol");
-    printBug("Failed parsing '%s' file. Read data was: '%s'", path, buf);
-    free(buf);
-    return UNKNOWN_FREQ;
-  }
-  
-  // We will be getting the frequency in KHz
-  // We consider it is an error if frequency is
-  // greater than 10 GHz or less than 100 MHz
-  if(ret > 10000 * 1000 || ret <  100 * 1000) {
-    printBug("Invalid data was read from file '%s': %ld\n", path, ret);
-    return UNKNOWN_FREQ;
-  }
-  
-  free(buf);
-  if (close(fd) == -1) {
-    perror("close");
-    printErr("Closing '%s' failed\n", path);    
-  }
-  
-  return ret/1000;
-}
-
-long get_max_freq_from_file() {
-  return get_freq_from_file(_PATH_FREQUENCY_MAX);
-}
-
-long get_min_freq_from_file() {
-  return get_freq_from_file(_PATH_FREQUENCY_MIN);
-}

src/udev.h

@@ -1,7 +0,0 @@
-#ifndef __UDEV__
-#define __UDEV__
-
-long get_max_freq_from_file();
-long get_min_freq_from_file();
-
-#endif

src/x86/apic.c

@@ -1,18 +1,26 @@
 #ifdef _WIN32
-#include <windows.h>
-#else
-#define _GNU_SOURCE
-#include <sched.h>
+  #define NOMINMAX
+  #include <windows.h>
+#elif defined __linux__
+  #define _GNU_SOURCE
+  #include <sched.h>
+#elif defined __FreeBSD__
+  #include <sys/param.h>
+  #include <sys/cpuset.h>
+#elif defined __APPLE__
+  #define UNUSED(x) (void)(x)
 #endif
 
 #include <stdlib.h>
 #include <stdint.h>
 #include <string.h>
 #include <stdio.h>
+#include <unistd.h>
+#include <errno.h>
 
 #include "apic.h"
 #include "cpuid_asm.h"
-#include "global.h"
+#include "../common/global.h"
 
 /*
  * bit_scan_reverse and create_mask code taken from:
@@ -20,7 +28,7 @@
  */
 unsigned char bit_scan_reverse(uint32_t* index, uint64_t mask) {
   for(uint64_t i = (8 * sizeof(uint64_t)); i > 0; i--) {
-    if((mask & (1LL << (i-1))) != 0) {
+    if((mask & (1ULL << (i-1))) != 0) {
       *index = (uint64_t) (i-1);
       break;
     }
@@ -66,22 +74,33 @@ uint32_t get_apic_id(bool x2apic_id) {
   }
 }
 
+#ifndef __APPLE__
 bool bind_to_cpu(int cpu_id) {
   #ifdef _WIN32
     HANDLE process = GetCurrentProcess();
     DWORD_PTR processAffinityMask = 1 << cpu_id;
     return SetProcessAffinityMask(process, processAffinityMask);
-  #else    
+  #elif defined __linux__
     cpu_set_t currentCPU;
     CPU_ZERO(&currentCPU);
     CPU_SET(cpu_id, &currentCPU);
     if (sched_setaffinity (0, sizeof(currentCPU), &currentCPU) == -1) {
-      perror("sched_setaffinity");
+      printWarn("sched_setaffinity: %s", strerror(errno));
+      return false;
+    }
+    return true;
+  #elif defined __FreeBSD__
+    cpuset_t currentCPU;
+    CPU_ZERO(&currentCPU);
+    CPU_SET(cpu_id, &currentCPU);
+    if(cpuset_setaffinity(CPU_LEVEL_WHICH, CPU_WHICH_TID, -1, sizeof(cpuset_t), &currentCPU) == -1) {
+      printWarn("cpuset_setaffinity: %s", strerror(errno));
       return false;
     }
     return true;
   #endif
 }
+#endif
 
 bool fill_topo_masks_apic(struct topology* topo) {
   uint32_t eax = 0x00000001;
@@ -184,15 +203,15 @@ uint32_t max_apic_id_size(uint32_t** cache_id_apic, struct topology* topo) {
   }
 
   max++;
-  if(max > topo->total_cores) return max;
+  if(max > (uint32_t) topo->total_cores) return max;
   return topo->total_cores;
 }
 
 bool build_topo_from_apic(uint32_t* apic_pkg, uint32_t* apic_smt, uint32_t** cache_id_apic, struct topology* topo) {
   uint32_t size = max_apic_id_size(cache_id_apic, topo);
-  uint32_t* sockets = malloc(sizeof(uint32_t) * size);
-  uint32_t* smt = malloc(sizeof(uint32_t) * size);
-  uint32_t* apic_id = malloc(sizeof(uint32_t) * size);
+  uint32_t* sockets = emalloc(sizeof(uint32_t) * size);
+  uint32_t* smt = emalloc(sizeof(uint32_t) * size);
+  uint32_t* apic_id = emalloc(sizeof(uint32_t) * size);
   uint32_t num_caches = 0;
 
   memset(sockets, 0, sizeof(uint32_t) * size);
@@ -254,21 +273,88 @@ void get_cache_topology_from_apic(struct topology* topo) {
   }
 }
 
+bool apic_array_full(uint32_t* apic_ids, int n) {
+  for(int i=0; i < n; i++) {
+    if(apic_ids[i] == (uint32_t) -1) return false;
+  }
+  return true;
+}
+
+void add_apic_to_array(uint32_t apic, uint32_t* apic_ids, int n) {
+  int i=0;
+  int last=0;
+  bool found = false;
+
+  while(!found && i < n) {
+    if(apic_ids[i] == apic) found = true;
+    if(apic_ids[i] != (uint32_t) -1) last = i+1;
+    i++;
+  }
+
+  if(!found) {
+    apic_ids[last] = apic;
+    //printf("Added %d\n", apic);
+  }
+}
+
+bool fill_apic_ids(uint32_t* apic_ids, int n, bool x2apic_id) {
+#ifdef __APPLE__
+  // macOS extremely dirty approach...
+  printf("cpufetch is computing APIC IDs, please wait...\n");
+  bool end = false;
+  uint32_t apic;
+  for(int i=0; i < n; i++) apic_ids[i] = (uint32_t) -1;
+
+  while(!end) {
+    apic = get_apic_id(x2apic_id);
+
+    add_apic_to_array(apic, apic_ids, n);
+    end = apic_array_full(apic_ids, n);
+    usleep(1000);
+  }
+#else
+  for(int i=0; i < n; i++) {
+    if(!bind_to_cpu(i)) {
+      printErr("Failed binding to CPU %d", i);
+      return false;
+    }
+    apic_ids[i] = get_apic_id(x2apic_id);
+  }
+#endif
+  return true;
+}
+
 bool get_topology_from_apic(struct cpuInfo* cpu, struct topology* topo) {
   uint32_t apic_id;
-  uint32_t* apic_pkg = malloc(sizeof(uint32_t) * topo->total_cores);
-  uint32_t* apic_core = malloc(sizeof(uint32_t) * topo->total_cores);
-  uint32_t* apic_smt = malloc(sizeof(uint32_t) * topo->total_cores);
-  uint32_t** cache_smt_id_apic = malloc(sizeof(uint32_t*) * topo->total_cores);
-  uint32_t** cache_id_apic = malloc(sizeof(uint32_t*) * topo->total_cores);
-  bool x2apic_id = cpu->maxLevels >= 0x0000000B;
+  uint32_t* apic_ids = emalloc(sizeof(uint32_t) * topo->total_cores);
+  uint32_t* apic_pkg = emalloc(sizeof(uint32_t) * topo->total_cores);
+  uint32_t* apic_core = emalloc(sizeof(uint32_t) * topo->total_cores);
+  uint32_t* apic_smt = emalloc(sizeof(uint32_t) * topo->total_cores);
+  uint32_t** cache_smt_id_apic = emalloc(sizeof(uint32_t*) * topo->total_cores);
+  uint32_t** cache_id_apic = emalloc(sizeof(uint32_t*) * topo->total_cores);
+  bool x2apic_id;
+
+  if(cpu->maxLevels >= 0x0000000B) {
+    uint32_t eax = 0x0000000B;
+    uint32_t ebx = 0;
+    uint32_t ecx = 0;
+    uint32_t edx = 0;
+
+    cpuid(&eax, &ebx, &ecx, &edx);
+
+    if(ebx == 0) x2apic_id = false;
+    else x2apic_id = true;
+  }
+  else {
+    x2apic_id = false;
+  }
 
   for(int i=0; i < topo->total_cores; i++) {
-    cache_smt_id_apic[i] = malloc(sizeof(uint32_t) * (topo->cach->max_cache_level));
-    cache_id_apic[i] = malloc(sizeof(uint32_t) * (topo->cach->max_cache_level));
+    cache_smt_id_apic[i] = emalloc(sizeof(uint32_t) * (topo->cach->max_cache_level));
+    cache_id_apic[i] = emalloc(sizeof(uint32_t) * (topo->cach->max_cache_level));
   }
-  topo->apic->cache_select_mask = malloc(sizeof(uint32_t) * (topo->cach->max_cache_level));
-  topo->apic->cache_id_apic = malloc(sizeof(uint32_t) * (topo->cach->max_cache_level));
+  topo->apic->cache_select_mask = emalloc(sizeof(uint32_t) * (topo->cach->max_cache_level));
+  topo->apic->cache_id_apic = emalloc(sizeof(uint32_t) * (topo->cach->max_cache_level));
 
   if(x2apic_id) {
     if(!fill_topo_masks_x2apic(topo))
@@ -281,12 +367,11 @@ bool get_topology_from_apic(struct cpuInfo* cpu, struct topology* topo) {
 
   get_cache_topology_from_apic(topo);
 
+  if(!fill_apic_ids(apic_ids, topo->total_cores, x2apic_id))
+    return false;
+
   for(int i=0; i < topo->total_cores; i++) {
-    if(!bind_to_cpu(i)) {
-      printErr("Failed binding to CPU %d", i);
-      return false;
-    }
-    apic_id = get_apic_id(x2apic_id);
+    apic_id = apic_ids[i];
 
     apic_pkg[i] = (apic_id & topo->apic->pkg_mask) >> topo->apic->pkg_mask_shift;
     apic_core[i] = (apic_id & topo->apic->core_mask) >> topo->apic->smt_mask_width;
@@ -337,6 +422,10 @@ bool get_topology_from_apic(struct cpuInfo* cpu, struct topology* topo) {
 }
 
 uint32_t is_smt_enabled_amd(struct topology* topo) {
+#ifdef __APPLE__
+  UNUSED(topo);
+  return 1;
+#else
   uint32_t id;
 
   for(int i = 0; i < topo->total_cores; i++) {
@@ -349,4 +438,5 @@ uint32_t is_smt_enabled_amd(struct topology* topo) {
   }
 
   return 1;
+#endif
 }

src/x86/apic.h

@@ -17,4 +17,8 @@ struct apic {
 bool get_topology_from_apic(struct cpuInfo* cpu, struct topology* topo);
 uint32_t is_smt_enabled_amd(struct topology* topo);
 
+#ifndef __APPLE__
+bool bind_to_cpu(int cpu_id);
+#endif
+
 #endif

src/x86/cpuid.c

@@ -0,0 +1,914 @@
+#ifdef _WIN32
+  #define NOMINMAX
+  #include <windows.h>
+#else
+  #include "../common/udev.h"
+  #include <unistd.h>
+#endif
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <assert.h>
+#include <stdbool.h>
+
+#include "cpuid.h"
+#include "cpuid_asm.h"
+#include "../common/global.h"
+#include "apic.h"
+#include "uarch.h"
+
+#define CPU_VENDOR_INTEL_STRING "GenuineIntel"
+#define CPU_VENDOR_AMD_STRING   "AuthenticAMD"
+
+static const char *hv_vendors_string[] = {
+  [HV_VENDOR_KVM]       = "KVMKVMKVM",
+  [HV_VENDOR_QEMU]      = "TCGTCGTCGTCG",
+  [HV_VENDOR_HYPERV]    = "Microsoft Hv",
+  [HV_VENDOR_VMWARE]    = "VMwareVMware",
+  [HV_VENDOR_XEN]       = "XenVMMXenVMM",
+  [HV_VENDOR_PARALLELS] = "lrpepyh vr",
+};
+
+static char *hv_vendors_name[] = {
+  [HV_VENDOR_KVM]       = "KVM",
+  [HV_VENDOR_QEMU]      = "QEMU",
+  [HV_VENDOR_HYPERV]    = "Microsoft Hyper-V",
+  [HV_VENDOR_VMWARE]    = "VMware",
+  [HV_VENDOR_XEN]       = "Xen",
+  [HV_VENDOR_PARALLELS] = "Parallels",
+  [HV_VENDOR_INVALID]   = STRING_UNKNOWN
+};
+
+#define HYPERVISOR_NAME_MAX_LENGTH 17
+
+#define MASK 0xFF
+
+/*
+ * cpuid reference: http://www.sandpile.org/x86/cpuid.htm
+ * cpuid amd: https://www.amd.com/system/files/TechDocs/25481.pdf
+ */
+
+void get_name_cpuid(char* name, uint32_t reg1, uint32_t reg2, uint32_t reg3) {
+  uint32_t c = 0;
+
+  name[c++] = reg1       & MASK;
+  name[c++] = (reg1>>8)  & MASK;
+  name[c++] = (reg1>>16) & MASK;
+  name[c++] = (reg1>>24) & MASK;
+
+  name[c++] = reg2       & MASK;
+  name[c++] = (reg2>>8)  & MASK;
+  name[c++] = (reg2>>16) & MASK;
+  name[c++] = (reg2>>24) & MASK;
+
+  name[c++] = reg3       & MASK;
+  name[c++] = (reg3>>8)  & MASK;
+  name[c++] = (reg3>>16) & MASK;
+  name[c++] = (reg3>>24) & MASK;
+}
+
+char* get_str_cpu_name_internal() {
+  uint32_t eax = 0;
+  uint32_t ebx = 0;
+  uint32_t ecx = 0;
+  uint32_t edx = 0;
+  uint32_t c = 0;
+
+  char * name = emalloc(sizeof(char) * CPU_NAME_MAX_LENGTH);
+  memset(name, 0, CPU_NAME_MAX_LENGTH);
+
+  for(int i=0; i < 3; i++) {
+    eax = 0x80000002 + i;
+    cpuid(&eax, &ebx, &ecx, &edx);
+
+    name[c++] = eax       & MASK;
+    name[c++] = (eax>>8)  & MASK;
+    name[c++] = (eax>>16) & MASK;
+    name[c++] = (eax>>24) & MASK;
+    name[c++] = ebx       & MASK;
+    name[c++] = (ebx>>8)  & MASK;
+    name[c++] = (ebx>>16) & MASK;
+    name[c++] = (ebx>>24) & MASK;
+    name[c++] = ecx       & MASK;
+    name[c++] = (ecx>>8)  & MASK;
+    name[c++] = (ecx>>16) & MASK;
+    name[c++] = (ecx>>24) & MASK;
+    name[c++] = edx       & MASK;
+    name[c++] = (edx>>8)  & MASK;
+    name[c++] = (edx>>16) & MASK;
+    name[c++] = (edx>>24) & MASK;
+  }
+  name[c] = '\0';
+
+  //Remove unused characters
+  char *str = name;
+  char *dest = name;
+  // Remove spaces before name
+  while (*str != '\0' && *str == ' ')str++;
+  // Remove spaces between the name and after it
+  while (*str != '\0') {
+    while (*str == ' ' && *(str + 1) == ' ') str++;
+    *dest++ = *str++;
+  }
+  *dest = '\0';
+
+  return name;
+}
+
+struct uarch* get_cpu_uarch(struct cpuInfo* cpu) {
+  uint32_t eax = 0x00000001;
+  uint32_t ebx = 0;
+  uint32_t ecx = 0;
+  uint32_t edx = 0;
+
+  cpuid(&eax, &ebx, &ecx, &edx);
+
+  uint32_t stepping = eax & 0xF;
+  uint32_t model = (eax >> 4) & 0xF;
+  uint32_t emodel = (eax >> 16) & 0xF;
+  uint32_t family = (eax >> 8) & 0xF;
+  uint32_t efamily = (eax >> 20) & 0xFF;
+
+  return get_uarch_from_cpuid(cpu, efamily, family, emodel, model, (int)stepping);
+}
+
+int64_t get_peak_performance(struct cpuInfo* cpu, struct topology* topo, int64_t freq) {
+  /*
+   * PP = PeakPerformance
+   * SP = SinglePrecision
+   *
+   * PP(SP) =
+   * N_CORES                             *
+   * FREQUENCY                           *
+   * 2(Two vector units)                 *
+   * 2(If cpu has fma)                   *
+   * 16(If AVX512), 8(If AVX), 4(If SSE) *
+   */
+
+  //First, check we have consistent data
+  if(freq == UNKNOWN_FREQ) {
+    return -1;
+  }
+
+  struct features* feat = cpu->feat;
+  int vpus = get_number_of_vpus(cpu);
+  int64_t flops = topo->physical_cores * topo->sockets * (freq*1000000) * vpus;
+
+  if(feat->FMA3 || feat->FMA4)
+    flops = flops*2;
+
+  // Ice Lake has AVX512, but it has 1 VPU for AVX512, while
+  // it has 2 for AVX2. If this is a Ice Lake CPU, we are computing
+  // the peak performance supposing AVX2, not AVX512
+  if(feat->AVX512 && vpus_are_AVX512(cpu))
+    flops = flops*16;
+  else if(feat->AVX || feat->AVX2)
+    flops = flops*8;
+  else if(feat->SSE)
+    flops = flops*4;
+
+  // See https://sites.utexas.edu/jdm4372/2018/01/22/a-peculiar-
+  // throughput-limitation-on-intels-xeon-phi-x200-knights-landing/
+  if(is_knights_landing(cpu))
+    flops = flops * 6 / 7;
+
+  return flops;
+}
+
+struct hypervisor* get_hp_info(bool hv_present) {
+  struct hypervisor* hv = emalloc(sizeof(struct hypervisor));
+  if(!hv_present) {
+    hv->present = false;
+    return hv;
+  }
+
+  hv->present = true;
+
+  uint32_t eax = 0x40000000;
+  uint32_t ebx = 0;
+  uint32_t ecx = 0;
+  uint32_t edx = 0;
+
+  cpuid(&eax, &ebx, &ecx, &edx);
+
+  char name[13];
+  memset(name, 0, 13);
+  get_name_cpuid(name, ebx, ecx, edx);
+
+  bool found = false;
+  uint8_t len = sizeof(hv_vendors_string) / sizeof(hv_vendors_string[0]);
+
+  for(uint8_t v=0; v < len && !found; v++) {
+    if(strcmp(hv_vendors_string[v], name) == 0) {
+      hv->hv_vendor = v;
+      found = true;
+    }
+  }
+
+  if(!found) {
+    hv->hv_vendor = HV_VENDOR_INVALID;
+    printWarn("Unknown hypervisor vendor: %s", name);
+  }
+
+  hv->hv_name = hv_vendors_name[hv->hv_vendor];
+
+  return hv;
+}
+
+struct cpuInfo* get_cpu_info() {
+  struct cpuInfo* cpu = emalloc(sizeof(struct cpuInfo));
+  struct features* feat = emalloc(sizeof(struct features));
+  cpu->feat = feat;
+
+  bool *ptr = &(feat->AES);
+  for(uint32_t i = 0; i < sizeof(struct features)/sizeof(bool); i++, ptr++) {
+    *ptr = false;
+  }
+
+  uint32_t eax = 0;
+  uint32_t ebx = 0;
+  uint32_t ecx = 0;
+  uint32_t edx = 0;
+
+  //Get max cpuid level
+  cpuid(&eax, &ebx, &ecx, &edx);
+  cpu->maxLevels = eax;
+
+  //Fill vendor
+  char name[13];
+  memset(name,0,13);
+  get_name_cpuid(name, ebx, edx, ecx);
+
+  if(strcmp(CPU_VENDOR_INTEL_STRING,name) == 0)
+    cpu->cpu_vendor = CPU_VENDOR_INTEL;
+  else if (strcmp(CPU_VENDOR_AMD_STRING,name) == 0)
+    cpu->cpu_vendor = CPU_VENDOR_AMD;
+  else {
+    cpu->cpu_vendor = CPU_VENDOR_INVALID;
+    printErr("Unknown CPU vendor: %s", name);
+    return NULL;
+  }
+
+  //Get max extended level
+  eax = 0x80000000;
+  ebx = 0;
+  ecx = 0;
+  edx = 0;
+  cpuid(&eax, &ebx, &ecx, &edx);
+  cpu->maxExtendedLevels = eax;
+
+  //Fill instructions support
+  if (cpu->maxLevels >= 0x00000001){
+    eax = 0x00000001;
+    cpuid(&eax, &ebx, &ecx, &edx);
+    feat->SSE    = (edx & (1U << 25)) != 0;
+    feat->SSE2   = (edx & (1U << 26)) != 0;
+    feat->SSE3   = (ecx & (1U <<  0)) != 0;
+
+    feat->SSSE3  = (ecx & (1U <<  9)) != 0;
+    feat->SSE4_1 = (ecx & (1U << 19)) != 0;
+    feat->SSE4_2 = (ecx & (1U << 20)) != 0;
+
+    feat->AES    = (ecx & (1U << 25)) != 0;
+
+    feat->AVX    = (ecx & (1U << 28)) != 0;
+    feat->FMA3   = (ecx & (1U << 12)) != 0;
+
+    bool hv_present = (ecx & (1U << 31)) != 0;
+    if((cpu->hv = get_hp_info(hv_present)) == NULL)
+      return NULL;
+  }
+  else {
+    printWarn("Can't read features information from cpuid (needed level is 0x%.8X, max is 0x%.8X)", 0x00000001, cpu->maxLevels);
+  }
+
+  if (cpu->maxLevels >= 0x00000007){
+    eax = 0x00000007;
+    ecx = 0x00000000;
+    cpuid(&eax, &ebx, &ecx, &edx);
+    feat->AVX2         = (ebx & (1U <<  5)) != 0;
+    feat->SHA          = (ebx & (1U << 29)) != 0;
+    feat->AVX512       = (((ebx & (1U << 16)) != 0) ||
+                        ((ebx & (1U << 28)) != 0)  ||
+                        ((ebx & (1U << 26)) != 0)  ||
+                        ((ebx & (1U << 27)) != 0)  ||
+                        ((ebx & (1U << 31)) != 0)  ||
+                        ((ebx & (1U << 30)) != 0)  ||
+                        ((ebx & (1U << 17)) != 0)  ||
+                        ((ebx & (1U << 21)) != 0));
+  }
+  else {
+    printWarn("Can't read features information from cpuid (needed level is 0x%.8X, max is 0x%.8X)", 0x00000007, cpu->maxLevels);
+  }
+
+  if (cpu->maxExtendedLevels >= 0x80000001){
+    eax = 0x80000001;
+    cpuid(&eax, &ebx, &ecx, &edx);
+    feat->SSE4a = (ecx & (1U <<  6)) != 0;
+    feat->FMA4  = (ecx & (1U << 16)) != 0;
+  }
+  else {
+    printWarn("Can't read features information from cpuid (needed extended level is 0x%.8X, max is 0x%.8X)", 0x80000001, cpu->maxExtendedLevels);
+  }
+
+  if (cpu->maxExtendedLevels >= 0x80000004){
+    cpu->cpu_name = get_str_cpu_name_internal();
+  }
+  else {
+    cpu->cpu_name = emalloc(sizeof(char) * (strlen(STRING_UNKNOWN) + 1));
+    strcpy(cpu->cpu_name, STRING_UNKNOWN);
+    printWarn("Can't read cpu name from cpuid (needed extended level is 0x%.8X, max is 0x%.8X)", 0x80000004, cpu->maxExtendedLevels);
+  }
+
+  cpu->topology_extensions = false;
+  if(cpu->cpu_vendor == CPU_VENDOR_AMD && cpu->maxExtendedLevels >= 0x80000001) {
+    eax = 0x80000001;
+    cpuid(&eax, &ebx, &ecx, &edx);
+    cpu->topology_extensions = (ecx >> 22) & 1;
+  }
+
+  cpu->arch = get_cpu_uarch(cpu);
+  cpu->freq = get_frequency_info(cpu);
+  cpu->cach = get_cache_info(cpu);
+  cpu->topo = get_topology_info(cpu, cpu->cach);
+  cpu->peak_performance = get_peak_performance(cpu, cpu->topo, get_freq(cpu->freq));
+
+  if(cpu->cach == NULL || cpu->topo == NULL) {
+    return NULL;
+  }
+  return cpu;
+}
+
+bool get_cache_topology_amd(struct cpuInfo* cpu, struct topology* topo) {
+  if(cpu->maxExtendedLevels >= 0x8000001D && cpu->topology_extensions) {
+    uint32_t i, eax, ebx, ecx, edx, num_sharing_cache, cache_type, cache_level;
+
+    i = 0;
+    do {
+      eax = 0x8000001D;
+      ebx = 0;
+      ecx = i; // cache id
+      edx = 0;
+
+      cpuid(&eax, &ebx, &ecx, &edx);
+
+      cache_type = eax & 0x1F;
+
+      if(cache_type > 0) {
+        num_sharing_cache = ((eax >> 14) & 0xFFF) + 1;
+        cache_level = (eax >>= 5) & 0x7;
+
+        switch (cache_type) {
+          case 1: // Data Cache (We assume this is L1d)
+            if(cache_level != 1) {
+              printBug("Found data cache at level %d (expected 1)", cache_level);
+              return false;
+            }
+            topo->cach->L1d->num_caches = topo->logical_cores / num_sharing_cache;
+            break;
+
+          case 2: // Instruction Cache (We assume this is L1i)
+            if(cache_level != 1) {
+              printBug("Found instruction cache at level %d (expected 1)", cache_level);
+              return false;
+            }
+            topo->cach->L1i->num_caches = topo->logical_cores / num_sharing_cache;
+            break;
+
+          case 3: // Unified Cache (This may be L2 or L3)
+            if(cache_level == 2) {
+              topo->cach->L2->num_caches = topo->logical_cores / num_sharing_cache;
+            }
+            else if(cache_level == 3) {
+              topo->cach->L3->num_caches = topo->logical_cores / num_sharing_cache;
+            }
+            else {
+              printWarn("Found unknown unified cache at level %d", cache_level);
+            }
+            break;
+
+          default: // Unknown cache type
+            printBug("Unknown cache type %d with level %d found at i=%d", cache_type, cache_level, i);
+            return false;
+        }
+      }
+
+      i++;
+    } while (cache_type > 0);
+  }
+  else {
+    printWarn("Can't read topology information from cpuid (needed extended level is 0x%.8X, max is 0x%.8X and topology_extensions=%s). Guessing cache topology", 0x8000001D, cpu->maxExtendedLevels, cpu->topology_extensions ? "true" : "false");
+    topo->cach->L1i->num_caches = topo->physical_cores;
+    topo->cach->L1d->num_caches = topo->physical_cores;
+
+    if(topo->cach->L3->exists) {
+      topo->cach->L2->num_caches = topo->physical_cores;
+      topo->cach->L3->num_caches = 1;
+    }
+    else {
+      topo->cach->L2->num_caches = 1;
+    }
+  }
+
+  return true;
+}
+
+// Main reference: https://software.intel.com/content/www/us/en/develop/articles/intel-64-architecture-processor-topology-enumeration.html
+// Very interesting resource: https://wiki.osdev.org/Detecting_CPU_Topology_(80x86)
+struct topology* get_topology_info(struct cpuInfo* cpu, struct cache* cach) {
+  struct topology* topo = emalloc(sizeof(struct topology));
+  init_topology_struct(topo, cach);
+
+  uint32_t eax = 0;
+  uint32_t ebx = 0;
+  uint32_t ecx = 0;
+  uint32_t edx = 0;
+
+  // Ask the OS the total number of cores it sees
+  // If we have one socket, it will be same as the cpuid,
+  // but in dual socket it will not!
+  // TODO: Replace by apic?
+  #ifdef _WIN32
+    SYSTEM_INFO info;
+    GetSystemInfo(&info);
+    topo->total_cores = info.dwNumberOfProcessors;
+  #else
+    if((topo->total_cores = sysconf(_SC_NPROCESSORS_ONLN)) == -1) {
+      printWarn("sysconf(_SC_NPROCESSORS_ONLN): %s", strerror(errno));
+      topo->total_cores = topo->logical_cores; // fallback
+    }
+  #endif
+
+  switch(cpu->cpu_vendor) {
+    case CPU_VENDOR_INTEL:
+      if (cpu->maxLevels >= 0x00000004) {
+        get_topology_from_apic(cpu, topo);
+      }
+      else {
+        printWarn("Can't read topology information from cpuid (needed level is 0x%.8X, max is 0x%.8X)", 0x00000001, cpu->maxLevels);
+        topo->physical_cores = 1;
+        topo->logical_cores = 1;
+        topo->smt_available = 1;
+        topo->smt_supported = 1;
+      }
+      break;
+    case CPU_VENDOR_AMD:
+      if (cpu->maxExtendedLevels >= 0x80000008) {
+        eax = 0x80000008;
+        cpuid(&eax, &ebx, &ecx, &edx);
+        topo->logical_cores = (ecx & 0xFF) + 1;
+
+        if (cpu->maxExtendedLevels >= 0x8000001E && cpu->topology_extensions) {
+          eax = 0x8000001E;
+          cpuid(&eax, &ebx, &ecx, &edx);
+          topo->smt_supported = ((ebx >> 8) & 0x03) + 1;
+        }
+        else {
+          printWarn("Can't read topology information from cpuid (needed extended level is 0x%.8X, max is 0x%.8X and topology_extensions=%s)", 0x8000001E, cpu->maxExtendedLevels, cpu->topology_extensions ? "true" : "false");
+          topo->smt_supported = 1;
+        }
+      }
+      else {
+        printWarn("Can't read topology information from cpuid (needed extended level is 0x%.8X, max is 0x%.8X)", 0x80000008, cpu->maxExtendedLevels);
+        topo->physical_cores = 1;
+        topo->logical_cores = 1;
+        topo->smt_supported = 1;
+      }
+
+      if (cpu->maxLevels >= 0x00000001) {
+        if(topo->smt_supported > 1)
+          topo->smt_available = is_smt_enabled_amd(topo);
+        else
+          topo->smt_available = 1;
+      }
+      else {
+        printWarn("Can't read topology information from cpuid (needed level is 0x%.8X, max is 0x%.8X)", 0x0000000B, cpu->maxLevels);
+        topo->smt_available = 1;
+      }
+      topo->physical_cores = topo->logical_cores / topo->smt_available;
+
+      if(topo->smt_supported > 1)
+        topo->sockets = topo->total_cores / topo->smt_supported / topo->physical_cores; // Idea borrowed from lscpu
+      else
+        topo->sockets = topo->total_cores / topo->physical_cores;
+
+      get_cache_topology_amd(cpu, topo);
+
+      break;
+
+    default:
+      printBug("Cant get topology because VENDOR is empty");
+      return NULL;
+  }
+
+  return topo;
+}
+
+struct cache* get_cache_info_amd_fallback(struct cache* cach) {
+  uint32_t eax = 0x80000005;
+  uint32_t ebx = 0;
+  uint32_t ecx = 0;
+  uint32_t edx = 0;
+  cpuid(&eax, &ebx, &ecx, &edx);
+
+  cach->L1d->size = (ecx >> 24) * 1024;
+  cach->L1i->size = (edx >> 24) * 1024;
+
+  eax = 0x80000006;
+  cpuid(&eax, &ebx, &ecx, &edx);
+
+  cach->L2->size = (ecx >> 16) * 1024;
+  cach->L3->size = (edx >> 18) * 512 * 1024;
+
+  cach->L1i->exists = cach->L1i->size > 0;
+  cach->L1d->exists = cach->L1d->size > 0;
+  cach->L2->exists = cach->L2->size > 0;
+  cach->L3->exists = cach->L3->size > 0;
+
+  if(cach->L3->exists)
+   cach->max_cache_level = 4;
+  else
+   cach->max_cache_level = 3;
+
+  return cach;
+}
+
+struct cache* get_cache_info_general(struct cache* cach, uint32_t level) {
+  uint32_t eax = 0;
+  uint32_t ebx = 0;
+  uint32_t ecx = 0;
+  uint32_t edx = 0;
+  int i=0;
+  int32_t cache_type;
+
+  do {
+    eax = level; // get cache info
+    ebx = 0;
+    ecx = i; // cache id
+    edx = 0;
+
+    cpuid(&eax, &ebx, &ecx, &edx);
+
+    cache_type = eax & 0x1F;
+
+    // If its 0, we tried fetching a non existing cache
+    if (cache_type > 0) {
+      int32_t cache_level = (eax >>= 5) & 0x7;
+      uint32_t cache_sets = ecx + 1;
+      uint32_t cache_coherency_line_size = (ebx & 0xFFF) + 1;
+      uint32_t cache_physical_line_partitions = ((ebx >>= 12) & 0x3FF) + 1;
+      uint32_t cache_ways_of_associativity = ((ebx >>= 10) & 0x3FF) + 1;
+
+      int32_t cache_total_size = cache_ways_of_associativity * cache_physical_line_partitions * cache_coherency_line_size * cache_sets;
+      cach->max_cache_level++;
+
+      switch (cache_type) {
+        case 1: // Data Cache (We assume this is L1d)
+          if(cache_level != 1) {
+            printBug("Found data cache at level %d (expected 1)", cache_level);
+            return NULL;
+          }
+          cach->L1d->size = cache_total_size;
+          cach->L1d->exists = true;
+          break;
+
+        case 2: // Instruction Cache (We assume this is L1i)
+          if(cache_level != 1) {
+            printBug("Found instruction cache at level %d (expected 1)", cache_level);
+            return NULL;
+          }
+          cach->L1i->size = cache_total_size;
+          cach->L1i->exists = true;
+          break;
+
+        case 3: // Unified Cache (This may be L2 or L3)
+          if(cache_level == 2) {
+            cach->L2->size = cache_total_size;
+            cach->L2->exists = true;
+          }
+          else if(cache_level == 3) {
+            cach->L3->size = cache_total_size;
+            cach->L3->exists = true;
+          }
+          else {
+            printWarn("Found unknown unified cache at level %d (size is %d bytes)", cache_level, cache_total_size);
+            cach->max_cache_level--;
+          }
+          break;
+
+        default: // Unknown cache type
+          printBug("Unknown cache type %d with level %d found at i=%d", cache_type, cache_level, i);
+          return NULL;
+      }
+    }
+
+    i++;
+  } while (cache_type > 0);
+
+  return cach;
+}
+
+struct cache* get_cache_info(struct cpuInfo* cpu) {
+  struct cache* cach = emalloc(sizeof(struct cache));
+  init_cache_struct(cach);
+
+  uint32_t level;
+
+  // We use standard 0x00000004 for Intel
+  // We use extended 0x8000001D for AMD
+  // or 0x80000005/6 for old AMD
+  if(cpu->cpu_vendor == CPU_VENDOR_INTEL) {
+    level = 0x00000004;
+    if(cpu->maxLevels < level) {
+      printWarn("Can't read cache information from cpuid (needed level is 0x%.8X, max is 0x%.8X)", level, cpu->maxLevels);
+      return NULL;
+    }
+    else {
+      cach = get_cache_info_general(cach, level);
+    }
+  }
+  else {
+    level = 0x8000001D;
+    if(cpu->maxExtendedLevels < level || !cpu->topology_extensions) {
+      printWarn("Can't read cache information from cpuid (needed extended level is 0x%.8X, max is 0x%.8X and topology_extensions=%s)", level, cpu->maxExtendedLevels, cpu->topology_extensions ? "true" : "false");
+      level = 0x80000006;
+      if(cpu->maxExtendedLevels < level) {
+        printWarn("Can't read cache information from cpuid using old method (needed extended level is 0x%.8X, max is 0x%.8X)", level, cpu->maxExtendedLevels);
+        return NULL;
+      }
+      printWarn("Fallback to old method using 0x%.8X and 0x%.8X", level-1, level);
+      cach = get_cache_info_amd_fallback(cach);
+    }
+    else {
+      cach = get_cache_info_general(cach, level);
+    }
+  }
+
+  return cach;
+}
+
+struct frequency* get_frequency_info(struct cpuInfo* cpu) {
+  struct frequency* freq = emalloc(sizeof(struct frequency));
+
+  if(cpu->maxLevels < 0x00000016) {
+    #if defined (_WIN32) || defined (__APPLE__)
+      printWarn("Can't read frequency information from cpuid (needed level is 0x%.8X, max is 0x%.8X)", 0x00000016, cpu->maxLevels);
+      freq->base = UNKNOWN_FREQ;
+      freq->max = UNKNOWN_FREQ;
+    #else
+      printWarn("Can't read frequency information from cpuid (needed level is 0x%.8X, max is 0x%.8X). Using udev", 0x00000016, cpu->maxLevels);
+      freq->base = UNKNOWN_FREQ;
+      freq->max = get_max_freq_from_file(0);
+
+      if(freq->max == 0) {
+        printWarn("Read max CPU frequency from udev and got 0 MHz");
+        freq->max = UNKNOWN_FREQ;
+      }
+    #endif
+  }
+  else {
+    uint32_t eax = 0x00000016;
+    uint32_t ebx = 0;
+    uint32_t ecx = 0;
+    uint32_t edx = 0;
+
+    cpuid(&eax, &ebx, &ecx, &edx);
+
+    freq->base = eax;
+    freq->max = ebx;
+
+    if(freq->base == 0) {
+      printWarn("Read base CPU frequency from CPUID and got 0 MHz");
+      freq->base = UNKNOWN_FREQ;
+    }
+    if(freq->max == 0) {
+      printWarn("Read max CPU frequency from CPUID and got 0 MHz");
+      #ifdef __linux__
+        printWarn("Using udev to detect frequency");
+        freq->max = get_max_freq_from_file(0);
+
+        if(freq->max == 0) {
+          printWarn("Read max CPU frequency from udev and got 0 MHz");
+          freq->max = UNKNOWN_FREQ;
+        }
+      #else
+        freq->max = UNKNOWN_FREQ;
+      #endif
+    }
+  }
+
+  return freq;
+}
+
+// STRING FUNCTIONS
+char* get_str_topology(struct cpuInfo* cpu, struct topology* topo, bool dual_socket) {
+  int topo_sockets = dual_socket ? topo->sockets : 1;
+  char* string;
+
+  if(topo->smt_supported > 1) {
+    // 4 for digits, 21 for ' cores (SMT disabled)' which is the longest possible output
+    uint32_t max_size = 4+21+1;
+    string = emalloc(sizeof(char) * max_size);
+
+    if(topo->smt_available > 1)
+      snprintf(string, max_size, "%d cores (%d threads)", topo->physical_cores * topo_sockets, topo->logical_cores * topo_sockets);
+    else {
+      if(cpu->cpu_vendor == CPU_VENDOR_AMD)
+        snprintf(string, max_size, "%d cores (SMT disabled)", topo->physical_cores * topo_sockets);
+      else
+        snprintf(string, max_size, "%d cores (HT disabled)", topo->physical_cores * topo_sockets);
+    }
+  }
+  else {
+    uint32_t max_size = 4+7+1;
+    string = emalloc(sizeof(char) * max_size);
+    snprintf(string, max_size, "%d cores",topo->physical_cores * topo_sockets);
+  }
+
+  return string;
+}
+
+char* get_str_avx(struct cpuInfo* cpu) {
+  //If all AVX are available, it will use up to 15
+  char* string = emalloc(sizeof(char)*17+1);
+  if(!cpu->feat->AVX)
+    snprintf(string,2+1,"No");
+  else if(!cpu->feat->AVX2)
+    snprintf(string,3+1,"AVX");
+  else if(!cpu->feat->AVX512)
+    snprintf(string,8+1,"AVX,AVX2");
+  else
+    snprintf(string,15+1,"AVX,AVX2,AVX512");
+
+  return string;
+}
+
+char* get_str_sse(struct cpuInfo* cpu) {
+  uint32_t last = 0;
+  uint32_t SSE_sl = 4;
+  uint32_t SSE2_sl = 5;
+  uint32_t SSE3_sl = 5;
+  uint32_t SSSE3_sl = 6;
+  uint32_t SSE4a_sl = 6;
+  uint32_t SSE4_1_sl = 7;
+  uint32_t SSE4_2_sl = 7;
+  char* string = emalloc(sizeof(char)*SSE_sl+SSE2_sl+SSE3_sl+SSSE3_sl+SSE4a_sl+SSE4_1_sl+SSE4_2_sl+1);
+
+  if(cpu->feat->SSE) {
+      snprintf(string+last,SSE_sl+1,"SSE,");
+      last+=SSE_sl;
+  }
+  if(cpu->feat->SSE2) {
+      snprintf(string+last,SSE2_sl+1,"SSE2,");
+      last+=SSE2_sl;
+  }
+  if(cpu->feat->SSE3) {
+      snprintf(string+last,SSE3_sl+1,"SSE3,");
+      last+=SSE3_sl;
+  }
+  if(cpu->feat->SSSE3) {
+      snprintf(string+last,SSSE3_sl+1,"SSSE3,");
+      last+=SSSE3_sl;
+  }
+  if(cpu->feat->SSE4a) {
+      snprintf(string+last,SSE4a_sl+1,"SSE4a,");
+      last+=SSE4a_sl;
+  }
+  if(cpu->feat->SSE4_1) {
+      snprintf(string+last,SSE4_1_sl+1,"SSE4.1,");
+      last+=SSE4_1_sl;
+  }
+  if(cpu->feat->SSE4_2) {
+      snprintf(string+last,SSE4_2_sl+1,"SSE4.2,");
+      last+=SSE4_2_sl;
+  }
+
+  //Purge last comma
+  string[last-1] = '\0';
+  return string;
+}
+
+char* get_str_fma(struct cpuInfo* cpu) {
+  char* string = emalloc(sizeof(char)*9+1);
+  if(!cpu->feat->FMA3)
+    snprintf(string,2+1,"No");
+  else if(!cpu->feat->FMA4)
+    snprintf(string,4+1,"FMA3");
+  else
+    snprintf(string,9+1,"FMA3,FMA4");
+
+  return string;
+}
+
+void print_debug(struct cpuInfo* cpu) {
+  uint32_t eax = 0x00000001;
+  uint32_t ebx = 0;
+  uint32_t ecx = 0;
+  uint32_t edx = 0;
+
+  cpuid(&eax, &ebx, &ecx, &edx);
+
+  printf("%s\n", cpu->cpu_name);
+  if(cpu->hv->present) {
+    printf("- Hypervisor: %s\n", cpu->hv->hv_name);
+  }
+  printf("- Max standard level: 0x%.8X\n", cpu->maxLevels);
+  printf("- Max extended level: 0x%.8X\n", cpu->maxExtendedLevels);
+  if(cpu->cpu_vendor == CPU_VENDOR_AMD) {
+    printf("- AMD topology extensions: %d\n", cpu->topology_extensions);
+  }
+  printf("- CPUID dump: 0x%.8X\n", eax);
+
+  free_cpuinfo_struct(cpu);
+}
+
+// TODO: Query HV and Xeon Phi levels
+void print_raw(struct cpuInfo* cpu) {
+  uint32_t eax;
+  uint32_t ebx;
+  uint32_t ecx;
+  uint32_t edx;
+  printf("%s\n\n", cpu->cpu_name);
+  printf("  CPUID leaf sub   EAX        EBX        ECX        EDX       \n");
+  printf("--------------------------------------------------------------\n");
+
+  for(int c=0; c < cpu->topo->total_cores; c++) {
+    #ifndef __APPLE__
+    if(!bind_to_cpu(c)) {
+      printErr("Failed binding to CPU %d", c);
+      return;
+    }
+    #endif
+
+    printf("CPU %d:\n", c);
+
+    for(uint32_t reg=0x00000000; reg <= cpu->maxLevels; reg++) {
+      if(reg == 0x00000004) {
+        for(uint32_t reg2=0x00000000; reg2 < cpu->cach->max_cache_level; reg2++) {
+          eax = reg;
+          ebx = 0;
+          ecx = reg2;
+          edx = 0;
+
+          cpuid(&eax, &ebx, &ecx, &edx);
+
+          printf("  0x%.8X 0x%.2X: 0x%.8X 0x%.8X 0x%.8X 0x%.8X\n", reg, reg2, eax, ebx, ecx, edx);
+        }
+      }
+      else if(reg == 0x0000000B) {
+        for(uint32_t reg2=0x00000000; reg2 < cpu->topo->smt_supported; reg2++) {
+          eax = reg;
+          ebx = 0;
+          ecx = reg2;
+          edx = 0;
+
+          cpuid(&eax, &ebx, &ecx, &edx);
+
+          printf("  0x%.8X 0x%.2X: 0x%.8X 0x%.8X 0x%.8X 0x%.8X\n", reg, reg2, eax, ebx, ecx, edx);
+        }
+      }
+      else {
+        eax = reg;
+        ebx = 0;
+        ecx = 0;
+        edx = 0;
+
+        cpuid(&eax, &ebx, &ecx, &edx);
+
+        printf("  0x%.8X 0x%.2X: 0x%.8X 0x%.8X 0x%.8X 0x%.8X\n", reg, 0x00, eax, ebx, ecx, edx);
+      }
+    }
+    for(uint32_t reg=0x80000000; reg <= cpu->maxExtendedLevels; reg++) {
+      if(reg == 0x8000001D) {
+        for(uint32_t reg2=0x00000000; reg2 < cpu->cach->max_cache_level; reg2++) {
+          eax = reg;
+          ebx = 0;
+          ecx = reg2;
+          edx = 0;
+
+          cpuid(&eax, &ebx, &ecx, &edx);
+
+          printf("  0x%.8X 0x%.2X: 0x%.8X 0x%.8X 0x%.8X 0x%.8X\n", reg, reg2, eax, ebx, ecx, edx);
+        }
+      }
+      else {
+        eax = reg;
+        ebx = 0;
+        ecx = 0;
+        edx = 0;
+
+        cpuid(&eax, &ebx, &ecx, &edx);
+
+        printf("  0x%.8X 0x%.2X: 0x%.8X 0x%.8X 0x%.8X 0x%.8X\n", reg, 0x00, eax, ebx, ecx, edx);
+      }
+    }
+  }
+}
+
+void free_topo_struct(struct topology* topo) {
+  free(topo->apic->cache_select_mask);
+  free(topo->apic->cache_id_apic);
+  free(topo->apic);
+  free(topo);
+}

src/x86/cpuid.h

@@ -0,0 +1,21 @@
+#ifndef __CPUID__
+#define __CPUID__
+
+#include "../common/cpu.h"
+
+struct cpuInfo* get_cpu_info();
+struct cache* get_cache_info(struct cpuInfo* cpu);
+struct frequency* get_frequency_info(struct cpuInfo* cpu);
+struct topology* get_topology_info(struct cpuInfo* cpu, struct cache* cach);
+
+char* get_str_avx(struct cpuInfo* cpu);
+char* get_str_sse(struct cpuInfo* cpu);
+char* get_str_fma(struct cpuInfo* cpu);
+char* get_str_topology(struct cpuInfo* cpu, struct topology* topo, bool dual_socket);
+
+void print_debug(struct cpuInfo* cpu);
+void print_raw(struct cpuInfo* cpu);
+
+void free_topo_struct(struct topology* topo);
+
+#endif

src/x86/uarch.c

@@ -4,13 +4,14 @@
 #include <string.h>
 
 #include "uarch.h"
-#include "global.h"
+#include "../common/global.h"
 
 /*
  * - cpuid codes are based on Todd Allen's cpuid program
  *   http://www.etallen.com/cpuid.html
  * - This should be updated from time to time, to support newer CPUs. A good reference to look at:
  *   https://en.wikichip.org/
+ *   http://instlatx64.atw.hu/
  */
 
 // From Todd Allen:
@@ -43,64 +44,71 @@ typedef uint32_t MICROARCH;
 // Unknown manufacturing process
 #define UNK                  -1
 
-#define UARCH_UNKNOWN         0x000
-#define UARCH_P5              0x001
-#define UARCH_P6              0x002
-#define UARCH_DOTHAN          0x003
-#define UARCH_YONAH           0x004
-#define UARCH_MEROM           0x005
-#define UARCH_PENYR           0x006
-#define UARCH_NEHALEM         0x007
-#define UARCH_WESTMERE        0x008
-#define UARCH_BONNELL         0x009
-#define UARCH_SALTWELL        0x010
-#define UARCH_SANDY_BRIDGE    0x011
-#define UARCH_SILVERMONT      0x012
-#define UARCH_IVY_BRIDGE      0x013
-#define UARCH_HASWELL         0x014
-#define UARCH_BROADWELL       0x015
-#define UARCH_AIRMONT         0x016
-#define UARCH_KABY_LAKE       0x017
-#define UARCH_SKYLAKE         0x018
-#define UARCH_CASCADE_LAKE    0x019
-#define UARCH_COOPER_LAKE     0x020
-#define UARCH_KNIGHTS_LANDING 0x021
-#define UARCH_KNIGHTS_MILL    0x022
-#define UARCH_GOLDMONT        0x023
-#define UARCH_PALM_COVE       0x024
-#define UARCH_SUNNY_COVE      0x025
-#define UARCH_GOLDMONT_PLUS   0x026
-#define UARCH_TREMONT         0x027
-#define UARCH_WILLOW_COVE     0x028
-#define UARCH_COFFE_LAKE      0x029
-#define UARCH_ITANIUM         0x030
-#define UARCH_KNIGHTS_FERRY   0x031
-#define UARCH_KNIGHTS_CORNER  0x032
-#define UARCH_WILLAMETTE      0x033
-#define UARCH_NORTHWOOD       0x034
-#define UARCH_PRESCOTT        0x035
-#define UARCH_CEDAR_MILL      0x036
-#define UARCH_ITANIUM2        0x037
-#define UARCH_ICE_LAKE        0x038
-
-#define UARCH_AM486           0x038
-#define UARCH_AM5X86          0x039
-#define UARCH_K6              0x040
-#define UARCH_K7              0x041
-#define UARCH_K8              0x042
-#define UARCH_K10             0x043
-#define UARCH_PUMA_2008       0x044
-#define UARCH_BOBCAT          0x045
-#define UARCH_BULLDOZER       0x046
-#define UARCH_PILEDRIVER      0x047
-#define UARCH_STEAMROLLER     0x048
-#define UARCH_EXCAVATOR       0x049
-#define UARCH_JAGUAR          0x050
-#define UARCH_PUMA_2014       0x051
-#define UARCH_ZEN             0x052
-#define UARCH_ZEN_PLUS        0x053
-#define UARCH_ZEN2            0x054
-#define UARCH_ZEN3            0x055
+enum {
+  UARCH_UNKNOWN,
+  // INTEL //
+  UARCH_P5,
+  UARCH_P6,
+  UARCH_DOTHAN,
+  UARCH_YONAH,
+  UARCH_MEROM,
+  UARCH_PENYR,
+  UARCH_NEHALEM,
+  UARCH_WESTMERE,
+  UARCH_BONNELL,
+  UARCH_SALTWELL,
+  UARCH_SANDY_BRIDGE,
+  UARCH_SILVERMONT,
+  UARCH_IVY_BRIDGE,
+  UARCH_HASWELL,
+  UARCH_BROADWELL,
+  UARCH_AIRMONT,
+  UARCH_KABY_LAKE,
+  UARCH_COMET_LAKE,
+  UARCH_ROCKET_LAKE,
+  UARCH_AMBER_LAKE,
+  UARCH_WHISKEY_LAKE,
+  UARCH_SKYLAKE,
+  UARCH_CASCADE_LAKE,
+  UARCH_COOPER_LAKE,
+  UARCH_KNIGHTS_LANDING,
+  UARCH_KNIGHTS_MILL,
+  UARCH_GOLDMONT,
+  UARCH_PALM_COVE,
+  UARCH_SUNNY_COVE,
+  UARCH_GOLDMONT_PLUS,
+  UARCH_TREMONT,
+  UARCH_WILLOW_COVE,
+  UARCH_COFFE_LAKE,
+  UARCH_ITANIUM,
+  UARCH_KNIGHTS_FERRY,
+  UARCH_KNIGHTS_CORNER,
+  UARCH_WILLAMETTE,
+  UARCH_NORTHWOOD,
+  UARCH_PRESCOTT,
+  UARCH_CEDAR_MILL,
+  UARCH_ITANIUM2,
+  UARCH_ICE_LAKE,
+  // AMD //
+  UARCH_AM486,
+  UARCH_AM5X86,
+  UARCH_K6,
+  UARCH_K7,
+  UARCH_K8,
+  UARCH_K10,
+  UARCH_PUMA_2008,
+  UARCH_BOBCAT,
+  UARCH_BULLDOZER,
+  UARCH_PILEDRIVER,
+  UARCH_STEAMROLLER,
+  UARCH_EXCAVATOR,
+  UARCH_JAGUAR,
+  UARCH_PUMA_2014,
+  UARCH_ZEN,
+  UARCH_ZEN_PLUS,
+  UARCH_ZEN2,
+  UARCH_ZEN3
+};
 
 struct uarch {
   MICROARCH uarch;
@@ -111,18 +119,18 @@ struct uarch {
 #define UARCH_START if (false) {}
 #define CHECK_UARCH(arch, ef_, f_, em_, m_, s_, str, uarch, process) \
    else if (ef_ == ef && f_ == f && (em_ == NA || em_ == em) && (m_ == NA || m_ == m) && (s_ == NA || s_ == s)) fill_uarch(arch, str, uarch, process);
-#define UARCH_END else { printBug("Unknown microarchitecture detected: M=0x%.8X EM=0x%.8X F=0x%.8X EF=0x%.8X S=0x%.8X", m, em, f, ef, s); fill_uarch(arch, "Unknown", UARCH_UNKNOWN, 0); }
+#define UARCH_END else { printBug("Unknown microarchitecture detected: M=0x%.8X EM=0x%.8X F=0x%.8X EF=0x%.8X S=0x%.8X", m, em, f, ef, s); fill_uarch(arch, STRING_UNKNOWN, UARCH_UNKNOWN, 0); }
 
 void fill_uarch(struct uarch* arch, char* str, MICROARCH u, uint32_t process) {
-  arch->uarch_str = malloc(sizeof(char) * (strlen(str)+1));
+  arch->uarch_str = emalloc(sizeof(char) * (strlen(str)+1));
   strcpy(arch->uarch_str, str);
   arch->uarch = u;
   arch->process= process;
 }
 
-// iNApired in Todd Allen's decode_uarch_intel
+// Inspired in Todd Allen's decode_uarch_intel
 struct uarch* get_uarch_from_cpuid_intel(uint32_t ef, uint32_t f, uint32_t em, uint32_t m, int s) {
-  struct uarch* arch = malloc(sizeof(struct uarch));
+  struct uarch* arch = emalloc(sizeof(struct uarch));
 
   // EF: Extended Family                                                           //
   // F:  Family                                                                    //
@@ -212,7 +220,10 @@ struct uarch* get_uarch_from_cpuid_intel(uint32_t ef, uint32_t f, uint32_t em, u
   CHECK_UARCH(arch, 0,  6,  8, 10, NA, "Tremont",         UARCH_TREMONT,          10) // no spec update; only geekbench.com example
   CHECK_UARCH(arch, 0,  6,  8, 12, NA, "Willow Cove",     UARCH_WILLOW_COVE,      10) // found only on en.wikichip.org
   CHECK_UARCH(arch, 0,  6,  8, 13, NA, "Willow Cove",     UARCH_WILLOW_COVE,      10) // LX*
-  CHECK_UARCH(arch, 0,  6,  8, 14, NA, "Kaby Lake",       UARCH_KABY_LAKE,        14)
+  CHECK_UARCH(arch, 0,  6,  8, 14,  9, "Amber Lake",      UARCH_AMBER_LAKE,       14) // wikichip
+  CHECK_UARCH(arch, 0,  6,  8, 14, 10, "Kaby Lake",       UARCH_KABY_LAKE,        14) // wikichip
+  CHECK_UARCH(arch, 0,  6,  8, 14, 11, "Whiskey Lake",    UARCH_WHISKEY_LAKE,     14) // wikichip
+  CHECK_UARCH(arch, 0,  6,  8, 14, 12, "Comet Lake",      UARCH_COMET_LAKE,       14) // wikichip
   CHECK_UARCH(arch, 0,  6,  9,  6, NA, "Tremont",         UARCH_TREMONT,          10) // LX*
   CHECK_UARCH(arch, 0,  6,  9, 12, NA, "Tremont",         UARCH_TREMONT,          10) // LX*
   CHECK_UARCH(arch, 0,  6,  9, 13, NA, "Sunny Cove",      UARCH_SUNNY_COVE,       10) // LX*
@@ -221,8 +232,9 @@ struct uarch* get_uarch_from_cpuid_intel(uint32_t ef, uint32_t f, uint32_t em, u
   CHECK_UARCH(arch, 0,  6,  9, 14, 11, "Coffee Lake",     UARCH_COFFE_LAKE,       14)
   CHECK_UARCH(arch, 0,  6,  9, 14, 12, "Coffee Lake",     UARCH_COFFE_LAKE,       14)
   CHECK_UARCH(arch, 0,  6,  9, 14, 13, "Coffee Lake",     UARCH_COFFE_LAKE,       14)
-  CHECK_UARCH(arch, 0,  6, 10,  5, NA, "Kaby Lake",       UARCH_KABY_LAKE,        14) // LX*
-  CHECK_UARCH(arch, 0,  6, 10,  6, NA, "Kaby Lake",       UARCH_KABY_LAKE,        14) // no spec update; only iNAtlatx64 example
+  CHECK_UARCH(arch, 0,  6, 10,  5, NA, "Comet Lake",      UARCH_COMET_LAKE,       14) // wikichip
+  CHECK_UARCH(arch, 0,  6, 10,  6, NA, "Comet Lake",      UARCH_COMET_LAKE,       14) // instlatx64.atw.hu (i7-10710U)
+  CHECK_UARCH(arch, 0,  6, 10,  7, NA, "Rocket Lake",     UARCH_ROCKET_LAKE,      14) // instlatx64.atw.hu (i7-11700K)
   CHECK_UARCH(arch, 0, 11,  0,  0, NA, "Knights Ferry",   UARCH_KNIGHTS_FERRY,    45) // found only on en.wikichip.org
   CHECK_UARCH(arch, 0, 11,  0,  1, NA, "Knights Corner",  UARCH_KNIGHTS_CORNER,   22)
   CHECK_UARCH(arch, 0, 15,  0,  0, NA, "Willamette",      UARCH_WILLAMETTE,      180)
@@ -241,7 +253,7 @@ struct uarch* get_uarch_from_cpuid_intel(uint32_t ef, uint32_t f, uint32_t em, u
 
 // iNApired in Todd Allen's decode_uarch_amd
 struct uarch* get_uarch_from_cpuid_amd(uint32_t ef, uint32_t f, uint32_t em, uint32_t m, int s) {
-  struct uarch* arch = malloc(sizeof(struct uarch));
+  struct uarch* arch = emalloc(sizeof(struct uarch));
 
   // EF: Extended Family                                                           //
   // F:  Family                                                                    //
@@ -333,15 +345,17 @@ struct uarch* get_uarch_from_cpuid_amd(uint32_t ef, uint32_t f, uint32_t em, uin
   CHECK_UARCH(arch,  8, 15,  1,  8, NA, "Zen+",        UARCH_ZEN_PLUS,    12) // found only on en.wikichip.org
   CHECK_UARCH(arch,  8, 15,  3,  1, NA, "Zen 2",       UARCH_ZEN2,         7) // found only on en.wikichip.org
   CHECK_UARCH(arch,  8, 15,  6,  0, NA, "Zen 2",       UARCH_ZEN2,         7) // undocumented, geekbench.com example
-  CHECK_UARCH(arch,  8, 15,  7,  1, NA, "Zen 2",       UARCH_ZEN2,         7) // undocumented, but samples from Steven Noonan
-  CHECK_UARCH(arch, 10, 15, NA, NA, NA, "Zen 3",       UARCH_ZEN3,         7) // undocumented, LX*
+  CHECK_UARCH(arch,  8, 15,  6,  8, NA, "Zen 2",       UARCH_ZEN2,         7) // found on instlatx64
+  CHECK_UARCH(arch,  8, 15,  7,  1, NA, "Zen 2",       UARCH_ZEN2,         7) // samples from Steven Noonan and instlatx64
+  CHECK_UARCH(arch, 10, 15,  2,  1, NA, "Zen 3",       UARCH_ZEN3,         7) // instlatx64
+  CHECK_UARCH(arch, 10, 15,  5,  0, NA, "Zen 3",       UARCH_ZEN3,         7) // instlatx64
   UARCH_END
 
   return arch;
 }
 
 struct uarch* get_uarch_from_cpuid(struct cpuInfo* cpu, uint32_t ef, uint32_t f, uint32_t em, uint32_t m, int s) {
-  if(cpu->cpu_vendor == VENDOR_INTEL)
+  if(cpu->cpu_vendor == CPU_VENDOR_INTEL)
     return get_uarch_from_cpuid_intel(ef, f, em, m, s);
   else
     return get_uarch_from_cpuid_amd(ef, f, em, m, s);
@@ -351,17 +365,23 @@ bool vpus_are_AVX512(struct cpuInfo* cpu) {
   return cpu->arch->uarch != UARCH_ICE_LAKE;
 }
 
-int get_number_of_vpus(struct cpuInfo* cpu) {
-  if(cpu->cpu_vendor == VENDOR_AMD)
-    return 1;
+bool is_knights_landing(struct cpuInfo* cpu) {
+  return cpu->arch->uarch == UARCH_KNIGHTS_LANDING;
+}
 
+int get_number_of_vpus(struct cpuInfo* cpu) {
   switch(cpu->arch->uarch) {
+      // Intel
       case UARCH_HASWELL:
       case UARCH_BROADWELL:
 
       case UARCH_SKYLAKE:
       case UARCH_CASCADE_LAKE:
       case UARCH_KABY_LAKE:
+      case UARCH_COMET_LAKE:
+      case UARCH_ROCKET_LAKE:
+      case UARCH_AMBER_LAKE:
+      case UARCH_WHISKEY_LAKE:
       case UARCH_COFFE_LAKE:
       case UARCH_PALM_COVE:
 
@@ -369,6 +389,10 @@ int get_number_of_vpus(struct cpuInfo* cpu) {
       case UARCH_KNIGHTS_MILL:
 
       case UARCH_ICE_LAKE:
+
+      // AMD
+      case UARCH_ZEN2:
+      case UARCH_ZEN3:
         return 2;
       default:
         return 1;
@@ -380,13 +404,22 @@ char* get_str_uarch(struct cpuInfo* cpu) {
 }
 
 char* get_str_process(struct cpuInfo* cpu) {
-  char* str = malloc(sizeof(char) * (4+2+1));
-  uint32_t process = cpu->arch->process;
+  char* str = emalloc(sizeof(char) * (strlen(STRING_UNKNOWN)+1));
+  int32_t process = cpu->arch->process;
 
-  if(process > 100)    
+  if(process == UNK) {
+    snprintf(str, strlen(STRING_UNKNOWN)+1, STRING_UNKNOWN);
+  }
+  else if(process > 100) {
     sprintf(str, "%.2fum", (double)process/100);
-  else
+  }
+  else if(process > 0){
     sprintf(str, "%dnm", process);
+  }
+  else {
+    snprintf(str, strlen(STRING_UNKNOWN)+1, STRING_UNKNOWN);
+    printBug("Found invalid process: '%d'", process);
+  }
 
   return str;
 }

src/x86/uarch.h

@@ -9,6 +9,7 @@ struct uarch;
 
 struct uarch* get_uarch_from_cpuid(struct cpuInfo* cpu, uint32_t ef, uint32_t f, uint32_t em, uint32_t m, int s);
 bool vpus_are_AVX512(struct cpuInfo* cpu);
+bool is_knights_landing(struct cpuInfo* cpu);
 int get_number_of_vpus(struct cpuInfo* cpu);
 char* get_str_uarch(struct cpuInfo* cpu);
 char* get_str_process(struct cpuInfo* cpu);

src/x86/uarch_decode.sh

@@ -0,0 +1,23 @@
+#!/bin/bash -u
+
+CPUID=0x00A50F00
+
+efamily=$(((${CPUID}>>20)&0xFF))
+family=$(((${CPUID}>>8)&0xF))
+emodel=$(((${CPUID}>>16)&0xF))
+model=$(((${CPUID}>>4)&0xF))
+stepping=$((${CPUID}&0xF))
+
+printf 'CPUID: 0x%.8X\n' $CPUID
+printf -- '- EF = 0x%X (%d)\n' $efamily $efamily
+printf -- '- F  = 0x%X (%d)\n' $family $family
+printf -- '- EM = 0x%X (%d)\n' $emodel $emodel
+printf -- '- M  = 0x%X (%d)\n' $model $model
+printf -- '- S  = 0x%X (%d)\n' $stepping $stepping
+
+#EF=$efamily
+#F=$family
+#EM=$emodel
+#M=$model
+#S=$stepping
+#grep -E "\s*CHECK_UARCH\(arch,\s*${EF},\s*${F},\s*(${EM}|NA),\s*(${M}|NA),\s*(${S}|NA)" uarch.c