[v1.02][x86] Detect and print core type in ADL

LICENSE

@@ -1,21 +1,339 @@
-MIT License
+                    GNU GENERAL PUBLIC LICENSE
+                       Version 2, June 1991
 
-Copyright (c) 2018 Dr-Noob
+ Copyright (C) 1989, 1991 Free Software Foundation, Inc.,
+ 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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+ of this license document, but changing it is not allowed.
 
-Permission is hereby granted, free of charge, to any person obtaining a copy
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+Public License instead of this License.

Makefile

@@ -12,7 +12,7 @@ COMMON_HDR = $(SRC_COMMON)ascii.h $(SRC_COMMON)cpu.h $(SRC_COMMON)udev.h $(SRC_C
 
 ifneq ($(OS),Windows_NT)
 	arch := $(shell uname -m)
-	ifeq ($(arch), $(filter $(arch), x86_64 amd64 i686))
+	ifeq ($(arch), $(filter $(arch), x86_64 amd64 i386 i486 i586 i686))
 		SRC_DIR=src/x86/
 		SOURCE += $(COMMON_SRC) $(SRC_DIR)cpuid.c $(SRC_DIR)apic.c $(SRC_DIR)cpuid_asm.c $(SRC_DIR)uarch.c
 		HEADERS += $(COMMON_HDR) $(SRC_DIR)cpuid.h $(SRC_DIR)apic.h $(SRC_DIR)cpuid_asm.h $(SRC_DIR)uarch.h $(SRC_DIR)freq/freq.h
@@ -28,7 +28,7 @@ ifneq ($(OS),Windows_NT)
 		SRC_DIR=src/ppc/
 		SOURCE += $(COMMON_SRC) $(SRC_DIR)ppc.c $(SRC_DIR)uarch.c $(SRC_DIR)udev.c
 		HEADERS += $(COMMON_HDR) $(SRC_DIR)ppc.h $(SRC_DIR)uarch.h  $(SRC_DIR)udev.c
-		CFLAGS += -DARCH_PPC -std=gnu99 -fstack-protector-all
+		CFLAGS += -DARCH_PPC -std=gnu99 -fstack-protector-all -Wno-language-extension-token
 	else ifeq ($(arch), $(filter $(arch), arm aarch64_be aarch64 arm64 armv8b armv8l armv7l armv6l))
 		SRC_DIR=src/arm/
 		SOURCE += $(COMMON_SRC) $(SRC_DIR)midr.c $(SRC_DIR)uarch.c $(SRC_DIR)soc.c $(SRC_DIR)udev.c
@@ -70,14 +70,14 @@ static: $(OUTPUT)
 strict: CFLAGS += -O2 -Werror -fsanitize=undefined -D_FORTIFY_SOURCE=2
 strict: $(OUTPUT)
 
-freq_nov.o: Makefile $(SRC_DIR)freq/freq_nov.c $(SRC_DIR)freq/freq_nov.h
+freq_nov.o: Makefile $(SRC_DIR)freq/freq_nov.c $(SRC_DIR)freq/freq_nov.h $(SRC_DIR)freq/freq.h
 	$(CC) $(CFLAGS) $(SANITY_FLAGS) -c -pthread $(SRC_DIR)freq/freq_nov.c -o $@
 
-freq_avx.o: Makefile $(SRC_DIR)freq/freq_avx.c $(SRC_DIR)freq/freq_avx.h
+freq_avx.o: Makefile $(SRC_DIR)freq/freq_avx.c $(SRC_DIR)freq/freq_avx.h $(SRC_DIR)freq/freq.h
-	$(CC) $(CFLAGS) $(SANITY_FLAGS) -c -mavx -mfma -pthread $(SRC_DIR)freq/freq_avx.c -o $@
+	$(CC) $(CFLAGS) $(SANITY_FLAGS) -c -mavx -pthread $(SRC_DIR)freq/freq_avx.c -o $@
 
-freq_avx512.o: Makefile $(SRC_DIR)freq/freq_avx512.c $(SRC_DIR)freq/freq_avx512.h
+freq_avx512.o: Makefile $(SRC_DIR)freq/freq_avx512.c $(SRC_DIR)freq/freq_avx512.h $(SRC_DIR)freq/freq.h
-	$(CC) $(CFLAGS) $(SANITY_FLAGS) -c -mavx512f -mfma -pthread $(SRC_DIR)freq/freq_avx512.c -o $@
+	$(CC) $(CFLAGS) $(SANITY_FLAGS) -c -mavx512f -pthread $(SRC_DIR)freq/freq_avx512.c -o $@
 
 $(OUTPUT): Makefile $(SOURCE) $(HEADERS)
 	$(CC) $(CFLAGS) $(SANITY_FLAGS) $(SOURCE) -o $(OUTPUT)

src/arm/midr.c

@@ -10,12 +10,6 @@
   #include <asm/hwcap.h>
 #elif defined __APPLE__ || __MACH__
   #include "sysctl.h"
-  // From Linux kernel: arch/arm64/include/asm/cputype.h
-  #define MIDR_APPLE_M1_ICESTORM  0x610F0220
-  #define MIDR_APPLE_M1_FIRESTORM 0x610F0230
-  #ifndef CPUFAMILY_ARM_FIRESTORM_ICESTORM
-    #define CPUFAMILY_ARM_FIRESTORM_ICESTORM 0x1B588BB3
-  #endif
 #endif
 
 #include "../common/global.h"
@@ -87,12 +81,23 @@ int64_t get_peak_performance(struct cpuInfo* cpu) {
   }
 
   int64_t flops = 0;
-
   ptr = cpu;
+
+  if(cpu->soc->soc_vendor == SOC_VENDOR_APPLE) {
+    // Special case for M1/M2
+    // First we find the E cores, then the P
+    // M1 have 2 (E cores) or 4 (P cores) FMA units
+    // Source: https://dougallj.github.io/applecpu/firestorm-simd.html
+    flops += ptr->topo->total_cores * (get_freq(ptr->freq) * 1000000) * 2 * 4 * 2;
+    ptr = ptr->next_cpu;
+    flops += ptr->topo->total_cores * (get_freq(ptr->freq) * 1000000) * 2 * 4 * 4;
+  }
+  else {
     for(int i=0; i < cpu->num_cpus; ptr = ptr->next_cpu, i++) {
       flops += ptr->topo->total_cores * (get_freq(ptr->freq) * 1000000);
     }
     if(cpu->feat->NEON) flops = flops * 4;
+  }
 
   return flops;
 }
@@ -244,7 +249,7 @@ struct cpuInfo* get_cpu_info_linux(struct cpuInfo* cpu) {
 }
 
 #elif defined __APPLE__ || __MACH__
-void fill_cpu_info_firestorm_icestorm(struct cpuInfo* cpu) {
+void fill_cpu_info_firestorm_icestorm(struct cpuInfo* cpu, uint32_t pcores, uint32_t ecores) {
   // 1. Fill ICESTORM
   struct cpuInfo* ice = cpu;
 
@@ -254,7 +259,7 @@ void fill_cpu_info_firestorm_icestorm(struct cpuInfo* cpu) {
   ice->feat = get_features_info();
   ice->topo = malloc(sizeof(struct topology));
   ice->topo->cach = ice->cach;
-  ice->topo->total_cores = 4;
+  ice->topo->total_cores = ecores;
   ice->freq = malloc(sizeof(struct frequency));
   ice->freq->base = UNKNOWN_DATA;
   ice->freq->max = 2064;
@@ -270,7 +275,7 @@ void fill_cpu_info_firestorm_icestorm(struct cpuInfo* cpu) {
   fire->feat = get_features_info();
   fire->topo = malloc(sizeof(struct topology));
   fire->topo->cach = fire->cach;
-  fire->topo->total_cores = 4;
+  fire->topo->total_cores = pcores;
   fire->freq = malloc(sizeof(struct frequency));
   fire->freq->base = UNKNOWN_DATA;
   fire->freq->max = 3200;
@@ -279,15 +284,82 @@ void fill_cpu_info_firestorm_icestorm(struct cpuInfo* cpu) {
   fire->next_cpu = NULL;
 }
 
+void fill_cpu_info_avalanche_blizzard(struct cpuInfo* cpu, uint32_t pcores, uint32_t ecores) {
+  // 1. Fill BLIZZARD
+  struct cpuInfo* bli = cpu;
+
+  bli->midr = MIDR_APPLE_M2_BLIZZARD;
+  bli->arch = get_uarch_from_midr(bli->midr, bli);
+  bli->cach = get_cache_info(bli);
+  bli->feat = get_features_info();
+  bli->topo = malloc(sizeof(struct topology));
+  bli->topo->cach = bli->cach;
+  bli->topo->total_cores = pcores;
+  bli->freq = malloc(sizeof(struct frequency));
+  bli->freq->base = UNKNOWN_DATA;
+  bli->freq->max = 2800;
+  bli->hv = malloc(sizeof(struct hypervisor));
+  bli->hv->present = false;
+  bli->next_cpu = malloc(sizeof(struct cpuInfo));
+
+  // 2. Fill AVALANCHE
+  struct cpuInfo* ava = bli->next_cpu;
+  ava->midr = MIDR_APPLE_M2_AVALANCHE;
+  ava->arch = get_uarch_from_midr(ava->midr, ava);
+  ava->cach = get_cache_info(ava);
+  ava->feat = get_features_info();
+  ava->topo = malloc(sizeof(struct topology));
+  ava->topo->cach = ava->cach;
+  ava->topo->total_cores = ecores;
+  ava->freq = malloc(sizeof(struct frequency));
+  ava->freq->base = UNKNOWN_DATA;
+  ava->freq->max = 3500;
+  ava->hv = malloc(sizeof(struct hypervisor));
+  ava->hv->present = false;
+  ava->next_cpu = NULL;
+}
+
 struct cpuInfo* get_cpu_info_mach(struct cpuInfo* cpu) {
   uint32_t cpu_family = get_sys_info_by_name("hw.cpufamily");
 
-  // Manually fill the cpuInfo assuming that the CPU
+  // Manually fill the cpuInfo assuming that
-  // is a ARM_FIRESTORM_ICESTORM (Apple M1)
+  // the CPU is an Apple M1/M2
   if(cpu_family == CPUFAMILY_ARM_FIRESTORM_ICESTORM) {
     cpu->num_cpus = 2;
+    // Now detect the M1 version
+    uint32_t cpu_subfamily = get_sys_info_by_name("hw.cpusubfamily");
+    if(cpu_subfamily == CPUSUBFAMILY_ARM_HG) {
+      // Apple M1
+      fill_cpu_info_firestorm_icestorm(cpu, 4, 4);
+    }
+    else if(cpu_subfamily == CPUSUBFAMILY_ARM_HS || cpu_subfamily == CPUSUBFAMILY_ARM_HC_HD) {
+      // Apple M1 Pro/Max/Ultra. Detect number of cores
+      uint32_t physicalcpu = get_sys_info_by_name("hw.physicalcpu");
+      if(physicalcpu == 20) {
+        // M1 Ultra
+        fill_cpu_info_firestorm_icestorm(cpu, 16, 4);
+      }
+      else if(physicalcpu == 8 || physicalcpu == 10) {
+        // M1 Pro/Max
+        fill_cpu_info_firestorm_icestorm(cpu, physicalcpu-2, 2);
+      }
+      else {
+        printBug("Found invalid physical cpu number: %d", physicalcpu);
+        return NULL;
+      }
+    }
+    else {
+      printBug("Found invalid cpu_subfamily: 0x%.8X", cpu_subfamily);
+      return NULL;
+    }
+    cpu->soc = get_soc();
+    cpu->peak_performance = get_peak_performance(cpu);
+  }
+  else if(cpu_family == CPUFAMILY_ARM_AVALANCHE_BLIZZARD) {
+    // Just the "normal" M2 exists for now
+    cpu->num_cpus = 2;
+    fill_cpu_info_avalanche_blizzard(cpu, 4, 4);
     cpu->soc = get_soc();
-    fill_cpu_info_firestorm_icestorm(cpu);
     cpu->peak_performance = get_peak_performance(cpu);
   }
   else {

src/arm/soc.c

@@ -8,6 +8,10 @@
 #include "udev.h"
 #include "../common/global.h"
 
+#if defined(__APPLE__) || defined(__MACH__)
+  #include "sysctl.h"
+#endif
+
 #define min(a,b) (((a)<(b))?(a):(b))
 #define ARRAY_SIZE(arr)     (sizeof(arr) / sizeof((arr)[0]))
 
@@ -17,7 +21,8 @@ static char* soc_trademark_string[] = {
   [SOC_VENDOR_EXYNOS]     = "Exynos ",
   [SOC_VENDOR_KIRIN]      = "Kirin ",
   [SOC_VENDOR_BROADCOM]   = "Broadcom BCM",
-  [SOC_VENDOR_APPLE]      = "Apple "
+  [SOC_VENDOR_APPLE]      = "Apple ",
+  [SOC_VENDOR_ALLWINNER]  = "Allwinner "
 };
 
 static char* soc_rpi_string[] = {
@@ -38,10 +43,10 @@ void fill_soc(struct system_on_chip* soc, char* soc_name, SOC soc_model, int32_t
 }
 
 bool match_soc(struct system_on_chip* soc, char* raw_name, char* expected_name, char* soc_name, SOC soc_model, int32_t process) {
-  if(strlen(raw_name) > strlen(expected_name))
+  int len1 = strlen(raw_name);
-    return false;
+  int len2 = strlen(expected_name);
+  int len = min(len1, len2);
 
-  int len = strlen(raw_name);
   if(strncmp(raw_name, expected_name, len) != 0) {
     return false;
   }
@@ -106,11 +111,11 @@ bool match_broadcom(char* soc_name, struct system_on_chip* soc) {
 bool match_hisilicon(char* soc_name, struct system_on_chip* soc) {
   char* tmp;
 
-  if((tmp = strstr(soc_name, "Hi")) == NULL)
+  if((tmp = strstr(soc_name, "hi")) == NULL)
     return false;
 
   SOC_START
-  SOC_EQ(tmp, "Hi3620GFC",  "K3V2",  SOC_HISILICON_3620, soc, 40)
+  SOC_EQ(tmp, "hi3620GFC",  "K3V2",  SOC_HISILICON_3620, soc, 40)
   //SOC_EQ(tmp, "?",        "K3V2E", SOC_KIRIN, soc,  ?)
   //SOC_EQ(tmp, "?",        "620",   SOC_KIRIN, soc, 28)
   //SOC_EQ(tmp, "?",        "650",   SOC_KIRIN, soc, 16)
@@ -126,18 +131,18 @@ bool match_hisilicon(char* soc_name, struct system_on_chip* soc) {
   //SOC_EQ(tmp, "?",        "9000E", SOC_KIRIN, soc,  5)
   //SOC_EQ(tmp, "?",        "910",   SOC_KIRIN, soc, 28)
   //SOC_EQ(tmp, "?",        "910T",  SOC_KIRIN, soc, 28)
-  SOC_EQ(tmp, "Hi3630",     "920",   SOC_HISILICON_3630, soc, 28)
+  SOC_EQ(tmp, "hi3630",     "920",   SOC_HISILICON_3630, soc, 28)
   //SOC_EQ(tmp, "?",        "925",   SOC_KIRIN, soc, 28)
   //SOC_EQ(tmp, "?",        "930",   SOC_KIRIN, soc, ?)
   //SOC_EQ(tmp, "?",        "935",   SOC_KIRIN, soc, ?)
-  SOC_EQ(tmp, "Hi3650",     "950",   SOC_HISILICON_3650, soc, 16)
+  SOC_EQ(tmp, "hi3650",     "950",   SOC_HISILICON_3650, soc, 16)
   //SOC_EQ(tmp, "?",        "955",   SOC_KIRIN, soc, ?)
-  SOC_EQ(tmp, "Hi3660",     "960",   SOC_HISILICON_3660, soc, 16)
+  SOC_EQ(tmp, "hi3660",     "960",   SOC_HISILICON_3660, soc, 16)
   //SOC_EQ(tmp, "?",        "960S",  SOC_KIRIN, soc, 16)
-  SOC_EQ(tmp, "Hi3670",     "970",   SOC_HISILICON_3670, soc, 10)
+  SOC_EQ(tmp, "hi3670",     "970",   SOC_HISILICON_3670, soc, 10)
-  SOC_EQ(tmp, "Hi3680",     "980",   SOC_HISILICON_3680, soc,  7)
+  SOC_EQ(tmp, "hi3680",     "980",   SOC_HISILICON_3680, soc,  7)
   //SOC_EQ(tmp, "?",        "985",   SOC_KIRIN, soc,  7)
-  SOC_EQ(tmp, "Hi3690",     "990",   SOC_HISILICON_3690, soc,  7)
+  SOC_EQ(tmp, "hi3690",     "990",   SOC_HISILICON_3690, soc,  7)
   SOC_END
 }
 
@@ -454,6 +459,49 @@ bool match_qualcomm(char* soc_name, struct system_on_chip* soc) {
   SOC_END
 }
 
+// https://linux-sunxi.org/Allwinner_SoC_Family
+bool match_allwinner(char* soc_name, struct system_on_chip* soc) {
+  char* tmp;
+
+  if((tmp = strstr(soc_name, "sun")) == NULL)
+    return false;
+
+  SOC_START
+  // A series 32 bits
+  SOC_EQ(tmp, "sun4i", "A10",   SOC_ALLWINNER_A10,  soc, 55)
+  SOC_EQ(tmp, "sun5i", "A13",   SOC_ALLWINNER_A13,  soc, 55)
+  SOC_EQ(tmp, "sun5i", "A10s",  SOC_ALLWINNER_A10S, soc, 55)
+  SOC_EQ(tmp, "sun7i", "A20",   SOC_ALLWINNER_A20,  soc, 40)
+  SOC_EQ(tmp, "sun8i", "A23",   SOC_ALLWINNER_A23,  soc, 40)
+  SOC_EQ(tmp, "sun6i", "A31",   SOC_ALLWINNER_A31,  soc, 40)
+  SOC_EQ(tmp, "sun6i", "A31s",  SOC_ALLWINNER_A31S, soc, 40)
+  SOC_EQ(tmp, "sun8i", "A33",   SOC_ALLWINNER_A33,  soc, 40)
+  SOC_EQ(tmp, "sun8i", "A40",   SOC_ALLWINNER_A40,  soc, 40)
+  SOC_EQ(tmp, "sun8i", "A50",   SOC_ALLWINNER_A50,  soc, 28)
+  SOC_EQ(tmp, "sun9i", "A80",   SOC_ALLWINNER_A80,  soc, 28)
+  SOC_EQ(tmp, "sun8i", "A83T",  SOC_ALLWINNER_A83T, soc, 28)
+
+  // H series 32 bits
+  SOC_EQ(tmp, "sun8i", "H2+",   SOC_ALLWINNER_HZP,  soc, 40)
+  SOC_EQ(tmp, "sun8i", "H3",    SOC_ALLWINNER_H3,   soc, 40)
+  SOC_EQ(tmp, "sun8i", "H8",    SOC_ALLWINNER_H8,   soc, 28)
+
+  // H series 64 bits
+  SOC_EQ(tmp, "sun50i", "H5",   SOC_ALLWINNER_H5,   soc, 40)
+  SOC_EQ(tmp, "sun50i", "H6",   SOC_ALLWINNER_H6,   soc, 28)
+  SOC_EQ(tmp, "sun50i", "H616", SOC_ALLWINNER_H616, soc, 28)
+
+  // R series 32 bits
+  SOC_EQ(tmp, "sun5i", "R8",    SOC_ALLWINNER_R8,   soc, 55)
+  SOC_EQ(tmp, "sun8i", "R16",   SOC_ALLWINNER_R16,  soc, 40)
+  SOC_EQ(tmp, "sun8i", "R40",   SOC_ALLWINNER_R40,  soc, 40)
+  SOC_EQ(tmp, "sun8i", "R58",   SOC_ALLWINNER_R58,  soc, 28)
+
+  // R series  64 bits
+  SOC_EQ(tmp, "sun50i", "R329", SOC_ALLWINNER_R328, soc, 28)
+  SOC_END
+}
+
 bool match_special(char* soc_name, struct system_on_chip* soc) {
   char* tmp;
 
@@ -490,6 +538,9 @@ struct system_on_chip* parse_soc_from_string(struct system_on_chip* soc) {
   if(match_hisilicon(raw_name, soc))
     return soc;
 
+  if(match_allwinner(raw_name, soc))
+    return soc;
+
   match_broadcom(raw_name, soc);
   return soc;
 }
@@ -595,6 +646,56 @@ struct system_on_chip* guess_soc_raspbery_pi(struct system_on_chip* soc) {
   return soc;
 }
 
+#if defined(__APPLE__) || defined(__MACH__)
+struct system_on_chip* guess_soc_apple(struct system_on_chip* soc) {
+  uint32_t cpu_family = get_sys_info_by_name("hw.cpufamily");
+  uint32_t cpu_subfamily = get_sys_info_by_name("hw.cpusubfamily");
+
+  if(cpu_family == CPUFAMILY_ARM_FIRESTORM_ICESTORM) {
+    // Check M1 version
+    if(cpu_subfamily == CPUSUBFAMILY_ARM_HG) {
+      fill_soc(soc, "M1", SOC_APPLE_M1, 5);
+    }
+    else if(cpu_subfamily == CPUSUBFAMILY_ARM_HS) {
+      fill_soc(soc, "M1 Pro", SOC_APPLE_M1_PRO, 5);
+    }
+    else if(cpu_subfamily == CPUSUBFAMILY_ARM_HC_HD) {
+      // Could be M1 Max or M1 Ultra (2x M1 Max)
+      uint32_t physicalcpu = get_sys_info_by_name("hw.physicalcpu");
+      if(physicalcpu == 20) {
+        fill_soc(soc, "M1 Ultra", SOC_APPLE_M1_ULTRA, 5);
+      }
+      else if(physicalcpu == 10) {
+        fill_soc(soc, "M1 Max", SOC_APPLE_M1_MAX, 5);
+      }
+      else {
+        printBug("Found invalid physical cpu number: %d", physicalcpu);
+        soc->soc_vendor = SOC_VENDOR_UNKNOWN;
+      }
+    }
+    else {
+      printBug("Found invalid cpu_subfamily: 0x%.8X", cpu_subfamily);
+      soc->soc_vendor = SOC_VENDOR_UNKNOWN;
+    }
+  }
+  else if(cpu_family == CPUFAMILY_ARM_AVALANCHE_BLIZZARD) {
+    // Check M2 version
+    if(cpu_subfamily == CPUSUBFAMILY_ARM_HG) {
+      fill_soc(soc, "M2", SOC_APPLE_M2, 5);
+    }
+    else {
+      printBug("Found invalid cpu_subfamily: 0x%.8X", cpu_subfamily);
+      soc->soc_vendor = SOC_VENDOR_UNKNOWN;
+    }
+  }
+  else {
+    printBug("Found invalid cpu_family: 0x%.8X", cpu_family);
+    soc->soc_vendor = SOC_VENDOR_UNKNOWN;
+  }
+  return soc;
+}
+#endif
+
 struct system_on_chip* get_soc() {
   struct system_on_chip* soc = emalloc(sizeof(struct system_on_chip));
   soc->raw_name = NULL;
@@ -628,7 +729,13 @@ struct system_on_chip* get_soc() {
 #endif // ifdef __ANDROID__
   }
 #elif defined __APPLE__ || __MACH__
-    fill_soc(soc, "M1", SOC_APPLE_M1, 5);
+  soc = guess_soc_apple(soc);
+  if(soc->soc_vendor == SOC_VENDOR_UNKNOWN) {
+    printWarn("SoC detection failed using cpu_subfamily");
+  }
+  else {
+    return soc;
+  }
 #endif // ifdef __linux__
 
   if(soc->raw_name == NULL) {

src/arm/soc.h

@@ -13,7 +13,8 @@ enum {
   SOC_VENDOR_EXYNOS,
   SOC_VENDOR_KIRIN,
   SOC_VENDOR_BROADCOM,
-  SOC_VENDOR_APPLE
+  SOC_VENDOR_APPLE,
+  SOC_VENDOR_ALLWINNER
 };
 
 struct system_on_chip {

src/arm/socs.h

@@ -253,7 +253,35 @@ enum {
   SOC_SNAPD_SM8250_AB,
   SOC_SNAPD_SM8350,
   // APPLE
-  SOC_APPLE_M1
+  SOC_APPLE_M1,
+  SOC_APPLE_M1_PRO,
+  SOC_APPLE_M1_MAX,
+  SOC_APPLE_M1_ULTRA,
+  SOC_APPLE_M2,
+  // ALLWINNER
+  SOC_ALLWINNER_A10,
+  SOC_ALLWINNER_A13,
+  SOC_ALLWINNER_A10S,
+  SOC_ALLWINNER_A20,
+  SOC_ALLWINNER_A23,
+  SOC_ALLWINNER_A31,
+  SOC_ALLWINNER_A31S,
+  SOC_ALLWINNER_A33,
+  SOC_ALLWINNER_A40,
+  SOC_ALLWINNER_A50,
+  SOC_ALLWINNER_A80,
+  SOC_ALLWINNER_A83T,
+  SOC_ALLWINNER_HZP,
+  SOC_ALLWINNER_H3,
+  SOC_ALLWINNER_H8,
+  SOC_ALLWINNER_H5,
+  SOC_ALLWINNER_H6,
+  SOC_ALLWINNER_H616,
+  SOC_ALLWINNER_R8,
+  SOC_ALLWINNER_R16,
+  SOC_ALLWINNER_R40,
+  SOC_ALLWINNER_R58,
+  SOC_ALLWINNER_R328
 };
 
 inline static VENDOR get_soc_vendor_from_soc(SOC soc) {
@@ -262,7 +290,8 @@ inline static VENDOR get_soc_vendor_from_soc(SOC soc) {
   else if(soc >= SOC_EXYNOS_3475 && soc <= SOC_EXYNOS_880) return SOC_VENDOR_EXYNOS;
   else if(soc >= SOC_MTK_MT6893 && soc <= SOC_MTK_MT8783) return SOC_VENDOR_MEDIATEK;
   else if(soc >= SOC_SNAPD_QSD8650 && soc <= SOC_SNAPD_SM8350) return SOC_VENDOR_SNAPDRAGON;
-  else if(soc >= SOC_APPLE_M1 && soc <= SOC_APPLE_M1) return SOC_VENDOR_APPLE;
+  else if(soc >= SOC_APPLE_M1 && soc <= SOC_APPLE_M2) return SOC_VENDOR_APPLE;
+  else if(soc >= SOC_ALLWINNER_A10 && soc <= SOC_ALLWINNER_R328) return SOC_VENDOR_ALLWINNER;
   return SOC_VENDOR_UNKNOWN;
 }
 

src/arm/sysctl.h

@@ -1,6 +1,36 @@
 #ifndef __SYSCTL__
 #define __SYSCTL__
 
+// From Linux kernel: arch/arm64/include/asm/cputype.h
+#define MIDR_APPLE_M1_ICESTORM  0x610F0220
+#define MIDR_APPLE_M1_FIRESTORM 0x610F0230
+// Kernel does not include those, so I just assume that
+// APPLE_CPU_PART_M2_BLIZZARD=0x30,M2_AVALANCHE=0x31
+#define MIDR_APPLE_M2_BLIZZARD  0x610F0300
+#define MIDR_APPLE_M2_AVALANCHE 0x610F0310
+
+// M1 / A14
+#ifndef CPUFAMILY_ARM_FIRESTORM_ICESTORM
+  #define CPUFAMILY_ARM_FIRESTORM_ICESTORM 0x1B588BB3
+#endif
+// M2 / A15
+#ifndef CPUFAMILY_ARM_AVALANCHE_BLIZZARD
+  #define CPUFAMILY_ARM_AVALANCHE_BLIZZARD 0xDA33D83D
+#endif
+
+// For detecting different M1 types
+// NOTE: Could also be achieved detecting different
+// MIDR values (e.g., APPLE_CPU_PART_M1_ICESTORM_PRO)
+#ifndef CPUSUBFAMILY_ARM_HG
+  #define CPUSUBFAMILY_ARM_HG 2
+#endif
+#ifndef CPUSUBFAMILY_ARM_HS
+  #define CPUSUBFAMILY_ARM_HS 4
+#endif
+#ifndef CPUSUBFAMILY_ARM_HC_HD
+  #define CPUSUBFAMILY_ARM_HC_HD 5
+#endif
+
 uint32_t get_sys_info_by_name(char* name);
 
 #endif

src/arm/uarch.c

@@ -33,6 +33,7 @@ enum {
   ISA_ARMv8_2_A,
   ISA_ARMv8_3_A,
   ISA_ARMv8_4_A,
+  ISA_ARMv8_5_A
 };
 
 enum {
@@ -95,6 +96,8 @@ enum {
   UARCH_THUNDER,    // Apple A13 processor (little cores).
   UARCH_ICESTORM,   // Apple M1 processor (little cores).
   UARCH_FIRESTORM,  // Apple M1 processor (big cores).
+  UARCH_BLIZZARD,   // Apple M2 processor (little cores).
+  UARCH_AVALANCHE,  // Apple M2 processor (big cores).
   // CAVIUM
   UARCH_THUNDERX,   // Cavium ThunderX
   UARCH_THUNDERX2,  //  Cavium ThunderX2 (originally Broadcom Vulkan).
@@ -103,7 +106,9 @@ enum {
   UARCH_BRAHMA_B15,
   UARCH_BRAHMA_B53,
   UARCH_XGENE,        // Applied Micro X-Gene.
-  UARCH_TAISHAN_V110  // HiSilicon TaiShan v110 (Huawei Kunpeng 920 series processors).
+  UARCH_TAISHAN_V110, // HiSilicon TaiShan v110 (Huawei Kunpeng 920 series processors).
+  // PHYTIUM
+  UARCH_XIAOMI,       // Not to be confused with Xiaomi Inc
 };
 
 static const ISA isas_uarch[] = {
@@ -153,9 +158,12 @@ static const ISA isas_uarch[] = {
   [UARCH_EXYNOS_M3]    = ISA_ARMv8_A,
   [UARCH_EXYNOS_M4]    = ISA_ARMv8_2_A,
   [UARCH_EXYNOS_M5]    = ISA_ARMv8_2_A,
-  [UARCH_ICESTORM]     = ISA_ARMv8_4_A,
+  [UARCH_ICESTORM]     = ISA_ARMv8_5_A, // https://github.com/llvm/llvm-project/blob/main/llvm/include/llvm/Support/AArch64TargetParser.def
-  [UARCH_FIRESTORM]    = ISA_ARMv8_4_A,
+  [UARCH_FIRESTORM]    = ISA_ARMv8_5_A,
+  [UARCH_BLIZZARD]     = ISA_ARMv8_5_A, // Not confirmed
+  [UARCH_AVALANCHE]    = ISA_ARMv8_5_A,
   [UARCH_PJ4]          = ISA_ARMv7_A,
+  [UARCH_XIAOMI]       = ISA_ARMv8_A,
 };
 
 static char* isas_string[] = {
@@ -169,7 +177,8 @@ static char* isas_string[] = {
   [ISA_ARMv8_1_A] = "ARMv8.1",
   [ISA_ARMv8_2_A] = "ARMv8.2",
   [ISA_ARMv8_3_A] = "ARMv8.3",
-  [ISA_ARMv8_4_A] = "ARMv8.4"
+  [ISA_ARMv8_4_A] = "ARMv8.4",
+  [ISA_ARMv8_5_A] = "ARMv8.5"
 };
 
 #define UARCH_START if (false) {}
@@ -289,8 +298,13 @@ struct uarch* get_uarch_from_midr(uint32_t midr, struct cpuInfo* cpu) {
   CHECK_UARCH(arch, cpu, 'S', 0x003, 1,  NA, "Exynos M4",             UARCH_EXYNOS_M4,    CPU_VENDOR_SAMSUNG)   // Exynos 9820
   CHECK_UARCH(arch, cpu, 'S', 0x004, 1,  NA, "Exynos M5",             UARCH_EXYNOS_M5,    CPU_VENDOR_SAMSUNG)   // Exynos 9820 (this one looks wrong at uarch.c ...)
 
+  CHECK_UARCH(arch, cpu, 'p', 0x663, 1,  NA, "Xiaomi",                UARCH_XIAOMI,       CPU_VENDOR_PHYTIUM)   // From a fellow contributor (https://github.com/Dr-Noob/cpufetch/issues/125)
+                                                                                                                // Also interesting: https://en.wikipedia.org/wiki/FeiTeng_(processor)
+
   CHECK_UARCH(arch, cpu, 'a', 0x022, NA, NA, "Icestorm",              UARCH_ICESTORM,     CPU_VENDOR_APPLE)
   CHECK_UARCH(arch, cpu, 'a', 0x023, NA, NA, "Firestorm",             UARCH_FIRESTORM,    CPU_VENDOR_APPLE)
+  CHECK_UARCH(arch, cpu, 'a', 0x030, NA, NA, "Blizzard",              UARCH_BLIZZARD,     CPU_VENDOR_APPLE)
+  CHECK_UARCH(arch, cpu, 'a', 0x031, NA, NA, "Avalanche",             UARCH_AVALANCHE,    CPU_VENDOR_APPLE)
 
   CHECK_UARCH(arch, cpu, 'V', 0x581, NA, NA, "PJ4",                   UARCH_PJ4,          CPU_VENDOR_MARVELL)
   CHECK_UARCH(arch, cpu, 'V', 0x584, NA, NA, "PJ4B-MP",               UARCH_PJ4,          CPU_VENDOR_MARVELL)

src/common/ascii.h

@@ -218,6 +218,24 @@ $C1    kMMMMMMMMMMMMMMMMMMMMMMd    \
 $C1     'KMMMMMMMWXXWMMMMMMMk.     \
 $C1       \"cooc\"*    \"*coo'\"       "
 
+#define ASCII_ALLWINNER \
+"$C1                                               \
+$C1                #################              \
+$C1          .########             #####    ####  \
+$C1       ######                        #######   \
+$C1    #####.    ##             ..##     ####.    \
+$C1  .####      ####          #####     ####      \
+$C1 ####       ## ###          ###.   #####  .    \
+$C1####       ##   ## ####   .###### ####*   .    \
+$C1###       ##  ##.###  ## #### .######          \
+$C1###      #.##     ###  #####   #####    .      \
+$C1###     ###        ### .###     ###    .       \
+$C1 #### ###          ####             #.         \
+$C1   ####                          #*            \
+$C1      #####                 ##.                \
+$C1            ###########.                       \
+$C1                                               "
+
 // --------------------- LONG LOGOS ------------------------- //
 #define ASCII_AMD_L \
 "$C1                                                              \
@@ -317,7 +335,9 @@ asciiL logo_kirin       = { ASCII_KIRIN,       53, 12, false, {C_FG_RED},
 asciiL logo_broadcom    = { ASCII_BROADCOM,    44, 19, false, {C_FG_WHITE, C_FG_RED},             {C_FG_WHITE,   C_FG_RED}     };
 asciiL logo_arm         = { ASCII_ARM,         42,  5, false, {C_FG_CYAN},                        {C_FG_WHITE,   C_FG_CYAN}    };
 asciiL logo_ibm         = { ASCII_IBM,         42,  9, false, {C_FG_CYAN, C_FG_WHITE},            {C_FG_CYAN,    C_FG_WHITE}   };
-asciiL logo_apple       = { ASCII_APPLE,       32, 17, false, {C_FG_WHITE},                       {C_FG_B_BLACK, C_FG_B_WHITE} };
+asciiL logo_apple       = { ASCII_APPLE,       32, 17, false, {C_FG_WHITE},                       {C_FG_CYAN,    C_FG_B_WHITE} };
+asciiL logo_allwinner   = { ASCII_ALLWINNER,   47, 16, false, {C_FG_CYAN},                        {C_FG_B_BLACK, C_FG_B_CYAN } };
+
 // Long variants          | ----------------------------------------------------------------------------------------------------|
 asciiL logo_amd_l       = { ASCII_AMD_L,       62, 19, true,  {C_BG_WHITE, C_BG_GREEN},           {C_FG_WHITE, C_FG_GREEN}     };
 asciiL logo_intel_l     = { ASCII_INTEL_L,     62, 19, true,  {C_BG_CYAN, C_BG_WHITE},            {C_FG_CYAN,  C_FG_WHITE}     };

src/common/cpu.h

@@ -19,6 +19,7 @@ enum {
   CPU_VENDOR_HUAWUEI,
   CPU_VENDOR_SAMSUNG,
   CPU_VENDOR_MARVELL,
+  CPU_VENDOR_PHYTIUM,
 // OTHERS
   CPU_VENDOR_UNKNOWN,
   CPU_VENDOR_INVALID
@@ -34,6 +35,12 @@ enum {
   HV_VENDOR_INVALID
 };
 
+enum {
+  CORE_TYPE_EFFICIENCY,
+  CORE_TYPE_PERFORMANCE,
+  CORE_TYPE_UNKNOWN
+};
+
 #define UNKNOWN_DATA -1
 #define CPU_NAME_MAX_LENGTH 64
 
@@ -77,6 +84,7 @@ struct topology {
   uint32_t smt_supported; // Number of SMT that CPU supports (equal to smt_available if SMT is enabled)
 #ifdef ARCH_X86
   uint32_t smt_available; // Number of SMT that is currently enabled
+  int32_t total_cores_module; // Total cores in the current module (only makes sense in hybrid archs, like ADL)
   struct apic* apic;
 #endif
 #endif
@@ -130,6 +138,10 @@ struct cpuInfo {
   uint32_t maxExtendedLevels;
   // Topology Extensions (AMD only)
   bool topology_extensions;
+  // Hybrid Flag (Intel only)
+  bool hybrid_flag;
+  // Core Type (P/E)
+  uint32_t core_type;
 #elif ARCH_PPC
   uint32_t pvr;
 #elif ARCH_ARM
@@ -139,11 +151,18 @@ struct cpuInfo {
 
 #ifdef ARCH_ARM
   struct system_on_chip* soc;
+#endif
+
+#if defined(ARCH_X86) || defined(ARCH_ARM)
   // If SoC contains more than one CPU and they
   // are different, the others will be stored in
   // the next_cpu field
   struct cpuInfo* next_cpu;
   uint8_t num_cpus;
+#ifdef ARCH_X86
+  // The index of the first core in the module
+  uint32_t first_core_id;
+#endif
 #endif
 };
 

src/common/global.c

@@ -60,7 +60,7 @@ void printBug(const char *fmt, ...) {
 #if defined(ARCH_X86) || defined(ARCH_PPC)
   fprintf(stderr, "Please, create a new issue with this error message, the output of 'cpufetch' and 'cpufetch --debug' on https://github.com/Dr-Noob/cpufetch/issues\n");
 #elif ARCH_ARM
-  fprintf(stderr, "Please, create a new issue with this error message, your smartphone/computer model, the output of 'cpufetch' and 'cpufetch --debug' on https://github.com/Dr-Noob/cpufetch/issues\n");
+  fprintf(stderr, "Please, create a new issue with this error message, your smartphone/computer model, the output of 'cpufetch --verbose' and 'cpufetch --debug' on https://github.com/Dr-Noob/cpufetch/issues\n");
 #endif
 }
 
@@ -111,3 +111,15 @@ void* ecalloc(size_t nmemb, size_t size) {
 
   return ptr;
 }
+
+void* erealloc(void *ptr, size_t size) {
+  void* newptr = realloc(ptr, size);
+
+  if(newptr == NULL) {
+    printErr("realloc failed: %s", strerror(errno));
+    exit(1);
+  }
+
+  return newptr;
+}
+

src/common/global.h

@@ -15,5 +15,6 @@ int max(int a, int b);
 char *strremove(char *str, const char *sub);
 void* emalloc(size_t size);
 void* ecalloc(size_t nmemb, size_t size);
+void* erealloc(void *ptr, size_t size);
 
 #endif

src/common/main.c

@@ -33,7 +33,7 @@
   static const char* OS_STR = "Unknown OS";
 #endif
 
-static const char* VERSION = "1.01";
+static const char* VERSION = "1.02";
 
 void print_help(char *argv[]) {
   const char **t = args_str;

src/common/printer.c

@@ -44,6 +44,8 @@ enum {
   ATTRIBUTE_NAME,
 #elif ARCH_ARM
   ATTRIBUTE_SOC,
+#endif
+#if defined(ARCH_X86) || defined(ARCH_ARM)
   ATTRIBUTE_CPU_NUM,
 #endif
   ATTRIBUTE_HYPERVISOR,
@@ -75,6 +77,8 @@ static const char* ATTRIBUTE_FIELDS [] = {
   "Part Number:",
 #elif ARCH_ARM
   "SoC:",
+#endif
+#if defined(ARCH_X86) || defined(ARCH_ARM)
   "",
 #endif
   "Hypervisor:",
@@ -106,6 +110,8 @@ static const char* ATTRIBUTE_FIELDS_SHORT [] = {
   "P/N:",
 #elif ARCH_ARM
   "SoC:",
+#endif
+#if defined(ARCH_X86) || defined(ARCH_ARM)
   "",
 #endif
   "Hypervisor:",
@@ -353,6 +359,8 @@ void choose_ascii_art(struct ascii* art, struct color** cs, struct terminal* ter
     art->art = &logo_broadcom;
   else if(art->vendor == SOC_VENDOR_APPLE)
     art->art = &logo_apple;
+  else if(art->vendor == SOC_VENDOR_ALLWINNER)
+    art->art = &logo_allwinner;
   else {
     art->art = choose_ascii_art_aux(&logo_arm_l, &logo_arm, term, lf);
   }
@@ -422,11 +430,12 @@ uint32_t longest_field_length(struct ascii* art, int la) {
 }
 
 #if defined(ARCH_X86) || defined(ARCH_PPC)
-void print_ascii_generic(struct ascii* art, uint32_t la, int32_t termw, const char** attribute_fields) {
+void print_ascii_generic(struct ascii* art, uint32_t la, int32_t termw, const char** attribute_fields, bool hybrid_architecture) {
   struct ascii_logo* logo = art->art;
   int attr_to_print = 0;
   int attr_type;
   char* attr_value;
+  int32_t beg_space;
   int32_t space_right;
   int32_t space_up = ((int)logo->height - (int)art->n_attributes_set)/2;
   int32_t space_down = (int)logo->height - (int)art->n_attributes_set - (int)space_up;
@@ -437,6 +446,7 @@ void print_ascii_generic(struct ascii* art, uint32_t la, int32_t termw, const ch
   lbuf->buf = emalloc(sizeof(char) * LINE_BUFFER_SIZE);
   lbuf->pos = 0;
   lbuf->chars = 0;
+  bool add_space = false;
 
   printf("\n");
   for(int32_t n=0; n < iters; n++) {
@@ -471,9 +481,24 @@ void print_ascii_generic(struct ascii* art, uint32_t la, int32_t termw, const ch
       attr_value = art->attributes[attr_to_print]->value;
       attr_to_print++;
 
-      space_right = 1 + (la - strlen(attribute_fields[attr_type]));
+      if(attr_type == ATTRIBUTE_L3) {
-      printOut(lbuf, strlen(attribute_fields[attr_type]) + space_right + strlen(attr_value),
+        add_space = false;
-               "%s%s%s%*s%s%s%s", logo->color_text[0], attribute_fields[attr_type], art->reset, space_right, "", logo->color_text[1], attr_value, art->reset);
+      }
+      if(attr_type == ATTRIBUTE_CPU_NUM) {
+        printOut(lbuf, strlen(attr_value), "%s%s%s", logo->color_text[0], attr_value, art->reset);
+        add_space = true;
+      }
+      else {
+        beg_space = 0;
+        space_right = 2 + 1 + (la - strlen(attribute_fields[attr_type]));
+        if(hybrid_architecture && add_space) {
+          beg_space = 2;
+          space_right -= 2;
+        }
+
+        printOut(lbuf, beg_space + strlen(attribute_fields[attr_type]) + space_right + strlen(attr_value),
+                 "%*s%s%s%s%*s%s%s%s", beg_space, "", logo->color_text[0], attribute_fields[attr_type], art->reset, space_right, "", logo->color_text[1], attr_value, art->reset);
+      }
     }
     printOutLine(lbuf, art, termw);
     printf("\n");
@@ -498,21 +523,20 @@ bool print_cpufetch_x86(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
     return false;
 
   art->new_intel_logo = choose_new_intel_logo(cpu);
-  char* uarch = get_str_uarch(cpu);
-  char* manufacturing_process = get_str_process(cpu);
-  char* sockets = get_str_sockets(cpu->topo);
-  char* max_frequency = get_str_freq(cpu->freq);
-  char* n_cores = get_str_topology(cpu, cpu->topo, false);
-  char* n_cores_dual = get_str_topology(cpu, cpu->topo, true);
-  char* cpu_name = get_str_cpu_name(cpu, fcpuname);
-  char* avx = get_str_avx(cpu);
-  char* fma = get_str_fma(cpu);
 
-  char* l1i = get_str_l1i(cpu->cach);
+  uint32_t socket_num = 1;
-  char* l1d = get_str_l1d(cpu->cach);
+  char* l1i, *l1d, *l2, *l3, *n_cores, *n_cores_dual, *sockets;
-  char* l2 = get_str_l2(cpu->cach);
+  l1i = l1d = l2 = l3 = n_cores = n_cores_dual = sockets = NULL;
-  char* l3 = get_str_l3(cpu->cach);
+
+  char* cpu_name = get_str_cpu_name(cpu, fcpuname);
+  char* uarch = get_str_uarch(cpu);
   char* pp = get_str_peak_performance(cpu->peak_performance);
+  char* manufacturing_process = get_str_process(cpu);
+  bool hybrid_architecture = cpu->next_cpu != NULL;
+
+  if(cpu->cach != NULL) {
+    l3 = get_str_l3(cpu->cach);
+  }
 
   setAttribute(art, ATTRIBUTE_NAME, cpu_name);
   if(cpu->hv->present) {
@@ -520,8 +544,36 @@ bool print_cpufetch_x86(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
   }
   setAttribute(art, ATTRIBUTE_UARCH, uarch);
   setAttribute(art, ATTRIBUTE_TECHNOLOGY, manufacturing_process);
+
+  struct cpuInfo* ptr = cpu;
+  for(int i = 0; i < cpu->num_cpus; ptr = ptr->next_cpu, i++) {
+    char* max_frequency = get_str_freq(ptr->freq);
+    char* avx = get_str_avx(ptr);
+    char* fma = get_str_fma(ptr);
+    char* cpu_num = emalloc(sizeof(char) * 9);
+
+    if(ptr->topo != NULL) {
+      sockets = get_str_sockets(ptr->topo);
+      n_cores = get_str_topology(ptr, ptr->topo, false);
+      n_cores_dual = get_str_topology(ptr, ptr->topo, true);
+    }
+
+    if(ptr->cach != NULL) {
+      l1i = get_str_l1i(ptr->cach);
+      l1d = get_str_l1d(ptr->cach);
+      l2 = get_str_l2(ptr->cach);
+    }
+
+    if(hybrid_architecture) {
+      if(ptr->core_type == CORE_TYPE_EFFICIENCY) sprintf(cpu_num, "E-cores:");
+      else if(ptr->core_type == CORE_TYPE_PERFORMANCE) sprintf(cpu_num, "P-cores:");
+      else printBug("Found invalid core type!\n");
+
+      setAttribute(art, ATTRIBUTE_CPU_NUM, cpu_num);
+    }
     setAttribute(art, ATTRIBUTE_FREQUENCY, max_frequency);
-  uint32_t socket_num = get_nsockets(cpu->topo);
+    if(ptr->topo != NULL) {
+      socket_num = get_nsockets(ptr->topo);
       if (socket_num > 1) {
         setAttribute(art, ATTRIBUTE_SOCKETS, sockets);
         setAttribute(art, ATTRIBUTE_NCORES, n_cores);
@@ -530,16 +582,17 @@ bool print_cpufetch_x86(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
       else {
         setAttribute(art, ATTRIBUTE_NCORES, n_cores);
       }
+    }
     setAttribute(art, ATTRIBUTE_AVX, avx);
     setAttribute(art, ATTRIBUTE_FMA, fma);
-  setAttribute(art,ATTRIBUTE_L1i,l1i);
+    if(l1i != NULL) setAttribute(art, ATTRIBUTE_L1i, l1i);
-  setAttribute(art,ATTRIBUTE_L1d,l1d);
+    if(l1d != NULL) setAttribute(art, ATTRIBUTE_L1d, l1d);
-  setAttribute(art,ATTRIBUTE_L2,l2);
+    if(l2 != NULL) setAttribute(art, ATTRIBUTE_L2, l2);
-  if(l3 != NULL) {
-    setAttribute(art,ATTRIBUTE_L3,l3);
   }
+  if(l3 != NULL) setAttribute(art, ATTRIBUTE_L3, l3);
   setAttribute(art, ATTRIBUTE_PEAK, pp);
 
+  // Step 3. Print output
   const char** attribute_fields = ATTRIBUTE_FIELDS;
   uint32_t longest_attribute = longest_attribute_length(art, attribute_fields);
   uint32_t longest_field = longest_field_length(art, longest_attribute);
@@ -552,15 +605,12 @@ bool print_cpufetch_x86(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
     longest_attribute = longest_attribute_length(art, attribute_fields);
   }
 
-  print_ascii_generic(art, longest_attribute, term->w, attribute_fields);
+  print_ascii_generic(art, longest_attribute, term->w, attribute_fields, hybrid_architecture);
 
   free(manufacturing_process);
-  free(max_frequency);
   free(sockets);
   free(n_cores);
   free(n_cores_dual);
-  free(avx);
-  free(fma);
   free(l1i);
   free(l1d);
   free(l2);
@@ -571,8 +621,8 @@ bool print_cpufetch_x86(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
   free(art);
 
   if(cs != NULL) free_colors_struct(cs);
-  free_cache_struct(cpu->cach);
+  if(cpu->cach != NULL) free_cache_struct(cpu->cach);
-  free_topo_struct(cpu->topo);
+  if(cpu->topo != NULL) free_topo_struct(cpu->topo);
   free_freq_struct(cpu->freq);
   free_cpuinfo_struct(cpu);
 
@@ -586,6 +636,7 @@ bool print_cpufetch_ppc(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
   if(art == NULL)
     return false;
 
+  // Step 1. Retrieve attributes
   char* uarch = get_str_uarch(cpu);
   char* manufacturing_process = get_str_process(cpu);
   char* sockets = get_str_sockets(cpu->topo);
@@ -601,6 +652,7 @@ bool print_cpufetch_ppc(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
   char* l3 = get_str_l3(cpu->cach);
   char* pp = get_str_peak_performance(cpu->peak_performance);
 
+  // Step 2. Set attributes
   if(cpu_name != NULL) {
     setAttribute(art,ATTRIBUTE_NAME,cpu_name);
   }
@@ -625,6 +677,7 @@ bool print_cpufetch_ppc(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
   }
   setAttribute(art,ATTRIBUTE_PEAK,pp);
 
+  // Step 3. Print output
   const char** attribute_fields = ATTRIBUTE_FIELDS;
   uint32_t longest_attribute = longest_attribute_length(art, attribute_fields);
   uint32_t longest_field = longest_field_length(art, longest_attribute);

src/common/udev.c

@@ -54,13 +54,18 @@ char* read_file(char* path, int* len) {
   //File exists, read it
   int bytes_read = 0;
   int offset = 0;
-  int block = 128;
+  int block = 1024;
-  char* buf = emalloc(sizeof(char)*DEFAULT_FILE_SIZE);
+  int buf_size = block * 4;
-  memset(buf, 0, sizeof(char)*DEFAULT_FILE_SIZE);
+  char* buf = emalloc(sizeof(char) * buf_size);
 
   while ((bytes_read = read(fd, buf+offset, block)) > 0) {
     offset += bytes_read;
+    if(offset + block > buf_size) {
+      buf = erealloc(buf, sizeof(char) * (buf_size + block));
+      buf_size += block;
     }
+  }
+  buf[offset] = '\0';
 
   if (close(fd) == -1) {
     return NULL;
@@ -160,48 +165,85 @@ long get_l3_cache_size(uint32_t core) {
   return get_cache_size_from_file(path);
 }
 
+void add_shared_map(uint32_t** src, int src_idx, uint32_t** dst, int dst_idx, int n) {
+  for(int j=0; j < n; j++) {
+    dst[dst_idx][j] = src[src_idx][j];
+  }
+}
+
+bool maps_equal(uint32_t* map1, uint32_t* map2, int n) {
+  for(int i=0; i < n; i++) {
+    if(map1[i] != map2[i]) return false;
+  }
+  return true;
+}
+
 int get_num_caches_from_files(char** paths, int num_paths) {
-  int SHARED_MAP_MAX_LEN = 8 + 1;
   int filelen;
   char* buf;
-  uint32_t* shared_maps = emalloc(sizeof(uint32_t *) * num_paths);
+  char* tmpbuf;
 
-  // 1. Read cpu_shared_map from every core
+  // 1. Count the number of bitmasks per file
+  if((buf = read_file(paths[0], &filelen)) == NULL) {
+    printWarn("Could not open '%s'", paths[0]);
+    return -1;
+  }
+  int num_bitmasks = 1;
+  for(int i=0; buf[i]; i++) {
+    num_bitmasks += (buf[i] == ',');
+  }
+
+  // 2. Read cpu_shared_map from every core
+  uint32_t** shared_maps = emalloc(sizeof(uint32_t *) * num_paths);
   for(int i=0; i < num_paths; i++) {
+    shared_maps[i] = emalloc(sizeof(uint32_t) * num_bitmasks);
+
     if((buf = read_file(paths[i], &filelen)) == NULL) {
       printWarn("Could not open '%s'", paths[i]);
       return -1;
     }
 
-    if(filelen > SHARED_MAP_MAX_LEN) {
+    for(int j=0; j < num_bitmasks; j++) {
-      printBug("Shared map length is %d while the max is be %d", filelen, SHARED_MAP_MAX_LEN);
-      return -1;
-    }
-
       char* end;
+      tmpbuf = emalloc(sizeof(char) * (strlen(buf) + 1));
+      char* commaend = strstr(buf, ",");
+      if(commaend == NULL) {
+        strcpy(tmpbuf, buf);
+      }
+      else {
+        strncpy(tmpbuf, buf, commaend-buf);
+      }
       errno = 0;
-    long ret = strtol(buf, &end, 16);
+      long ret = strtol(tmpbuf, &end, 16);
       if(errno != 0) {
-      printBug("strtol: %s", strerror(errno));
+        printf("strtol: %s", strerror(errno));
         free(buf);
         return -1;
       }
 
-    shared_maps[i] = (uint32_t) ret;
+      shared_maps[i][j] = (uint32_t) ret;
+      buf = commaend + 1;
+      free(tmpbuf);
+    }
   }
 
   // 2. Count number of different masks; this is the number of caches
   int num_caches = 0;
   bool found = false;
-  uint32_t* unique_shared_maps = emalloc(sizeof(uint32_t *) * num_paths);
+  uint32_t** unique_shared_maps = emalloc(sizeof(uint32_t *) * num_paths);
-  for(int i=0; i < num_paths; i++) unique_shared_maps[i] = 0;
+  for(int i=0; i < num_paths; i++) {
+    unique_shared_maps[i] = emalloc(sizeof(uint32_t) * num_bitmasks);
+    for(int j=0; j < num_bitmasks; j++) {
+      unique_shared_maps[i][j] = 0;
+    }
+  }
 
   for(int i=0; i < num_paths; i++) {
     for(int j=0; j < num_paths && !found; j++) {
-      if(shared_maps[i] == unique_shared_maps[j]) found = true;
+      if(maps_equal(shared_maps[i], unique_shared_maps[j], num_bitmasks)) found = true;
     }
     if(!found) {
-      unique_shared_maps[num_caches] = shared_maps[i];
+      add_shared_map(shared_maps, i, unique_shared_maps, num_caches, num_bitmasks);
       num_caches++;
     }
     found = false;

src/common/udev.h

@@ -27,7 +27,6 @@
 
 #define _PATH_FREQUENCY_MAX_LEN 100
 #define _PATH_CACHE_MAX_LEN     200
-#define DEFAULT_FILE_SIZE       4096
 
 char* read_file(char* path, int* len);
 long get_max_freq_from_file(uint32_t core);

src/ppc/ppc.c

@@ -181,9 +181,6 @@ struct cpuInfo* get_cpu_info() {
   feat->altivec = has_altivec(cpu->arch);
   cpu->peak_performance = get_peak_performance(cpu, cpu->topo, get_freq(cpu->freq));
 
-  if(cpu->cach == NULL || cpu->topo == NULL) {
-    return NULL;
-  }
   return cpu;
 }
 

src/ppc/ppc.h

@@ -1,5 +1,5 @@
-#ifndef __POWERPC__
+#ifndef __CPUFETCH_POWERPC__
-#define __POWERPC__
+#define __CPUFETCH_POWERPC__
 
 #include "../common/cpu.h"
 

src/x86/apic.c

@@ -102,6 +102,59 @@ bool bind_to_cpu(int cpu_id) {
 }
 #endif
 
+int get_total_cores_module(int total_cores, int module) {
+  int total_modules = 2;
+  int32_t current_module_idx = -1;
+  bool end = false;
+  int32_t* core_types = emalloc(sizeof(uint32_t) * total_modules);
+  for(int i=0; i < total_modules; i++) core_types[i] = -1;
+  int cores_in_module = 0;
+  int i = 0;
+
+  // Get the original mask to restore it later
+  cpu_set_t original_mask;
+  if(sched_getaffinity(0, sizeof(original_mask), &original_mask) == -1) {
+    printWarn("sched_getaffinity: %s", strerror(errno));
+    return false;
+  }
+
+  while(!end) {
+    if(!bind_to_cpu(i)) {
+      return -1;
+    }
+    uint32_t eax = 0x0000001A;
+    uint32_t ebx = 0;
+    uint32_t ecx = 0;
+    uint32_t edx = 0;
+    cpuid(&eax, &ebx, &ecx, &edx);
+    int32_t core_type = eax >> 24 & 0xFF;
+    bool found = false;
+
+    for(int j=0; j < total_modules && !found; j++) {
+      if(core_types[j] == core_type) found = true;
+    }
+    if(!found) {
+      current_module_idx++;
+      core_types[current_module_idx] = core_type;
+    }
+    if(current_module_idx == module) {
+      cores_in_module++;
+      if(i+1 == total_cores) end = true;
+    }
+    else if(cores_in_module > 0) end = true;
+    i++;
+  }
+
+  // Reset the original affinity
+  if (sched_setaffinity (0, sizeof(original_mask), &original_mask) == -1) {
+    printWarn("sched_setaffinity: %s", strerror(errno));
+    return false;
+  }
+
+  //printf("Module %d has %d cores\n", module, cores_in_module);
+  return cores_in_module;
+}
+
 bool fill_topo_masks_apic(struct topology* topo) {
   uint32_t eax = 0x00000001;
   uint32_t ebx = 0;
@@ -197,14 +250,14 @@ uint32_t max_apic_id_size(uint32_t** cache_id_apic, struct topology* topo) {
   uint32_t max = 0;
 
   for(int i=0; i < topo->cach->max_cache_level; i++) {
-    for(int j=0; j < topo->total_cores; j++) {
+    for(int j=0; j < topo->total_cores_module; j++) {
       if(cache_id_apic[j][i] > max) max = cache_id_apic[j][i];
     }
   }
 
   max++;
-  if(max > (uint32_t) topo->total_cores) return max;
+  if(max > (uint32_t) topo->total_cores_module) return max;
-  return topo->total_cores;
+  return topo->total_cores_module;
 }
 
 bool build_topo_from_apic(uint32_t* apic_pkg, uint32_t* apic_smt, uint32_t** cache_id_apic, struct topology* topo) {
@@ -219,18 +272,18 @@ bool build_topo_from_apic(uint32_t* apic_pkg, uint32_t* apic_smt, uint32_t** cac
   memset(apic_id, 0, sizeof(uint32_t) * size);
 
   // System topology
-  for(int i=0; i < topo->total_cores; i++) {
+  for(int i=0; i < topo->total_cores_module; i++) {
     sockets[apic_pkg[i]] = 1;
     smt[apic_smt[i]] = 1;
   }
-  for(int i=0; i < topo->total_cores; i++) {
+  for(int i=0; i < topo->total_cores_module; i++) {
     if(sockets[i] != 0)
       topo->sockets++;
     if(smt[i] != 0)
       topo->smt_available++;
   }
 
-  topo->logical_cores = topo->total_cores / topo->sockets;
+  topo->logical_cores = topo->total_cores_module / topo->sockets;
   topo->physical_cores = topo->logical_cores / topo->smt_available;
 
   // Cache topology
@@ -238,7 +291,7 @@ bool build_topo_from_apic(uint32_t* apic_pkg, uint32_t* apic_smt, uint32_t** cac
     num_caches = 0;
     memset(apic_id, 0, sizeof(uint32_t) * size);
 
-    for(int c=0; c < topo->total_cores; c++) {
+    for(int c=0; c < topo->total_cores_module; c++) {
       apic_id[cache_id_apic[c][i]]++;
     }
     for(uint32_t c=0; c < size; c++) {
@@ -297,7 +350,7 @@ void add_apic_to_array(uint32_t apic, uint32_t* apic_ids, int n) {
   }
 }
 
-bool fill_apic_ids(uint32_t* apic_ids, int n, bool x2apic_id) {
+bool fill_apic_ids(uint32_t* apic_ids, int first_core, int n, bool x2apic_id) {
 #ifdef __APPLE__
   // macOS extremely dirty approach...
   printf("cpufetch is computing APIC IDs, please wait...\n");
@@ -322,12 +375,12 @@ bool fill_apic_ids(uint32_t* apic_ids, int n, bool x2apic_id) {
   }
   #endif
 
-  for(int i=0; i < n; i++) {
+  for(int i=first_core; i < first_core+n; i++) {
     if(!bind_to_cpu(i)) {
       printErr("Failed binding the process to CPU %d", i);
       return false;
     }
-    apic_ids[i] = get_apic_id(x2apic_id);
+    apic_ids[i-first_core] = get_apic_id(x2apic_id);
   }
 
   #ifdef __linux__
@@ -344,12 +397,12 @@ bool fill_apic_ids(uint32_t* apic_ids, int n, bool x2apic_id) {
 
 bool get_topology_from_apic(struct cpuInfo* cpu, struct topology* topo) {
   uint32_t apic_id;
-  uint32_t* apic_ids = emalloc(sizeof(uint32_t) * topo->total_cores);
+  uint32_t* apic_ids = emalloc(sizeof(uint32_t) * topo->total_cores_module);
-  uint32_t* apic_pkg = emalloc(sizeof(uint32_t) * topo->total_cores);
+  uint32_t* apic_pkg = emalloc(sizeof(uint32_t) * topo->total_cores_module);
-  uint32_t* apic_core = emalloc(sizeof(uint32_t) * topo->total_cores);
+  uint32_t* apic_core = emalloc(sizeof(uint32_t) * topo->total_cores_module);
-  uint32_t* apic_smt = emalloc(sizeof(uint32_t) * topo->total_cores);
+  uint32_t* apic_smt = emalloc(sizeof(uint32_t) * topo->total_cores_module);
-  uint32_t** cache_smt_id_apic = emalloc(sizeof(uint32_t*) * topo->total_cores);
+  uint32_t** cache_smt_id_apic = emalloc(sizeof(uint32_t*) * topo->total_cores_module);
-  uint32_t** cache_id_apic = emalloc(sizeof(uint32_t*) * topo->total_cores);
+  uint32_t** cache_id_apic = emalloc(sizeof(uint32_t*) * topo->total_cores_module);
   bool x2apic_id;
 
   if(cpu->maxLevels >= 0x0000000B) {
@@ -367,7 +420,7 @@ bool get_topology_from_apic(struct cpuInfo* cpu, struct topology* topo) {
     x2apic_id = false;
   }
 
-  for(int i=0; i < topo->total_cores; i++) {
+  for(int i=0; i < topo->total_cores_module; i++) {
     cache_smt_id_apic[i] = emalloc(sizeof(uint32_t) * (topo->cach->max_cache_level));
     cache_id_apic[i] = emalloc(sizeof(uint32_t) * (topo->cach->max_cache_level));
   }
@@ -385,10 +438,10 @@ bool get_topology_from_apic(struct cpuInfo* cpu, struct topology* topo) {
 
   get_cache_topology_from_apic(topo);
 
-  if(!fill_apic_ids(apic_ids, topo->total_cores, x2apic_id))
+  if(!fill_apic_ids(apic_ids, cpu->first_core_id, topo->total_cores_module, x2apic_id))
     return false;
 
-  for(int i=0; i < topo->total_cores; i++) {
+  for(int i=0; i < topo->total_cores_module; i++) {
     apic_id = apic_ids[i];
 
     apic_pkg[i] = (apic_id & topo->apic->pkg_mask) >> topo->apic->pkg_mask_shift;
@@ -404,20 +457,19 @@ bool get_topology_from_apic(struct cpuInfo* cpu, struct topology* topo) {
   /* DEBUG
   for(int i=0; i < topo->cach->max_cache_level; i++) {
     printf("[CACH %1d]", i);
-    for(int j=0; j < topo->total_cores; j++)
+    for(int j=0; j < topo->total_cores_module; j++)
       printf("[%03d]", cache_id_apic[j][i]);
     printf("\n");
   }
-  for(int i=0; i < topo->total_cores; i++)
+  for(int i=0; i < topo->total_cores_module; i++)
     printf("[%2d] 0x%.8X\n", i, apic_pkg[i]);
   printf("\n");
-  for(int i=0; i < topo->total_cores; i++)
+  for(int i=0; i < topo->total_cores_module; i++)
     printf("[%2d] 0x%.8X\n", i, apic_core[i]);
   printf("\n");
-  for(int i=0; i < topo->total_cores; i++)
+  for(int i=0; i < topo->total_cores_module; i++)
     printf("[%2d] 0x%.8X\n", i, apic_smt[i]);*/
 
-
   bool ret = build_topo_from_apic(apic_pkg, apic_smt, cache_id_apic, topo);
 
   // Assumption: If we cant get smt_available, we assume it is equal to smt_supported...
@@ -429,7 +481,7 @@ bool get_topology_from_apic(struct cpuInfo* cpu, struct topology* topo) {
   free(apic_pkg);
   free(apic_core);
   free(apic_smt);
-  for(int i=0; i < topo->total_cores; i++) {
+  for(int i=0; i < topo->total_cores_module; i++) {
     free(cache_smt_id_apic[i]);
     free(cache_id_apic[i]);
   }

src/x86/apic.h

@@ -21,4 +21,6 @@ uint32_t is_smt_enabled_amd(struct topology* topo);
 bool bind_to_cpu(int cpu_id);
 #endif
 
+int get_total_cores_module(int total_cores, int module);
+
 #endif

src/x86/cpuid.c

@@ -179,7 +179,7 @@ struct uarch* get_cpu_uarch(struct cpuInfo* cpu) {
   return get_uarch_from_cpuid(cpu, eax, efamily, family, emodel, model, (int)stepping);
 }
 
-int64_t get_peak_performance(struct cpuInfo* cpu, struct topology* topo, int64_t max_freq, bool accurate_pp) {
+int64_t get_peak_performance(struct cpuInfo* cpu, bool accurate_pp) {
   /*
    * PP = PeakPerformance
    * SP = SinglePrecision
@@ -192,10 +192,17 @@ int64_t get_peak_performance(struct cpuInfo* cpu, struct topology* topo, int64_t
    * 16(If AVX512), 8(If AVX), 4(If SSE) *
    */
 
+  struct cpuInfo* ptr = cpu;
+  int64_t total_flops = 0;
+
+  for(int i=0; i < cpu->num_cpus; ptr = ptr->next_cpu, i++) {
+    struct topology* topo = ptr->topo;
+    int64_t max_freq = get_freq(ptr->freq);
+
     int64_t freq;
   #ifdef __linux__
     if(accurate_pp)
-    freq = measure_frequency(cpu);
+      freq = measure_frequency(ptr);
     else
       freq = max_freq;
   #else
@@ -209,8 +216,8 @@ int64_t get_peak_performance(struct cpuInfo* cpu, struct topology* topo, int64_t
       return -1;
     }
 
-  struct features* feat = cpu->feat;
+    struct features* feat = ptr->feat;
-  int vpus = get_number_of_vpus(cpu);
+    int vpus = get_number_of_vpus(ptr);
     int64_t flops = topo->physical_cores * topo->sockets * (freq*1000000) * vpus;
 
     if(feat->FMA3 || feat->FMA4)
@@ -219,7 +226,7 @@ int64_t get_peak_performance(struct cpuInfo* cpu, struct topology* topo, int64_t
     // Ice Lake has AVX512, but it has 1 VPU for AVX512, while
     // it has 2 for AVX2. If this is a Ice Lake CPU, we are computing
     // the peak performance supposing AVX2, not AVX512
-  if(feat->AVX512 && vpus_are_AVX512(cpu))
+    if(feat->AVX512 && vpus_are_AVX512(ptr))
       flops = flops*16;
     else if(feat->AVX || feat->AVX2)
       flops = flops*8;
@@ -228,10 +235,13 @@ int64_t get_peak_performance(struct cpuInfo* cpu, struct topology* topo, int64_t
 
     // See https://sites.utexas.edu/jdm4372/2018/01/22/a-peculiar-
     // throughput-limitation-on-intels-xeon-phi-x200-knights-landing/
-  if(is_knights_landing(cpu))
+    if(is_knights_landing(ptr))
       flops = flops * 6 / 7;
 
-  return flops;
+    total_flops += flops;
+  }
+
+  return total_flops;
 }
 
 struct hypervisor* get_hp_info(bool hv_present) {
@@ -274,48 +284,19 @@ struct hypervisor* get_hp_info(bool hv_present) {
   return hv;
 }
 
-struct cpuInfo* get_cpu_info() {
+struct features* get_features_info(struct cpuInfo* cpu) {
-  struct cpuInfo* cpu = emalloc(sizeof(struct cpuInfo));
-  struct features* feat = emalloc(sizeof(struct features));
-  cpu->feat = feat;
-
-  bool *ptr = &(feat->AES);
-  for(uint32_t i = 0; i < sizeof(struct features)/sizeof(bool); i++, ptr++) {
-    *ptr = false;
-  }
-
   uint32_t eax = 0;
   uint32_t ebx = 0;
   uint32_t ecx = 0;
   uint32_t edx = 0;
 
-  //Get max cpuid level
+  struct features* feat = emalloc(sizeof(struct features));
-  cpuid(&eax, &ebx, &ecx, &edx);
-  cpu->maxLevels = eax;
 
-  //Fill vendor
+  bool *ptr = &(feat->AES);
-  char name[13];
+  for(uint32_t i = 0; i < sizeof(struct features)/sizeof(bool); i++, ptr++) {
-  memset(name,0,13);
+    *ptr = false;
-  get_name_cpuid(name, ebx, edx, ecx);
-
-  if(strcmp(CPU_VENDOR_INTEL_STRING,name) == 0)
-    cpu->cpu_vendor = CPU_VENDOR_INTEL;
-  else if (strcmp(CPU_VENDOR_AMD_STRING,name) == 0)
-    cpu->cpu_vendor = CPU_VENDOR_AMD;
-  else {
-    cpu->cpu_vendor = CPU_VENDOR_INVALID;
-    printErr("Unknown CPU vendor: %s", name);
-    return NULL;
   }
 
-  //Get max extended level
-  eax = 0x80000000;
-  ebx = 0;
-  ecx = 0;
-  edx = 0;
-  cpuid(&eax, &ebx, &ecx, &edx);
-  cpu->maxExtendedLevels = eax;
-
   //Fill instructions support
   if (cpu->maxLevels >= 0x00000001){
     eax = 0x00000001;
@@ -370,6 +351,116 @@ struct cpuInfo* get_cpu_info() {
     printWarn("Can't read features information from cpuid (needed extended level is 0x%.8X, max is 0x%.8X)", 0x80000001, cpu->maxExtendedLevels);
   }
 
+  return feat;
+}
+
+bool set_cpu_module(int m, int total_modules, int32_t* first_core) {
+  if(total_modules > 1) {
+    // We have a hybrid architecture.
+    // 1. Find the first core from module m
+    int32_t core_id = -1;
+    int32_t currrent_module_idx = -1;
+    int32_t* core_types = emalloc(sizeof(uint32_t) * total_modules);
+    for(int i=0; i < total_modules; i++) core_types[i] = -1;
+    int i = 0;
+
+    while(core_id == -1) {
+      if(!bind_to_cpu(i)) {
+        return false;
+      }
+      uint32_t eax = 0x0000001A;
+      uint32_t ebx = 0;
+      uint32_t ecx = 0;
+      uint32_t edx = 0;
+      cpuid(&eax, &ebx, &ecx, &edx);
+      int32_t core_type = eax >> 24 & 0xFF;
+      bool found = false;
+
+      for(int j=0; j < total_modules && !found; j++) {
+        if(core_types[j] == core_type) found = true;
+      }
+      if(!found) {
+        currrent_module_idx++;
+        core_types[currrent_module_idx] = core_type;
+        if(currrent_module_idx == m) {
+          core_id = i;
+        }
+      }
+
+      i++;
+    }
+
+    *first_core = core_id;
+
+    //printf("Module %d: Core %d\n", m, core_id);
+    // 2. Now bind to that core
+    if(!bind_to_cpu(core_id)) {
+      return false;
+    }
+  }
+
+  return true;
+}
+
+int32_t get_core_type() {
+  uint32_t eax = 0x0000001A;
+  uint32_t ebx = 0;
+  uint32_t ecx = 0;
+  uint32_t edx = 0;
+
+  eax = 0x0000001A;
+  cpuid(&eax, &ebx, &ecx, &edx);
+
+  int32_t type = eax >> 24 & 0xFF;
+  if(type == 0x20) return CORE_TYPE_EFFICIENCY;
+  else if(type == 0x40) return CORE_TYPE_PERFORMANCE;
+  else {
+    printErr("Found invalid core type: 0x%.8X\n", type);
+    return CORE_TYPE_UNKNOWN;
+  }
+}
+
+struct cpuInfo* get_cpu_info() {
+  struct cpuInfo* cpu = emalloc(sizeof(struct cpuInfo));
+  cpu->peak_performance = -1;
+  cpu->next_cpu = NULL;
+  cpu->topo = NULL;
+  cpu->cach = NULL;
+  cpu->feat = NULL;
+
+  uint32_t modules = 1;
+  uint32_t eax = 0;
+  uint32_t ebx = 0;
+  uint32_t ecx = 0;
+  uint32_t edx = 0;
+
+  //Get max cpuid level
+  cpuid(&eax, &ebx, &ecx, &edx);
+  cpu->maxLevels = eax;
+
+  //Fill vendor
+  char name[13];
+  memset(name,0,13);
+  get_name_cpuid(name, ebx, edx, ecx);
+
+  if(strcmp(CPU_VENDOR_INTEL_STRING,name) == 0)
+    cpu->cpu_vendor = CPU_VENDOR_INTEL;
+  else if (strcmp(CPU_VENDOR_AMD_STRING,name) == 0)
+    cpu->cpu_vendor = CPU_VENDOR_AMD;
+  else {
+    cpu->cpu_vendor = CPU_VENDOR_INVALID;
+    printErr("Unknown CPU vendor: %s", name);
+    return NULL;
+  }
+
+  //Get max extended level
+  eax = 0x80000000;
+  ebx = 0;
+  ecx = 0;
+  edx = 0;
+  cpuid(&eax, &ebx, &ecx, &edx);
+  cpu->maxExtendedLevels = eax;
+
   if (cpu->maxExtendedLevels >= 0x80000004){
     cpu->cpu_name = get_str_cpu_name_internal();
   }
@@ -386,15 +477,67 @@ struct cpuInfo* get_cpu_info() {
     cpu->topology_extensions = (ecx >> 22) & 1;
   }
 
-  cpu->arch = get_cpu_uarch(cpu);
+  cpu->hybrid_flag = false;
-  cpu->freq = get_frequency_info(cpu);
+  if(cpu->cpu_vendor == CPU_VENDOR_INTEL && cpu->maxLevels >= 0x00000007) {
-  cpu->cach = get_cache_info(cpu);
+    eax = 0x00000007;
-  cpu->topo = get_topology_info(cpu, cpu->cach);
+    ecx = 0x00000000;
-  cpu->peak_performance = get_peak_performance(cpu, cpu->topo, get_freq(cpu->freq), accurate_pp());
+    cpuid(&eax, &ebx, &ecx, &edx);
-
+    cpu->hybrid_flag = (edx >> 15) & 0x1;
-  if(cpu->cach == NULL || cpu->topo == NULL) {
-    return NULL;
   }
+
+  if(cpu->hybrid_flag) modules = 2;
+
+  struct cpuInfo* ptr = cpu;
+  for(uint32_t i=0; i < modules; i++) {
+    int32_t first_core;
+    set_cpu_module(i, modules, &first_core);
+
+    if(i > 0) {
+      ptr->next_cpu = emalloc(sizeof(struct cpuInfo));
+      ptr = ptr->next_cpu;
+      ptr->next_cpu = NULL;
+      ptr->peak_performance = -1;
+      ptr->topo = NULL;
+      ptr->cach = NULL;
+      ptr->feat = NULL;
+      // We assume that this cores have the
+      // same cpuid capabilities
+      ptr->cpu_vendor = cpu->cpu_vendor;
+      ptr->maxLevels = cpu->maxLevels;
+      ptr->maxExtendedLevels = cpu->maxExtendedLevels;
+      ptr->hybrid_flag = cpu->hybrid_flag;
+    }
+
+    if(cpu->hybrid_flag) {
+      // Detect core type
+      eax = 0x0000001A;
+      cpuid(&eax, &ebx, &ecx, &edx);
+      ptr->core_type = get_core_type();
+    }
+    ptr->first_core_id = first_core;
+    ptr->feat = get_features_info(ptr);
+
+    // If any field of the struct is NULL,
+    // return inmideately, as further functions
+    // require valid fields (cach, topo, etc)
+    ptr->arch = get_cpu_uarch(ptr);
+    ptr->freq = get_frequency_info(ptr);
+
+    ptr->cach = get_cache_info(ptr);
+    if(ptr->cach == NULL) return cpu;
+
+    if(cpu->hybrid_flag) {
+      ptr->topo = get_topology_info(ptr, ptr->cach, i);
+    }
+    else {
+      ptr->topo = get_topology_info(ptr, ptr->cach, -1);
+    }
+    if(cpu->topo == NULL) return cpu;
+  }
+
+  cpu->num_cpus = modules;
+  cpu->peak_performance = get_peak_performance(cpu, accurate_pp());
+
   return cpu;
 }
 
@@ -472,7 +615,7 @@ bool get_cache_topology_amd(struct cpuInfo* cpu, struct topology* topo) {
   return true;
 }
 
-void get_topology_from_udev(struct cpuInfo* cpu, struct topology* topo) {
+void get_topology_from_udev(struct topology* topo) {
   // TODO: To be improved in the future
   topo->total_cores = get_ncores_from_cpuinfo();
   topo->logical_cores = topo->total_cores;
@@ -484,7 +627,7 @@ void get_topology_from_udev(struct cpuInfo* cpu, struct topology* topo) {
 
 // Main reference: https://software.intel.com/content/www/us/en/develop/articles/intel-64-architecture-processor-topology-enumeration.html
 // Very interesting resource: https://wiki.osdev.org/Detecting_CPU_Topology_(80x86)
-struct topology* get_topology_info(struct cpuInfo* cpu, struct cache* cach) {
+struct topology* get_topology_info(struct cpuInfo* cpu, struct cache* cach, int module) {
   struct topology* topo = emalloc(sizeof(struct topology));
   init_topology_struct(topo, cach);
 
@@ -508,6 +651,13 @@ struct topology* get_topology_info(struct cpuInfo* cpu, struct cache* cach) {
     }
   #endif
 
+  if(cpu->hybrid_flag) {
+    topo->total_cores_module = get_total_cores_module(topo->total_cores, module);
+  }
+  else {
+    topo->total_cores_module = topo->total_cores;
+  }
+
   switch(cpu->cpu_vendor) {
     case CPU_VENDOR_INTEL:
       if (cpu->maxLevels >= 0x00000004) {
@@ -515,7 +665,7 @@ struct topology* get_topology_info(struct cpuInfo* cpu, struct cache* cach) {
         if(!toporet) {
           #ifdef __linux__
             printWarn("Failed to retrieve topology from APIC, using udev...\n");
-            get_topology_from_udev(cpu, topo);
+            get_topology_from_udev(topo);
           #else
             printErr("Failed to retrieve topology from APIC, assumming default values...\n");
             topo->logical_cores = UNKNOWN_DATA;
@@ -911,6 +1061,9 @@ void print_debug(struct cpuInfo* cpu) {
   if(cpu->cpu_vendor == CPU_VENDOR_AMD) {
     printf("- AMD topology extensions: %d\n", cpu->topology_extensions);
   }
+  if(cpu->cpu_vendor == CPU_VENDOR_INTEL) {
+    printf("- Hybrid Flag: %d\n", cpu->hybrid_flag);
+  }
   printf("- CPUID dump: 0x%.8X\n", eax);
 
   free_cpuinfo_struct(cpu);

src/x86/cpuid.h

@@ -6,7 +6,7 @@
 struct cpuInfo* get_cpu_info();
 struct cache* get_cache_info(struct cpuInfo* cpu);
 struct frequency* get_frequency_info(struct cpuInfo* cpu);
-struct topology* get_topology_info(struct cpuInfo* cpu, struct cache* cach);
+struct topology* get_topology_info(struct cpuInfo* cpu, struct cache* cach, int module);
 
 char* get_str_avx(struct cpuInfo* cpu);
 char* get_str_sse(struct cpuInfo* cpu);

src/x86/freq/freq.h

@@ -5,7 +5,7 @@
 #include "../../common/cpu.h"
 
 #define MEASURE_TIME_SECONDS         5
-#define LOOP_ITERS          1000000000
+#define LOOP_ITERS           100000000
 
 int64_t measure_frequency(struct cpuInfo* cpu);
 

src/x86/freq/freq_avx.c

@@ -15,14 +15,25 @@ void* compute_avx() {
 
   struct timeval begin, now;
 
-  __m256 a = _mm256_set1_ps(1.5);
+  __m256 a[8];
-  __m256 b = _mm256_set1_ps(1.2);
+  __m256 b[8];
-  __m256 c = _mm256_set1_ps(0.0);
+
+  for(int i=0; i < 8; i++) {
+    a[i] = _mm256_set1_ps(1.5);
+    b[i] = _mm256_set1_ps(1.2);
+  }
 
   gettimeofday(&begin, NULL);
   while(!end) {
     for(uint64_t i=0; i < LOOP_ITERS; i++) {
-      c = _mm256_fmadd_ps(a, b, c);
+      a[0] = _mm256_add_ps(a[0], b[0]);
+      a[1] = _mm256_add_ps(a[1], b[1]);
+      a[2] = _mm256_add_ps(a[2], b[2]);
+      a[3] = _mm256_add_ps(a[3], b[3]);
+      a[4] = _mm256_add_ps(a[4], b[4]);
+      a[5] = _mm256_add_ps(a[5], b[5]);
+      a[6] = _mm256_add_ps(a[6], b[6]);
+      a[7] = _mm256_add_ps(a[7], b[7]);
     }
 
     gettimeofday(&now, NULL);
@@ -35,7 +46,8 @@ void* compute_avx() {
     printf("fopen: %s", strerror(errno));
   }
   else {
-    fprintf(fp, "%f", c[0]);
+    for(int i=0; i < 8; i++)
+      fprintf(fp, "%f", a[i][0]);
     fclose(fp);
   }
 

src/x86/freq/freq_avx512.c

@@ -10,12 +10,6 @@
 #include <stdint.h>
 #include "freq.h"
 
-/*
- * For AVX512, it seems that multiple independent
- * instructions are needed to force the CPU to
- * use AVX512 frequency, since with only one instruction
- * (as the AVX implementaion) it still uses AVX frequency
- */
 void* compute_avx512() {
   bool end = false;
 
@@ -23,7 +17,6 @@ void* compute_avx512() {
 
   __m512 a[8];
   __m512 b[8];
-  __m512 mult;
 
   for(int i=0; i < 8; i++) {
     a[i] = _mm512_set1_ps(1.5);
@@ -33,14 +26,14 @@ void* compute_avx512() {
   gettimeofday(&begin, NULL);
   while(!end) {
     for(uint64_t i=0; i < LOOP_ITERS; i++) {
-      a[0] = _mm512_fmadd_ps(mult, a[0], b[0]);
+      a[0] = _mm512_add_ps(a[0], b[0]);
-      a[1] = _mm512_fmadd_ps(mult, a[1], b[1]);
+      a[1] = _mm512_add_ps(a[1], b[1]);
-      a[2] = _mm512_fmadd_ps(mult, a[2], b[2]);
+      a[2] = _mm512_add_ps(a[2], b[2]);
-      a[3] = _mm512_fmadd_ps(mult, a[3], b[3]);
+      a[3] = _mm512_add_ps(a[3], b[3]);
-      a[4] = _mm512_fmadd_ps(mult, a[4], b[4]);
+      a[4] = _mm512_add_ps(a[4], b[4]);
-      a[5] = _mm512_fmadd_ps(mult, a[5], b[5]);
+      a[5] = _mm512_add_ps(a[5], b[5]);
-      a[6] = _mm512_fmadd_ps(mult, a[6], b[6]);
+      a[6] = _mm512_add_ps(a[6], b[6]);
-      a[7] = _mm512_fmadd_ps(mult, a[7], b[7]);
+      a[7] = _mm512_add_ps(a[7], b[7]);
     }
 
     gettimeofday(&now, NULL);

src/x86/uarch.c

@@ -79,7 +79,7 @@ enum {
   UARCH_GOLDMONT_PLUS,
   UARCH_TREMONT,
   UARCH_LAKEMONT,
-  UARCH_COFFE_LAKE,
+  UARCH_COFFEE_LAKE,
   UARCH_ITANIUM,
   UARCH_KNIGHTS_FERRY,
   UARCH_KNIGHTS_CORNER,
@@ -90,6 +90,7 @@ enum {
   UARCH_ITANIUM2,
   UARCH_ICE_LAKE,
   UARCH_TIGER_LAKE,
+  UARCH_ALDER_LAKE,
   // AMD //
   UARCH_AM486,
   UARCH_AM5X86,
@@ -108,7 +109,8 @@ enum {
   UARCH_ZEN,
   UARCH_ZEN_PLUS,
   UARCH_ZEN2,
-  UARCH_ZEN3
+  UARCH_ZEN3,
+  UARCH_ZEN3_PLUS
 };
 
 struct uarch {
@@ -224,18 +226,19 @@ struct uarch* get_uarch_from_cpuid_intel(uint32_t ef, uint32_t f, uint32_t em, u
   CHECK_UARCH(arch, 0,  6,  8, 12, NA, "Tiger Lake",      UARCH_TIGER_LAKE,       10) // instlatx64
   CHECK_UARCH(arch, 0,  6,  8, 13, NA, "Tiger Lake",      UARCH_TIGER_LAKE,       10) // instlatx64
   // CHECK_UARCH(arch, 0,  6,  8, 14,  9, ...) It is not possible to determine uarch only from CPUID dump (can be Kaby Lake or Amber Lake)
-  CHECK_UARCH(arch, 0,  6,  8, 14, 10, "Kaby Lake",       UARCH_KABY_LAKE,        14) // wikichip
+  CHECK_UARCH(arch, 0,  6,  8, 14, 10, "Coffee Lake",     UARCH_COFFEE_LAKE,      14) // wikichip
   CHECK_UARCH(arch, 0,  6,  8, 14, 11, "Whiskey Lake",    UARCH_WHISKEY_LAKE,     14) // wikichip
   CHECK_UARCH(arch, 0,  6,  8, 14, 12, "Comet Lake",      UARCH_COMET_LAKE,       14) // wikichip
   CHECK_UARCH(arch, 0,  6,  9,  6, NA, "Tremont",         UARCH_TREMONT,          10) // LX*
+  CHECK_UARCH(arch, 0,  6,  9,  7, NA, "Alder Lake",      UARCH_ALDER_LAKE,       10) // wikichip
   CHECK_UARCH(arch, 0,  6,  9, 10, NA, "Tremont",         UARCH_TREMONT,          10) // instlatx64
   CHECK_UARCH(arch, 0,  6,  9, 12, NA, "Tremont",         UARCH_TREMONT,          10) // LX*
   CHECK_UARCH(arch, 0,  6,  9, 13, NA, "Sunny Cove",      UARCH_SUNNY_COVE,       10) // LX*
   CHECK_UARCH(arch, 0,  6,  9, 14,  9, "Kaby Lake",       UARCH_KABY_LAKE,        14)
-  CHECK_UARCH(arch, 0,  6,  9, 14, 10, "Coffee Lake",     UARCH_COFFE_LAKE,       14)
+  CHECK_UARCH(arch, 0,  6,  9, 14, 10, "Coffee Lake",     UARCH_COFFEE_LAKE,      14)
-  CHECK_UARCH(arch, 0,  6,  9, 14, 11, "Coffee Lake",     UARCH_COFFE_LAKE,       14)
+  CHECK_UARCH(arch, 0,  6,  9, 14, 11, "Coffee Lake",     UARCH_COFFEE_LAKE,      14)
-  CHECK_UARCH(arch, 0,  6,  9, 14, 12, "Coffee Lake",     UARCH_COFFE_LAKE,       14)
+  CHECK_UARCH(arch, 0,  6,  9, 14, 12, "Coffee Lake",     UARCH_COFFEE_LAKE,      14)
-  CHECK_UARCH(arch, 0,  6,  9, 14, 13, "Coffee Lake",     UARCH_COFFE_LAKE,       14)
+  CHECK_UARCH(arch, 0,  6,  9, 14, 13, "Coffee Lake",     UARCH_COFFEE_LAKE,      14)
   CHECK_UARCH(arch, 0,  6, 10,  5, NA, "Comet Lake",      UARCH_COMET_LAKE,       14) // wikichip
   CHECK_UARCH(arch, 0,  6, 10,  6, NA, "Comet Lake",      UARCH_COMET_LAKE,       14) // instlatx64.atw.hu (i7-10710U)
   CHECK_UARCH(arch, 0,  6, 10,  7, NA, "Rocket Lake",     UARCH_ROCKET_LAKE,      14) // instlatx64.atw.hu (i7-11700K)
@@ -356,8 +359,10 @@ struct uarch* get_uarch_from_cpuid_amd(uint32_t ef, uint32_t f, uint32_t em, uin
   CHECK_UARCH(arch,  8, 15,  6,  0, NA, "Zen 2",       UARCH_ZEN2,         7) // undocumented, geekbench.com example
   CHECK_UARCH(arch,  8, 15,  6,  8, NA, "Zen 2",       UARCH_ZEN2,         7) // found on instlatx64
   CHECK_UARCH(arch,  8, 15,  7,  1, NA, "Zen 2",       UARCH_ZEN2,         7) // samples from Steven Noonan and instlatx64
+  CHECK_UARCH(arch,  8, 15,  9,  0,  2, "Zen 2",       UARCH_ZEN2,         7) // Steam Deck (instlatx64)
   CHECK_UARCH(arch, 10, 15,  0,  1, NA, "Zen 3",       UARCH_ZEN3,         7) // instlatx64
   CHECK_UARCH(arch, 10, 15,  2,  1, NA, "Zen 3",       UARCH_ZEN3,         7) // instlatx64
+  CHECK_UARCH(arch, 10, 15,  4,  4, NA, "Zen 3+",      UARCH_ZEN3_PLUS,    6) // instlatx64 (they say it is Zen3...)
   CHECK_UARCH(arch, 10, 15,  5,  0, NA, "Zen 3",       UARCH_ZEN3,         7) // instlatx64
   UARCH_END
 
@@ -406,7 +411,7 @@ int get_number_of_vpus(struct cpuInfo* cpu) {
       case UARCH_ROCKET_LAKE:
       case UARCH_AMBER_LAKE:
       case UARCH_WHISKEY_LAKE:
-      case UARCH_COFFE_LAKE:
+      case UARCH_COFFEE_LAKE:
       case UARCH_PALM_COVE:
 
       case UARCH_KNIGHTS_LANDING:
@@ -414,10 +419,12 @@ int get_number_of_vpus(struct cpuInfo* cpu) {
 
       case UARCH_ICE_LAKE:
       case UARCH_TIGER_LAKE:
+      case UARCH_ALDER_LAKE:
 
       // AMD
       case UARCH_ZEN2:
       case UARCH_ZEN3:
+      case UARCH_ZEN3_PLUS:
         return 2;
       default:
         return 1;
@@ -426,6 +433,7 @@ int get_number_of_vpus(struct cpuInfo* cpu) {
 
 bool choose_new_intel_logo_uarch(struct cpuInfo* cpu) {
   switch(cpu->arch->uarch) {
+    case UARCH_ALDER_LAKE:
     case UARCH_ROCKET_LAKE:
     case UARCH_TIGER_LAKE:
       return true;