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@@ -98,7 +98,6 @@ enum riscv_isa_ext_id {
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// (Zicbop) https://github.com/riscv/riscv-CMOs/blob/master/cmobase/Zicbop.adoc
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// (Zicbop) https://github.com/riscv/riscv-CMOs/blob/master/cmobase/Zicbop.adoc
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// https://raw.githubusercontent.com/riscv/riscv-CMOs/master/specifications/cmobase-v1.0.1.pdf
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// https://raw.githubusercontent.com/riscv/riscv-CMOs/master/specifications/cmobase-v1.0.1.pdf
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// https://www.kernel.org/doc/Documentation/devicetree/bindings/riscv/extensions.yaml
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// https://www.kernel.org/doc/Documentation/devicetree/bindings/riscv/extensions.yaml
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// https://gcc.gnu.org/onlinedocs/gcc/RISC-V-Options.html
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// (Ime) https://github.com/riscv/integrated-matrix-extension (not confirmed, just a guess...)
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// (Ime) https://github.com/riscv/integrated-matrix-extension (not confirmed, just a guess...)
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// Included all except for G
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// Included all except for G
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static const struct extension extension_list[] = {
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static const struct extension extension_list[] = {
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@@ -136,63 +135,63 @@ static const struct extension extension_list[] = {
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{ RISCV_ISA_EXT_ZICSR, "(Zicsr) Control and Status Register" },
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{ RISCV_ISA_EXT_ZICSR, "(Zicsr) Control and Status Register" },
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{ RISCV_ISA_EXT_ZIFENCEI, "(Zifencei) Instruction-Fetch Fence" },
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{ RISCV_ISA_EXT_ZIFENCEI, "(Zifencei) Instruction-Fetch Fence" },
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{ RISCV_ISA_EXT_ZIHPM, "(Zihpm) Hardware Performance Counters" },
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{ RISCV_ISA_EXT_ZIHPM, "(Zihpm) Hardware Performance Counters" },
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{ RISCV_ISA_EXT_SMSTATEEN, "(Smstateen) Supervisor/Hypervisor State Enable" },
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{ RISCV_ISA_EXT_SMSTATEEN, "(Smstateen) " },
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{ RISCV_ISA_EXT_ZICOND, "(Zicond) Integer Conditional Operations" },
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{ RISCV_ISA_EXT_ZICOND, "(Zicond) Integer Conditional Operations" },
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{ RISCV_ISA_EXT_ZBC, "(Zbc) Carry-Less Multiplication" },
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{ RISCV_ISA_EXT_ZBC, "(Zbc) Carry-Less Multiplication" },
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{ RISCV_ISA_EXT_ZBKB, "(Zbkb) Bit-Manipulation for Cryptography (Byte ops)" },
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{ RISCV_ISA_EXT_ZBKB, "(Zbkb) " },
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{ RISCV_ISA_EXT_ZBKC, "(Zbkc) Bit-Manipulation for Cryptography (Carry-less ops)" },
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{ RISCV_ISA_EXT_ZBKC, "(Zbkc) " },
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{ RISCV_ISA_EXT_ZBKX, "(Zbkx) Bit-Manipulation for Cryptography (Crossbar ops)" },
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{ RISCV_ISA_EXT_ZBKX, "(Zbkx) " },
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{ RISCV_ISA_EXT_ZKND, "(Zknd) NIST AES Decryption Instructions" },
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{ RISCV_ISA_EXT_ZKND, "(Zknd) " },
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{ RISCV_ISA_EXT_ZKNE, "(Zkne) NIST AES Encryption Instructions" },
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{ RISCV_ISA_EXT_ZKNE, "(Zkne) " },
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{ RISCV_ISA_EXT_ZKNH, "(Zknh) NIST Hash (SHA-2/SHA-3) Instructions" },
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{ RISCV_ISA_EXT_ZKNH, "(Zknh) " },
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{ RISCV_ISA_EXT_ZKR, "(Zkr) Entropy Source Reading (Random)" },
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{ RISCV_ISA_EXT_ZKR, "(Zkr) " },
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{ RISCV_ISA_EXT_ZKSED, "(Zksed) SM4 Block Cipher Decryption" },
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{ RISCV_ISA_EXT_ZKSED, "(Zksed) " },
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{ RISCV_ISA_EXT_ZKSH, "(Zksh) SM3 Hash Instructions" },
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{ RISCV_ISA_EXT_ZKSH, "(Zksh) " },
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{ RISCV_ISA_EXT_ZKT, "(Zkt) Data-Independent Execution Latency" },
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{ RISCV_ISA_EXT_ZKT, "(Zkt) Data-Independent Execution Latency" },
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{ RISCV_ISA_EXT_ZVBB, "(Zvbb) Vector Basic Bit-Manipulation" },
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{ RISCV_ISA_EXT_ZVBB, "(Zvbb) " },
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{ RISCV_ISA_EXT_ZVBC, "(Zvbc) Vector Carry-Less Multiplication" },
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{ RISCV_ISA_EXT_ZVBC, "(Zvbc) " },
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{ RISCV_ISA_EXT_ZVKB, "(Zvkb) Vector Cryptography (Byte ops)" },
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{ RISCV_ISA_EXT_ZVKB, "(Zvkb) " },
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{ RISCV_ISA_EXT_ZVKG, "(Zvkg) Vector GCM/GMAC Instructions" },
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{ RISCV_ISA_EXT_ZVKG, "(Zvkg) " },
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{ RISCV_ISA_EXT_ZVKNED, "(Zvkned) Vector AES Decryption" },
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{ RISCV_ISA_EXT_ZVKNED, "(Zvkned) " },
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{ RISCV_ISA_EXT_ZVKNHA, "(Zvknha) Vector SHA-2 Hash (A variant)" },
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{ RISCV_ISA_EXT_ZVKNHA, "(Zvknha) " },
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{ RISCV_ISA_EXT_ZVKNHB, "(Zvknhb) Vector SHA-2 Hash (B variant)" },
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{ RISCV_ISA_EXT_ZVKNHB, "(Zvknhb) " },
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{ RISCV_ISA_EXT_ZVKSED, "(Zvksed) Vector SM4 Block Cipher Decryption" },
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{ RISCV_ISA_EXT_ZVKSED, "(Zvksed) " },
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{ RISCV_ISA_EXT_ZVKSH, "(Zvksh) Vector SM3 Hash Instructions" },
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{ RISCV_ISA_EXT_ZVKSH, "(Zvksh) " },
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{ RISCV_ISA_EXT_ZVKT, "(Zvkt) Vector Data-Independent Execution Latency" },
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{ RISCV_ISA_EXT_ZVKT, "(Zvkt) " },
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{ RISCV_ISA_EXT_ZFH, "(Zfh) Half-Precision Floating Point" },
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{ RISCV_ISA_EXT_ZFH, "(Zfh) " },
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{ RISCV_ISA_EXT_ZFHMIN, "(Zfhmin) Minimal Half-Precision Floating Point" },
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{ RISCV_ISA_EXT_ZFHMIN, "(Zfhmin) " },
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{ RISCV_ISA_EXT_ZIHINTNTL, "(Zihintntl) Non-Temporal Load/Store Hints" },
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{ RISCV_ISA_EXT_ZIHINTNTL, "(Zihintntl) " },
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{ RISCV_ISA_EXT_ZVFH, "(Zvfh) Vector Half-Precision Floating Point" },
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{ RISCV_ISA_EXT_ZVFH, "(Zvfh) " },
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{ RISCV_ISA_EXT_ZVFHMIN, "(Zvfhmin) Minimal Vector Half-Precision Floating Point" },
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{ RISCV_ISA_EXT_ZVFHMIN, "(Zvfhmin) " },
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{ RISCV_ISA_EXT_ZFA, "(Zfa) Additional Floating-Point Instructions" },
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{ RISCV_ISA_EXT_ZFA, "(Zfa) " },
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{ RISCV_ISA_EXT_ZTSO, "(Ztso) Total Store Ordering Memory Model" },
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{ RISCV_ISA_EXT_ZTSO, "(Ztso) " },
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{ RISCV_ISA_EXT_ZACAS, "(Zacas) Atomic Compare-and-Swap" },
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{ RISCV_ISA_EXT_ZACAS, "(Zacas) " },
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{ RISCV_ISA_EXT_ZVE32X, "(Zve32x) Embedded Vector Integer (32-bit elements)" },
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{ RISCV_ISA_EXT_ZVE32X, "(Zve32x) Vector Extensions (i32)" },
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{ RISCV_ISA_EXT_ZVE32F, "(Zve32f) Embedded Vector Floating Point (f32)" },
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{ RISCV_ISA_EXT_ZVE32F, "(Zve32f) Vector Extensions (f32)" },
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{ RISCV_ISA_EXT_ZVE64X, "(Zve64x) Embedded Vector Integer (64-bit elements)" },
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{ RISCV_ISA_EXT_ZVE64X, "(Zve64x) Vector Extensions (i64)" },
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{ RISCV_ISA_EXT_ZVE64F, "(Zve64f) Embedded Vector Floating Point (f64)" },
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{ RISCV_ISA_EXT_ZVE64F, "(Zve64f) Vector Extensions (f64)" },
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{ RISCV_ISA_EXT_ZVE64D, "(Zve64d) Embedded Vector Double-Precision FP (f64)" },
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{ RISCV_ISA_EXT_ZVE64D, "(Zve64d) Vector Extensions (???)" },
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{ RISCV_ISA_EXT_ZIMOP, "(Zimop) Integer Multiply-Only Instructions" },
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{ RISCV_ISA_EXT_ZIMOP, "(Zimop) " },
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{ RISCV_ISA_EXT_ZCA, "(Zca) Compressed Integer Instructions" },
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{ RISCV_ISA_EXT_ZCA, "(Zca) " },
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{ RISCV_ISA_EXT_ZCB, "(Zcb) Compressed Bit-Manipulation Instructions" },
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{ RISCV_ISA_EXT_ZCB, "(Zcb) " },
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{ RISCV_ISA_EXT_ZCD, "(Zcd) Compressed Double-Precision FP Instructions" },
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{ RISCV_ISA_EXT_ZCD, "(Zcd) " },
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{ RISCV_ISA_EXT_ZCF, "(Zcf) Compressed Single-Precision FP Instructions" },
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{ RISCV_ISA_EXT_ZCF, "(Zcf) " },
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{ RISCV_ISA_EXT_ZCMOP, "(Zcmop) Compressed Multiply-Only Instructions" },
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{ RISCV_ISA_EXT_ZCMOP, "(Zcmop) " },
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{ RISCV_ISA_EXT_ZAWRS, "(Zawrs) Wait-on-Reservation-Set Instruction" },
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{ RISCV_ISA_EXT_ZAWRS, "(Zawrs) " },
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{ RISCV_ISA_EXT_SVVPTC, "(Svvptc) Supervisor Virtual Page Table Cache Control" },
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{ RISCV_ISA_EXT_SVVPTC, "(Svvptc) " },
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{ RISCV_ISA_EXT_SMMPM, "(Smmpm) Supervisor Memory Protection Modification" },
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{ RISCV_ISA_EXT_SMMPM, "(Smmpm) " },
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{ RISCV_ISA_EXT_SMNPM, "(Smnpm) Supervisor Non-Privileged Memory Access Control" },
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{ RISCV_ISA_EXT_SMNPM, "(Smnpm) " },
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{ RISCV_ISA_EXT_SSNPM, "(Ssnpm) Supervisor Secure Non-Privileged Memory" },
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{ RISCV_ISA_EXT_SSNPM, "(Ssnpm) " },
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{ RISCV_ISA_EXT_ZABHA, "(Zabha) Atomic Byte/Halfword Operations" },
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{ RISCV_ISA_EXT_ZABHA, "(Zabha) " },
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{ RISCV_ISA_EXT_ZICCRSE, "(Ziccrse) Cache Control Range Start/End Operations" },
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{ RISCV_ISA_EXT_ZICCRSE, "(Ziccrse) " },
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{ RISCV_ISA_EXT_SVADE, "(Svade) Supervisor Virtual Address Deferred Exception" },
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{ RISCV_ISA_EXT_SVADE, "(Svade) " },
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{ RISCV_ISA_EXT_SVADU, "(Svadu) Supervisor Virtual Address Dirty Update" },
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{ RISCV_ISA_EXT_SVADU, "(Svadu) " },
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{ RISCV_ISA_EXT_ZFBFMIN, "(Zfbfmin) Minimal BFloat16 Floating Point" },
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{ RISCV_ISA_EXT_ZFBFMIN, "(Zfbfmin) " },
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{ RISCV_ISA_EXT_ZVFBFMIN, "(Zvfbfmin) Vector Minimal BFloat16 Floating Point" },
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{ RISCV_ISA_EXT_ZVFBFMIN, "(Zvfbfmin) " },
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{ RISCV_ISA_EXT_ZVFBFWMA, "(Zvfbfwma) Vector BFloat16 Widening Multiply-Accumulate" },
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{ RISCV_ISA_EXT_ZVFBFWMA, "(Zvfbfwma) " },
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{ RISCV_ISA_EXT_ZAAMO, "(Zaamo) Atomic Memory Operation (AMO) Instructions" },
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{ RISCV_ISA_EXT_ZAAMO, "(Zaamo) " },
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{ RISCV_ISA_EXT_ZALRSC, "(Zalrsc) Atomic Load-Reserved/Store-Conditional" },
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{ RISCV_ISA_EXT_ZALRSC, "(Zalrsc) " },
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{ RISCV_ISA_EXT_ZICBOP, "(Zicbop) Cache Block Prefetch/Zero Operations" },
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{ RISCV_ISA_EXT_ZICBOP, "(Zicbop) " },
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{ RISCV_ISA_EXT_IME, "(Ime) Integrated Matrix Extension" },
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{ RISCV_ISA_EXT_IME, "(Ime) Integrated Matrix Extension" },
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};
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};
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