mirror of
https://github.com/Dr-Noob/cpufetch.git
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177 lines
3.5 KiB
C
177 lines
3.5 KiB
C
#ifndef __CPU__
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#define __CPU__
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#include <stdint.h>
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#include <stdbool.h>
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enum {
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// ARCH_X86
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CPU_VENDOR_INTEL,
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CPU_VENDOR_AMD,
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// ARCH_ARM
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CPU_VENDOR_ARM,
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CPU_VENDOR_APPLE,
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CPU_VENDOR_BROADCOM,
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CPU_VENDOR_CAVIUM,
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CPU_VENDOR_NVIDIA,
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CPU_VENDOR_APM,
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CPU_VENDOR_QUALCOMM,
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CPU_VENDOR_HUAWUEI,
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CPU_VENDOR_SAMSUNG,
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CPU_VENDOR_MARVELL,
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CPU_VENDOR_PHYTIUM,
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// OTHERS
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CPU_VENDOR_UNKNOWN,
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CPU_VENDOR_INVALID
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};
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enum {
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HV_VENDOR_KVM,
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HV_VENDOR_QEMU,
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HV_VENDOR_HYPERV,
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HV_VENDOR_VMWARE,
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HV_VENDOR_XEN,
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HV_VENDOR_PARALLELS,
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HV_VENDOR_INVALID
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};
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#define UNKNOWN_DATA -1
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#define CPU_NAME_MAX_LENGTH 64
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typedef int32_t VENDOR;
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struct frequency {
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int32_t base;
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int32_t max;
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};
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struct hypervisor {
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bool present;
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char* hv_name;
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VENDOR hv_vendor;
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};
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struct cach {
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int32_t size;
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uint8_t num_caches;
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bool exists;
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// plenty of more properties to include in the future...
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};
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struct cache {
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struct cach* L1i;
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struct cach* L1d;
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struct cach* L2;
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struct cach* L3;
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struct cach** cach_arr;
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uint8_t max_cache_level;
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};
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struct topology {
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int32_t total_cores;
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struct cache* cach;
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#if defined(ARCH_X86) || defined(ARCH_PPC)
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int32_t physical_cores;
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int32_t logical_cores;
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uint32_t sockets;
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uint32_t smt_supported; // Number of SMT that CPU supports (equal to smt_available if SMT is enabled)
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#ifdef ARCH_X86
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uint32_t smt_available; // Number of SMT that is currently enabled
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struct apic* apic;
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#endif
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#endif
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};
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struct features {
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bool AES; // Must be the first field of features struct!
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#ifdef ARCH_X86
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bool AVX;
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bool AVX2;
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bool AVX512;
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bool SSE;
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bool SSE2;
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bool SSE3;
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bool SSSE3;
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bool SSE4a;
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bool SSE4_1;
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bool SSE4_2;
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bool FMA3;
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bool FMA4;
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bool SHA;
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#elif ARCH_PPC
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bool altivec;
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#elif ARCH_ARM
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bool NEON;
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bool SHA1;
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bool SHA2;
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bool CRC32;
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#endif
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};
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struct cpuInfo {
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VENDOR cpu_vendor;
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struct uarch* arch;
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struct hypervisor* hv;
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struct frequency* freq;
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struct cache* cach;
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struct topology* topo;
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struct features* feat;
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int64_t peak_performance;
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#if defined(ARCH_X86) || defined(ARCH_PPC)
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// CPU name from model
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char* cpu_name;
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#endif
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#ifdef ARCH_X86
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// Max cpuids levels
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uint32_t maxLevels;
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// Max cpuids extended levels
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uint32_t maxExtendedLevels;
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// Topology Extensions (AMD only)
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bool topology_extensions;
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#elif ARCH_PPC
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uint32_t pvr;
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#elif ARCH_ARM
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// Main ID register
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uint32_t midr;
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#endif
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#ifdef ARCH_ARM
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struct system_on_chip* soc;
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// If SoC contains more than one CPU and they
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// are different, the others will be stored in
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// the next_cpu field
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struct cpuInfo* next_cpu;
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uint8_t num_cpus;
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#endif
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};
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#if defined(ARCH_X86) || defined(ARCH_PPC)
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char* get_str_cpu_name(struct cpuInfo* cpu, bool fcpuname);
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char* get_str_sockets(struct topology* topo);
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uint32_t get_nsockets(struct topology* topo);
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#endif
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VENDOR get_cpu_vendor(struct cpuInfo* cpu);
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int64_t get_freq(struct frequency* freq);
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char* get_str_aes(struct cpuInfo* cpu);
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char* get_str_sha(struct cpuInfo* cpu);
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char* get_str_l1i(struct cache* cach);
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char* get_str_l1d(struct cache* cach);
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char* get_str_l2(struct cache* cach);
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char* get_str_l3(struct cache* cach);
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char* get_str_freq(struct frequency* freq);
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char* get_str_peak_performance(int64_t flops);
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void init_topology_struct(struct topology* topo, struct cache* cach);
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void init_cache_struct(struct cache* cach);
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void free_cache_struct(struct cache* cach);
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void free_freq_struct(struct frequency* freq);
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void free_cpuinfo_struct(struct cpuInfo* cpu);
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#endif
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