mirror of
https://github.com/Dr-Noob/cpufetch.git
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a19c421362
There are *a lot* of new extensions in the Linux kernel now (Linux v6.16) since the last time I checked (Linux v6.2.10), so added them all plus ime, which is not present in the kernel apparently, but that I spotted in a RISC-V chip. Previously, the mask was represented with a uint64_t value, which is fine as long as we have less than 65 possible extensions. This is not the case anymore, so instead I replaced that with a pointer of bool, which gets allocated depending on the max number of extensions that we support.
206 lines
9.7 KiB
C
206 lines
9.7 KiB
C
#ifndef __RISCV__
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#define __RISCV__
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#include "../common/cpu.h"
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struct extension {
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int id;
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char* str;
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};
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#define RISCV_ISA_EXT_NAME_LEN_MAX 32
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#define RISCV_ISA_EXT_BASE 26
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// https://elixir.bootlin.com/linux/latest/source/arch/riscv/include/asm/hwcap.h
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// This enum represent the logical ID for multi-letter RISC-V ISA extensions.
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// The logical ID should start from RISCV_ISA_EXT_BASE
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enum riscv_isa_ext_id {
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RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE,
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RISCV_ISA_EXT_SSTC,
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RISCV_ISA_EXT_SVINVAL,
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RISCV_ISA_EXT_SVPBMT,
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RISCV_ISA_EXT_ZBB,
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RISCV_ISA_EXT_ZICBOM,
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RISCV_ISA_EXT_ZIHINTPAUSE,
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RISCV_ISA_EXT_SVNAPOT,
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RISCV_ISA_EXT_ZICBOZ,
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RISCV_ISA_EXT_SMAIA,
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RISCV_ISA_EXT_SSAIA,
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RISCV_ISA_EXT_ZBA,
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RISCV_ISA_EXT_ZBS,
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RISCV_ISA_EXT_ZICNTR,
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RISCV_ISA_EXT_ZICSR,
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RISCV_ISA_EXT_ZIFENCEI,
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RISCV_ISA_EXT_ZIHPM,
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RISCV_ISA_EXT_SMSTATEEN,
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RISCV_ISA_EXT_ZICOND,
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RISCV_ISA_EXT_ZBC,
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RISCV_ISA_EXT_ZBKB,
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RISCV_ISA_EXT_ZBKC,
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RISCV_ISA_EXT_ZBKX,
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RISCV_ISA_EXT_ZKND,
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RISCV_ISA_EXT_ZKNE,
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RISCV_ISA_EXT_ZKNH,
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RISCV_ISA_EXT_ZKR,
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RISCV_ISA_EXT_ZKSED,
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RISCV_ISA_EXT_ZKSH,
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RISCV_ISA_EXT_ZKT,
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RISCV_ISA_EXT_ZVBB,
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RISCV_ISA_EXT_ZVBC,
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RISCV_ISA_EXT_ZVKB,
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RISCV_ISA_EXT_ZVKG,
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RISCV_ISA_EXT_ZVKNED,
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RISCV_ISA_EXT_ZVKNHA,
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RISCV_ISA_EXT_ZVKNHB,
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RISCV_ISA_EXT_ZVKSED,
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RISCV_ISA_EXT_ZVKSH,
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RISCV_ISA_EXT_ZVKT,
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RISCV_ISA_EXT_ZFH,
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RISCV_ISA_EXT_ZFHMIN,
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RISCV_ISA_EXT_ZIHINTNTL,
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RISCV_ISA_EXT_ZVFH,
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RISCV_ISA_EXT_ZVFHMIN,
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RISCV_ISA_EXT_ZFA,
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RISCV_ISA_EXT_ZTSO,
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RISCV_ISA_EXT_ZACAS,
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RISCV_ISA_EXT_ZVE32X,
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RISCV_ISA_EXT_ZVE32F,
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RISCV_ISA_EXT_ZVE64X,
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RISCV_ISA_EXT_ZVE64F,
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RISCV_ISA_EXT_ZVE64D,
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RISCV_ISA_EXT_ZIMOP,
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RISCV_ISA_EXT_ZCA,
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RISCV_ISA_EXT_ZCB,
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RISCV_ISA_EXT_ZCD,
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RISCV_ISA_EXT_ZCF,
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RISCV_ISA_EXT_ZCMOP,
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RISCV_ISA_EXT_ZAWRS,
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RISCV_ISA_EXT_SVVPTC,
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RISCV_ISA_EXT_SMMPM,
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RISCV_ISA_EXT_SMNPM,
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RISCV_ISA_EXT_SSNPM,
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RISCV_ISA_EXT_ZABHA,
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RISCV_ISA_EXT_ZICCRSE,
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RISCV_ISA_EXT_SVADE,
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RISCV_ISA_EXT_SVADU,
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RISCV_ISA_EXT_ZFBFMIN,
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RISCV_ISA_EXT_ZVFBFMIN,
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RISCV_ISA_EXT_ZVFBFWMA,
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RISCV_ISA_EXT_ZAAMO,
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RISCV_ISA_EXT_ZALRSC,
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RISCV_ISA_EXT_ZICBOP,
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RISCV_ISA_EXT_IME, // This is not in the kernel! but it was seen on a Muse Pi Pro board
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RISCV_ISA_EXT_ID_MAX
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};
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// https://five-embeddev.com/riscv-isa-manual/latest/preface.html#preface
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// https://en.wikichip.org/wiki/risc-v/standard_extensions
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// (Zicbop) https://github.com/riscv/riscv-CMOs/blob/master/cmobase/Zicbop.adoc
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// https://raw.githubusercontent.com/riscv/riscv-CMOs/master/specifications/cmobase-v1.0.1.pdf
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// https://www.kernel.org/doc/Documentation/devicetree/bindings/riscv/extensions.yaml
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// https://gcc.gnu.org/onlinedocs/gcc/RISC-V-Options.html
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// (Ime) https://github.com/riscv/integrated-matrix-extension (not confirmed, just a guess...)
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// Included all except for G
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static const struct extension extension_list[] = {
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{ 'i' - 'a', "(I) Integer Instruction Set" },
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{ 'm' - 'a', "(M) Integer Multiplication and Division" },
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{ 'a' - 'a', "(A) Atomic Instructions" },
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{ 'f' - 'a', "(F) Single-Precision Floating-Point" },
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{ 'd' - 'a', "(D) Double-Precision Floating-Point" },
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{ 'q' - 'a', "(Q) Quad-Precision Floating-Point" },
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{ 'l' - 'a', "(L) Decimal Floating-Point" },
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{ 'c' - 'a', "(C) Compressed Instructions" },
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{ 'b' - 'a', "(B) Double-Precision Floating-Point" },
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{ 'j' - 'a', "(J) Dynamically Translated Languages" },
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{ 't' - 'a', "(T) Transactional Memory" },
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{ 'p' - 'a', "(P) Packed-SIMD Instructions" },
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{ 'v' - 'a', "(V) Vector Operations" },
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{ 'n' - 'a', "(N) User-Level Interrupts" },
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{ 'h' - 'a', "(H) Hypervisor" },
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// multi-letter extensions
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{ RISCV_ISA_EXT_SSCOFPMF, "(Sscofpmf) Count OverFlow and Privilege Mode Filtering" },
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{ RISCV_ISA_EXT_SSTC, "(Sstc) S and VS level Time Compare" },
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{ RISCV_ISA_EXT_SVINVAL, "(Svinval) Fast TLB Invalidation" },
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{ RISCV_ISA_EXT_SVPBMT, "(Svpbmt) Page-based Memory Types" },
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{ RISCV_ISA_EXT_ZBB, "(Zbb) Basic bit-manipulation" },
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{ RISCV_ISA_EXT_ZICBOM, "(Zicbom) Cache Block Management Operations" },
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{ RISCV_ISA_EXT_ZIHINTPAUSE, "(Zihintpause) Pause Hint" },
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{ RISCV_ISA_EXT_SVNAPOT, "(Svnapot) Naturally Aligned Power of Two Pages" },
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{ RISCV_ISA_EXT_ZICBOZ, "(Zicboz) Cache Block Zero Operations" },
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{ RISCV_ISA_EXT_ZICBOP, "(Zicbop) Cache Block Prefetch Operations" },
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{ RISCV_ISA_EXT_SMAIA, "(Smaia) Advanced Interrupt Architecture" },
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{ RISCV_ISA_EXT_SSAIA, "(Ssaia) Advanced Interrupt Architecture" },
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{ RISCV_ISA_EXT_ZBA, "(Zba) Address Generation" },
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{ RISCV_ISA_EXT_ZBS, "(Zbs) Single-bit Instructions" },
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{ RISCV_ISA_EXT_ZICNTR, "(Zicntr) Base Counters and Timers" },
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{ RISCV_ISA_EXT_ZICSR, "(Zicsr) Control and Status Register" },
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{ RISCV_ISA_EXT_ZIFENCEI, "(Zifencei) Instruction-Fetch Fence" },
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{ RISCV_ISA_EXT_ZIHPM, "(Zihpm) Hardware Performance Counters" },
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{ RISCV_ISA_EXT_SMSTATEEN, "(Smstateen) Supervisor/Hypervisor State Enable" },
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{ RISCV_ISA_EXT_ZICOND, "(Zicond) Integer Conditional Operations" },
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{ RISCV_ISA_EXT_ZBC, "(Zbc) Carry-Less Multiplication" },
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{ RISCV_ISA_EXT_ZBKB, "(Zbkb) Bit-Manipulation for Cryptography (Byte ops)" },
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{ RISCV_ISA_EXT_ZBKC, "(Zbkc) Bit-Manipulation for Cryptography (Carry-less ops)" },
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{ RISCV_ISA_EXT_ZBKX, "(Zbkx) Bit-Manipulation for Cryptography (Crossbar ops)" },
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{ RISCV_ISA_EXT_ZKND, "(Zknd) NIST AES Decryption Instructions" },
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{ RISCV_ISA_EXT_ZKNE, "(Zkne) NIST AES Encryption Instructions" },
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{ RISCV_ISA_EXT_ZKNH, "(Zknh) NIST Hash (SHA-2/SHA-3) Instructions" },
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{ RISCV_ISA_EXT_ZKR, "(Zkr) Entropy Source Reading (Random)" },
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{ RISCV_ISA_EXT_ZKSED, "(Zksed) SM4 Block Cipher Decryption" },
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{ RISCV_ISA_EXT_ZKSH, "(Zksh) SM3 Hash Instructions" },
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{ RISCV_ISA_EXT_ZKT, "(Zkt) Data-Independent Execution Latency" },
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{ RISCV_ISA_EXT_ZVBB, "(Zvbb) Vector Basic Bit-Manipulation" },
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{ RISCV_ISA_EXT_ZVBC, "(Zvbc) Vector Carry-Less Multiplication" },
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{ RISCV_ISA_EXT_ZVKB, "(Zvkb) Vector Cryptography (Byte ops)" },
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{ RISCV_ISA_EXT_ZVKG, "(Zvkg) Vector GCM/GMAC Instructions" },
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{ RISCV_ISA_EXT_ZVKNED, "(Zvkned) Vector AES Decryption" },
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{ RISCV_ISA_EXT_ZVKNHA, "(Zvknha) Vector SHA-2 Hash (A variant)" },
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{ RISCV_ISA_EXT_ZVKNHB, "(Zvknhb) Vector SHA-2 Hash (B variant)" },
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{ RISCV_ISA_EXT_ZVKSED, "(Zvksed) Vector SM4 Block Cipher Decryption" },
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{ RISCV_ISA_EXT_ZVKSH, "(Zvksh) Vector SM3 Hash Instructions" },
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{ RISCV_ISA_EXT_ZVKT, "(Zvkt) Vector Data-Independent Execution Latency" },
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{ RISCV_ISA_EXT_ZFH, "(Zfh) Half-Precision Floating Point" },
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{ RISCV_ISA_EXT_ZFHMIN, "(Zfhmin) Minimal Half-Precision Floating Point" },
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{ RISCV_ISA_EXT_ZIHINTNTL, "(Zihintntl) Non-Temporal Load/Store Hints" },
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{ RISCV_ISA_EXT_ZVFH, "(Zvfh) Vector Half-Precision Floating Point" },
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{ RISCV_ISA_EXT_ZVFHMIN, "(Zvfhmin) Minimal Vector Half-Precision Floating Point" },
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{ RISCV_ISA_EXT_ZFA, "(Zfa) Additional Floating-Point Instructions" },
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{ RISCV_ISA_EXT_ZTSO, "(Ztso) Total Store Ordering Memory Model" },
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{ RISCV_ISA_EXT_ZACAS, "(Zacas) Atomic Compare-and-Swap" },
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{ RISCV_ISA_EXT_ZVE32X, "(Zve32x) Embedded Vector Integer (32-bit elements)" },
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{ RISCV_ISA_EXT_ZVE32F, "(Zve32f) Embedded Vector Floating Point (f32)" },
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{ RISCV_ISA_EXT_ZVE64X, "(Zve64x) Embedded Vector Integer (64-bit elements)" },
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{ RISCV_ISA_EXT_ZVE64F, "(Zve64f) Embedded Vector Floating Point (f64)" },
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{ RISCV_ISA_EXT_ZVE64D, "(Zve64d) Embedded Vector Double-Precision FP (f64)" },
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{ RISCV_ISA_EXT_ZIMOP, "(Zimop) Integer Multiply-Only Instructions" },
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{ RISCV_ISA_EXT_ZCA, "(Zca) Compressed Integer Instructions" },
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{ RISCV_ISA_EXT_ZCB, "(Zcb) Compressed Bit-Manipulation Instructions" },
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{ RISCV_ISA_EXT_ZCD, "(Zcd) Compressed Double-Precision FP Instructions" },
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{ RISCV_ISA_EXT_ZCF, "(Zcf) Compressed Single-Precision FP Instructions" },
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{ RISCV_ISA_EXT_ZCMOP, "(Zcmop) Compressed Multiply-Only Instructions" },
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{ RISCV_ISA_EXT_ZAWRS, "(Zawrs) Wait-on-Reservation-Set Instruction" },
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{ RISCV_ISA_EXT_SVVPTC, "(Svvptc) Supervisor Virtual Page Table Cache Control" },
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{ RISCV_ISA_EXT_SMMPM, "(Smmpm) Supervisor Memory Protection Modification" },
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{ RISCV_ISA_EXT_SMNPM, "(Smnpm) Supervisor Non-Privileged Memory Access Control" },
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{ RISCV_ISA_EXT_SSNPM, "(Ssnpm) Supervisor Secure Non-Privileged Memory" },
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{ RISCV_ISA_EXT_ZABHA, "(Zabha) Atomic Byte/Halfword Operations" },
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{ RISCV_ISA_EXT_ZICCRSE, "(Ziccrse) Cache Control Range Start/End Operations" },
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{ RISCV_ISA_EXT_SVADE, "(Svade) Supervisor Virtual Address Deferred Exception" },
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{ RISCV_ISA_EXT_SVADU, "(Svadu) Supervisor Virtual Address Dirty Update" },
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{ RISCV_ISA_EXT_ZFBFMIN, "(Zfbfmin) Minimal BFloat16 Floating Point" },
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{ RISCV_ISA_EXT_ZVFBFMIN, "(Zvfbfmin) Vector Minimal BFloat16 Floating Point" },
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{ RISCV_ISA_EXT_ZVFBFWMA, "(Zvfbfwma) Vector BFloat16 Widening Multiply-Accumulate" },
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{ RISCV_ISA_EXT_ZAAMO, "(Zaamo) Atomic Memory Operation (AMO) Instructions" },
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{ RISCV_ISA_EXT_ZALRSC, "(Zalrsc) Atomic Load-Reserved/Store-Conditional" },
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{ RISCV_ISA_EXT_ZICBOP, "(Zicbop) Cache Block Prefetch/Zero Operations" },
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{ RISCV_ISA_EXT_IME, "(Ime) Integrated Matrix Extension" },
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};
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struct cpuInfo* get_cpu_info(void);
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char* get_str_topology(struct cpuInfo* cpu, struct topology* topo);
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char* get_str_extensions(struct cpuInfo* cpu);
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uint32_t get_num_extensions(bool* mask);
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void print_debug(struct cpuInfo* cpu);
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#endif
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