Dr-Noob d8dad29a57 Fix SMT bug in AMD. I would like to improve it, since Intel can use APIC with 0x1 and 0xB (extended) while AMD does with 0x1 and extended seems to be 0x1E. Add support to detect more than one L3 cache. This is not a very elegant solution, since we still assume that we have the same number of caches as caches in a given level. To fix it, cpufetch should know how many caches are in a given level (hint, Linux knows using shared_cpu_map)

2020-08-29 15:42:56 +02:00

..

apic.c

Fix SMT bug in AMD. I would like to improve it, since Intel can use APIC with 0x1 and 0xB (extended) while AMD does with 0x1 and extended seems to be 0x1E. Add support to detect more than one L3 cache. This is not a very elegant solution, since we still assume that we have the same number of caches as caches in a given level. To fix it, cpufetch should know how many caches are in a given level (hint, Linux knows using shared_cpu_map)

2020-08-29 15:42:56 +02:00

apic.h

Complete topology read in AMD

2020-07-06 01:58:48 +02:00

args.c

Small corrections in code and Makefile

2020-07-12 15:39:34 +02:00

args.h

Support for 4 colors with --color (2 for ascii, 2 for text)

2020-07-03 09:42:30 +02:00

ascii.h

Add two different styles. The old one is now called retro, and the new one, which is the default, is called fancy

2020-07-02 18:53:28 +02:00

cpuid_asm.c

Big refactoring. Move ascii managment to printer. Mix extended and standart cpuid functions in cpuid file. Old cpuid renamed to cpuid_asm. Store cpu name in cpuInfo struct

2020-06-28 15:51:30 +02:00

cpuid_asm.h

Big refactoring. Move ascii managment to printer. Mix extended and standart cpuid functions in cpuid file. Old cpuid renamed to cpuid_asm. Store cpu name in cpuInfo struct

2020-06-28 15:51:30 +02:00

cpuid.c

Fix SMT bug in AMD. I would like to improve it, since Intel can use APIC with 0x1 and 0xB (extended) while AMD does with 0x1 and extended seems to be 0x1E. Add support to detect more than one L3 cache. This is not a very elegant solution, since we still assume that we have the same number of caches as caches in a given level. To fix it, cpufetch should know how many caches are in a given level (hint, Linux knows using shared_cpu_map)

2020-08-29 15:42:56 +02:00

cpuid.h

Fix SMT bug in AMD. I would like to improve it, since Intel can use APIC with 0x1 and 0xB (extended) while AMD does with 0x1 and extended seems to be 0x1E. Add support to detect more than one L3 cache. This is not a very elegant solution, since we still assume that we have the same number of caches as caches in a given level. To fix it, cpufetch should know how many caches are in a given level (hint, Linux knows using shared_cpu_map)

2020-08-29 15:42:56 +02:00

global.c

Add release and debug targets in Makefile. Improve robustness by checking cache sizes and snprintf returns

2020-06-21 13:37:44 +02:00

global.h

Improve error checking. Add partial support for verbose output

2020-06-20 19:21:07 +02:00

main.c

Fix SMT bug in AMD. I would like to improve it, since Intel can use APIC with 0x1 and 0xB (extended) while AMD does with 0x1 and extended seems to be 0x1E. Add support to detect more than one L3 cache. This is not a very elegant solution, since we still assume that we have the same number of caches as caches in a given level. To fix it, cpufetch should know how many caches are in a given level (hint, Linux knows using shared_cpu_map)

2020-08-29 15:42:56 +02:00

printer.c

Small corrections in code and Makefile

2020-07-12 15:39:34 +02:00

printer.h

Add legacy style (for Windows) and make it the default for Windows. Add verbose flag

2020-07-06 01:30:14 +02:00

udev.c

Big refactoring. Move ascii managment to printer. Mix extended and standart cpuid functions in cpuid file. Old cpuid renamed to cpuid_asm. Store cpu name in cpuInfo struct

2020-06-28 15:51:30 +02:00

udev.h

Add fallback in Linux in case we cant get the freq from cpuid, using udev (welcome back, udev...)

2020-06-22 12:05:04 +02:00