[v1.03][RISCV] Add support for RISCV extensions

src/riscv/riscv.c

@@ -28,6 +28,40 @@ int64_t get_peak_performance(struct cpuInfo* cpu) {
   return flops;
 }
 
+struct extensions* get_extensions_from_str(char* str) {
+  struct extensions* ext = emalloc(sizeof(struct extensions));
+  ext->mask = 0;
+  ext->str = NULL;
+
+  if(str == NULL) {
+    return ext;
+  }
+
+  int len = sizeof(char) * (strlen(str)+1);
+  ext->str = emalloc(sizeof(char) * len);
+  memset(ext->str, 0, len);
+  strncpy(ext->str, str, sizeof(char) * len);
+
+  // Code inspired in Linux kernel:
+  // https://elixir.bootlin.com/linux/v6.2.10/source/arch/riscv/kernel/cpufeature.c
+  char* isa = str;
+  if (!strncmp(isa, "rv32", 4))
+    isa += 4;
+  else if (!strncmp(isa, "rv64", 4))
+    isa += 4;
+  else {
+    printBug("get_extensions_from_str: ISA string must start with rv64 or rv32");
+    return ext;
+  }
+
+  for(char* e = isa; *e != '\0'; e++) {
+    int n = *e - 'a';
+    ext->mask |= 1UL << n;
+  }
+
+  return ext;
+}
+
 struct cpuInfo* get_cpu_info(void) {
   struct cpuInfo* cpu = malloc(sizeof(struct cpuInfo));
   //init_cpu_info(cpu);
@@ -37,8 +71,11 @@ struct cpuInfo* get_cpu_info(void) {
   cpu->topo = topo;
 
   char* cpuinfo_str = get_uarch_from_cpuinfo();
+  char* ext_str = get_extensions_from_cpuinfo();
   cpu->hv = emalloc(sizeof(struct hypervisor));
   cpu->hv->present = false;
+  cpu->ext = get_extensions_from_str(ext_str);
+  if(cpu->ext->str != NULL && cpu->ext->mask == 0) return NULL;
   cpu->arch = get_uarch_from_cpuinfo_str(cpuinfo_str, cpu);
   cpu->soc = get_soc();
   cpu->freq = get_frequency_info(0);
@@ -57,6 +94,9 @@ char* get_str_topology(struct cpuInfo* cpu, struct topology* topo) {
 }
 
 char* get_str_extensions(struct cpuInfo* cpu) {
+  if(cpu->ext != NULL) {
+    return cpu->ext->str;
+  }
   return NULL;
 }
 

src/riscv/riscv.h

@@ -3,6 +3,32 @@
 
 #include "../common/cpu.h"
 
+struct extension {
+  int id;
+  char* str;
+};
+
+// https://en.wikichip.org/wiki/risc-v/standard_extensions
+// Included all except for G
+static const struct extension extension_list[] = {
+  { 'i' - 'a', "(I) Integer Instruction Set" },
+  { 'm' - 'a', "(M) Integer Multiplication and Division" },
+  { 'a' - 'a', "(A) Atomic Instructions" },
+  { 'f' - 'a', "(F) Single-Precision Floating-Point" },
+  { 'd' - 'a', "(D) Double-Precision Floating-Point" },
+  { 'q' - 'a', "(Q) Quad-Precision Floating-Point" },
+  { 'l' - 'a', "(L) Decimal Floating-Point" },
+  { 'c' - 'a', "(C) Compressed Instructions" },
+  { 'b' - 'a', "(B) Double-Precision Floating-Point" },
+  { 'j' - 'a', "(J) Dynamically Translated Languages" },
+  { 't' - 'a', "(T) Transactional Memory" },
+  { 'p' - 'a', "(P) Packed-SIMD Instructions" },
+  { 'v' - 'a', "(V) Vector Operations" },
+  { 'n' - 'a', "(N) User-Level Interrupts" },
+  { 'h' - 'a', "(H) Hypervisor" },
+  { 's' - 'a', "(S) Supervisor-level Instructions" }
+};
+
 struct cpuInfo* get_cpu_info(void);
 char* get_str_topology(struct cpuInfo* cpu, struct topology* topo);
 char* get_str_extensions(struct cpuInfo* cpu);

src/riscv/udev.c

@@ -7,6 +7,7 @@
 #define _PATH_CPUINFO          "/proc/cpuinfo"
 #define _PATH_DEVTREE          "/proc/device-tree/compatible"
 #define CPUINFO_UARCH_STR      "uarch\t\t: "
+#define CPUINFO_EXTENSIONS_STR "isa\t\t: "
 #define DEVTREE_HARDWARE_FIELD 0
 
 char* get_field_from_devtree(int DEVTREE_FIELD) {
@@ -84,3 +85,8 @@ char* get_hardware_from_devtree(void) {
 char* get_uarch_from_cpuinfo(void) {
   return parse_cpuinfo_field(CPUINFO_UARCH_STR);
 }
+
+char* get_extensions_from_cpuinfo() {
+  return parse_cpuinfo_field(CPUINFO_EXTENSIONS_STR);
+}
+

src/riscv/udev.h

@@ -7,5 +7,6 @@
 
 char* get_hardware_from_devtree(void);
 char* get_uarch_from_cpuinfo(void);
+char* get_extensions_from_cpuinfo(void);
 
 #endif