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[v1.04][ARM] Add M3 number of SIMD VPUs
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@@ -392,6 +392,7 @@ int get_number_of_vpus(struct cpuInfo* cpu) {
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MICROARCH ua = cpu->arch->uarch;
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switch(ua) {
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case UARCH_EVEREST: // Just a guess, needs confirmation.
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case UARCH_FIRESTORM: // [https://dougallj.github.io/applecpu/firestorm-simd.html]
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case UARCH_AVALANCHE: // [https://en.wikipedia.org/wiki/Comparison_of_ARM_processors]
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case UARCH_CORTEX_X1: // [https://www.anandtech.com/show/15813/arm-cortex-a78-cortex-x1-cpu-ip-diverging/3]
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@@ -399,6 +400,7 @@ int get_number_of_vpus(struct cpuInfo* cpu) {
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case UARCH_CORTEX_X3: // [https://www.hwcooling.net/en/cortex-x3-the-new-fastest-arm-core-architecture-analysis: "The FPU and SIMD unit of the core still has four pipelines"]
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case UARCH_NEOVERSE_V1: // [https://en.wikichip.org/wiki/arm_holdings/microarchitectures/neoverse_v1]
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return 4;
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case UARCH_SAWTOOTH: // Needs confirmation, rn this is the best we know: https://mastodon.social/@dougall/111118317031041336
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case UARCH_EXYNOS_M3: // [https://www.anandtech.com/show/12361/samsung-exynos-m3-architecture]
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case UARCH_EXYNOS_M4: // [https://en.wikichip.org/wiki/samsung/microarchitectures/m4#Block_Diagram]
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case UARCH_EXYNOS_M5: // [https://en.wikichip.org/wiki/samsung/microarchitectures/m5]
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