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https://github.com/Dr-Noob/cpufetch.git
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[v1.06][X86] Add old Intel and AMD CPUs (#260)
* Add Intel and AMD 486, Intel Pentium Pro, and AMD K5 chips * Update infer_cpu_name_from_uarch to support added CPU uarches * Add sources for more of the legacy chip data * Add the more specific codename for Intel Pentium MMX Mobile chips * Document source of AMD 486/K5 variants * Add link to documentation for Intel 486 --------- Co-authored-by: Timothy Warren <tim@timshomepage.net>
This commit is contained in:
Timothy Warren
@@ -47,8 +47,10 @@ typedef uint32_t MICROARCH;
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enum {
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UARCH_UNKNOWN,
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// INTEL //
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UARCH_I486,
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UARCH_P5,
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UARCH_P5_MMX,
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UARCH_P6_PRO,
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UARCH_P6_PENTIUM_II,
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UARCH_P6_PENTIUM_III,
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UARCH_DOTHAN,
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@@ -97,6 +99,8 @@ enum {
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// AMD //
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UARCH_AM486,
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UARCH_AM5X86,
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UARCH_SSA5,
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UARCH_K5,
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UARCH_K6,
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UARCH_K7,
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UARCH_K8,
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@@ -149,16 +153,30 @@ struct uarch* get_uarch_from_cpuid_intel(uint32_t ef, uint32_t f, uint32_t em, u
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// ------------------------------------------------------------------------------- //
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// EF F EM M S //
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UARCH_START
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CHECK_UARCH(arch, 0, 4, 0, 0, NA, "i80486DX", UARCH_I486, UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
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CHECK_UARCH(arch, 0, 4, 0, 1, NA, "i80486DX-50", UARCH_I486, UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
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CHECK_UARCH(arch, 0, 4, 0, 2, NA, "i80486SX", UARCH_I486, UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
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CHECK_UARCH(arch, 0, 4, 0, 3, NA, "i80486DX2", UARCH_I486, UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
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CHECK_UARCH(arch, 0, 4, 0, 4, NA, "i80486SL", UARCH_I486, UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
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CHECK_UARCH(arch, 0, 4, 0, 5, NA, "i80486SX2", UARCH_I486, UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
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CHECK_UARCH(arch, 0, 4, 0, 7, NA, "i80486DX2WB", UARCH_I486, UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
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CHECK_UARCH(arch, 0, 4, 0, 8, NA, "i80486DX4", UARCH_I486, UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
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CHECK_UARCH(arch, 0, 4, 0, 9, NA, "i80486DX4WB", UARCH_I486, UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
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CHECK_UARCH(arch, 0, 5, 0, 0, NA, "P5", UARCH_P5, 800)
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CHECK_UARCH(arch, 0, 5, 0, 1, NA, "P5", UARCH_P5, 800)
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CHECK_UARCH(arch, 0, 5, 0, 2, NA, "P5", UARCH_P5, UNK)
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CHECK_UARCH(arch, 0, 5, 0, 3, NA, "P5", UARCH_P5, 600)
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CHECK_UARCH(arch, 0, 5, 0, 4, NA, "P5 (MMX)", UARCH_P5_MMX, UNK)
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CHECK_UARCH(arch, 0, 5, 0, 7, NA, "P5 (MMX)", UARCH_P5_MMX, UNK)
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CHECK_UARCH(arch, 0, 5, 0, 8, NA, "P5 (MMX)", UARCH_P5_MMX, 250)
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CHECK_UARCH(arch, 0, 5, 0, 2, NA, "P54C", UARCH_P5, UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
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CHECK_UARCH(arch, 0, 5, 0, 3, NA, "P24T (Overdrive)", UARCH_P5, 600) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
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CHECK_UARCH(arch, 0, 5, 0, 4, NA, "P55C (MMX)", UARCH_P5_MMX, 350) // https://www.cpu-world.com/CPUs/Pentium/TYPE-Pentium%20MMX.html
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CHECK_UARCH(arch, 0, 5, 0, 7, NA, "P54C", UARCH_P5, 350) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
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CHECK_UARCH(arch, 0, 5, 0, 8, NA, "Tillamook", UARCH_P5_MMX, 250) // http://instlatx64.atw.hu./
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CHECK_UARCH(arch, 0, 5, 0, 9, 0, "Lakemont", UARCH_LAKEMONT, 32)
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CHECK_UARCH(arch, 0, 5, 0, 9, NA, "P5 (MMX)", UARCH_P5_MMX, UNK)
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CHECK_UARCH(arch, 0, 5, 0, 10, 0, "Lakemont", UARCH_LAKEMONT, 32)
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CHECK_UARCH(arch, 0, 6, 0, 1, 1, "P6", UARCH_P6_PRO, UNK)
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CHECK_UARCH(arch, 0, 6, 0, 1, 2, "P6", UARCH_P6_PRO, UNK)
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CHECK_UARCH(arch, 0, 6, 0, 1, 6, "P6", UARCH_P6_PRO, 350)
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CHECK_UARCH(arch, 0, 6, 0, 1, 7, "P6", UARCH_P6_PRO, 350)
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CHECK_UARCH(arch, 0, 6, 0, 1, 9, "P6", UARCH_P6_PRO, 350)
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CHECK_UARCH(arch, 0, 6, 0, 0, NA, "P6 (Pentium II)", UARCH_P6_PENTIUM_II, UNK)
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CHECK_UARCH(arch, 0, 6, 0, 1, NA, "P6 (Pentium II)", UARCH_P6_PENTIUM_II, UNK) // process depends on core
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CHECK_UARCH(arch, 0, 6, 0, 2, NA, "P6 (Pentium II)", UARCH_P6_PENTIUM_II, UNK)
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@@ -279,11 +297,16 @@ struct uarch* get_uarch_from_cpuid_amd(uint32_t ef, uint32_t f, uint32_t em, uin
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// ----------------------------------------------------------------------------- //
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// EF F EM M S //
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UARCH_START
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CHECK_UARCH(arch, 0, 4, 0, 3, NA, "Am486", UARCH_AM486, UNK)
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CHECK_UARCH(arch, 0, 4, 0, 7, NA, "Am486", UARCH_AM486, UNK)
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CHECK_UARCH(arch, 0, 4, 0, 8, NA, "Am486", UARCH_AM486, UNK)
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CHECK_UARCH(arch, 0, 4, 0, 9, NA, "Am486", UARCH_AM486, UNK)
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CHECK_UARCH(arch, 0, 4, NA, NA, NA, "Am5x86", UARCH_AM5X86, UNK)
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CHECK_UARCH(arch, 0, 4, 0, 3, NA, "Am486DX2", UARCH_AM486, UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
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CHECK_UARCH(arch, 0, 4, 0, 7, NA, "Am486DX2WB", UARCH_AM486, UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
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CHECK_UARCH(arch, 0, 4, 0, 8, NA, "Am486DX4", UARCH_AM486, UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
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CHECK_UARCH(arch, 0, 4, 0, 9, NA, "Am486DX4WB", UARCH_AM486, UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
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CHECK_UARCH(arch, 0, 4, 0, 14, NA, "Am5x86", UARCH_AM5X86, 350) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
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CHECK_UARCH(arch, 0, 4, 0, 15, NA, "Am5x86WB", UARCH_AM5X86, 350) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
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CHECK_UARCH(arch, 0, 5, 0, 0, NA, "SSA5 (K5)", UARCH_SSA5, 350) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
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CHECK_UARCH(arch, 0, 5, 0, 1, NA, "K5", UARCH_K5, 350) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
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CHECK_UARCH(arch, 0, 5, 0, 2, NA, "K5", UARCH_K5, 350) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
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CHECK_UARCH(arch, 0, 5, 0, 3, NA, "K5", UARCH_K5, 350) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
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CHECK_UARCH(arch, 0, 5, 0, 6, NA, "K6", UARCH_K6, 300)
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CHECK_UARCH(arch, 0, 5, 0, 7, NA, "K6", UARCH_K6, 250) // *p from sandpile.org
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CHECK_UARCH(arch, 0, 5, 0, 10, NA, "K7", UARCH_K7, 130) // Geode NX
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@@ -479,16 +502,42 @@ char* infer_cpu_name_from_uarch(struct uarch* arch) {
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char *str = NULL;
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if (arch->uarch == UARCH_P5)
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str = "Intel Pentium";
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else if (arch->uarch == UARCH_P5_MMX)
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str = "Intel Pentium MMX";
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else if (arch->uarch == UARCH_P6_PENTIUM_II)
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str = "Intel Pentium II";
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else if (arch->uarch == UARCH_P6_PENTIUM_III)
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str = "Intel Pentium III";
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else
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printErr("Unable to find name from uarch: %d", arch->uarch);
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switch (arch->uarch) {
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// Intel
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case UARCH_I486:
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str = "Intel 486";
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break;
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case UARCH_P5:
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str = "Intel Pentium";
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break;
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case UARCH_P5_MMX:
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str = "Intel Pentium MMX";
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break;
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case UARCH_P6_PRO:
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str = "Intel Pentium Pro";
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break;
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case UARCH_P6_PENTIUM_II:
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str = "Intel Pentium II";
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break;
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case UARCH_P6_PENTIUM_III:
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str = "Intel Pentium III";
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break;
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// AMD
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case UARCH_AM486:
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str = "AMD 486";
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break;
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case UARCH_AM5X86:
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str = "AMD 5x86";
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break;
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case UARCH_SSA5:
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str = "AMD 5k86";
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break;
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default:
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printErr("Unable to find name from uarch: %d", arch->uarch);
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break;
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}
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if (str == NULL) {
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cpu_name = ecalloc(strlen(STRING_UNKNOWN) + 1, sizeof(char));
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