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Fix cache in AMD, using extended level

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Dr-Noob
2020-06-22 13:50:00 +02:00
parent 0725e9d876
commit 8211f24f46
2 changed files with 21 additions and 3 deletions
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2
src/main.c
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@@ -25,7 +25,7 @@ Peak FLOPS: 512 GFLOP/s(in simple precision)
***/
static const char* VERSION = "0.48";
static const char* VERSION = "0.49";
void print_help(int argc, char *argv[]) {
printf("Usage: %s [--version] [--help] [--style STYLE]\n\

22
src/standart.c
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@@ -29,6 +29,7 @@
/*
* cpuid reference: http://www.sandpile.org/x86/cpuid.htm
* cpuid amd: https://www.amd.com/system/files/TechDocs/25481.pdf
*/
struct cpuInfo {
@@ -258,17 +259,34 @@ struct topology* get_topology_info(struct cpuInfo* cpu) {
return topo;
}
// see https://stackoverflow.com/questions/12594208/c-program-to-determine-levels-size-of-cache
struct cache* get_cache_info(struct cpuInfo* cpu) {
struct cache* cach = malloc(sizeof(struct cache));
uint32_t eax = 0;
uint32_t ebx = 0;
uint32_t ecx = 0;
uint32_t edx = 0;
uint32_t level;
// We use standart 0x00000004 for Intel
// We use extended 0x8000001D for AMD
if(cpu->cpu_vendor == VENDOR_INTEL) {
level = 0x00000004;
if(cpu->maxLevels < level) {
printErr("Can't read cache information from cpuid (needed level is %d, max is %d)", level, cpu->maxLevels);
return NULL;
}
}
else {
level = 0x8000001D;
if(cpu->maxExtendedLevels < level) {
printErr("Can't read cache information from cpuid (needed extended level is %d, max is %d)", level, cpu->maxExtendedLevels);
return NULL;
}
}
// We suppose there are 4 caches (at most)
for(int i=0; i < 4; i++) {
eax = 4; // get cache info
eax = level; // get cache info
ebx = 0;
ecx = i; // cache id
edx = 0;