[v1.04][RISCV] Define to enum

src/riscv/riscv.h

@@ -29,35 +29,34 @@ static const struct extension extension_list[] = {
   { 's' - 'a', "(S) Supervisor-level Instructions" }
 };
 
-#define RISCV_ISA_EXT_MAX	64
+#define RISCV_ISA_EXT_MAX	   64
 #define RISCV_ISA_EXT_NAME_LEN_MAX 32
-#define RISCV_ISA_EXT_BASE 26
+#define RISCV_ISA_EXT_BASE         26
 
 // This enum represent the logical ID for multi-letter RISC-V ISA extensions.
 // The logical ID should start from RISCV_ISA_EXT_BASE and must not exceed
 // RISCV_ISA_EXT_MAX.
-#define RISCV_ISA_EXT_BASE		26
+enum riscv_isa_ext_id {
-
+  RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE,
-#define RISCV_ISA_EXT_SSCOFPMF		26
+  RISCV_ISA_EXT_SSTC,
-#define RISCV_ISA_EXT_SSTC		27
+  RISCV_ISA_EXT_SVINVAL,
-#define RISCV_ISA_EXT_SVINVAL		28
+  RISCV_ISA_EXT_SVPBMT,
-#define RISCV_ISA_EXT_SVPBMT		29
+  RISCV_ISA_EXT_ZBB,
-#define RISCV_ISA_EXT_ZBB		30
+  RISCV_ISA_EXT_ZICBOM,
-#define RISCV_ISA_EXT_ZICBOM		31
+  RISCV_ISA_EXT_ZIHINTPAUSE,
-#define RISCV_ISA_EXT_ZIHINTPAUSE	32
+  RISCV_ISA_EXT_SVNAPOT,
-#define RISCV_ISA_EXT_SVNAPOT		33
+  RISCV_ISA_EXT_ZICBOZ,
-#define RISCV_ISA_EXT_ZICBOZ		34
+  RISCV_ISA_EXT_SMAIA,
-#define RISCV_ISA_EXT_SMAIA		35
+  RISCV_ISA_EXT_SSAIA,
-#define RISCV_ISA_EXT_SSAIA		36
+  RISCV_ISA_EXT_ZBA,
-#define RISCV_ISA_EXT_ZBA		37
+  RISCV_ISA_EXT_ZBS,
-#define RISCV_ISA_EXT_ZBS		38
+  RISCV_ISA_EXT_ZICNTR,
-#define RISCV_ISA_EXT_ZICNTR		39
+  RISCV_ISA_EXT_ZICSR,
-#define RISCV_ISA_EXT_ZICSR		40
+  RISCV_ISA_EXT_ZIFENCEI,
-#define RISCV_ISA_EXT_ZIFENCEI		41
+  RISCV_ISA_EXT_ZIHPM,
-#define RISCV_ISA_EXT_ZIHPM		42
+  RISCV_ISA_EXT_ID_MAX
-
+};
-#define RISCV_ISA_EXT_MAX		64
+static_assert(RISCV_ISA_EXT_ID_MAX <= RISCV_ISA_EXT_MAX);
-#define RISCV_ISA_EXT_NAME_LEN_MAX	32
 
 struct cpuInfo* get_cpu_info(void);
 char* get_str_topology(struct cpuInfo* cpu, struct topology* topo);