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[v1.04][RISCV] Add multi-letter extensions to list

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Dr-Noob
2023-09-22 21:39:17 +01:00
parent a12defaf4b
commit bd3c66395d
2 changed files with 58 additions and 40 deletions
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31
src/riscv/riscv.c
View File

@@ -48,21 +48,22 @@ int parse_multi_letter_extension(struct extensions* ext, char* e) {
char* multi_letter_extension = emalloc(multi_letter_extension_len); char* multi_letter_extension = emalloc(multi_letter_extension_len);
strncpy(multi_letter_extension, e+1, multi_letter_extension_len); strncpy(multi_letter_extension, e+1, multi_letter_extension_len);
// TODO: Add more extensions // This should be up-to-date with
// https://en.wikipedia.org/wiki/RISC-V // https://elixir.bootlin.com/linux/latest/source/arch/riscv/kernel/cpufeature.c
SET_ISA_EXT_MAP("smaia", RISCV_ISA_EXT_SMAIA); // which should represent the list of extensions available in real chips
SET_ISA_EXT_MAP("ssaia", RISCV_ISA_EXT_SSAIA); SET_ISA_EXT_MAP("smaia", RISCV_ISA_EXT_SMAIA)
SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF); SET_ISA_EXT_MAP("ssaia", RISCV_ISA_EXT_SSAIA)
SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC); SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF)
SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL); SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC)
SET_ISA_EXT_MAP("svnapot", RISCV_ISA_EXT_SVNAPOT); SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL)
SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT); SET_ISA_EXT_MAP("svnapot", RISCV_ISA_EXT_SVNAPOT)
SET_ISA_EXT_MAP("zba", RISCV_ISA_EXT_ZBA); SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT)
SET_ISA_EXT_MAP("zbb", RISCV_ISA_EXT_ZBB); SET_ISA_EXT_MAP("zba", RISCV_ISA_EXT_ZBA)
SET_ISA_EXT_MAP("zbs", RISCV_ISA_EXT_ZBS); SET_ISA_EXT_MAP("zbb", RISCV_ISA_EXT_ZBB)
SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM); SET_ISA_EXT_MAP("zbs", RISCV_ISA_EXT_ZBS)
SET_ISA_EXT_MAP("zicboz", RISCV_ISA_EXT_ZICBOZ); SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM)
SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE); SET_ISA_EXT_MAP("zicboz", RISCV_ISA_EXT_ZICBOZ)
SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE)
else { else {
printBug("parse_multi_letter_extension: Unknown multi-letter extension: %s", multi_letter_extension); printBug("parse_multi_letter_extension: Unknown multi-letter extension: %s", multi_letter_extension);
return -1; return -1;

67
src/riscv/riscv.h
View File

@@ -8,34 +8,12 @@ struct extension {
char* str; char* str;
}; };
// https://en.wikichip.org/wiki/risc-v/standard_extensions
// Included all except for G
static const struct extension extension_list[] = {
{ 'i' - 'a', "(I) Integer Instruction Set" },
{ 'm' - 'a', "(M) Integer Multiplication and Division" },
{ 'a' - 'a', "(A) Atomic Instructions" },
{ 'f' - 'a', "(F) Single-Precision Floating-Point" },
{ 'd' - 'a', "(D) Double-Precision Floating-Point" },
{ 'q' - 'a', "(Q) Quad-Precision Floating-Point" },
{ 'l' - 'a', "(L) Decimal Floating-Point" },
{ 'c' - 'a', "(C) Compressed Instructions" },
{ 'b' - 'a', "(B) Double-Precision Floating-Point" },
{ 'j' - 'a', "(J) Dynamically Translated Languages" },
{ 't' - 'a', "(T) Transactional Memory" },
{ 'p' - 'a', "(P) Packed-SIMD Instructions" },
{ 'v' - 'a', "(V) Vector Operations" },
{ 'n' - 'a', "(N) User-Level Interrupts" },
{ 'h' - 'a', "(H) Hypervisor" },
{ 's' - 'a', "(S) Supervisor-level Instructions" }
};
#define RISCV_ISA_EXT_MAX 64
#define RISCV_ISA_EXT_NAME_LEN_MAX 32 #define RISCV_ISA_EXT_NAME_LEN_MAX 32
#define RISCV_ISA_EXT_BASE 26 #define RISCV_ISA_EXT_BASE 26
// https://elixir.bootlin.com/linux/latest/source/arch/riscv/include/asm/hwcap.h
// This enum represent the logical ID for multi-letter RISC-V ISA extensions. // This enum represent the logical ID for multi-letter RISC-V ISA extensions.
// The logical ID should start from RISCV_ISA_EXT_BASE and must not exceed // The logical ID should start from RISCV_ISA_EXT_BASE
// RISCV_ISA_EXT_MAX.
enum riscv_isa_ext_id { enum riscv_isa_ext_id {
RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE, RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE,
RISCV_ISA_EXT_SSTC, RISCV_ISA_EXT_SSTC,
@@ -56,7 +34,46 @@ enum riscv_isa_ext_id {
RISCV_ISA_EXT_ZIHPM, RISCV_ISA_EXT_ZIHPM,
RISCV_ISA_EXT_ID_MAX RISCV_ISA_EXT_ID_MAX
}; };
static_assert(RISCV_ISA_EXT_ID_MAX <= RISCV_ISA_EXT_MAX);
// https://five-embeddev.com/riscv-isa-manual/latest/preface.html#preface
// https://en.wikichip.org/wiki/risc-v/standard_extensions
// Included all except for G
static const struct extension extension_list[] = {
{ 'i' - 'a', "(I) Integer Instruction Set" },
{ 'm' - 'a', "(M) Integer Multiplication and Division" },
{ 'a' - 'a', "(A) Atomic Instructions" },
{ 'f' - 'a', "(F) Single-Precision Floating-Point" },
{ 'd' - 'a', "(D) Double-Precision Floating-Point" },
{ 'q' - 'a', "(Q) Quad-Precision Floating-Point" },
{ 'l' - 'a', "(L) Decimal Floating-Point" },
{ 'c' - 'a', "(C) Compressed Instructions" },
{ 'b' - 'a', "(B) Double-Precision Floating-Point" },
{ 'j' - 'a', "(J) Dynamically Translated Languages" },
{ 't' - 'a', "(T) Transactional Memory" },
{ 'p' - 'a', "(P) Packed-SIMD Instructions" },
{ 'v' - 'a', "(V) Vector Operations" },
{ 'n' - 'a', "(N) User-Level Interrupts" },
{ 'h' - 'a', "(H) Hypervisor" },
{ 's' - 'a', "(S) Supervisor-level Instructions" },
// multi-letter extensions
{ RISCV_ISA_EXT_SSCOFPMF, "(Sscofpmf) Count OverFlow and Privilege Mode Filtering" },
{ RISCV_ISA_EXT_SSTC, "(Sstc) S and VS level Time Compare" },
{ RISCV_ISA_EXT_SVINVAL, "(Svinval) Fast TLB Invalidation" },
{ RISCV_ISA_EXT_SVPBMT, "(Svpbmt) Page-based Memory Types" },
{ RISCV_ISA_EXT_ZBB, "(Zbb) Basic bit-manipulation" },
{ RISCV_ISA_EXT_ZICBOM, "(Zicbom) Cache Block Management Operations" },
{ RISCV_ISA_EXT_ZIHINTPAUSE, "(Zihintpause) Pause Hint" },
{ RISCV_ISA_EXT_SVNAPOT, "(Svnapot) Naturally Aligned Power of Two Pages" },
{ RISCV_ISA_EXT_ZICBOZ, "(Zicboz) Cache Block Zero Operations" },
{ RISCV_ISA_EXT_SMAIA, "(Smaia) Advanced Interrupt Architecture" },
{ RISCV_ISA_EXT_SSAIA, "(Ssaia) Advanced Interrupt Architecture" },
{ RISCV_ISA_EXT_ZBA, "(Zba) Address Generation" },
{ RISCV_ISA_EXT_ZBS, "(Zbs) Single-bit Instructions" },
{ RISCV_ISA_EXT_ZICNTR, "(Zicntr) Base Counters and Timers" },
{ RISCV_ISA_EXT_ZICSR, "(Zicsr) Control and Status Register" },
{ RISCV_ISA_EXT_ZIFENCEI, "(Zifencei) Instruction-Fetch Fence" },
{ RISCV_ISA_EXT_ZIHPM, "(Zihpm) Hardware Performance Counters" }
};
struct cpuInfo* get_cpu_info(void); struct cpuInfo* get_cpu_info(void);
char* get_str_topology(struct cpuInfo* cpu, struct topology* topo); char* get_str_topology(struct cpuInfo* cpu, struct topology* topo);