Dr-Noob
220dd02abd
[v0.89][ARM] Add very basic SoC parsing from cpuinfo/android strings. Only detects two SoCs, but allows debugging
2020-11-24 11:44:24 +01:00
Dr-Noob
685e78f2b7
[v0.88][ARM][BUGFIX] Fix bugs in single CPU SoCs and small bugs related to strings
2020-11-24 10:27:33 +01:00
Dr-Noob
71d660d7b1
[v0.88][ARM] Fetch raw soc name from cpuinfo or android (if supported)
2020-11-24 10:03:21 +01:00
Dr-Noob
bb05a4d577
[v0.88][ARM][BUGFIX] Fix some compilation issues
2020-11-23 18:45:42 +01:00
Dr-Noob
eaa86522a4
[v0.88][ARM] Add very basic SoC detection (Android only)
2020-11-23 18:30:00 +01:00
Dr-Noob
716706d0a7
[v0.88][ARM][BUGFIX] Fetch number of cores from /sys/devices/system/cpu/present file, instead of /proc/cpuinfo. Pay attention to cases where frequency and/or MIDR can not be fetched from cpuinfo. This happens when the CPU has offline cores
2020-11-22 15:18:15 +01:00
Dr-Noob
fcb2c716db
[v0.87][FREQ] Frequency in udev is now fetched as a per core basis. Before this commit, freq was always fetched from core 0. This allows ARM do detect the max frequency of each of the cores (which may or may not be the same in all of them)
2020-11-22 10:23:02 +01:00
Dr-Noob
0875c4d425
[v0.87][ARM] cpuInfo now holds all the structs (freq, cache, etc), instead of having them separated. This allows ARM to represent a single CPU, because from its pointer, it is able to access the specific frequency, cache, etc
2020-11-22 09:57:50 +01:00
Dr-Noob
5b0cbd622f
[v0.87][BUGFIX] Add checks to detect wrong ASCII arts. Fix ARM ASCII art
2020-11-21 19:21:19 +01:00
Dr-Noob
0b9f0e860c
[v0.87][PRINTER] ASCII art attributes are no longer fixed in a given position, and are not fixed in length (max length is now 100). Added different algorithms for printing ASCII art for X86 and ARM, which allows ARM to show each CPU inside a SoC
2020-11-21 19:04:57 +01:00
Dr-Noob
50931ee94d
[v0.86][BUGFIX] Fix print format for hex values
2020-11-21 16:45:51 +01:00
Dr-Noob
42ade63746
[v0.86][BUGFIX] Add old AMD CPUs cache fix to master branch
2020-11-21 16:41:08 +01:00
Dr-Noob
e4a4e13d56
[v0.82][BUGFIX] Using 0x80000006 in new AMD CPUs outputs wrong L3 size since it reports the full size instead the size of a single L3. Use old method just when is necessary
2020-11-21 16:37:51 +01:00
Dr-Noob
7d707916fb
[v0.86][OPTIONS] Replace levels option with debug option, which does the same on x86, but also exists on ARM, which prints MIDR registers (need work to be properly implemented)
2020-11-18 23:41:42 +01:00
Dr-Noob
c44a646cd1
[v0.85][ARM] Add SoC field in ARM and remove CPU Name field, which is only valid in x86. Fix Makefile for some strict compilers
2020-11-18 23:22:26 +01:00
Dr-Noob
8c11cb2422
[v0.84][ARM] Add ISA field in ARM. ISA depends on uarch, not on specific CPU. Fill all the missing data in uarch.c
2020-11-14 11:11:32 +01:00
Dr-Noob
27aabb35be
[v0.84][BUGFIX] Fix compilation issues
2020-11-10 18:51:13 +01:00
Dr-Noob
904cb46765
[v0.84][ARM] Add lots of new microarch detection
2020-11-10 18:50:32 +01:00
Dr-Noob
3aa13269b7
[v0.83][ARM] Add basic support for microarchitecture and CPU name detection. Need to add the remaining models
2020-11-08 16:49:01 +01:00
Dr-Noob
b978ddc83d
[v0.82][BUGFIX] Issue #33 : Use 0x80000006 for cache fetching in AMD, instead of 0x8000001D. This means that a different approach in Intel and AMD CPUs
2020-11-07 10:48:48 +01:00
Dr-Noob
9c8e169592
[v0.82][ARM][ASCII][Refactoring] ARM ascii changes. Remove the assumption that all sockets are equal in a ARM based SoC. Little more support for ARM processors. Add ARM color style
2020-11-06 10:06:13 +01:00
Dr-Noob
4f1722ead6
[v0.81][ARM][Refactoring] Refactoring and very basic ARM support
2020-11-05 13:44:46 +01:00
Dr-Noob
f4f68287aa
[v0.8][Refactoring] Refactoring ARM code and source code tree
2020-11-05 11:01:46 +01:00
Dr-Noob
1fad4fd10b
[v0.8][ARM] Building support in ARM
2020-11-05 09:28:41 +01:00
Dr-Noob
5cc9038f3d
Fix peak performance in KNL
2020-10-20 21:13:04 +02:00
Dr-Noob
ac86be2d7a
Fix bug in Windows where specifying a style while using a terminal that supports color does not enable the color support, so colors do not show correctly
2020-10-20 20:43:14 +02:00
Wunkolo
9867754d08
Implement VT100 escape-code detection for Windows
...
Latest versions of windows have support for the parsing VT100 escape
code sequences, allowing for terminal colors similar to Linux.
https://docs.microsoft.com/en-us/windows/console/console-virtual-terminal-sequences#screen-colors
Here I have it get the console mode, set the
`ENABLE_VIRTUAL_TERMINAL_PROCESSING` flag, and then grab the console
mode again to both verify that VT100 escape sequences are supported and
that it is enabled after setting it to determine if the printer should
allow for fancy-color mode.
2020-10-17 18:46:20 -07:00
Dr-Noob
5119ece0dd
Refactoring defines to enums
2020-10-14 10:55:46 +02:00
Dr-Noob
e37c7d9ae0
Basic support for virtual machines
2020-10-11 23:27:19 +02:00
Dr-Noob
500ccfa871
Stable version 0.7 heavily tested in many different CPUs
2020-09-01 20:44:48 +02:00
Dr-Noob
877833db0a
Dont fetch if smt is enabled if its not supported (AMD). Dont guess cache topology, fetch it from CPUID (AMD)
2020-09-01 13:08:44 +02:00
Dr-Noob
5cca6df218
Fix memory leaks. Add debug message when microarch is unknown
2020-09-01 11:32:08 +02:00
Dr-Noob
de8952b4ea
Fix bug which caused you couldnt use --version. Change --style to be more user friendly. Update --help
2020-09-01 11:00:11 +02:00
Dr-Noob
1f80566f63
New info to be displayed (uarch and process) instead of other info (sha, aes, sse)
2020-09-01 09:37:53 +02:00
Dr-Noob
ab1416563c
Fix PP in Ice Lake
2020-08-31 18:27:32 +02:00
Dr-Noob
1a9c0546f2
Add support for detecting AMD microarch
2020-08-31 15:56:21 +02:00
Dr-Noob
35efdd8f2c
Fix #26 . Guess number of VPUs according to microarchitecture
2020-08-31 14:04:41 +02:00
Dr-Noob
5148962fa3
Add code to detect CPU microarchitecture (Intel only, at the moment)
2020-08-31 13:18:25 +02:00
Dr-Noob
d998acdcdf
Fix #25 : Compute PP taking into account the number of sockets
2020-08-31 09:33:39 +02:00
Dr-Noob
81a45628f0
Code refactoring. Forgot to add verbose option to help
2020-08-30 13:55:37 +02:00
Dr-Noob
4f98a5bccf
Refactor previous commit
2020-08-30 12:42:38 +02:00
Dr-Noob
dae0f678ad
Fix #23 . I tried fetching the cache topology in AMD but could not find a proper way, so the code fallback to two commits ago. cpufetch has to guess cache sizes except L3, which can be fetched. Since I have been trying many approaches and stuff, the code needs to be refactored
2020-08-30 12:12:25 +02:00
Dr-Noob
69cc08759a
Fix #21 and #22 : Obtain the number of caches of every level instead of guessing them. It is done by fetching cache topology from apic. It works, but it needs a big refactoring. Moreover, it currently works only on Intel CPUs, so this breaks the cache in AMD.
2020-08-29 21:51:14 +02:00
Dr-Noob
d8dad29a57
Fix SMT bug in AMD. I would like to improve it, since Intel can use APIC with 0x1 and 0xB (extended) while AMD does with 0x1 and extended seems to be 0x1E. Add support to detect more than one L3 cache. This is not a very elegant solution, since we still assume that we have the same number of caches as caches in a given level. To fix it, cpufetch should know how many caches are in a given level (hint, Linux knows using shared_cpu_map)
2020-08-29 15:42:56 +02:00
Dr-Noob
ad6c3c88ce
Small corrections in code and Makefile
2020-07-12 15:39:34 +02:00
Dr-Noob
e114bde128
Complete topology read in AMD
2020-07-06 01:58:48 +02:00
Dr-Noob
7164409ca2
Add legacy style (for Windows) and make it the default for Windows. Add verbose flag
2020-07-06 01:30:14 +02:00
Dr-Noob
08f79bb914
Fix compilation in Windows and add support for bind to specific cores. Separate APIC code in other file
2020-07-06 01:16:59 +02:00
Dr-Noob
b457c86100
Add support for obtaining topology in old processors (with CPUID less than 0xB)
2020-07-05 19:59:55 +02:00
Dr-Noob
e5d86289b5
Use APIC to obtain topology. This is interesting because this will allow us to obtain it even on older CPUs (without CPUID 0xB) (will be added in future commits)
2020-07-05 16:52:41 +02:00
