Commit Graph

609 Commits

Author SHA1 Message Date
Dr-Noob
c4a7761a12 Add description for missign extensions 2025-10-30 19:28:34 +01:00
Dr-Noob
d36123a363 Completing extension strings... 2025-10-30 09:07:04 +01:00
Dr-Noob
8f40c45211 Fixes 2025-10-30 08:49:25 +01:00
Dr-Noob
6713af7de1 Fixes 2025-10-30 08:49:07 +01:00
Dr-Noob
9bd50264b3 Fixes 2025-10-30 08:36:50 +01:00
Dr-Noob
bdadac5dd8 Fixes 2025-10-30 08:35:58 +01:00
Dr-Noob
e823c769ff Attempting to replace 64-bit mask with bool array 2025-10-30 08:33:27 +01:00
Dr-Noob
2116f19073 Delete repeated entry 2025-10-30 07:48:21 +01:00
Dr-Noob
8ce24150e7 Add IME 2025-10-29 22:44:22 +01:00
Dr-Noob
a0cb54dc8b Add IME 2025-10-29 22:43:50 +01:00
Dr-Noob
8e6b0b1a2b Crazy amount of new extensions! 2025-10-29 22:39:22 +01:00
Dr-Noob
5bddbc6b06 [v1.06] Reorganize attributes in printer
This follows the same approach of gpufetch (in
6589de971750b7f4e52c0c35c031fe6204cefdba) where, instead of having a
separate struct for long and short names, both gets merged in a single
struct (ATTRIBUTE_INFO)

This indirectly fixes a bug in RISC-V printer where, if the output
was too large and the short name was selected, it could try to print
an out-of-bound value when accessing the ATTRIBUTE_PEAK. The reason is
that the long and short structures didnt have the same length (because
one attribute name was missing in the short struct). This is now fixed
since we have combined both long and short attribute names.

commit 6e8cccde32
Author: Dr-Noob <peibolms@gmail.com>
Date:   Wed Oct 29 21:54:38 2025 +0100

    Reorganize attributes in printer
2025-10-29 22:08:44 +01:00
Dr-Noob
a0c08ccc0b [v1.06][RISCV] Add support for SpacemiT K1-X SoC (#286) 2024-10-10 08:39:24 +01:00
Dr-Noob
65c75eb443 [v1.06][RISCV] Support for fetching mvendorid, marchid and mimpid (#286)
Getting these 3 RISC-V cpuinfo fields allows the detection of
microarchitecture (and other information), extending the RISC-V
detection capabilities. In particular, this is used here to detect
the marchid of Spacemit X60 uarch.

This commit also changes how the microarchitecture is fetched
(i.e., get_uarch) so that it does not rely only in the uarch field
in cpuinfo, but also on the marchid value.
2024-10-10 08:37:12 +01:00
Dr-Noob
2df8aa8217 [v1.06][X86] Warn the users whenever they use a VM (#293) 2024-10-09 08:52:47 +01:00
Dr-Noob
a5d52b59df [v1.06] Nit: Fix warning due to missing newline at the end of file 2024-10-09 08:29:51 +01:00
Dr-Noob
f09454d442 [v1.06][X86] Fix CPUID 000806EC clash (#298) 2024-10-07 08:30:30 +01:00
Dr-Noob
01406778be [v1.06][ARM] Add new Dimensity MTK SoCs (#288) 2024-09-22 22:13:50 +01:00
Dr-Noob
7d786ca1b7 [v1.06][ARM] Implement automatic SoC inferring from device tree
This is a major change in the SoC detection methodology.

Previous to this commit, the SoC (model, vendor and manufacturing
process) would only appear if the exact model was found in the LUT.
In other words, every supported SoC must be added manually to the LUT.
This would allow to show the precise SoC model and the manufacturing
process, which can only be hardcoded (i.e., it cannot be dynamically
determined).

This commit introduces guess_raw_soc_from_devtree, a new way of
inferring the SoC. This simply reads from the compatible file in the
device tree and tries to find a matching vendor to that string. If
there is a match, then we simply copy the model also from the
compatible string and show it directly.

This new implementation will show a less "precise" SoC name and
no manufacturing process because there would be no hardcoded value for
that SoC. However, it improves the scalability of the SoC detection
significantly because there is no longer a need to hardcode every
single SoC.

Lastly, there are some SoC vendors intentionally left outside the
scope of this function: For now I prefer to keep updating manually
the LUT for those to ensure the highest quality detection (e.g.,
showing precise SoC name and manufacturing process).
2024-09-22 17:11:31 +01:00
Dr-Noob
2e2e660b97 [v1.06][ARM] Add more NVIDIA SoCs 2024-09-12 08:08:53 +01:00
Dr-Noob
fbd50822cf [v1.06][ARM] Add more Marvell SoCs 2024-09-12 07:51:12 +01:00
Dr-Noob
bc8a779de6 [v1.06][ARM] Add more Amlogic SoCs 2024-09-11 18:38:56 +01:00
Dr-Noob
995ebc6736 [v1.06][RISCV] Add zicbop multi-letter extension (fixes #285) 2024-09-11 07:58:12 +01:00
Dr-Noob
ab43a11ef2 [v1.06][X86] Fix accurate-pp in hybrid architectures (fixes #169)
Overview of changes:
- Adds field max_pp in frequency struct to hold the max freq for peak-performance estimation.
- Instead of getting the max frequency in get_peak_performance, we get it in get_cpu_info (more natural).
- Adds fill_frequency_info_pp which fills the max_pp of the passed cpu by calling measure_frequency.

The approach is to call measure_frequency with a vector where the max frequencies are stored. Then,
the first time measure_frequency is called, the frequency is measured while running all the cores,
and the max frequency is computed per module (e.g., in the case of 2 modules, we would compute
the freq for the first and for the second module), and saved into this vector. Subsequent calls to
measure_frequency will just read the corresponding value for the vector. In other words, the frequency
is only measured once for the whole CPU.
2024-09-10 22:43:23 +01:00
Wunk
edbfc9722e [v1.06][ARM] Add Windows on Arm support (#273) 2024-09-10 09:40:46 +02:00
Dr-Noob
57bbe2de4f [v1.06][X86] Add Sapphire Rapids uarch (#281) 2024-09-10 08:32:18 +01:00
Dr-Noob
278efb75c9 [v1.06][ARM] Add support for Marvell SoC (#279) 2024-09-10 07:41:11 +01:00
Dr-Noob
343150e516 [v1.06][ARM] Add Tegra Orin (#275) 2024-09-09 08:19:18 +01:00
Dr-Noob
1e2c7e565c [v1.06][ARM] Add SC8280XP (on device tree) (#272) 2024-09-09 07:11:57 +01:00
Dr-Noob
977c35a9af [v1.06][X86] Add Zen5 uarch 2024-09-05 20:14:52 +01:00
Dr-Noob
eb8fad2843 [v1.06][ARM] Simplify is_ARMv8_or_newer 2024-09-02 08:27:58 +01:00
Dr-Noob
bd38951439 [v1.06][ARM] Update get_vpus_width to match SVE detection 2024-09-02 08:26:58 +01:00
Dr-Noob
057a36efd5 [v1.06][ARM] Add new microarchitectures 2024-09-02 08:20:40 +01:00
Dr-Noob
56901d70ab [v1.06][ARM] Add more NXP SoCs 2024-08-31 18:40:35 +01:00
Dr-Noob
5bd507e4b6 [v1.06][ARM] Add support for Amlogic A311D (#268) 2024-08-31 09:37:50 +01:00
Dr-Noob
9192ba3eb8 [v1.06][ARM] Add (another) cpufamily for M3 and set the ARM version, fixing peak performance wrong result (#230) 2024-08-29 08:13:05 +01:00
Dr-Noob
807a13d29e [v1.06] Fix manpage file extension (fixes #269) 2024-08-28 21:33:48 +01:00
Dr-Noob
15a803dae5 [v1.06][ARM] Check if HWCAP2_SVE2 is defined before using it (fixes #270) 2024-08-28 21:26:27 +01:00
Dr-Noob
0507355372 [v1.06][X86] Bugfix: set affinity in --accurate-pp
There are cases where measure_frequency is called after binding the
process to a specific core via bind_to_cpu (e.g., when iterating over
modules in hybrid architectures). Thus, in measure_frequency we must
set the affinity of the newly created threads, ensuring they are
binded to the right core.
2024-08-26 12:31:18 +01:00
Dr-Noob
9f66a137c5 [v1.06][ARM] Add support for NXP i.MX 8M Plus (#261) 2024-08-25 17:44:29 +01:00
Dr-Noob
324d0fbe94 [v1.06][PPC] Add support for Espresso (#231) 2024-08-25 16:50:58 +01:00
Dr-Noob
af8bb16302 [v1.06][ARM] Fix for commit 025e28c 2024-08-24 15:44:06 +01:00
Dr-Noob
40374121b8 [v1.06] Replace emalloc+memset with ecalloc when possible. Refactor some memory allocation code 2024-08-24 15:32:33 +01:00
Dr-Noob
025e28c516 [v1.06][ARM] Set Android properties as defines 2024-08-24 14:47:34 +01:00
Dr-Noob
7ad19d113c [v1.06] Remove soc_ prefix from field names in system_on_chip struct 2024-08-24 12:44:24 +01:00
Dr-Noob
13605ed0ce [v1.06][ARM] Remove BCM prefix from Broadcom vendor string 2024-08-24 12:34:57 +01:00
Dr-Noob
7689355a72 [v1.06][ARM] Add support for Apple SoCs in Asahi Linux (#263) 2024-08-23 08:37:13 +01:00
Timothy Warren
321a1ec375 [v1.06][X86] Add old Intel and AMD CPUs (#260)
* Add Intel and AMD 486, Intel Pentium Pro, and AMD K5 chips
* Update infer_cpu_name_from_uarch to support added CPU uarches
* Add sources for more of the legacy chip data
* Add the more specific codename for Intel Pentium MMX Mobile chips
* Document source of AMD 486/K5 variants
* Add link to documentation for Intel 486

---------

Co-authored-by: Timothy Warren <tim@timshomepage.net>
2024-08-20 09:25:01 +02:00
Dr-Noob
48c598cf3b [v1.06][ARM] Add support for Ampere Altra (#262) 2024-08-19 08:46:07 +01:00
Dr-Noob
aa94389bbe [v1.06][ARM] Fix two off-by-one bugs (#264) 2024-08-19 08:39:52 +01:00