[v1.06][ARM] Add SC8280XP (on device tree) (#272)

Makefile

@@ -70,27 +70,12 @@ $(error Aborting compilation)
 
 	OUTPUT=cpufetch
 else
-	arch := $(shell cc -dumpmachine)
+	# Assume x86_64
-	arch := $(firstword $(subst -, ,$(arch)))
-
-	ifeq ($(arch), $(filter $(arch), x86_64 amd64 i386 i486 i586 i686))
-		SRC_DIR=src/x86/
-		SOURCE += $(COMMON_SRC) $(SRC_DIR)cpuid.c $(SRC_DIR)apic.c $(SRC_DIR)cpuid_asm.c $(SRC_DIR)uarch.c
-		HEADERS += $(COMMON_HDR) $(SRC_DIR)cpuid.h $(SRC_DIR)apic.h $(SRC_DIR)cpuid_asm.h $(SRC_DIR)uarch.h
-		CFLAGS += -DARCH_X86 -std=c99
-	else ifeq ($(arch), $(filter $(arch), arm aarch64_be aarch64 arm64 armv8b armv8l armv7l armv6l))
-		SRC_DIR=src/arm/
-		SOURCE += $(COMMON_SRC) $(SRC_DIR)midr.c $(SRC_DIR)uarch.c $(SRC_COMMON)soc.c $(SRC_DIR)soc.c $(SRC_COMMON)pci.c $(SRC_DIR)udev.c sve.o
-		HEADERS += $(COMMON_HDR) $(SRC_DIR)midr.h $(SRC_DIR)uarch.h  $(SRC_COMMON)soc.h $(SRC_DIR)soc.h $(SRC_COMMON)pci.h $(SRC_DIR)udev.c $(SRC_DIR)socs.h
-		CFLAGS += -DARCH_ARM -std=c99
-	else
-		# Error lines should not be tabulated because Makefile complains about it
-$(warning Unsupported arch detected: $(arch). See https://github.com/Dr-Noob/cpufetch#1-support)
-$(warning If your architecture is supported but the compilation fails, please open an issue in https://github.com/Dr-Noob/cpufetch/issues)
-$(error Aborting compilation)
-	endif
-
 	GIT_VERSION := ""
+	SRC_DIR=src/x86/
+	SOURCE += $(COMMON_SRC) $(SRC_DIR)cpuid.c $(SRC_DIR)apic.c $(SRC_DIR)cpuid_asm.c $(SRC_DIR)uarch.c
+	HEADERS += $(COMMON_HDR) $(SRC_DIR)cpuid.h $(SRC_DIR)apic.h $(SRC_DIR)cpuid_asm.h $(SRC_DIR)uarch.h
+	CFLAGS += -DARCH_X86 -std=c99
 	SANITY_FLAGS += -Wno-pedantic-ms-format
 	OUTPUT=cpufetch.exe
 endif

README.md

@@ -63,7 +63,7 @@ cpufetch is a command-line tool written in C that displays the CPU information i
 | OS          | x86_64 / x86       | ARM                | RISC-V             | PowerPC            |
 |:-----------:|:------------------:|:------------------:|:------------------:|:------------------:|
 | GNU / Linux | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| Windows     | :heavy_check_mark: | :heavy_check_mark: | :x:                | :x:                |
+| Windows     | :heavy_check_mark: | :x:                | :x:                | :x:                |
 | Android     | :heavy_check_mark: | :heavy_check_mark: | :x:                | :x:                |
 | macOS       | :heavy_check_mark: | :heavy_check_mark: | :x:                | :heavy_check_mark: |
 | FreeBSD     | :heavy_check_mark: | :x:                | :x:                | :x:                |

src/arm/midr.c

@@ -11,10 +11,6 @@
   #include "../common/freq.h"
 #elif defined __APPLE__ || __MACH__
   #include "../common/sysctl.h"
-#elif defined _WIN32
-  #define WIN32_LEAN_AND_MEAN
-  #define NOMINMAX
-  #include <windows.h>
 #endif
 
 #include "../common/global.h"
@@ -25,60 +21,6 @@
 #include "uarch.h"
 #include "sve.h"
 
-
-#if defined _WIN32
-// Windows stores processor information in registery at:
-// "HKEY_LOCAL_MACHINE\HARDWARE\DESCRIPTION\System\CentralProcessor"
-// Within this directory, each core will get its own folder with
-// registery entries named `CP ####` that map to ARM system registers.
-// Ex. the MIDR register for core 0 is the `REG_QWORD` at:
-// "HKEY_LOCAL_MACHINE\HARDWARE\DESCRIPTION\System\CentralProcessor\0\CP 4000"
-// The name of these `CP ####`-registers follow their register ID encoding in hexadecimal
-// (op0&1):op1:crn:crm:op2.
-// More registers can be found here:
-// https://developer.arm.com/documentation/ddi0601/2024-06/AArch64-Registers
-// Some important ones:
-// CP 4000: MIDR_EL1
-// CP 4020: ID_AA64PFR0_EL1
-// CP 4021: ID_AA64PFR1_EL1
-// CP 4028: ID_AA64DFR0_EL1
-// CP 4029: ID_AA64DFR1_EL1
-// CP 402C: ID_AA64AFR0_EL1
-// CP 402D: ID_AA64AFR1_EL1
-// CP 4030: ID_AA64ISAR0_EL1
-// CP 4031: ID_AA64ISAR1_EL1
-// CP 4038: ID_AA64MMFR0_EL1
-// CP 4039: ID_AA64MMFR1_EL1
-// CP 403A: ID_AA64MMFR2_EL1
-
-bool read_registry_hklm_int(char* path, char* name, void* value, bool is64) {  
-  DWORD value_len;
-  int reg_type;
-  if (is64) {
-    value_len = sizeof(int64_t);
-    reg_type = RRF_RT_REG_QWORD;
-  }
-  else {
-    value_len = sizeof(int32_t);
-    reg_type = RRF_RT_REG_DWORD;
-  }
-
-  if(RegGetValueA(HKEY_LOCAL_MACHINE, path, name, reg_type, NULL, value, &value_len) != ERROR_SUCCESS) {
-    printBug("Error reading registry entry \"%s\\%s\"", path, name);
-    return false;
-  }
-  return true;
-}
-
-bool get_win32_core_info_int(uint32_t core_index, char* name, void* value, bool is64) {
-  // path + digits
-  uint32_t max_path_size = 45+3+1;
-  char* path = ecalloc(sizeof(char) * max_path_size, sizeof(char));
-  snprintf(path, max_path_size, "HARDWARE\\DESCRIPTION\\System\\CentralProcessor\\%u", core_index);
-  return read_registry_hklm_int(path, name, value, is64);
-}
-#endif
-
 bool cores_are_equal(int c1pos, int c2pos, uint32_t* midr_array, int32_t* freq_array) {
   return midr_array[c1pos] == midr_array[c2pos] && freq_array[c1pos] == freq_array[c2pos];
 }
@@ -266,46 +208,6 @@ struct features* get_features_info(void) {
   feat->NEON = true;
   feat->SVE = false;
   feat->SVE2 = false;
-#elif defined _WIN32
-
-  // CP 4020 maps to the ID_AA64PFR0_EL1 register on Windows
-  // https://developer.arm.com/documentation/ddi0601/2024-06/AArch64-Registers/ID-AA64PFR0-EL1--AArch64-Processor-Feature-Register-0
-  int64_t pfr0 = 0;
-  if(!get_win32_core_info_int(0, "CP 4020", &pfr0, true)) {
-    printWarn("Unable to retrieve PFR0 via registry");
-  }
-  else {
-    // AdvSimd[23:20]
-    // -1: Not available
-    //  0: AdvSimd support
-    //  1: AdvSimd support + FP16
-    int8_t adv_simd = ((int64_t)(pfr0 << (60 - 20)) >> 60);
-    feat->NEON = (adv_simd >= 0);
-
-    // SVE[35:32]
-    feat->SVE = (pfr0 >> 32) & 0xF ? true : false;
-  }
-
-  // Windoes does not expose a registry entry for the ID_AA64ZFR0_EL1 register
-  // this would have mapped to "CP 4024".
-  feat->SVE2 = false;
-
-  // CP 4030 maps to the ID_AA64ISAR0_EL1 register on Windows
-  // https://developer.arm.com/documentation/ddi0601/2024-06/AArch64-Registers/ID-AA64ISAR0-EL1--AArch64-Instruction-Set-Attribute-Register-0
-  int64_t isar0 = 0;
-  if(!get_win32_core_info_int(0, "CP 4030", &isar0, true)) {
-    printWarn("Unable to retrieve ISAR0 via registry");
-  }
-  else {
-    // AES[7:4]
-    feat->AES = (isar0 >> 4) & 0xF ? true : false;
-    // SHA1[11:8]
-    feat->SHA1 = (isar0 >> 8) & 0xF ? true : false;
-    // SHA2[15:12]
-    feat->SHA2 = (isar0 >> 12) & 0xF ? true : false;
-    // CRC32[19:16]
-    feat->CRC32 = (isar0 >> 16) & 0xF ? true : false;
-  }
 #endif  // ifdef __linux__
 
   if (feat->SVE || feat->SVE2) {
@@ -526,68 +428,6 @@ struct cpuInfo* get_cpu_info_mach(struct cpuInfo* cpu) {
 
   return cpu;
 }
-#elif defined _WIN32
-struct cpuInfo* get_cpu_info_windows(struct cpuInfo* cpu) {
-  init_cpu_info(cpu);
-
-  SYSTEM_INFO sys_info;
-  GetSystemInfo(&sys_info);
-  int ncores = sys_info.dwNumberOfProcessors;
-
-  uint32_t* midr_array = emalloc(sizeof(uint32_t) * ncores);
-  int32_t* freq_array = emalloc(sizeof(uint32_t) * ncores);
-  uint32_t* ids_array = emalloc(sizeof(uint32_t) * ncores);
-  for(int i=0; i < ncores; i++) {
-    // Cast from 64 to 32 bit to be able to re-use the pre-existing
-    // functions such as fill_ids_from_midr and cores_are_equal
-    int64_t midr_64;
-    if(!get_win32_core_info_int(i, "CP 4000", &midr_64, true)) {
-      return NULL;
-    }
-    midr_array[i] = midr_64;
-    if(!get_win32_core_info_int(i, "~MHz", &freq_array[i], false)) {
-      return NULL;
-    }
-  }
-
-  uint32_t sockets = fill_ids_from_midr(midr_array, freq_array, ids_array, ncores);
-
-  struct cpuInfo* ptr = cpu;
-  int midr_idx = 0;
-  int tmp_midr_idx = 0;
-  for(uint32_t i=0; i < sockets; i++) {
-    if(i > 0) {
-      ptr->next_cpu = emalloc(sizeof(struct cpuInfo));
-      ptr = ptr->next_cpu;
-      init_cpu_info(ptr);
-
-      tmp_midr_idx = midr_idx;
-      while(cores_are_equal(midr_idx, tmp_midr_idx, midr_array, freq_array)) tmp_midr_idx++;
-      midr_idx = tmp_midr_idx;
-    }
-
-    ptr->midr = midr_array[midr_idx];
-    ptr->arch = get_uarch_from_midr(ptr->midr, ptr);
-
-    ptr->feat = get_features_info();
-    
-    ptr->freq = emalloc(sizeof(struct frequency));
-    ptr->freq->measured = false;
-    ptr->freq->base = freq_array[midr_idx];
-    ptr->freq->max = UNKNOWN_DATA;
-
-    ptr->cach = get_cache_info(ptr);
-    ptr->topo = get_topology_info(ptr, ptr->cach, midr_array, freq_array, i, ncores);
-  }
-
-  cpu->num_cpus = sockets;
-  cpu->hv = emalloc(sizeof(struct hypervisor));
-  cpu->hv->present = false;
-  cpu->soc = get_soc(cpu);
-  cpu->peak_performance = get_peak_performance(cpu);
-
-  return cpu;
-}
 #endif
 
 struct cpuInfo* get_cpu_info(void) {
@@ -598,8 +438,6 @@ struct cpuInfo* get_cpu_info(void) {
     return get_cpu_info_linux(cpu);
   #elif defined __APPLE__ || __MACH__
     return get_cpu_info_mach(cpu);
-  #elif defined _WIN32
-    return get_cpu_info_windows(cpu);
   #endif
 }
 

src/arm/soc.c

@@ -14,28 +14,6 @@
   #include "../common/sysctl.h"
 #endif
 
-#if defined(_WIN32)
-  #define WIN32_LEAN_AND_MEAN
-  #define NOMINMAX
-  #include <windows.h>
-
-// Gets a RRF_RT_REG_SZ-entry from the Windows registry, returning a newly allocated
-// string and its length
-bool read_registry_hklm_sz(char* path, char* value, char** string, LPDWORD length) {
-	// First call to RegGetValueA gets the length of the string and determines how much
-  // memory should be allocated for the new string
-  if(RegGetValueA(HKEY_LOCAL_MACHINE, path, value, RRF_RT_REG_SZ, NULL, NULL, length) != ERROR_SUCCESS) {
-    return false;
-  }
-  *string = ecalloc(*length, sizeof(char));
-  // Second call actually writes the string data
-  if(RegGetValueA(HKEY_LOCAL_MACHINE, path, value, RRF_RT_REG_SZ, NULL, *string, length) != ERROR_SUCCESS) {
-    return false;
-  }
-  return true;
-}
-#endif
-
 #define NA -1
 #define min(a,b) (((a)<(b))?(a):(b))
 #define ARRAY_SIZE(arr)     (sizeof(arr) / sizeof((arr)[0]))
@@ -306,21 +284,7 @@ bool match_mediatek(char* soc_name, struct system_on_chip* soc) {
   soc->vendor = SOC_VENDOR_MEDIATEK;
 
   SOC_START
-  // TODO
+  // Dimensity //
-  // Dimensity 6000 Series //
-  // Dimensity 7000 Series //
-  // Dimensity 8000 Series //
-  // END TODO
-  // Dimensity 9000 Series //
-  SOC_EQ(tmp, "MT6983Z",  "Dimensity 9000",  SOC_MTK_MT6983Z,  soc, 4)
-  SOC_EQ(tmp, "MT8798Z/C","Dimensity 9000",  SOC_MTK_MT8798ZC, soc, 4)
-  SOC_EQ(tmp, "MT6983W",  "Dimensity 9000+", SOC_MTK_MT6983W,  soc, 4)
-  SOC_EQ(tmp, "MT8798Z/T","Dimensity 9000+", SOC_MTK_MT8798ZT, soc, 4)
-  SOC_EQ(tmp, "MT6985W",  "Dimensity 9200+", SOC_MTK_MT6985W,  soc, 4)
-  SOC_EQ(tmp, "MT6985",   "Dimensity 9200",  SOC_MTK_MT6985,   soc, 4)
-  SOC_EQ(tmp, "MT6989",   "Dimensity 9300",  SOC_MTK_MT6989,   soc, 4)
-  SOC_EQ(tmp, "MT8796",   "Dimensity 9300",  SOC_MTK_MT8796,   soc, 4)
-  // Dimensity 1000 //
   SOC_EQ(tmp, "MT6893Z",  "Dimensity 1300",  SOC_MTK_MT6893Z,  soc, 6)
   SOC_EQ(tmp, "MT6893",   "Dimensity 1200",  SOC_MTK_MT6893,   soc, 6)
   SOC_EQ(tmp, "MT6891",   "Dimensity 1100",  SOC_MTK_MT6891,   soc, 6)
@@ -330,21 +294,12 @@ bool match_mediatek(char* soc_name, struct system_on_chip* soc) {
   SOC_EQ(tmp, "MT6885Z",  "Dimensity 1000L", SOC_MTK_MT6885Z,  soc, 7)
   SOC_EQ(tmp, "MT6889Z",  "Dimensity 1000+", SOC_MTK_MT6889Z,  soc, 7)
   SOC_EQ(tmp, "MT6883Z",  "Dimensity 1000C", SOC_MTK_MT6883Z,  soc, 7)
-  // Dimensity 900
-  SOC_EQ(tmp, "MT6877V/Z","Dimensity 900",   SOC_MTK_MT6877VZ, soc, 6)
-  SOC_EQ(tmp, "MT6877T"  ,"Dimensity 920",   SOC_MTK_MT6877T,  soc, 6)
-  SOC_EQ(tmp, "MT6855"   ,"Dimensity 930",   SOC_MTK_MT6855,   soc, 6)
-  // Dimensity 800
-  SOC_EQ(tmp, "MT6873",   "Dimensity 800",   SOC_MTK_MT6873,   soc, 7)
-  SOC_EQ(tmp, "MT6853V/T","Dimensity 800U",  SOC_MTK_MT6853VT, soc, 7)
-  SOC_EQ(tmp, "MT6853T",  "Dimensity 800U",  SOC_MTK_MT6853T,  soc, 7)
-  SOC_EQ(tmp, "MT6833P",  "Dimensity 810",   SOC_MTK_MT6833P,  soc, 6)
-  SOC_EQ(tmp, "MT6833GP", "Dimensity 810",   SOC_MTK_MT6833GP, soc, 6)
-  SOC_EQ(tmp, "MT6833V",  "Dimensity 810",   SOC_MTK_MT6833V,  soc, 6)
-  SOC_EQ(tmp, "MT6875",   "Dimensity 820",   SOC_MTK_MT6875,   soc, 7)
-  // Dimensity 700
   SOC_EQ(tmp, "MT6833",   "Dimensity 700",   SOC_MTK_MT6833,   soc, 7)
-  SOC_EQ(tmp, "MT6853V",  "Dimensity 720",   SOC_MTK_MT6853,   soc, 7)
+  SOC_EQ(tmp, "MT6853",   "Dimensity 720",   SOC_MTK_MT6853,   soc, 7)
+  SOC_EQ(tmp, "MT6873",   "Dimensity 800",   SOC_MTK_MT6873,   soc, 7)
+  SOC_EQ(tmp, "MT6853V",  "Dimensity 800U",  SOC_MTK_MT6853V,  soc, 7)
+  SOC_EQ(tmp, "MT6833",   "Dimensity 810",   SOC_MTK_MT6833,   soc, 6)
+  SOC_EQ(tmp, "MT6875",   "Dimensity 820",   SOC_MTK_MT6875,   soc, 7)
   // Helio //
   SOC_EQ(tmp, "MT6761D",  "Helio A20",       SOC_MTK_MT6761D,  soc, 12)
   SOC_EQ(tmp, "MT6761",   "Helio A22",       SOC_MTK_MT6761,   soc, 12)
@@ -1016,18 +971,6 @@ struct system_on_chip* guess_soc_from_devtree(struct system_on_chip* soc) {
   DT_EQ(dt, len, soc, "apple,t6030", "M3 Pro",   SOC_APPLE_M3_PRO,   3)
   DT_EQ(dt, len, soc, "apple,t6031", "M3 Max",   SOC_APPLE_M3_MAX,   3)
   DT_EQ(dt, len, soc, "apple,t6034", "M3 Max",   SOC_APPLE_M3_MAX,   3)
-  // NVIDIA
-  // https://elixir.bootlin.com/linux/v6.10.6/source/arch/arm64/boot/dts/nvidia
-  // https://elixir.bootlin.com/linux/v6.10.6/source/arch/arm/boot/dts/nvidia
-  DT_EQ(dt, len, soc, "nvidia,tegra20",  "Tegra 2",      SOC_TEGRA_2,      40) // https://en.wikipedia.org/wiki/Tegra#Tegra_2
-  DT_EQ(dt, len, soc, "nvidia,tegra30",  "Tegra 3",      SOC_TEGRA_3,      40) // https://en.wikipedia.org/wiki/Tegra#Tegra_3
-  DT_EQ(dt, len, soc, "nvidia,tegra114", "Tegra 4",      SOC_TEGRA_4,      28) // https://en.wikipedia.org/wiki/Tegra#Tegra_4
-  DT_EQ(dt, len, soc, "nvidia,tegra124", "Tegra K1",     SOC_TEGRA_K1,     28) // https://en.wikipedia.org/wiki/Tegra#Tegra_K1
-  DT_EQ(dt, len, soc, "nvidia,tegra132", "Tegra K1",     SOC_TEGRA_K1,     28) // https://en.wikipedia.org/wiki/Tegra#Tegra_K1
-  DT_EQ(dt, len, soc, "nvidia,tegra210", "Tegra X1",     SOC_TEGRA_X1,     20) // https://en.wikipedia.org/wiki/Tegra#Tegra_X1
-  DT_EQ(dt, len, soc, "nvidia,tegra186", "Tegra X2",     SOC_TEGRA_X2,     16) // https://en.wikipedia.org/wiki/Tegra#Tegra_X2
-  DT_EQ(dt, len, soc, "nvidia,tegra194", "Tegra Xavier", SOC_TEGRA_XAVIER, 12) // https://en.wikipedia.org/wiki/Tegra#Xavier
-  DT_EQ(dt, len, soc, "nvidia,tegra234", "Tegra Orin",   SOC_TEGRA_ORIN,    8) // https://www.phoronix.com/news/NVIDIA-Orin-Tegra234-Audio, https://github.com/Dr-Noob/cpufetch/issues/275, https://en.wikipedia.org/wiki/Tegra#Orin
   // Qualcomm now also in devtree...
   // TODO: Integrate this with SOC_EQ
   DT_EQ(dt, len, soc, "qcom,sc8280", "8cx Gen 3", SOC_SNAPD_SC8280XP, 5)
@@ -1041,90 +984,14 @@ struct system_on_chip* guess_soc_from_devtree(struct system_on_chip* soc) {
   DT_EQ(dt, len, soc, "fsl,imx8dxp", "i.MX 8DualXPlus", SOC_NXP_IMX8DXP, NA)
   DT_EQ(dt, len, soc, "fsl,imx8qxp", "i.MX 8QuadXPlus", SOC_NXP_IMX8QXP, NA)
   DT_EQ(dt, len, soc, "fsl,imx93",   "i.MX 93",         SOC_NXP_IMX93,   NA)  
-  // [1] https://elixir.bootlin.com/linux/v6.10.6/source/arch/arm64/boot/dts/amlogic
+  // TODO: Add more Amlogic SoCs: https://elixir.bootlin.com/linux/v6.10.6/source/arch/arm64/boot/dts/amlogic
-  // [2] https://github.com/Dr-Noob/cpufetch/issues/268
+  // https://github.com/Dr-Noob/cpufetch/issues/268
-  // [3] https://www.amlogic.com/#Products/393/index.html
+  // https://www.amlogic.com/#Products/393/index.html
-  // [4] https://wikimovel.com
+  // https://wikimovel.com/index.php/Amlogic_A311D
-  // [5] https://wiki.postmarketos.org/wiki/Amlogic_S905W/S905D/S905X/S905L/S805X/S805Y/S905Z
+  DT_EQ(dt, len, soc, "amlogic,a311d", "A311D", SOC_AMLOGIC_A311D, 12)
-  DT_EQ(dt, len, soc, "amlogic,a311d",  "A311D",  SOC_AMLOGIC_A311D,  12) // [1,2,3,4]
-  DT_EQ(dt, len, soc, "amlogic,a311d2", "A311D2", SOC_AMLOGIC_A311D2, 12) // [1,4]
-  DT_EQ(dt, len, soc, "amlogic,s905w",  "S905W",  SOC_AMLOGIC_S905W,  28) // [1,5]
-  DT_EQ(dt, len, soc, "amlogic,s905d",  "S905D",  SOC_AMLOGIC_S905D,  28) // [1,5]
-  DT_EQ(dt, len, soc, "amlogic,s905x",  "S905X",  SOC_AMLOGIC_S905X,  28) // [1,4,5]
-  DT_EQ(dt, len, soc, "amlogic,s805x",  "S805X",  SOC_AMLOGIC_S805X,  28) // [1,5]
-  // Marvell
-  // https://elixir.bootlin.com/linux/v6.10.6/source/arch/arm64/boot/dts/marvell
-  DT_EQ(dt, len, soc, "marvell,armada3700", "Armada 3700", SOC_MARVELL_A3700,  28) // http://wiki.espressobin.net/tiki-index.php?page=Armada+3700 (pdf), https://github.com/Dr-Noob/cpufetch/issues/279
-  DT_EQ(dt, len, soc, "marvell,armada3710", "Armada 3710", SOC_MARVELL_A3710,  28) // https://gzhls.at/blob/ldb/2/7/4/2/6eacf9661c5a2d20c4d7cd3328ffba47bfd6.pdf
-  DT_EQ(dt, len, soc, "marvell,armada3720", "Armada 3720", SOC_MARVELL_A3720,  28) // https://gzhls.at/blob/ldb/2/7/4/2/6eacf9661c5a2d20c4d7cd3328ffba47bfd6.pdf
-  DT_EQ(dt, len, soc, "marvell,armada7200", "Armada 7200", SOC_MARVELL_A7200,  28) // Assuming same manufacturing process as 7400
-  DT_EQ(dt, len, soc, "marvell,armada7400", "Armada 7400", SOC_MARVELL_A7400,  28) // https://www.marvell.com/content/dam/marvell/en/public-collateral/embedded-processors/marvell-embedded-processors-armada-7040-product-brief-2017-12.pdf
-  DT_EQ(dt, len, soc, "marvell,armada8020", "Armada 8020", SOC_MARVELL_A8020,  28) // https://datasheet.datasheetarchive.com/originals/crawler/marvell.com/da7b6a997e49e9e93fa4b1f4cfbed71b.pdf
-  DT_EQ(dt, len, soc, "marvell,armada8040", "Armada 8040", SOC_MARVELL_A8040,  28) // https://www.verical.com/datasheet/marvell-technology-group-application-processors-and-soc-88f8040-a2-bvp4i160-6331367.pdf
-  DT_EQ(dt, len, soc, "marvell,cn9130",     "CN9130",      SOC_MARVELL_CN9130, NA) // https://www.marvell.com/content/dam/marvell/en/public-collateral/embedded-processors/marvell-infrastructure-processors-octeon-tx2-cn913x-product-brief.pdf
-  DT_EQ(dt, len, soc, "marvell,cn9131",     "CN9131",      SOC_MARVELL_CN9131, NA) // https://www.marvell.com/content/dam/marvell/en/public-collateral/embedded-processors/marvell-infrastructure-processors-octeon-tx2-cn913x-product-brief.pdf
-  DT_EQ(dt, len, soc, "marvell,cn9132",     "CN9132",      SOC_MARVELL_CN9132, NA) // https://www.marvell.com/content/dam/marvell/en/public-collateral/embedded-processors/marvell-infrastructure-processors-octeon-tx2-cn913x-product-brief.pdf
   DT_END(dt, len)
 }
 
-// This function is different from the rest guess_soc_from_xxx, which try infering
-// the exact SoC model by matching some string against a list of known values.
-// On the other hand, this function will just try to infer the SoC vendor first by
-// matching the device tree vendor name (i.e., the first value, before the comma).
-// If that is successfull, then it also fills in the SoC name using the string from
-// the device tree.
-// The critical difference is that this function does not need a LUT to fill in the
-// SoC, it just needs to find a known vendor. On the other hand, the detection is
-// less powerful since we cannot get the manufacturing process, and the SoC name will
-// come directly from the device tree, meaning that it will likely be less precise.
-struct system_on_chip* guess_raw_soc_from_devtree(struct system_on_chip* soc) {
-  int num_vendors;
-  struct devtree** dt_vendors = get_devtree_compatible_struct(&num_vendors);
-  if (dt_vendors == NULL) {
-    return soc;
-  }
-
-  typedef struct {
-    char* compatible;
-    VENDOR soc_vendor;
-  } devtreeToVendor;
-
-  // https://elixir.bootlin.com/linux/v6.10.6/source/arch/arm64/boot/dts
-  // grep -oR --color -E 'compatible = ".*"' <soc_vendor> | cut -d '=' -f2 | cut -d ',' -f1 | tr -d '"' | sort | uniq -c | sort
-  // - The following vendors are not included because they dont seem to be present in dts:
-  // SOC_VENDOR_(KIRIN, KUNPENG, GOOGLE, AMPERE).
-  // - The commented vendors are not included intentionally, because I prefer updating its LUT manually.
-  devtreeToVendor socFromDevtree[] = {
-    // {"qcom",       SOC_VENDOR_SNAPDRAGON},
-    // {"samsung",    SOC_VENDOR_EXYNOS},
-    // {"brcm",       SOC_VENDOR_BROADCOM},
-    // {"apple",      SOC_VENDOR_APPLE},
-    // {"rockchip",   SOC_VENDOR_ROCKCHIP},
-    // {"nvidia",     SOC_VENDOR_NVIDIA},
-    {"mediatek",   SOC_VENDOR_MEDIATEK},
-    {"fsl",        SOC_VENDOR_NXP     },
-    {"nxp",        SOC_VENDOR_NXP     },
-    {"amlogic",    SOC_VENDOR_AMLOGIC },
-    {"marvell",    SOC_VENDOR_MARVELL },
-    {NULL,         SOC_VENDOR_UNKNOWN }
-  };
-
-  int index = 0;
-  while (socFromDevtree[index].compatible != 0x0) {
-    for (int i=0; i < num_vendors; i++) {
-      if (strcmp(socFromDevtree[index].compatible, dt_vendors[i]->vendor) == 0) {
-        fill_soc_raw(soc, dt_vendors[i]->model, socFromDevtree[index].soc_vendor);
-        printWarn("Your SoC is unsupported by cpufetch but could still be detected successfully. If you want to help improve the project, please paste the output of 'cpufetch --verbose' on https://github.com/Dr-Noob/cpufetch/issues");
-        return soc;
-      }
-    }
-    index++;
-  }
-
-  printWarn("guess_raw_soc_from_devtree: No device matched the list");
-  return soc;
-}
-
 struct system_on_chip* guess_soc_from_pci(struct system_on_chip* soc, struct cpuInfo* cpu) {
   struct pci_devices * pci = get_pci_devices();
   if (pci == NULL) {
@@ -1351,11 +1218,6 @@ struct system_on_chip* get_soc(struct cpuInfo* cpu) {
     if(soc->vendor == SOC_VENDOR_UNKNOWN) {
       soc = guess_soc_from_pci(soc, cpu);
     }
-    if (soc->vendor == SOC_VENDOR_UNKNOWN) {
-      // If we fall here it means all previous functions failed to detect the SoC.
-      // In such case, try with our last resort. If it also fails, we will just give up
-      soc = guess_raw_soc_from_devtree(soc);
-    }
   }
 #elif defined __APPLE__ || __MACH__
   soc = guess_soc_apple(soc);
@@ -1365,30 +1227,14 @@ struct system_on_chip* get_soc(struct cpuInfo* cpu) {
   else {
     return soc;
   }
-#endif
+#endif // ifdef __linux__
 
-#if defined _WIN32
+  if(soc->model == SOC_MODEL_UNKNOWN) {
-  // Use the first core to determine the SoC
+    // raw_name might not be NULL, but if we were unable to find
-  char* processor_name_string = NULL;
+    // the exact SoC, just print "Unkwnown"
-  unsigned long processor_name_string_len = 0;
-  if(!read_registry_hklm_sz("HARDWARE\\DESCRIPTION\\System\\CentralProcessor\\0", "ProcessorNameString", &processor_name_string, &processor_name_string_len)) {
-    printWarn("Failed to aquire SoC name from registery");
-    return soc;
-  }
-
-  soc->name = processor_name_string;
-  soc->raw_name = processor_name_string;
-  soc->vendor = try_match_soc_vendor_name(processor_name_string);
-  soc->model = SOC_MODEL_UNKNOWN;
-  soc->process = UNKNOWN;
-#else
-  if(soc->raw_name == NULL) {
-    // We were unable to find the SoC, so just initialize raw_name
-    // with the unknown string
     soc->raw_name = emalloc(sizeof(char) * (strlen(STRING_UNKNOWN)+1));
     snprintf(soc->raw_name, strlen(STRING_UNKNOWN)+1, STRING_UNKNOWN);
   }
-#endif 
 
   return soc;
 }

src/arm/socs.h

@@ -192,22 +192,6 @@ enum {
   SOC_MTK_MT9950,
   SOC_MTK_MT9972,
   SOC_MTK_MT9982,
-  SOC_MTK_MT6983Z,
-  SOC_MTK_MT8798ZC,
-  SOC_MTK_MT6983W,
-  SOC_MTK_MT8798ZT,
-  SOC_MTK_MT6985W,
-  SOC_MTK_MT6985,
-  SOC_MTK_MT6989,
-  SOC_MTK_MT8796,
-  SOC_MTK_MT6877VZ,
-  SOC_MTK_MT6877T,
-  SOC_MTK_MT6855,
-  SOC_MTK_MT6853VT,
-  SOC_MTK_MT6853T,
-  SOC_MTK_MT6833P,
-  SOC_MTK_MT6833GP,
-  SOC_MTK_MT6833V,
   // Snapdragon //
   SOC_SNAPD_QSD8650,
   SOC_SNAPD_QSD8250,
@@ -396,15 +380,7 @@ enum {
   SOC_GOOGLE_TENSOR_G2,
   SOC_GOOGLE_TENSOR_G3,
   // NVIDIA,
-  SOC_TEGRA_2,
-  SOC_TEGRA_3,
-  SOC_TEGRA_4,
-  SOC_TEGRA_K1,
-  SOC_TEGRA_K2,
   SOC_TEGRA_X1,
-  SOC_TEGRA_X2,
-  SOC_TEGRA_XAVIER,
-  SOC_TEGRA_ORIN,
   // ALTRA
   SOC_AMPERE_ALTRA,
   // NXP
@@ -418,22 +394,6 @@ enum {
   SOC_NXP_IMX93,
   // AMLOGIC
   SOC_AMLOGIC_A311D,
-  SOC_AMLOGIC_A311D2,
-  SOC_AMLOGIC_S905W,
-  SOC_AMLOGIC_S905D,
-  SOC_AMLOGIC_S905X,
-  SOC_AMLOGIC_S805X,
-  // MARVELL
-  SOC_MARVELL_A3700,
-  SOC_MARVELL_A3710,
-  SOC_MARVELL_A3720,
-  SOC_MARVELL_A7200,
-  SOC_MARVELL_A7400,
-  SOC_MARVELL_A8020,
-  SOC_MARVELL_A8040,
-  SOC_MARVELL_CN9130,
-  SOC_MARVELL_CN9131,
-  SOC_MARVELL_CN9132,
   // UNKNOWN
   SOC_MODEL_UNKNOWN
 };
@@ -443,17 +403,16 @@ inline static VENDOR get_soc_vendor_from_soc(SOC soc) {
   else if(soc >= SOC_HISILICON_3620 && soc <= SOC_HISILICON_9000S) return SOC_VENDOR_KIRIN;
   else if(soc >= SOC_KUNPENG_920 && soc <= SOC_KUNPENG_930) return SOC_VENDOR_KUNPENG;
   else if(soc >= SOC_EXYNOS_3475 && soc <= SOC_EXYNOS_880) return SOC_VENDOR_EXYNOS;
-  else if(soc >= SOC_MTK_MT5327 && soc <= SOC_MTK_MT6833V) return SOC_VENDOR_MEDIATEK;
+  else if(soc >= SOC_MTK_MT6893 && soc <= SOC_MTK_MT8783) return SOC_VENDOR_MEDIATEK;
   else if(soc >= SOC_SNAPD_QSD8650 && soc <= SOC_SNAPD_SC8280XP) return SOC_VENDOR_SNAPDRAGON;
   else if(soc >= SOC_APPLE_M1 && soc <= SOC_APPLE_M3_MAX) return SOC_VENDOR_APPLE;
   else if(soc >= SOC_ALLWINNER_A10 && soc <= SOC_ALLWINNER_R328) return SOC_VENDOR_ALLWINNER;
   else if(soc >= SOC_ROCKCHIP_3288 && soc <= SOC_ROCKCHIP_3588) return SOC_VENDOR_ROCKCHIP;
   else if(soc >= SOC_GOOGLE_TENSOR && soc <= SOC_GOOGLE_TENSOR_G3) return SOC_VENDOR_GOOGLE;
-  else if(soc >= SOC_TEGRA_2 && soc <= SOC_TEGRA_ORIN) return SOC_VENDOR_NVIDIA;
+  else if(soc >= SOC_TEGRA_X1 && soc <= SOC_TEGRA_X1) return SOC_VENDOR_NVIDIA;
   else if(soc >= SOC_AMPERE_ALTRA && soc <= SOC_AMPERE_ALTRA) return SOC_VENDOR_AMPERE;
   else if(soc >= SOC_NXP_IMX8QM && soc <= SOC_NXP_IMX93) return SOC_VENDOR_NXP;
-  else if(soc >= SOC_AMLOGIC_A311D && soc <= SOC_AMLOGIC_S805X) return SOC_VENDOR_AMLOGIC;
+  else if(soc >= SOC_AMLOGIC_A311D && soc <= SOC_AMLOGIC_A311D) return SOC_VENDOR_AMLOGIC;
-  else if(soc >= SOC_MARVELL_A3700 && soc <= SOC_MARVELL_CN9132) return SOC_VENDOR_MARVELL;
   return SOC_VENDOR_UNKNOWN;
 }
 

src/common/ascii.h

@@ -433,38 +433,6 @@ $C1#########.###  ##  ##  ##  ##   ###    ######   ##   ###  \
 $C1                                          ###             \
 $C1                                       ###                "
 
-#define ASCII_MARVELL \
-"$C1                       ...........          ........... \
-$C1                   .###          .       .##          . \
-$C1                 .#####          .      ####          . \
-$C1                #######          .   #######          . \
-$C1             .#########__________. #########__________. \
-$C1          .###########|__________|#########|__________| \
-$C1        ############   ______############   __________  \
-$C1     .#########       |__________|######   |__________| \
-$C1   ###########         ___###########       __________  \
-$C1.##########           |__________|         |__________| "
-
-#define ASCII_SPACEMIT \
-"$C1                      :#:  \
-$C1                   :####:  \
-$C1                :#######:  \
-$C1              :#########:  \
-$C1              :#########:  \
-$C1              :#######:    \
-$C1              :####:       \
-$C1              :#:          \
-$C1:##:             :#:       \
-$C1:####:         :###:       \
-$C1:#######:     :####:       \
-$C1:##########:  :###:        \
-$C1:###########: :#:          \
-$C1:###########:              \
-$C1 :##########:              \
-$C1    :#######:              \
-$C1       :####:              \
-$C1         :##:              "
-
 // --------------------- LONG LOGOS ------------------------- //
 #define ASCII_AMD_L \
 "$C1                                                              \
@@ -643,8 +611,6 @@ asciiL logo_nvidia      = { ASCII_NVIDIA,      45, 19, false, {C_FG_GREEN, C_FG_
 asciiL logo_ampere      = { ASCII_AMPERE,      50, 17, false, {C_FG_RED},                                     {C_FG_WHITE,   C_FG_RED}     };
 asciiL logo_nxp         = { ASCII_NXP,         55,  8, false, {C_FG_YELLOW, C_FG_CYAN, C_FG_GREEN},           {C_FG_CYAN,    C_FG_WHITE}   };
 asciiL logo_amlogic     = { ASCII_AMLOGIC,     58,  8, false, {C_FG_BLUE},                                    {C_FG_BLUE,    C_FG_B_WHITE} };
-asciiL logo_marvell     = { ASCII_MARVELL,     56, 10, false, {C_FG_B_BLACK},                                 {C_FG_B_BLACK, C_FG_B_WHITE} };
-asciiL logo_spacemit    = { ASCII_SPACEMIT,    27, 18, false, {C_FG_B_GREEN},                                 {C_FG_B_GREEN, C_FG_B_WHITE} };
 
 // Long variants          | ----------------------------------------------------------------------------------------------------------------|
 asciiL logo_amd_l       = { ASCII_AMD_L,       62, 19, true,  {C_BG_WHITE, C_BG_GREEN},                       {C_FG_WHITE, C_FG_GREEN}     };

src/common/cpu.c

@@ -34,12 +34,6 @@ int64_t get_freq(struct frequency* freq) {
   return freq->max;
 }
 
-#ifdef ARCH_X86
-int64_t get_freq_pp(struct frequency* freq) {
-  return freq->max_pp;
-}
-#endif
-
 #if defined(ARCH_X86) || defined(ARCH_PPC)
 char* get_str_cpu_name(struct cpuInfo* cpu, bool fcpuname) {
   #ifdef ARCH_X86

src/common/cpu.h

@@ -25,7 +25,6 @@ enum {
   CPU_VENDOR_RISCV,
   CPU_VENDOR_SIFIVE,
   CPU_VENDOR_THEAD,
-  CPU_VENDOR_SPACEMIT,
 // OTHERS
   CPU_VENDOR_UNKNOWN,
   CPU_VENDOR_INVALID
@@ -61,11 +60,6 @@ struct frequency {
   int32_t max;
   // Indicates if max frequency was measured
   bool measured;
-#ifdef ARCH_X86
-  // Max frequency when running vectorized code.
-  // Used only for peak performance computation.
-  int32_t max_pp;
-#endif
 };
 
 struct hypervisor {
@@ -194,8 +188,6 @@ struct cpuInfo {
 #ifdef ARCH_X86
   // The index of the first core in the module
   uint32_t first_core_id;
-  // The index of this module
-  uint32_t module_id;
 #endif
 #endif
 };
@@ -208,9 +200,6 @@ uint32_t get_nsockets(struct topology* topo);
 
 VENDOR get_cpu_vendor(struct cpuInfo* cpu);
 int64_t get_freq(struct frequency* freq);
-#ifdef ARCH_X86
-int64_t get_freq_pp(struct frequency* freq);
-#endif
 
 char* get_str_aes(struct cpuInfo* cpu);
 char* get_str_sha(struct cpuInfo* cpu);

src/common/printer.c

@@ -20,7 +20,6 @@
   #include "../arm/uarch.h"
   #include "../arm/midr.h"
   #include "../arm/soc.h"
-  #include "../arm/socs.h"
   #include "../common/soc.h"
 #elif ARCH_RISCV
   #include "../riscv/riscv.h"
@@ -45,17 +44,9 @@
 #define MAX_ATTRIBUTES      100
 #define MAX_TERM_SIZE       1024
 
-typedef struct {
-  int id;
-  const char *name;
-  const char *shortname;
-} AttributeField;
-
 enum {
-#if defined(ARCH_X86)
+#if defined(ARCH_X86) || defined(ARCH_PPC)
   ATTRIBUTE_NAME,
-#elif defined(ARCH_PPC)
-  ATTRIBUTE_PART_NUMBER,
 #elif defined(ARCH_ARM) || defined(ARCH_RISCV)
   ATTRIBUTE_SOC,
 #endif
@@ -87,40 +78,76 @@ enum {
   ATTRIBUTE_PEAK
 };
 
-static const AttributeField ATTRIBUTE_INFO[] = {
+static const char* ATTRIBUTE_FIELDS [] = {
-#if defined(ARCH_X86)
+#ifdef ARCH_X86
-  { ATTRIBUTE_NAME,        "Name:",              "Name:"          },
+  "Name:",
-#elif defined(ARCH_PPC)
+#elif ARCH_PPC
-  { ATTRIBUTE_PART_NUMBER, "Part Number:",       "P/N:"           },
+  "Part Number:",
 #elif defined(ARCH_ARM) || defined(ARCH_RISCV)
-  { ATTRIBUTE_SOC,         "SoC:",               "SoC:"           },
+  "SoC:",
 #endif
 #if defined(ARCH_X86) || defined(ARCH_ARM)
-  { ATTRIBUTE_CPU_NUM,     "",                   ""               },     
+  "",
 #endif
-  { ATTRIBUTE_HYPERVISOR,  "Hypervisor:",        "Hypervisor:"    },
+  "Hypervisor:",
-  { ATTRIBUTE_UARCH,       "Microarchitecture:", "uArch:"         },
+  "Microarchitecture:",
-  { ATTRIBUTE_TECHNOLOGY,  "Technology:",        "Technology:"    },
+  "Technology:",
-  { ATTRIBUTE_FREQUENCY,   "Max Frequency:",     "Max Freq:"      },
+  "Max Frequency:",
-  { ATTRIBUTE_SOCKETS,     "Sockets:",           "Sockets:"       },
+  "Sockets:",
-  { ATTRIBUTE_NCORES,      "Cores:",             "Cores:"         },
+  "Cores:",
-  { ATTRIBUTE_NCORES_DUAL, "Cores (Total):",     "Cores (Total):" },
+  "Cores (Total):",
 #ifdef ARCH_X86
-  { ATTRIBUTE_SSE,         "SSE:",               "SSE:"           },
+  "SSE:",
-  { ATTRIBUTE_AVX,         "AVX:",               "AVX:"           },
+  "AVX:",
-  { ATTRIBUTE_FMA,         "FMA:",               "FMA:"           },
+  "FMA:",
 #elif ARCH_PPC
-  { ATTRIBUTE_ALTIVEC,     "Altivec: ",          "Altivec: "      },
+  "Altivec: ",
-#elif ARCH_ARM
+#elif defined(ARCH_ARM)
-  { ATTRIBUTE_FEATURES,    "Features: ",         "Features: "     },
+  "Features: ",
-#elif ARCH_RISCV
+#elif defined(ARCH_RISCV)
-  { ATTRIBUTE_EXTENSIONS,  "Extensions: ",       "Extensions: "   },
+  "Extensions: ",
 #endif
-  { ATTRIBUTE_L1i,         "L1i Size:",          "L1i Size:"      },
+  "L1i Size:",
-  { ATTRIBUTE_L1d,         "L1d Size:",          "L1d Size:"      },
+  "L1d Size:",
-  { ATTRIBUTE_L2,          "L2 Size:",           "L2 Size:"       },
+  "L2 Size:",
-  { ATTRIBUTE_L3,          "L3 Size:",           "L3 Size:"       },
+  "L3 Size:",
-  { ATTRIBUTE_PEAK,        "Peak Performance:",  "Peak Perf.:"    },
+  "Peak Performance:",
+};
+
+static const char* ATTRIBUTE_FIELDS_SHORT [] = {
+#if defined(ARCH_X86)
+  "Name:",
+#elif ARCH_PPC
+  "P/N:",
+#elif ARCH_ARM
+  "SoC:",
+#endif
+#if defined(ARCH_X86) || defined(ARCH_ARM)
+  "",
+#endif
+  "Hypervisor:",
+  "uArch:",
+  "Technology:",
+  "Max Freq:",
+  "Sockets:",
+  "Cores:",
+  "Cores (Total):",
+#ifdef ARCH_X86
+  "SSE:",
+  "AVX:",
+  "FMA:",
+#elif ARCH_PPC
+  "Altivec: ",
+#elif defined(ARCH_ARM)
+  "Features: ",
+#elif defined(ARCH_RISCV)
+  "Extensions: ",
+#endif
+  "L1i Size:",
+  "L1d Size:",
+  "L2 Size:",
+  "L3 Size:",
+  "Peak Perf.:",
 };
 
 struct terminal {
@@ -368,8 +395,6 @@ void choose_ascii_art(struct ascii* art, struct color** cs, struct terminal* ter
     art->art = &logo_nxp;
   else if(art->vendor == SOC_VENDOR_AMLOGIC)
     art->art = &logo_amlogic;
-  else if(art->vendor == SOC_VENDOR_MARVELL)
-    art->art = &logo_marvell;
   else if(art->vendor == SOC_VENDOR_NVIDIA)
     art->art = choose_ascii_art_aux(&logo_nvidia_l, &logo_nvidia, term, lf);
   else {
@@ -384,8 +409,6 @@ void choose_ascii_art(struct ascii* art, struct color** cs, struct terminal* ter
     art->art = &logo_allwinner;
   else if(art->vendor == SOC_VENDOR_SIPEED)
     art->art = &logo_sipeed;
-  else if(art->vendor == SOC_VENDOR_SPACEMIT)
-    art->art = &logo_spacemit;
   else
     art->art = &logo_riscv;
 #endif
@@ -426,14 +449,13 @@ void choose_ascii_art(struct ascii* art, struct color** cs, struct terminal* ter
   }
 }
 
-uint32_t longest_attribute_length(struct ascii* art, bool use_short) {
+uint32_t longest_attribute_length(struct ascii* art, const char** attribute_fields) {
   uint32_t max = 0;
   uint64_t len = 0;
 
   for(uint32_t i=0; i < art->n_attributes_set; i++) {
     if(art->attributes[i]->value != NULL) {
-      const char* str = use_short ? ATTRIBUTE_INFO[art->attributes[i]->type].shortname : ATTRIBUTE_INFO[art->attributes[i]->type].name;
+      len = strlen(attribute_fields[art->attributes[i]->type]);
-      len = strlen(str);
       if(len > max) max = len;
     }
   }
@@ -458,7 +480,7 @@ uint32_t longest_field_length(struct ascii* art, int la) {
 }
 
 #if defined(ARCH_X86) || defined(ARCH_PPC)
-void print_ascii_generic(struct ascii* art, uint32_t la, int32_t termw, bool use_short, bool hybrid_architecture) {
+void print_ascii_generic(struct ascii* art, uint32_t la, int32_t termw, const char** attribute_fields, bool hybrid_architecture) {
   struct ascii_logo* logo = art->art;
   int attr_to_print = 0;
   int attr_type;
@@ -520,15 +542,14 @@ void print_ascii_generic(struct ascii* art, uint32_t la, int32_t termw, bool use
       else {
 #endif
         beg_space = 0;
-        const char* attr_str = use_short ? ATTRIBUTE_INFO[attr_type].shortname : ATTRIBUTE_INFO[attr_type].name;
+        space_right = 2 + 1 + (la - strlen(attribute_fields[attr_type]));
-        space_right = 2 + 1 + (la - strlen(attr_str));
         if(hybrid_architecture && add_space) {
           beg_space = 2;
           space_right -= 2;
         }
 
-        printOut(lbuf, beg_space + strlen(attr_str) + space_right + strlen(attr_value),
+        printOut(lbuf, beg_space + strlen(attribute_fields[attr_type]) + space_right + strlen(attr_value),
-                 "%*s%s%s%s%*s%s%s%s", beg_space, "", logo->color_text[0], attr_str, art->reset, space_right, "", logo->color_text[1], attr_value, art->reset);
+                 "%*s%s%s%s%*s%s%s%s", beg_space, "", logo->color_text[0], attribute_fields[attr_type], art->reset, space_right, "", logo->color_text[1], attr_value, art->reset);
 #ifdef ARCH_X86
       }
 #endif
@@ -637,19 +658,19 @@ bool print_cpufetch_x86(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
   setAttribute(art, ATTRIBUTE_PEAK, pp);
 
   // Step 3. Print output
-  bool use_short = false;
+  const char** attribute_fields = ATTRIBUTE_FIELDS;
-  uint32_t longest_attribute = longest_attribute_length(art, use_short);
+  uint32_t longest_attribute = longest_attribute_length(art, attribute_fields);
   uint32_t longest_field = longest_field_length(art, longest_attribute);
   choose_ascii_art(art, cs, term, longest_field);
 
   if(!ascii_fits_screen(term->w, *art->art, longest_field)) {
     // Despite of choosing the smallest logo, the output does not fit
     // Choose the shorter field names and recalculate the longest attr
-    use_short = true;
+    attribute_fields = ATTRIBUTE_FIELDS_SHORT;
-    longest_attribute = longest_attribute_length(art, use_short);
+    longest_attribute = longest_attribute_length(art, attribute_fields);
   }
 
-  print_ascii_generic(art, longest_attribute, term->w, use_short, hybrid_architecture);
+  print_ascii_generic(art, longest_attribute, term->w, attribute_fields, hybrid_architecture);
 
   free(manufacturing_process);
   free(sockets);
@@ -698,7 +719,7 @@ bool print_cpufetch_ppc(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
 
   // Step 2. Set attributes
   if(cpu_name != NULL) {
-    setAttribute(art, ATTRIBUTE_PART_NUMBER, cpu_name);
+    setAttribute(art, ATTRIBUTE_NAME, cpu_name);
   }
   setAttribute(art, ATTRIBUTE_UARCH, uarch);
   if(cpu->hv->present) {
@@ -725,19 +746,19 @@ bool print_cpufetch_ppc(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
   setAttribute(art, ATTRIBUTE_PEAK, pp);
 
   // Step 3. Print output
-  bool use_short = false;
+  const char** attribute_fields = ATTRIBUTE_FIELDS;
-  uint32_t longest_attribute = longest_attribute_length(art, use_short);
+  uint32_t longest_attribute = longest_attribute_length(art, attribute_fields);
   uint32_t longest_field = longest_field_length(art, longest_attribute);
   choose_ascii_art(art, cs, term, longest_field);
 
   if(!ascii_fits_screen(term->w, *art->art, longest_field)) {
     // Despite of choosing the smallest logo, the output does not fit
     // Choose the shorter field names and recalculate the longest attr
-    use_short = true;
+    attribute_fields = ATTRIBUTE_FIELDS_SHORT;
-    longest_attribute = longest_attribute_length(art, use_short);
+    longest_attribute = longest_attribute_length(art, attribute_fields);
   }
 
-  print_ascii_generic(art, longest_attribute, term->w, use_short, false);
+  print_ascii_generic(art, longest_attribute, term->w, attribute_fields, false);
 
   return true;
 }
@@ -765,7 +786,7 @@ uint32_t longest_field_length_arm(struct ascii* art, int la) {
   return max;
 }
 
-void print_ascii_arm(struct ascii* art, uint32_t la, int32_t termw, bool use_short) {
+void print_ascii_arm(struct ascii* art, uint32_t la, int32_t termw, const char** attribute_fields) {
   struct ascii_logo* logo = art->art;
   int attr_to_print = 0;
   int attr_type;
@@ -836,15 +857,14 @@ void print_ascii_arm(struct ascii* art, uint32_t la, int32_t termw, bool use_sho
       }
       else {
         beg_space = 0;
-        const char* attr_str = use_short ? ATTRIBUTE_INFO[attr_type].shortname : ATTRIBUTE_INFO[attr_type].name;
+        space_right = 2 + 1 + (la - strlen(attribute_fields[attr_type]));
-        space_right = 2 + 1 + (la - strlen(attr_str));
         if(add_space) {
           beg_space = 2;
           space_right -= 2;
         }
 
-        printOut(lbuf, beg_space + strlen(attr_str) + space_right + strlen(attr_value),
+        printOut(lbuf, beg_space + strlen(attribute_fields[attr_type]) + space_right + strlen(attr_value),
-               "%*s%s%s%s%*s%s%s%s", beg_space, "", logo->color_text[0], attr_str, art->reset, space_right, "", logo->color_text[1], attr_value, art->reset);
+               "%*s%s%s%s%*s%s%s%s", beg_space, "", logo->color_text[0], attribute_fields[attr_type], art->reset, space_right, "", logo->color_text[1], attr_value, art->reset);
       }
     }
     printOutLine(lbuf, art, termw);
@@ -865,18 +885,7 @@ bool print_cpufetch_arm(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
   char* soc_name = get_soc_name(cpu->soc);
   char* features = get_str_features(cpu);
   setAttribute(art, ATTRIBUTE_SOC, soc_name);
-
-  // Currently no reliable way to identify the specific SoC on Windows
-  // https://github.com/Dr-Noob/cpufetch/pull/273
-  // Hide manufacturing process
-#if !defined(_WIN32)
-  // In the case that the model is unknown but the vendor isn't (this is, when
-  // guess_raw_soc_from_devtree succeeded), do not show the manufacturing process
-  // (as it will be unknown)
-  if (cpu->soc->model != SOC_MODEL_UNKNOWN ||
-    (cpu->soc->model == SOC_MODEL_UNKNOWN && cpu->soc->vendor == SOC_VENDOR_UNKNOWN))
   setAttribute(art, ATTRIBUTE_TECHNOLOGY, manufacturing_process);
-#endif
 
   if(cpu->num_cpus == 1) {
     char* uarch = get_str_uarch(cpu);
@@ -914,8 +923,8 @@ bool print_cpufetch_arm(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
     setAttribute(art, ATTRIBUTE_HYPERVISOR, cpu->hv->hv_name);
   }
 
-  bool use_short = false;
+  const char** attribute_fields = ATTRIBUTE_FIELDS;
-  uint32_t longest_attribute = longest_attribute_length(art, use_short);
+  uint32_t longest_attribute = longest_attribute_length(art, attribute_fields);
   uint32_t longest_field = longest_field_length_arm(art, longest_attribute);
   choose_ascii_art(art, cs, term, longest_field);
 
@@ -927,11 +936,11 @@ bool print_cpufetch_arm(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
   if(!ascii_fits_screen(term->w, *art->art, longest_field)) {
     // Despite of choosing the smallest logo, the output does not fit
     // Choose the shorter field names and recalculate the longest attr
-    use_short = true;
+    attribute_fields = ATTRIBUTE_FIELDS_SHORT;
-    longest_attribute = longest_attribute_length(art, use_short);
+    longest_attribute = longest_attribute_length(art, attribute_fields);
   }
 
-  print_ascii_arm(art, longest_attribute, term->w, use_short);
+  print_ascii_arm(art, longest_attribute, term->w, attribute_fields);
 
   free(manufacturing_process);
   free(pp);
@@ -956,7 +965,7 @@ uint64_t number_of_bits(uint64_t i) {
   return (((i + (i >> 4)) & 0xF0F0F0F0F0F0F0F) * 0x101010101010101) >> 56;
 }
 
-void print_ascii_riscv(struct ascii* art, uint32_t la, int32_t termw, bool use_short, uint64_t extensions_mask) {
+void print_ascii_riscv(struct ascii* art, uint32_t la, int32_t termw, const char** attribute_fields, uint64_t extensions_mask) {
   struct ascii_logo* logo = art->art;
   int attr_to_print = 0;
   int attr_type;
@@ -1024,11 +1033,10 @@ void print_ascii_riscv(struct ascii* art, uint32_t la, int32_t termw, bool use_s
       else {
         attr_to_print++;
         beg_space = 0;
-        const char* attr_str = use_short ? ATTRIBUTE_INFO[attr_type].shortname : ATTRIBUTE_INFO[attr_type].name;
+        space_right = 2 + 1 + (la - strlen(attribute_fields[attr_type]));
-        space_right = 2 + 1 + (la - strlen(attr_str));
 
-        printOut(lbuf, beg_space + strlen(attr_str) + space_right + strlen(attr_value),
+        printOut(lbuf, beg_space + strlen(attribute_fields[attr_type]) + space_right + strlen(attr_value),
-                 "%*s%s%s%s%*s%s%s%s", beg_space, "", logo->color_text[0], attr_str, art->reset, space_right, "", logo->color_text[1], attr_value, art->reset);
+                 "%*s%s%s%s%*s%s%s%s", beg_space, "", logo->color_text[0], attribute_fields[attr_type], art->reset, space_right, "", logo->color_text[1], attr_value, art->reset);
       }
     }
     printOutLine(lbuf, art, termw);
@@ -1066,19 +1074,19 @@ bool print_cpufetch_riscv(struct cpuInfo* cpu, STYLE s, struct color** cs, struc
   setAttribute(art, ATTRIBUTE_PEAK, pp);
 
   // Step 3. Print output
-  bool use_short = false;
+  const char** attribute_fields = ATTRIBUTE_FIELDS;
-  uint32_t longest_attribute = longest_attribute_length(art, use_short);
+  uint32_t longest_attribute = longest_attribute_length(art, attribute_fields);
   uint32_t longest_field = longest_field_length(art, longest_attribute);
   choose_ascii_art(art, cs, term, longest_field);
 
   if(!ascii_fits_screen(term->w, *art->art, longest_field)) {
     // Despite of choosing the smallest logo, the output does not fit
     // Choose the shorter field names and recalculate the longest attr
-    use_short = true;
+    attribute_fields = ATTRIBUTE_FIELDS_SHORT;
-    longest_attribute = longest_attribute_length(art, use_short);
+    longest_attribute = longest_attribute_length(art, attribute_fields);
   }
 
-  print_ascii_riscv(art, longest_attribute, term->w, use_short, cpu->ext->mask);
+  print_ascii_riscv(art, longest_attribute, term->w, attribute_fields, cpu->ext->mask);
 
   return true;
 }

src/common/soc.c

@@ -24,12 +24,10 @@ static char* soc_trademark_string[] = {
   [SOC_VENDOR_AMPERE]     = "Ampere ",
   [SOC_VENDOR_NXP]        = "NXP ",
   [SOC_VENDOR_AMLOGIC]    = "Amlogic ",
-  [SOC_VENDOR_MARVELL]    = "Marvell",
   // RISC-V
   [SOC_VENDOR_SIFIVE]     = "SiFive ",
   [SOC_VENDOR_STARFIVE]   = "StarFive ",
   [SOC_VENDOR_SIPEED]     = "Sipeed ",
-  [SOC_VENDOR_SPACEMIT]   = "SpacemiT ",
   // ARM & RISC-V
   [SOC_VENDOR_ALLWINNER]  = "Allwinner "
 };
@@ -80,28 +78,6 @@ void fill_soc(struct system_on_chip* soc, char* soc_name, SOC soc_model, int32_t
   }
 }
 
-void fill_soc_raw(struct system_on_chip* soc, char* soc_name, VENDOR vendor) {
-  soc->model = SOC_MODEL_UNKNOWN;
-  soc->vendor = vendor;
-  soc->process = UNKNOWN;
-
-  int len = strlen(soc_name) + strlen(soc_trademark_string[soc->vendor]) + 1;
-  soc->raw_name = emalloc(sizeof(char) * len);
-  sprintf(soc->raw_name, "%s%s", soc_trademark_string[soc->vendor], soc_name);
-}
-
-#ifdef _WIN32
-VENDOR try_match_soc_vendor_name(char* vendor_name)
-{
-  for(size_t i=1; i < sizeof(soc_trademark_string)/sizeof(soc_trademark_string[0]); i++) {
-    if(strstr(vendor_name, soc_trademark_string[i]) != NULL) {
-      return i;
-    }
-  }
-  return SOC_VENDOR_UNKNOWN;
-}
-#endif
-
 bool match_soc(struct system_on_chip* soc, char* raw_name, char* expected_name, char* soc_name, SOC soc_model, int32_t process) {
   int len1 = strlen(raw_name);
   int len2 = strlen(expected_name);

src/common/soc.h

@@ -28,12 +28,10 @@ enum {
   SOC_VENDOR_AMPERE,
   SOC_VENDOR_NXP,
   SOC_VENDOR_AMLOGIC,
-  SOC_VENDOR_MARVELL,
   // RISC-V
   SOC_VENDOR_SIFIVE,
   SOC_VENDOR_STARFIVE,
   SOC_VENDOR_SIPEED,
-  SOC_VENDOR_SPACEMIT,
   // ARM & RISC-V
   SOC_VENDOR_ALLWINNER
 };
@@ -52,10 +50,6 @@ VENDOR get_soc_vendor(struct system_on_chip* soc);
 bool match_soc(struct system_on_chip* soc, char* raw_name, char* expected_name, char* soc_name, SOC soc_model, int32_t process);
 char* get_str_process(struct system_on_chip* soc);
 void fill_soc(struct system_on_chip* soc, char* soc_name, SOC soc_model, int32_t process);
-void fill_soc_raw(struct system_on_chip* soc, char* soc_name, VENDOR vendor);
-#ifdef _WIN32
-VENDOR try_match_soc_vendor_name(char* vendor_name);
-#endif
 
 #define SOC_START if (false) {}
 #define SOC_EQ(raw_name, expected_name, soc_name, soc_model, soc, process) \

src/common/udev.c

@@ -361,69 +361,3 @@ char* get_devtree_compatible(int *filelen) {
 
   return buf;
 }
-
-// Returns a list of structs devtree, each containing both the vendor and the
-// model, coming from the compatible file from the device tree. In this
-// context, vendor refers to the first string of every entry and the model to
-// the second. For instance, given a compatible file with:
-// "str1,foo1.str2,foo2" (where . denotes the NULL byte, i.e., the separator),
-// then this function will return a list with two structs, the first one
-// containing str1 and foo1 and the other containing str2 and foo2.
-struct devtree** get_devtree_compatible_struct(int *num_vendors_ptr) {
-  int len;
-  char* dt = get_devtree_compatible(&len);
-  if (dt == NULL) {
-    return NULL;
-  }
-
-  int num_vendors = 0;
-  char* ptr = dt;
-
-  for (int ptrpos = 0; ptrpos < len; ptrpos = (ptr-dt)) {
-    ptr = memchr(ptr, '\0', len);
-    if (ptr == NULL) {
-      printBug("get_devtree_compatible_struct: Unable to find delimiter (1) (num_vendors=%d)", num_vendors);
-      return NULL;
-    }
-    ptr++;
-    num_vendors++;
-  }
-
-  struct devtree** vendors = emalloc(sizeof(struct devtree *) * num_vendors);
-  ptr = dt;
-
-  for (int ptrpos = 0, i = 0; ptrpos < len; ptrpos = (ptr-dt), i++) {
-    char* comma_ptr = strstr(ptr, ",");
-    if (comma_ptr == NULL) {
-      printBug("get_devtree_compatible_struct: Unable to find comma (num_vendors=%d)", num_vendors);
-      return NULL;
-    }
-    comma_ptr = comma_ptr-1; // Point right before comma
-
-    char* end_ptr = memchr(comma_ptr, '\0', len - ptrpos);
-    if (end_ptr == NULL) {
-      printBug("get_devtree_compatible_struct: Unable to find delimiter (2) (num_vendors=%d)", num_vendors);
-      return NULL;
-    }
-
-    int vendor_str_len = (comma_ptr-ptr)+1;
-    int model_str_len = (end_ptr-(comma_ptr+2))+1;
-
-    vendors[i] = emalloc(sizeof(struct devtree));
-    vendors[i]->vendor = ecalloc(vendor_str_len, sizeof(char));
-    vendors[i]->model = ecalloc(model_str_len, sizeof(char));
-
-    strncpy(vendors[i]->vendor, ptr, vendor_str_len);
-    strncpy(vendors[i]->model, comma_ptr+2, model_str_len);
-
-    ptr = memchr(ptr, '\0', len);
-    if (ptr == NULL) {
-      printBug("get_devtree_compatible_struct: Unable to find delimiter (3) (num_vendors=%d)", num_vendors);
-      return NULL;
-    }
-    ptr++; // Point right after delimiter
-  }
-
-  *num_vendors_ptr = num_vendors;
-  return vendors;
-}

src/common/udev.h

@@ -31,11 +31,6 @@
 #define _PATH_CACHE_MAX_LEN     200
 #define _PATH_PACKAGE_MAX_LEN   200
 
-struct devtree {
-  char* vendor;
-  char* model;
-};
-
 char* read_file(char* path, int* len);
 long get_max_freq_from_file(uint32_t core);
 long get_min_freq_from_file(uint32_t core);
@@ -49,6 +44,5 @@ int get_ncores_from_cpuinfo(void);
 char* get_field_from_cpuinfo(char* CPUINFO_FIELD);
 bool is_devtree_compatible(char* str);
 char* get_devtree_compatible(int *filelen);
-struct devtree** get_devtree_compatible_struct(int *num_vendors);
 
 #endif

src/riscv/riscv.c

@@ -62,7 +62,6 @@ int parse_multi_letter_extension(struct extensions* ext, char* e) {
   SET_ISA_EXT_MAP("zicbom",      RISCV_ISA_EXT_ZICBOM)
   SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE)
   SET_ISA_EXT_MAP("svnapot",     RISCV_ISA_EXT_SVNAPOT)
-  SET_ISA_EXT_MAP("zicbop",      RISCV_ISA_EXT_ZICBOP)
   SET_ISA_EXT_MAP("zicboz",      RISCV_ISA_EXT_ZICBOZ)
   SET_ISA_EXT_MAP("smaia",       RISCV_ISA_EXT_SMAIA)
   SET_ISA_EXT_MAP("ssaia",       RISCV_ISA_EXT_SSAIA)
@@ -72,65 +71,6 @@ int parse_multi_letter_extension(struct extensions* ext, char* e) {
   SET_ISA_EXT_MAP("zicsr",       RISCV_ISA_EXT_ZICSR)
   SET_ISA_EXT_MAP("zifencei",    RISCV_ISA_EXT_ZIFENCEI)
   SET_ISA_EXT_MAP("zihpm",       RISCV_ISA_EXT_ZIHPM)
-  SET_ISA_EXT_MAP("smstateen",   RISCV_ISA_EXT_SMSTATEEN)
-  SET_ISA_EXT_MAP("zicond",      RISCV_ISA_EXT_ZICOND)
-  SET_ISA_EXT_MAP("zbc",         RISCV_ISA_EXT_ZBC)
-  SET_ISA_EXT_MAP("zbkb",        RISCV_ISA_EXT_ZBKB)
-  SET_ISA_EXT_MAP("zbkc",        RISCV_ISA_EXT_ZBKC)
-  SET_ISA_EXT_MAP("zbkx",        RISCV_ISA_EXT_ZBKX)
-  SET_ISA_EXT_MAP("zknd",        RISCV_ISA_EXT_ZKND)
-  SET_ISA_EXT_MAP("zkne",        RISCV_ISA_EXT_ZKNE)
-  SET_ISA_EXT_MAP("zknh",        RISCV_ISA_EXT_ZKNH)
-  SET_ISA_EXT_MAP("zkr",         RISCV_ISA_EXT_ZKR)
-  SET_ISA_EXT_MAP("zksed",       RISCV_ISA_EXT_ZKSED)
-  SET_ISA_EXT_MAP("zksh",        RISCV_ISA_EXT_ZKSH)
-  SET_ISA_EXT_MAP("zkt",         RISCV_ISA_EXT_ZKT)
-  SET_ISA_EXT_MAP("zvbb",        RISCV_ISA_EXT_ZVBB)
-  SET_ISA_EXT_MAP("zvbc",        RISCV_ISA_EXT_ZVBC)
-  SET_ISA_EXT_MAP("zvkb",        RISCV_ISA_EXT_ZVKB)
-  SET_ISA_EXT_MAP("zvkg",        RISCV_ISA_EXT_ZVKG)
-  SET_ISA_EXT_MAP("zvkned",      RISCV_ISA_EXT_ZVKNED)
-  SET_ISA_EXT_MAP("zvknha",      RISCV_ISA_EXT_ZVKNHA)
-  SET_ISA_EXT_MAP("zvknhb",      RISCV_ISA_EXT_ZVKNHB)
-  SET_ISA_EXT_MAP("zvksed",      RISCV_ISA_EXT_ZVKSED)
-  SET_ISA_EXT_MAP("zvksh",       RISCV_ISA_EXT_ZVKSH)
-  SET_ISA_EXT_MAP("zvkt",        RISCV_ISA_EXT_ZVKT)
-  SET_ISA_EXT_MAP("zfh",         RISCV_ISA_EXT_ZFH)
-  SET_ISA_EXT_MAP("zfhmin",      RISCV_ISA_EXT_ZFHMIN)
-  SET_ISA_EXT_MAP("zihintntl",   RISCV_ISA_EXT_ZIHINTNTL)
-  SET_ISA_EXT_MAP("zvfh",        RISCV_ISA_EXT_ZVFH)
-  SET_ISA_EXT_MAP("zvfhmin",     RISCV_ISA_EXT_ZVFHMIN)
-  SET_ISA_EXT_MAP("zfa",         RISCV_ISA_EXT_ZFA)
-  SET_ISA_EXT_MAP("ztso",        RISCV_ISA_EXT_ZTSO)
-  SET_ISA_EXT_MAP("zacas",       RISCV_ISA_EXT_ZACAS)
-  SET_ISA_EXT_MAP("zve32x",      RISCV_ISA_EXT_ZVE32X)
-  SET_ISA_EXT_MAP("zve32f",      RISCV_ISA_EXT_ZVE32F)
-  SET_ISA_EXT_MAP("zve64x",      RISCV_ISA_EXT_ZVE64X)
-  SET_ISA_EXT_MAP("zve64f",      RISCV_ISA_EXT_ZVE64F)
-  SET_ISA_EXT_MAP("zve64d",      RISCV_ISA_EXT_ZVE64D)
-  SET_ISA_EXT_MAP("zimop",       RISCV_ISA_EXT_ZIMOP)
-  SET_ISA_EXT_MAP("zca",         RISCV_ISA_EXT_ZCA)
-  SET_ISA_EXT_MAP("zcb",         RISCV_ISA_EXT_ZCB)
-  SET_ISA_EXT_MAP("zcd",         RISCV_ISA_EXT_ZCD)
-  SET_ISA_EXT_MAP("zcf",         RISCV_ISA_EXT_ZCF)
-  SET_ISA_EXT_MAP("zcmop",       RISCV_ISA_EXT_ZCMOP)
-  SET_ISA_EXT_MAP("zawrs",       RISCV_ISA_EXT_ZAWRS)
-  SET_ISA_EXT_MAP("svvptc",      RISCV_ISA_EXT_SVVPTC)
-  SET_ISA_EXT_MAP("smmpm",       RISCV_ISA_EXT_SMMPM)
-  SET_ISA_EXT_MAP("smnpm",       RISCV_ISA_EXT_SMNPM)
-  SET_ISA_EXT_MAP("ssnpm",       RISCV_ISA_EXT_SSNPM)
-  SET_ISA_EXT_MAP("zabha",       RISCV_ISA_EXT_ZABHA)
-  SET_ISA_EXT_MAP("ziccrse",     RISCV_ISA_EXT_ZICCRSE)
-  SET_ISA_EXT_MAP("svade",       RISCV_ISA_EXT_SVADE)
-  SET_ISA_EXT_MAP("svadu",       RISCV_ISA_EXT_SVADU)
-  SET_ISA_EXT_MAP("zfbfmin",     RISCV_ISA_EXT_ZFBFMIN)
-  SET_ISA_EXT_MAP("zvfbfmin",    RISCV_ISA_EXT_ZVFBFMIN)
-  SET_ISA_EXT_MAP("zvfbfwma",    RISCV_ISA_EXT_ZVFBFWMA)
-  SET_ISA_EXT_MAP("zaamo",       RISCV_ISA_EXT_ZAAMO)
-  SET_ISA_EXT_MAP("zalrsc",      RISCV_ISA_EXT_ZALRSC)
-  SET_ISA_EXT_MAP("zicbop",      RISCV_ISA_EXT_ZICBOP)
-  SET_ISA_EXT_MAP("ime",         RISCV_ISA_EXT_IME)
-
   if(!maskset) {
     printBug("parse_multi_letter_extension: Unknown multi-letter extension: %s", multi_letter_extension);
     return -1;
@@ -160,8 +100,8 @@ struct extensions* get_extensions_from_str(char* str) {
     return ext;
   }
 
-  int len = strlen(str)+1;
+  int len = strlen(str);
-  ext->str = emalloc(len * sizeof(char));
+  ext->str = ecalloc(len+1, sizeof(char));
   strncpy(ext->str, str, sizeof(char) * len);
 
   // Code inspired in Linux kernel (riscv_fill_hwcap):
@@ -216,12 +156,13 @@ struct cpuInfo* get_cpu_info(void) {
   topo->cach = NULL;
   cpu->topo = topo;
 
+  char* cpuinfo_str = get_uarch_from_cpuinfo();
   char* ext_str = get_extensions_from_cpuinfo();
   cpu->hv = emalloc(sizeof(struct hypervisor));
   cpu->hv->present = false;
   cpu->ext = get_extensions_from_str(ext_str);
   if(cpu->ext->str != NULL && cpu->ext->mask == 0) return NULL;
-  cpu->arch = get_uarch(cpu);
+  cpu->arch = get_uarch_from_cpuinfo_str(cpuinfo_str, cpu);
   cpu->soc = get_soc(cpu);
   cpu->freq = get_frequency_info(0);
   cpu->peak_performance = get_peak_performance(cpu);

src/riscv/riscv.h

@@ -32,71 +32,11 @@ enum riscv_isa_ext_id {
   RISCV_ISA_EXT_ZICSR,
   RISCV_ISA_EXT_ZIFENCEI,
   RISCV_ISA_EXT_ZIHPM,
-  RISCV_ISA_EXT_SMSTATEEN,
-  RISCV_ISA_EXT_ZICOND,
-  RISCV_ISA_EXT_ZBC,
-  RISCV_ISA_EXT_ZBKB,
-  RISCV_ISA_EXT_ZBKC,
-  RISCV_ISA_EXT_ZBKX,
-  RISCV_ISA_EXT_ZKND,
-  RISCV_ISA_EXT_ZKNE,
-  RISCV_ISA_EXT_ZKNH,
-  RISCV_ISA_EXT_ZKR,
-  RISCV_ISA_EXT_ZKSED,
-  RISCV_ISA_EXT_ZKSH,
-  RISCV_ISA_EXT_ZKT,
-  RISCV_ISA_EXT_ZVBB,
-  RISCV_ISA_EXT_ZVBC,
-  RISCV_ISA_EXT_ZVKB,
-  RISCV_ISA_EXT_ZVKG,
-  RISCV_ISA_EXT_ZVKNED,
-  RISCV_ISA_EXT_ZVKNHA,
-  RISCV_ISA_EXT_ZVKNHB,
-  RISCV_ISA_EXT_ZVKSED,
-  RISCV_ISA_EXT_ZVKSH,
-  RISCV_ISA_EXT_ZVKT,
-  RISCV_ISA_EXT_ZFH,
-  RISCV_ISA_EXT_ZFHMIN,
-  RISCV_ISA_EXT_ZIHINTNTL,
-  RISCV_ISA_EXT_ZVFH,
-  RISCV_ISA_EXT_ZVFHMIN,
-  RISCV_ISA_EXT_ZFA,
-  RISCV_ISA_EXT_ZTSO,
-  RISCV_ISA_EXT_ZACAS,
-  RISCV_ISA_EXT_ZVE32X,
-  RISCV_ISA_EXT_ZVE32F,
-  RISCV_ISA_EXT_ZVE64X,
-  RISCV_ISA_EXT_ZVE64F,
-  RISCV_ISA_EXT_ZVE64D,
-  RISCV_ISA_EXT_ZIMOP,
-  RISCV_ISA_EXT_ZCA,
-  RISCV_ISA_EXT_ZCB,
-  RISCV_ISA_EXT_ZCD,
-  RISCV_ISA_EXT_ZCF,
-  RISCV_ISA_EXT_ZCMOP,
-  RISCV_ISA_EXT_ZAWRS,
-  RISCV_ISA_EXT_SVVPTC,
-  RISCV_ISA_EXT_SMMPM,
-  RISCV_ISA_EXT_SMNPM,
-  RISCV_ISA_EXT_SSNPM,
-  RISCV_ISA_EXT_ZABHA,
-  RISCV_ISA_EXT_ZICCRSE,
-  RISCV_ISA_EXT_SVADE,
-  RISCV_ISA_EXT_SVADU,
-  RISCV_ISA_EXT_ZFBFMIN,
-  RISCV_ISA_EXT_ZVFBFMIN,
-  RISCV_ISA_EXT_ZVFBFWMA,
-  RISCV_ISA_EXT_ZAAMO,
-  RISCV_ISA_EXT_ZALRSC,
-  RISCV_ISA_EXT_ZICBOP,
-  RISCV_ISA_EXT_IME,
   RISCV_ISA_EXT_ID_MAX
 };
 
 // https://five-embeddev.com/riscv-isa-manual/latest/preface.html#preface
 // https://en.wikichip.org/wiki/risc-v/standard_extensions
-// (Zicbop) https://github.com/riscv/riscv-CMOs/blob/master/cmobase/Zicbop.adoc
-// https://raw.githubusercontent.com/riscv/riscv-CMOs/master/specifications/cmobase-v1.0.1.pdf
 // Included all except for G
 static const struct extension extension_list[] = {
   { 'i' - 'a', "(I) Integer Instruction Set" },
@@ -124,7 +64,6 @@ static const struct extension extension_list[] = {
   { RISCV_ISA_EXT_ZIHINTPAUSE, "(Zihintpause) Pause Hint" },
   { RISCV_ISA_EXT_SVNAPOT,     "(Svnapot) Naturally Aligned Power of Two Pages" },
   { RISCV_ISA_EXT_ZICBOZ,      "(Zicboz) Cache Block Zero Operations" },
-  { RISCV_ISA_EXT_ZICBOP,      "(Zicbop) Cache Block Prefetch Operations" },
   { RISCV_ISA_EXT_SMAIA,       "(Smaia) Advanced Interrupt Architecture" },
   { RISCV_ISA_EXT_SSAIA,       "(Ssaia) Advanced Interrupt Architecture" },
   { RISCV_ISA_EXT_ZBA,         "(Zba) Address Generation" },
@@ -132,65 +71,7 @@ static const struct extension extension_list[] = {
   { RISCV_ISA_EXT_ZICNTR,      "(Zicntr) Base Counters and Timers" },
   { RISCV_ISA_EXT_ZICSR,       "(Zicsr) Control and Status Register" },
   { RISCV_ISA_EXT_ZIFENCEI,    "(Zifencei) Instruction-Fetch Fence" },
-  { RISCV_ISA_EXT_ZIHPM,       "(Zihpm) Hardware Performance Counters" },
+  { RISCV_ISA_EXT_ZIHPM,       "(Zihpm) Hardware Performance Counters" }
-  { RISCV_ISA_EXT_SMSTATEEN,   "(smstateen) " },
-  { RISCV_ISA_EXT_ZICOND,      "(zicond) " },
-  { RISCV_ISA_EXT_ZBC,         "(zbc) " },
-  { RISCV_ISA_EXT_ZBKB,        "(zbkb) " },
-  { RISCV_ISA_EXT_ZBKC,        "(zbkc) " },
-  { RISCV_ISA_EXT_ZBKX,        "(zbkx) " },
-  { RISCV_ISA_EXT_ZKND,        "(zknd) " },
-  { RISCV_ISA_EXT_ZKNE,        "(zkne) " },
-  { RISCV_ISA_EXT_ZKNH,        "(zknh) " },
-  { RISCV_ISA_EXT_ZKR,         "(zkr) " },
-  { RISCV_ISA_EXT_ZKSED,       "(zksed) " },
-  { RISCV_ISA_EXT_ZKSH,        "(zksh) " },
-  { RISCV_ISA_EXT_ZKT,         "(zkt) " },
-  { RISCV_ISA_EXT_ZVBB,        "(zvbb) " },
-  { RISCV_ISA_EXT_ZVBC,        "(zvbc) " },
-  { RISCV_ISA_EXT_ZVKB,        "(zvkb) " },
-  { RISCV_ISA_EXT_ZVKG,        "(zvkg) " },
-  { RISCV_ISA_EXT_ZVKNED,      "(zvkned) " },
-  { RISCV_ISA_EXT_ZVKNHA,      "(zvknha) " },
-  { RISCV_ISA_EXT_ZVKNHB,      "(zvknhb) " },
-  { RISCV_ISA_EXT_ZVKSED,      "(zvksed) " },
-  { RISCV_ISA_EXT_ZVKSH,       "(zvksh) " },
-  { RISCV_ISA_EXT_ZVKT,        "(zvkt) " },
-  { RISCV_ISA_EXT_ZFH,         "(zfh) " },
-  { RISCV_ISA_EXT_ZFHMIN,      "(zfhmin) " },
-  { RISCV_ISA_EXT_ZIHINTNTL,   "(zihintntl) " },
-  { RISCV_ISA_EXT_ZVFH,        "(zvfh) " },
-  { RISCV_ISA_EXT_ZVFHMIN,     "(zvfhmin) " },
-  { RISCV_ISA_EXT_ZFA,         "(zfa) " },
-  { RISCV_ISA_EXT_ZTSO,        "(ztso) " },
-  { RISCV_ISA_EXT_ZACAS,       "(zacas) " },
-  { RISCV_ISA_EXT_ZVE32X,      "(zve32x) " },
-  { RISCV_ISA_EXT_ZVE32F,      "(zve32f) " },
-  { RISCV_ISA_EXT_ZVE64X,      "(zve64x) " },
-  { RISCV_ISA_EXT_ZVE64F,      "(zve64f) " },
-  { RISCV_ISA_EXT_ZVE64D,      "(zve64d) " },
-  { RISCV_ISA_EXT_ZIMOP,       "(zimop) " },
-  { RISCV_ISA_EXT_ZCA,         "(zca) " },
-  { RISCV_ISA_EXT_ZCB,         "(zcb) " },
-  { RISCV_ISA_EXT_ZCD,         "(zcd) " },
-  { RISCV_ISA_EXT_ZCF,         "(zcf) " },
-  { RISCV_ISA_EXT_ZCMOP,       "(zcmop) " },
-  { RISCV_ISA_EXT_ZAWRS,       "(zawrs) " },
-  { RISCV_ISA_EXT_SVVPTC,      "(svvptc) " },
-  { RISCV_ISA_EXT_SMMPM,       "(smmpm) " },
-  { RISCV_ISA_EXT_SMNPM,       "(smnpm) " },
-  { RISCV_ISA_EXT_SSNPM,       "(ssnpm) " },
-  { RISCV_ISA_EXT_ZABHA,       "(zabha) " },
-  { RISCV_ISA_EXT_ZICCRSE,     "(ziccrse) " },
-  { RISCV_ISA_EXT_SVADE,       "(svade) " },
-  { RISCV_ISA_EXT_SVADU,       "(svadu) " },
-  { RISCV_ISA_EXT_ZFBFMIN,     "(zfbfmin) " },
-  { RISCV_ISA_EXT_ZVFBFMIN,    "(zvfbfmin) " },
-  { RISCV_ISA_EXT_ZVFBFWMA,    "(zvfbfwma) " },
-  { RISCV_ISA_EXT_ZAAMO,       "(zaamo) " },
-  { RISCV_ISA_EXT_ZALRSC,      "(zalrsc) " },
-  { RISCV_ISA_EXT_ZICBOP,      "(zicbop) " },
-  { RISCV_ISA_EXT_IME,         "(ime) Integrated Matrix Extension" },
 };
 
 struct cpuInfo* get_cpu_info(void);

src/riscv/soc.c

@@ -38,12 +38,6 @@ bool match_sipeed(char* soc_name, struct system_on_chip* soc) {
   SOC_END
 }
 
-bool match_spacemit(char* soc_name, struct system_on_chip* soc) {
-  SOC_START
-  SOC_EQ(soc_name, "k1-x", "K1-X", SOC_SPACEMIT_K1X, soc, 22) // https://github.com/Dr-Noob/cpufetch/issues/286 https://www.spacemit.com/en/spacemit-x60-core/
-  SOC_END
-}
-
 struct system_on_chip* parse_soc_from_string(struct system_on_chip* soc) {
   char* raw_name = soc->raw_name;
 
@@ -56,9 +50,6 @@ struct system_on_chip* parse_soc_from_string(struct system_on_chip* soc) {
   if(match_sifive(raw_name, soc))
     return soc;
 
-  if(match_spacemit(raw_name, soc))
-    return soc;
-
   match_sipeed(raw_name, soc);
   return soc;
 }

src/riscv/socs.h

@@ -13,8 +13,6 @@ enum {
   SOC_ALLWINNER_D1H,
   // SIPEED
   SOC_SIPEED_LICHEEPI4A,
-  // SPACEMIT
-  SOC_SPACEMIT_K1X,
   // UNKNOWN
   SOC_MODEL_UNKNOWN
 };
@@ -24,7 +22,6 @@ inline static VENDOR get_soc_vendor_from_soc(SOC soc) {
   if(soc >= SOC_STARFIVE_VF2 && soc <= SOC_STARFIVE_VF2) return SOC_VENDOR_STARFIVE;
   if(soc >= SOC_ALLWINNER_D1H && soc <= SOC_ALLWINNER_D1H) return SOC_VENDOR_ALLWINNER;
   if(soc >= SOC_SIPEED_LICHEEPI4A && soc <= SOC_SIPEED_LICHEEPI4A) return SOC_VENDOR_SIPEED;
-  if(soc >= SOC_SPACEMIT_K1X && soc <= SOC_SPACEMIT_K1X) return SOC_VENDOR_SPACEMIT;
   return SOC_VENDOR_UNKNOWN;
 }
 

src/riscv/uarch.c

@@ -4,7 +4,6 @@
 #include <string.h>
 
 #include "uarch.h"
-#include "udev.h"
 #include "../common/global.h"
 
 typedef uint32_t MICROARCH;
@@ -13,7 +12,6 @@ struct uarch {
   MICROARCH uarch;
   char* uarch_str;
   char* cpuinfo_str;
-  struct riscv_cpuinfo* ci;
 };
 
 enum {
@@ -23,20 +21,13 @@ enum {
   UARCH_U74,
   // THEAD
   UARCH_C906,
-  UARCH_C910,
+  UARCH_C910
-  // SPACEMIT
-  UARCH_X60
 };
 
 #define UARCH_START if (false) {}
 #define CHECK_UARCH(arch, cpu, cpuinfo_str, uarch_str, str, uarch, vendor) \
    else if (strcmp(cpuinfo_str, uarch_str) == 0) fill_uarch(arch, cpu, str, uarch, vendor);
-#define UARCH_END else { printWarn("Unknown microarchitecture detected: uarch='%s'", cpuinfo_str); fill_uarch(arch, cpu, "Unknown", UARCH_UNKNOWN, CPU_VENDOR_UNKNOWN); }
+#define UARCH_END else { printBug("Unknown microarchitecture detected: uarch='%s'", cpuinfo_str); fill_uarch(arch, cpu, "Unknown", UARCH_UNKNOWN, CPU_VENDOR_UNKNOWN); }
-
-#define ARCHID_START if (false) {}
-#define CHECK_ARCHID(arch, marchid_val, str, uarch, vendor) \
-  else if (arch->ci->marchid == (unsigned long) marchid_val) fill_uarch(arch, cpu, str, uarch, vendor);
-#define ARCHID_END else { printWarn("Unknown microarchitecture detected: marchid=0x%.8X", arch->ci->marchid); fill_uarch(arch, cpu, "Unknown", UARCH_UNKNOWN, CPU_VENDOR_UNKNOWN); }
 
 void fill_uarch(struct uarch* arch, struct cpuInfo* cpu, char* str, MICROARCH u, VENDOR vendor) {
   arch->uarch = u;
@@ -48,8 +39,14 @@ void fill_uarch(struct uarch* arch, struct cpuInfo* cpu, char* str, MICROARCH u,
 // https://elixir.bootlin.com/linux/latest/source/Documentation/devicetree/bindings/riscv/cpus.yaml
 // SiFive: https://www.sifive.com/risc-v-core-ip
 // T-Head: https://www.t-head.cn/product/c906
-struct uarch* get_uarch_from_cpuinfo_str(char* cpuinfo_str, struct cpuInfo* cpu, struct uarch* arch) {
+struct uarch* get_uarch_from_cpuinfo_str(char* cpuinfo_str, struct cpuInfo* cpu) {
+  struct uarch* arch = emalloc(sizeof(struct uarch));
   arch->cpuinfo_str = cpuinfo_str;
+  if(cpuinfo_str == NULL) {
+    printWarn("get_uarch_from_cpuinfo: Unable to detect microarchitecture, cpuinfo_str is NULL");
+    fill_uarch(arch, cpu, "Unknown", UARCH_UNKNOWN, CPU_VENDOR_UNKNOWN);
+    return arch;
+  }
 
   // U74/U74-MC:
   // SiFive says that U74-MC is "Multicore: four U74 cores and one S76 core" while
@@ -73,41 +70,6 @@ struct uarch* get_uarch_from_cpuinfo_str(char* cpuinfo_str, struct cpuInfo* cpu,
   return arch;
 }
 
-// Use marchid to get the microarchitecture
-struct uarch* get_uarch_from_riscv_cpuinfo(struct cpuInfo* cpu, struct uarch* arch) {
-
-  ARCHID_START
-  CHECK_ARCHID(arch, 0x8000000058000001, "X60", UARCH_X60, CPU_VENDOR_SPACEMIT) // https://github.com/Dr-Noob/cpufetch/issues/286
-  ARCHID_END
-
-  return arch;
-}
-
-struct uarch* get_uarch(struct cpuInfo* cpu) {
-  char* cpuinfo_str = get_uarch_from_cpuinfo();
-  struct uarch* arch = emalloc(sizeof(struct uarch));
-  arch->uarch = UARCH_UNKNOWN;
-  arch->ci = NULL;
-
-  if (cpuinfo_str == NULL) {
-    printWarn("get_uarch_from_cpuinfo: Unable to detect microarchitecture using uarch: cpuinfo_str is NULL");
-    arch->ci = get_riscv_cpuinfo();
-
-    if (arch->ci == NULL || arch->ci->marchid == 0)
-      printWarn("get_riscv_cpuinfo: Unable to get marchid from udev");
-    else
-      arch = get_uarch_from_riscv_cpuinfo(cpu, arch);
-  }
-  else {
-    arch = get_uarch_from_cpuinfo_str(cpuinfo_str, cpu, arch);
-  }
-
-  if (arch->uarch == UARCH_UNKNOWN)
-    fill_uarch(arch, cpu, "Unknown", UARCH_UNKNOWN, CPU_VENDOR_UNKNOWN);
-
-  return arch;
-}
-
 char* get_str_uarch(struct cpuInfo* cpu) {
   return cpu->arch->uarch_str;
 }

src/riscv/uarch.h

@@ -9,6 +9,6 @@ struct uarch;
 char* get_arch_cpuinfo_str(struct cpuInfo* cpu);
 char* get_str_uarch(struct cpuInfo* cpu);
 void free_uarch_struct(struct uarch* arch);
-struct uarch* get_uarch(struct cpuInfo* cpu);
+struct uarch* get_uarch_from_cpuinfo_str(char* cpuinfo_str, struct cpuInfo* cpu);
 
 #endif

src/riscv/udev.c

@@ -7,9 +7,6 @@
 #define _PATH_DEVTREE          "/proc/device-tree/compatible"
 #define CPUINFO_UARCH_STR      "uarch\t\t: "
 #define CPUINFO_EXTENSIONS_STR "isa\t\t: "
-#define CPUINFO_RISCV_MVENDORID "mvendorid\t:"
-#define CPUINFO_RISCV_MARCHID   "marchid\t\t:"
-#define CPUINFO_RISCV_MIMPID    "mimpid\t\t:"
 #define DEVTREE_HARDWARE_FIELD 0
 
 char* get_field_from_devtree(int DEVTREE_FIELD) {
@@ -78,52 +75,6 @@ char* parse_cpuinfo_field(char* field_str) {
   return ret;
 }
 
-unsigned long parse_cpuinfo_field_uint64(char* field_str) {
-  int filelen;
-  char* buf;
-  if((buf = read_file(_PATH_CPUINFO, &filelen)) == NULL) {
-    printWarn("read_file: %s: %s", _PATH_CPUINFO, strerror(errno));
-    return 0;
-  }
-
-  char* tmp = strstr(buf, field_str);
-  if(tmp == NULL) return 0;
-  tmp += strlen(field_str);
-
-  char* end;
-  errno = 0;
-  unsigned long ret = strtoul(tmp, &end, 16);
-  if (errno != 0) {
-    printWarn("strtoul: %s: %s", strerror(errno), tmp);
-    return 0;
-  }
-
-  return ret;
-}
-
-// Creates and fills in the riscv_cpuinfo struct (which contains
-// mvendorid, marchid and mimpid) using cpuinfo to fetch the values.
-//
-// Every RISC-V hart (hardware thread) [1] provides a
-// marchid (Machine Architecture ID register) CSR that encodes its
-// base microarchitecture [2]. For more information about
-// marchid and the rest of values, see [3].
-// [1] https://groups.google.com/a/groups.riscv.org/g/sw-dev/c/QKjUDjz_vKo
-// [2] https://github.com/riscv/riscv-isa-manual/blob/main/marchid.md
-// [3] https://five-embeddev.com/riscv-priv-isa-manual/Priv-v1.12/machine.html#machine-architecture-id-register-marchid
-struct riscv_cpuinfo *get_riscv_cpuinfo(void) {
-  struct riscv_cpuinfo* ci = emalloc(sizeof(struct riscv_cpuinfo));
-
-  ci->mvendorid = parse_cpuinfo_field_uint64(CPUINFO_RISCV_MVENDORID);
-  ci->marchid = parse_cpuinfo_field_uint64(CPUINFO_RISCV_MARCHID);
-  ci->mimpid = parse_cpuinfo_field_uint64(CPUINFO_RISCV_MIMPID);
-
-  if (ci->mvendorid == 0 && ci->mvendorid == 0 && ci->mvendorid == 0)
-    return NULL;
-
-  return ci;
-}
-
 char* get_hardware_from_devtree(void) {
   return get_field_from_devtree(DEVTREE_HARDWARE_FIELD);
 }

src/riscv/udev.h

@@ -5,16 +5,8 @@
 
 #define UNKNOWN -1
 
-// https://elixir.bootlin.com/linux/v6.10.6/source/arch/riscv/include/asm/cpufeature.h#L21
-struct riscv_cpuinfo {
-  unsigned long mvendorid;
-  unsigned long marchid;
-  unsigned long mimpid;
-};
-
 char* get_hardware_from_devtree(void);
 char* get_uarch_from_cpuinfo(void);
 char* get_extensions_from_cpuinfo(void);
-struct riscv_cpuinfo *get_riscv_cpuinfo(void);
 
 #endif

src/x86/cpuid.c

@@ -210,14 +210,18 @@ int64_t get_peak_performance(struct cpuInfo* cpu, bool accurate_pp) {
 
   for(int i=0; i < cpu->num_cpus; ptr = ptr->next_cpu, i++) {
     struct topology* topo = ptr->topo;
-    int64_t freq = get_freq(ptr->freq);
+    int64_t max_freq = get_freq(ptr->freq);
 
+    int64_t freq;
   #ifdef __linux__
     if(accurate_pp)
-      freq = get_freq_pp(ptr->freq);
+      freq = measure_frequency(ptr);
+    else
+      freq = max_freq;
   #else
     // Silence compiler warning
     (void)(accurate_pp);
+    freq = max_freq;
   #endif
 
     //First, check we have consistent data
@@ -333,15 +337,6 @@ struct features* get_features_info(struct cpuInfo* cpu) {
     bool hv_present = (ecx & (1U << 31)) != 0;
     if((cpu->hv = get_hp_info(hv_present)) == NULL)
       return NULL;
-    if(cpu->hv->present) {
-      // Hypervisor will likely mess up something and users will think that
-      // there is something wrong with cpufetch whereas actually cpufetch has
-      // nothing to do with it.
-      // https://github.com/Dr-Noob/cpufetch/issues/96
-      // https://github.com/Dr-Noob/cpufetch/issues/267
-      // https://github.com/Dr-Noob/cpufetch/issues/293
-      printWarn("You are running an hypervisor. Please note that it will likely tamper your results, so do not post an issue if you find anything incorrect");
-    }
   }
   else {
     printWarn("Can't read features information from cpuid (needed level is 0x%.8X, max is 0x%.8X)", 0x00000001, cpu->maxLevels);
@@ -455,23 +450,6 @@ int32_t get_core_type(void) {
   }
 }
 
-#ifdef __linux__
-// Gets the max frequency for estimating the peak performance,
-// filling in the passed cpuInfo parameter with this information.
-void fill_frequency_info_pp(struct cpuInfo* cpu) {
-  int32_t unused;
-  int32_t *max_freq_pp_vec = malloc(sizeof(int32_t) * cpu->num_cpus);
-  struct cpuInfo* ptr = cpu;
-
-  for (uint32_t i=0; i < cpu->num_cpus; i++) {
-    set_cpu_module(i, cpu->num_cpus, &unused);
-
-    ptr->freq->max_pp = measure_frequency(ptr, max_freq_pp_vec);
-    ptr = ptr->next_cpu;
-  }
-}
-#endif
-
 struct cpuInfo* get_cpu_info(void) {
   struct cpuInfo* cpu = emalloc(sizeof(struct cpuInfo));
   cpu->peak_performance = -1;
@@ -568,7 +546,6 @@ struct cpuInfo* get_cpu_info(void) {
       ptr->core_type = get_core_type();
     }
     ptr->first_core_id = first_core;
-    ptr->module_id = i;
     ptr->feat = get_features_info(ptr);
 
     ptr->arch = get_cpu_uarch(ptr);
@@ -593,13 +570,6 @@ struct cpuInfo* get_cpu_info(void) {
     if(ptr->topo == NULL) return cpu;
   }
 
-#ifdef __linux__
-  // If accurate_pp is requested, we need to get the max frequency
-  // after fetching the topology for all CPU modules, since the topology
-  // is required by fill_frequency_info_pp
-  if (accurate_pp()) fill_frequency_info_pp(cpu);
-#endif
-
   cpu->peak_performance = get_peak_performance(cpu, accurate_pp());
 
   return cpu;
@@ -1035,7 +1005,6 @@ struct frequency* get_frequency_info(struct cpuInfo* cpu) {
     }
   #endif
 
-  freq->max_pp = UNKNOWN_DATA;
   return freq;
 }
 

src/x86/freq/freq.c

@@ -21,12 +21,9 @@
 #define FREQ_VECTOR_SIZE         1<<16
 
 struct freq_thread {
-  // Inputs
-  struct cpuInfo* cpu;
   bool end;
   bool measure;
-  // Output
+  double freq;
-  int32_t *max_pp;
 };
 
 double vector_average_harmonic(double* v, int len) {
@@ -51,7 +48,6 @@ void* measure_freq(void *freq_ptr) {
   char* line = NULL;
   size_t len = 0;
   ssize_t read;
-  struct cpuInfo* cpu = freq->cpu;
 
   int v = 0;
   double* freq_vector = malloc(sizeof(double) * FREQ_VECTOR_SIZE);
@@ -80,43 +76,18 @@ void* measure_freq(void *freq_ptr) {
     sleep_ms(500);
   }
 
-  if (cpu->hybrid_flag) {
+  freq->freq = vector_average_harmonic(freq_vector, v);
-    // We have an heterogeneous architecture. After measuring the
+  printWarn("AVX2 measured freq=%f\n", freq->freq);
-    // frequency for all cores, we now need to compute the average
-    // independently for each CPU module.
-    struct cpuInfo* ptr = cpu;
-    double* freq_vector_ptr = freq_vector;
-
-    for (int i=0; i < cpu->num_cpus; ptr = ptr->next_cpu, i++) {
-      freq->max_pp[i] = vector_average_harmonic(freq_vector_ptr, ptr->topo->total_cores_module);
-      printWarn("AVX2 measured freq=%d (module %d)", freq->max_pp[i], i);
-
-      freq_vector_ptr = freq_vector_ptr + ptr->topo->total_cores_module;
-    }
-  }
-  else {
-    freq->max_pp[0] = vector_average_harmonic(freq_vector, v);
-    printWarn("AVX2 measured freq=%d\n", freq->max_pp[0]);
-  }
 
   return NULL;
 }
 
-int32_t measure_frequency(struct cpuInfo* cpu, int32_t *max_freq_pp_vec) {
+int64_t measure_frequency(struct cpuInfo* cpu) {
-  if (cpu->hybrid_flag && cpu->module_id > 0) {
-    // We have a hybrid architecture and we have already
-    // measured the frequency for this module in a previous
-    // call to this function, so now just return it.
-    return max_freq_pp_vec[cpu->module_id];
-  }
-
   int ret;
   int num_spaces;
   struct freq_thread* freq_struct = malloc(sizeof(struct freq_thread));
   freq_struct->end = false;
   freq_struct->measure = false;
-  freq_struct->cpu = cpu;
-  freq_struct->max_pp = max_freq_pp_vec;
 
   void* (*compute_function)(void*);
 
@@ -188,5 +159,5 @@ int32_t measure_frequency(struct cpuInfo* cpu, int32_t *max_freq_pp_vec) {
   }
 
   printf("\r%*c", num_spaces, ' ');
-  return max_freq_pp_vec[0];
+  return freq_struct->freq;
 }

src/x86/freq/freq.h

@@ -8,6 +8,6 @@
 #define MEASURE_TIME_SECONDS         5
 #define LOOP_ITERS           100000000
 
-int32_t measure_frequency(struct cpuInfo* cpu, int32_t *max_freq_pp_vec);
+int64_t measure_frequency(struct cpuInfo* cpu);
 
 #endif

src/x86/uarch.c

@@ -93,7 +93,6 @@ enum {
   UARCH_CEDAR_MILL,
   UARCH_ITANIUM2,
   UARCH_ICE_LAKE,
-  UARCH_SAPPHIRE_RAPIDS,
   UARCH_TIGER_LAKE,
   UARCH_ALDER_LAKE,
   UARCH_RAPTOR_LAKE,
@@ -120,9 +119,7 @@ enum {
   UARCH_ZEN3,
   UARCH_ZEN3_PLUS,
   UARCH_ZEN4,
-  UARCH_ZEN4C,
+  UARCH_ZEN4C
-  UARCH_ZEN5,
-  UARCH_ZEN5C,
 };
 
 struct uarch {
@@ -255,8 +252,7 @@ struct uarch* get_uarch_from_cpuid_intel(uint32_t ef, uint32_t f, uint32_t em, u
   // CHECK_UARCH(arch, 0,  6,  8, 14,  9, ...) It is not possible to determine uarch only from CPUID dump (can be Kaby Lake or Amber Lake)
   // CHECK_UARCH(arch, 0,  6,  8, 14, 10, ...) It is not possible to determine uarch only from CPUID dump (can be Kaby Lake R or Coffee Lake U)
   CHECK_UARCH(arch, 0,  6,  8, 14, 11, "Whiskey Lake",      UARCH_WHISKEY_LAKE,     14) // wikichip
-  // CHECK_UARCH(arch, 0,  6,  8, 14, 12, ...) It is not possible to determine uarch only from CPUID dump (can be Comet Lake U or Whiskey Lake U)
+  CHECK_UARCH(arch, 0,  6,  8, 14, 12, "Comet Lake",        UARCH_COMET_LAKE,       14) // wikichip
-  CHECK_UARCH(arch, 0,  6,  8, 15,  8, "Sapphire Rapids",   UARCH_SAPPHIRE_RAPIDS,   7) // wikichip
   CHECK_UARCH(arch, 0,  6,  9,  6, NA, "Tremont",           UARCH_TREMONT,          10) // LX*
   CHECK_UARCH(arch, 0,  6,  9,  7, NA, "Alder Lake",        UARCH_ALDER_LAKE,       10) // instlatx64 (Alder Lake-S)
   CHECK_UARCH(arch, 0,  6,  9, 10, NA, "Alder Lake",        UARCH_ALDER_LAKE,       10) // instlatx64 (Alder Lake-P)
@@ -414,12 +410,6 @@ struct uarch* get_uarch_from_cpuid_amd(uint32_t ef, uint32_t f, uint32_t em, uin
   CHECK_UARCH(arch, 10, 15,  8, NA, NA, "Zen 4",       UARCH_ZEN4,         5) // instlatx64 (AMD MI300C)
   CHECK_UARCH(arch, 10, 15,  9, NA, NA, "Zen 4",       UARCH_ZEN4,         5) // instlatx64 (AMD MI300A)
   CHECK_UARCH(arch, 10, 15, 10, NA, NA, "Zen 4c",      UARCH_ZEN4C,        5) // instlatx64
-  CHECK_UARCH(arch, 11, 15,  0, NA, NA, "Zen 5",       UARCH_ZEN5,         4) // Turin/EPYC (instlatx64)
-  CHECK_UARCH(arch, 11, 15,  1, NA, NA, "Zen 5c",      UARCH_ZEN5C,        3) // Zen5c EPYC (instlatx64, https://en.wikipedia.org/wiki/Zen_5#cite_note-10)
-  CHECK_UARCH(arch, 11, 15,  2, NA, NA, "Zen 5",       UARCH_ZEN5,         4) // Strix Point (instlatx64)
-  CHECK_UARCH(arch, 11, 15,  4, NA, NA, "Zen 5",       UARCH_ZEN5,         4) // Granite Ridge (instlatx64)
-  CHECK_UARCH(arch, 11, 15,  6, NA, NA, "Zen 5",       UARCH_ZEN5,         4) // Krackan Point (instlatx64)
-  CHECK_UARCH(arch, 11, 15,  7, NA, NA, "Zen 5",       UARCH_ZEN5,         4) // Strix Halo (instlatx64)
   UARCH_END
 
   return arch;
@@ -447,7 +437,6 @@ struct uarch* get_uarch_from_cpuid_hygon(uint32_t ef, uint32_t f, uint32_t em, u
 struct uarch* get_uarch_from_cpuid(struct cpuInfo* cpu, uint32_t dump, uint32_t ef, uint32_t f, uint32_t em, uint32_t m, int s) {
   if(cpu->cpu_vendor == CPU_VENDOR_INTEL) {
     struct uarch* arch = emalloc(sizeof(struct uarch));
-    // TODO: Refactor these 3 checks in a common function.
     if(dump == 0x000806E9) {
       if (cpu->cpu_name == NULL) {
         printErr("Unable to find uarch without CPU name");
@@ -487,30 +476,6 @@ struct uarch* get_uarch_from_cpuid(struct cpuInfo* cpu, uint32_t dump, uint32_t
 
       return arch;
     }
-    else if (dump == 0x000806EC) {
-      if (cpu->cpu_name == NULL) {
-        printErr("Unable to find uarch without CPU name");
-        fill_uarch(arch, STRING_UNKNOWN, UARCH_UNKNOWN, UNK);
-        return arch;
-      }
-
-      // It is not possible to determine uarch only from CPUID dump (can be Comet Lake U or Whiskey Lake U)
-      // https://github.com/Dr-Noob/cpufetch/issues/298
-      if (strstr(cpu->cpu_name, "i3-8145U") != NULL ||
-          strstr(cpu->cpu_name, "i5-8265U") != NULL ||
-          strstr(cpu->cpu_name, "i5-8365U") != NULL ||
-          strstr(cpu->cpu_name, "i7-8565U") != NULL ||
-          strstr(cpu->cpu_name, "i7-8665U") != NULL ||
-          strstr(cpu->cpu_name, "5405U")    != NULL ||
-          strstr(cpu->cpu_name, "4205U")    != NULL) {
-        fill_uarch(arch, "Whiskey Lake", UARCH_WHISKEY_LAKE, 14);
-      }
-      else {
-        fill_uarch(arch, "Comet Lake", UARCH_COMET_LAKE, 14);
-      }
-
-      return arch;
-    }
     return get_uarch_from_cpuid_intel(ef, f, em, m, s);
   }
   else if(cpu->cpu_vendor == CPU_VENDOR_AMD) {
@@ -587,8 +552,6 @@ char* infer_cpu_name_from_uarch(struct uarch* arch) {
 }
 
 bool vpus_are_AVX512(struct cpuInfo* cpu) {
-  // Zen5 actually has 2 x AVX512 units
-  // https://www.anandtech.com/show/21469/amd-details-ryzen-ai-300-series-for-mobile-strix-point-with-rdna-35-igpu-xdna-2-npu
   return cpu->arch->uarch != UARCH_ICE_LAKE &&
          cpu->arch->uarch != UARCH_TIGER_LAKE &&
          cpu->arch->uarch != UARCH_ZEN4 &&
@@ -618,7 +581,6 @@ int get_number_of_vpus(struct cpuInfo* cpu) {
       case UARCH_KNIGHTS_LANDING:
       case UARCH_KNIGHTS_MILL:
 
-      case UARCH_SAPPHIRE_RAPIDS:
       case UARCH_ICE_LAKE:
       case UARCH_TIGER_LAKE:
       case UARCH_ALDER_LAKE:
@@ -630,8 +592,6 @@ int get_number_of_vpus(struct cpuInfo* cpu) {
       case UARCH_ZEN3_PLUS:
       case UARCH_ZEN4:
       case UARCH_ZEN4C:
-      case UARCH_ZEN5:
-      case UARCH_ZEN5C:
         return 2;
       default:
         return 1;